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Device composite clocks tend to reproduce the usual sel/div/gate arrangement. Add macros to help define simple composite clocks in the system. The idea is _not_ to replace all instances of mux, div or gate with those macros. It is rather to use it for recurring and/or simple composite clocks, reducing controller verbosity where it makes sense. This should help reviews focus on the tricky parts. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-10-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
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*/
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#ifndef __MESON_CLKC_UTILS_H__
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#define __MESON_CLKC_UTILS_H__
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#include <linux/of_device.h>
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#include <linux/clk-provider.h>
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struct platform_device;
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struct meson_clk_hw_data {
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struct clk_hw **hws;
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unsigned int num;
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};
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struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
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struct meson_clkc_data {
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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struct meson_clk_hw_data hw_clks;
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};
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int meson_clkc_syscon_probe(struct platform_device *pdev);
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int meson_clkc_mmio_probe(struct platform_device *pdev);
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#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \
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struct clk_regmap _name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = _ops, \
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.parent_data = (_pdata), \
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.num_parents = 1, \
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.flags = (_flags), \
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}, \
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}
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#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \
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__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
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#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \
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__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
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/* Helpers for the usual sel/div/gate composite clocks */
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#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \
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_table, _dflags, _iflags) \
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struct clk_regmap _prefix##_name##_sel = { \
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.data = &(struct clk_regmap_mux_data) { \
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.offset = (_reg), \
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.mask = (_mask), \
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.shift = (_shift), \
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.flags = (_dflags), \
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.table = (_table), \
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}, \
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.hw.init = &(struct clk_init_data){ \
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.name = #_name "_sel", \
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.ops = &clk_regmap_mux_ops, \
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.parent_data = _pdata, \
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.num_parents = ARRAY_SIZE(_pdata), \
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.flags = (_iflags), \
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}, \
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}
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#define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \
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_dflags, _iflags) \
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struct clk_regmap _prefix##_name##_div = { \
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.data = &(struct clk_regmap_div_data) { \
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.offset = (_reg), \
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.shift = (_shift), \
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.width = (_width), \
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.flags = (_dflags), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_div", \
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.ops = &clk_regmap_divider_ops, \
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.parent_hws = (const struct clk_hw *[]) { \
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&_prefix##_name##_sel.hw \
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}, \
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.num_parents = 1, \
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.flags = (_iflags), \
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}, \
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}
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#define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \
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struct clk_regmap _prefix##_name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_hws = (const struct clk_hw *[]) { \
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&_prefix##_name##_div.hw \
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}, \
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.num_parents = 1, \
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.flags = (_iflags), \
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}, \
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}
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#endif
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