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77 Commits

Author SHA1 Message Date
Dmytro Laktyushkin
c34892144d drm/amd/display: dce 8 - 12 mem_input refactor to new style 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:12 -04:00
Dmytro Laktyushkin
9037d802a9 drm/amd/display: refactor bw related variable structure in val_ctx 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:01 -04:00
Tony Cheng
a2b8659db9 drm/amd/display: decouple resource_pool from resource_context 
to avoid null access in case res_ctx is used to access res_pool before it's fully constructed

also make it clear which function has dependency on resource_pool

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:41 -04:00
Dmytro Laktyushkin
e6303950ea drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:39 -04:00
Dmytro Laktyushkin
2180e7cca4 drm/amd/display: update dce8 & 10 bw programming 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:24:08 -04:00
Jordan Lazare
28f7245432 drm/amd/display: Fill in vrefresh and min_vblank_time for dce8/dce10 
PPLib is now calling into DC to get vrefresh and min_vblank_time, but
since full bandwidth calcs are missing for those generations, the pplib
structures were never being filled. This change fills the currently
required fields to prevent screen corruption.

Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:22:25 -04:00
Reza Amini
934d292316 drm/amd/display: remove surface validation against stream rect 
Surface information is by default copied from old context in dc_commit_stream.
Thus unchange streams will not be affected. For new streams, we shouldn't
validate the new mode against the surface configuration of old_context.

Signed-off-by: Reza Amini <reza.amini@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:52 -04:00
Alex Deucher
d4e13b0db1 drm/amd/display: decouple per-crtc-plane model 
Current design has per-crtc-plane model.
As a result, for asic's that support underlay,
are unable to expose it to user space for modesetting.

To enable this, the drm driver intialisation now runs
for number of surfaces instead of stream/crtc.

This patch plumbs surface capabilities to drm framework
so that it can be effectively used by user space.

Tests: (On Chromium OS for Stoney Only)
* 'modetest -p'  now shows additional plane
  with YUV capabilities in case of CZ and ST.
* 'plane_test' fails with below error:
  [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0
  as ther is no support for YUYV
* Checked multimonitor display works fine

Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:35 -04:00
Tony Cheng
3f8a944016 drm/amd/display: support CP2520 pattern 2 for HBR2 compliance 
- also some clean up

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:20:16 -04:00
Dmytro Laktyushkin
3853c184ed drm/amd/display: fix dce100_validate_bandwidth return value 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:42 -04:00
Dmytro Laktyushkin
cf43759306 drm/amd/display: bandwidth update fix 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:31 -04:00
Dmytro Laktyushkin
45209ef719 drm/amd/display: remove apply_clk_constraints, used validate_bandwidth universally 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:27 -04:00
Tony Cheng
a37656b99a drm/amd/display: report cursor size base on the ASIC 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:14:31 -04:00
Dmytro Laktyushkin
a99240d5f8 drm/amd/display: use disp clock value in context rather than bw_results 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:14:00 -04:00
Leon Elazar
3efeef11f4 drm/amd/display: surface validation on dce100 
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:13:16 -04:00
Joshua Aberback
4d35b093e6 drm/amd/display: Proper de-allocation of OPP 
- refactor opp_destroy functions to dce common file
  - fixes memory leak, dce specific variations didn't free regamma_params
- remove unused dce110_regamma structure

Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:11:42 -04:00
Harry Wentland
f0e3db90a6 drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:11:28 -04:00
Aric Cyr
ab2541b673 drm/amd/display: Remove dc_target object 
dc_target does not fit well into DRM framework so removed it.
This will prevent the driver from leveraging the pipe-split
code for tiled displays, so will have to be handled at a higher
level.  Most places that used dc_target now directly use dc_stream
instead.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:09:40 -04:00
Tony Cheng
7fc698a0c0 drm/amd/display: limit HBR3 support to Polaris and up 
- also fix YCbCr420 supported on Polaris and up

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:08:19 -04:00
Zeyu Fan
ab3ee7a556 drm/amd/display: OPP refactor and consolidation for DCE. 
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:05:47 -04:00
Dmytro Laktyushkin
9a70eba7f2 drm/amd/display: consolidate dce8-11.2 display clock code 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:03:01 -04:00
Dmytro Laktyushkin
e9c58bb439 drm/amd/display: remove clocks_state enum 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:02:58 -04:00
Dmytro Laktyushkin
3bad7c5ccf drm/amd/display: remove store clock state 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:02:52 -04:00
Dmytro Laktyushkin
5d6d185f32 drm/amd/display: restyle display clock calls part 2 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:02:48 -04:00
Dmytro Laktyushkin
1a687574a7 drm/amd/display: restyle display clock calls part 1 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:02:44 -04:00
Tony Cheng
197062bf12 drm/amd/display: refactor DCE11 DVVM 
- move to new programming style
- clean up table to make it obvious what we are programming

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:02:31 -04:00
Harry Wentland
4562236b3b drm/amd/dc: Add dc display driver (v2) 
Supported DCE versions: 8.0, 10.0, 11.0, 11.2

v2: rebase against 4.11

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:01:32 -04:00