When the device-tree board file was added for the Tegra234 VDK simulator
it incorrectly used the names 'cbb' and 'sdhci' instead of 'bus' and
'mmc', respectively. The names 'bus' and 'mmc' are required by the
device-tree json-schema validation tools. Therefore, fix this by
renaming these nodes accordingly.
Fixes: 639448912b ("arm64: tegra: Initial Tegra234 VDK support")
Reported-by: Ashish Singhal <ashishsingha@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AON HSP node's "reg" property size 0xa0000 will overlap with other
resources. This patch fixes that wrong value with correct size 0x90000.
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Fixes: a38570c22e ("arm64: tegra: Add nodes for TCU on Tegra194")
Signed-off-by: Thierry Reding <treding@nvidia.com>
USB host mode is broken on the OTG port of Jetson TX1 platform because
the USB_VBUS_EN0 regulator (regulator@11) is being overwritten by the
vdd-cam-1v2 regulator. This commit rearranges USB_VBUS_EN0 to be
regulator@14.
Fixes: 257c8047be ("arm64: tegra: jetson-tx1: Add camera supplies")
Cc: stable@vger.kernel.org
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Jetson Xavier NX board routes UARTA to the 40-pin header and UARTC
to a 12-pin debug header. The UARTs can be used by either the Tegra
Combined UART (TCU) driver or the Tegra 8250 driver. By default, the
TCU will use UARTC on Jetson Xavier NX. Currently, device-tree for
Xavier NX enables the TCU and the Tegra 8250 node for UARTC. Fix this
by disabling the Tegra 8250 node for UARTC and enabling the Tegra 8250
node for UARTA.
Fixes: 3f9efbbe57 ("arm64: tegra: Add support for Jetson Xavier NX")
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Commit ff4c371d2b ("arm64: defconfig: Build ADMA and ACONNECT driver")
enable the Tegra ADMA and ACONNECT drivers and this is causing resume
from system suspend to fail on Jetson TX2. Resume is failing because the
ACONNECT driver is being resumed before the BPMP driver, and the ACONNECT
driver is attempting to power on a power-domain that is provided by the
BPMP. While a proper fix for the resume sequencing problem is identified,
disable the ACONNECT for Jetson TX2 temporarily to avoid breaking system
suspend.
Please note that ACONNECT driver is used by the Audio Processing Engine
(APE) on Tegra, but because there is no mainline support for APE on
Jetson TX2 currently, disabling the ACONNECT does not disable any useful
feature at the moment.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It
supports a subset of the peripherals that will be available in the final
chip and serves as a bootstrapping platform.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Populate the EEPROMs that are present on the Jetson Xavier NX developer
platform.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Populate the label property for the AT24 EEPROMs on the various Jetson
platforms. Note that the name 'module' is used to identify the EEPROM
on the processor module board and the name 'system' is used to identify
the EEPROM on the main base board (which is sometimes referred to as
the carrier board).
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under ACONNECT
* AHUB includes many HW accelerators and below components are added
as its children.
* ADMAIF
* I2S
* DMIC
* DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does
not have this module)
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
These devices are required for audio sub system and current patch
ensures probe path of these devices gets tested. Later sound card
support would be added which can use these devices at runtime.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PWM on Tegra210 can run at a maximum frequency of 48 MHz and cannot
reach the minimum period is 5334 ns. The currently configured period of
4880 ns is not within the valid range, so set it to 8000 ns. This value
was taken from the downstream DTS files and seems to work fine.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Both display controllers can drive both DSI and both SOR outputs on
Tegra210. Describe this in device tree so that the operating system
doesn't have to guess.
Signed-off-by: Thierry Reding <treding@nvidia.com>
There is no GPIO hooked up to the write-protection pin of the SD slot.
Make sure to describe this properly in device tree to avoid errors or
warnings being emitted by the operating system.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The VBUS supply for the micro USB port on Jetson Nano is derived from
the main system supply and always on. Describe in nevertheless to fix
warnings during boot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
All four DPAUX controllers on Tegra194 control the pin configuration of
their companion I2C controllers. Wire up all the pinctrl states for the
I2C controllers so that their pins can be correctly muxed when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The P2888 processor module contains an EEPROM that provides means of
identifying the module. The P2822 carrier board contains the same EEPROM
with information identifying the carrier board. Both of them ar accessed
via the GEN_I2C1 bus.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
On Tegra194, data on valid operating points for the CPUs needs to be
queried from BPMP. However, there is no node representing CPU complex.
So, add a compatible string to the 'cpus' node instead of using dummy
node to bind the cpufreq driver to. Also, add reference to the BPMP
instance for the CPU complex.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR controller needs the AVDD I/O and VDD HDMI PLL supplies in order
to operate correctly. Make sure to specify them for the Norrin board.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The VI I2C controller provides an I2C bus and therefore needs to define
the #address-cells and #size-cells properties.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 VI I2C is in VE power domain and i2c-vi node should have
power-domains property.
Current Tegra210 i2c-vi device node is missing both VI I2C clocks
and power-domains property.
This patch adds them.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra210 DPAUX controller is not compatible with that found on
Tegra124, so it must have a separate compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DPAUX controller device tree bindings require the bus to have an
i2c-bus subnode to distinguish between I2C clients and pinmux groups.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The VBUS for USB3 connector on the Jetson TX2 is connected to the
vdd_usb1 supply and although this is populated for the USB2 port
on the USB3 connector it is not populated for the USB3 port and
causes the following warning to be seen on boot ...
usb3-0: supply vbus not found, using dummy regulator
Fix this by also adding the VBUS supply to the USB3 port.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Populate the DFLL node and corresponding PWM pin nodes in order to
enable CPUFREQ support on the Jetson Nano platform.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the device-tree source files for the Tegra194 Jetson Xavier NX
Developer Kit. The Xavier NX Developer Kit consists of a small form
factor system-on-module (SOM) board (part number p3668-0000) and a
carrier board (part number p3509-0000).
The Xavier NX Developer Kit SOM features a micro-SD card slot, however,
there is also a variant of the SOM available that features a 16GB eMMC.
Given that the carrier board can be used with the different SOM
variants, that have different part numbers, both the compatible string
and file name of the device-tree source file for the Developer Kit is a
concatenation of the SOM and carrier board part numbers.
Based on some initial work by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Re-order Tegra194's PCIe aperture mappings to have IO window moved to
64-bit aperture and have the entire 32-bit aperture used for accessing
the configuration space. This makes it to use the entire 32MB of the 32-bit
aperture for ECAM purpose while booting through ACPI.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch enables VI and CSI in device tree for Jetson Nano.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jetson TX1 development board has a camera expansion connector which
has 2V8, 1V8 and 1V2 supplies to power up the camera sensor on the
supported camera modules.
Camera module designed as per Jetson TX1 camera expansion connector
may use these supplies for camera sensor avdd 2V8, digital core 1V8,
and digital interface 1V2 voltages.
These supplies are from fixed regulators on TX1 carrier board with
enable control signals from I2C GPIO expanders.
This patch adds these camera supplies to Jetson TX1 device tree to
allow using these when a camera module is used.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This is purely to make the json-schema validation tools happy because
they cannot deal with string arrays that may be in arbitrary order.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The control backbone is a simple-bus and hence its device tree node
should be named "bus@<unit-address>" according to the bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Standardize on "pmic" as the node name for the PMIC on Tegra210 systems
and use consistent names for pinmux and GPIO hog nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device tree nodes for interrupt controllers should be named "interrupt-
controller", so rename the AGIC accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AON GPIO controller on Tegra194 currently only uses a single
interrupt, so remove the extra ones.
Signed-off-by: Thierry Reding <treding@nvidia.com>
SRAM nodes should be named sram@<unit-address> to match the bindings.
While at it, also remove the unneeded, custom compatible string for
SRAM partition nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
It's very difficult to describe string lists that can be in arbitrary
order using the json-schema based validation tooling. Since the OS is
not going to care either way, take the easy way out and reorder these
entries to match the order defined in the bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The address-bits and page-size properties that are currently used are
not valid properties according to the bindings. Use the address-width
and pagesize properties instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
