From ed44b8cdfdb4b3ecd5fe59fff03c01798dadaa1a Mon Sep 17 00:00:00 2001 From: Dylan Hung Date: Tue, 19 Oct 2021 16:36:30 +0800 Subject: [PATCH] clk: aspeed: revise ast2600 i3c clock and reset revise the i3c clock and reset control. Signed-off-by: Dylan Hung Change-Id: I81d00ce3c5c6c22d208ad34855def9df9c0b407d --- drivers/char/ipmi/Kconfig | 26 ++++++++++++++ drivers/char/ipmi/Makefile | 2 ++ drivers/clk/clk-ast2600.c | 43 ++++++++++++++++++----- include/dt-bindings/clock/ast2600-clock.h | 17 +++++---- 4 files changed, 71 insertions(+), 17 deletions(-) diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig index 19f1efc0bc3d..d15a34842883 100644 --- a/drivers/char/ipmi/Kconfig +++ b/drivers/char/ipmi/Kconfig @@ -177,6 +177,32 @@ config ASPEED_BT_IPMI_BMC found on Aspeed SOCs (AST2400 and AST2500). The driver implements the BMC side of the BT interface. +config SSIF_IPMI_BMC + tristate "SSIF IPMI BMC driver" + select I2C + select I2C_SLAVE + help + This enables the IPMI SMBus system interface (SSIF) at the + management (BMC) side. + + The driver implements the BMC side of the SMBus system + interface (SSIF). + +config ASPEED_SSIF_IPMI_BMC + depends on ARCH_ASPEED || COMPILE_TEST + select SSIF_IPMI_BMC + tristate "Aspeed SSIF IPMI BMC driver" + help + Provides a driver for the SSIF IPMI interface found on + Aspeed AST2500 SoC. + + The driver implements the BMC side of the SMBus system + interface (SSIF), specific for Aspeed AST2500 SoC. + + + The driver implements the BMC side of + the IPMI over SSIF interface. + config IPMB_DEVICE_INTERFACE tristate 'IPMB Interface handler' depends on I2C diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile index 3390985b4802..54d46699be49 100644 --- a/drivers/char/ipmi/Makefile +++ b/drivers/char/ipmi/Makefile @@ -30,3 +30,5 @@ obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o obj-$(CONFIG_ASPEED_KCS_IPMI_BMC) += kcs_bmc_aspeed.o obj-$(CONFIG_NPCM7XX_KCS_IPMI_BMC) += kcs_bmc_npcm7xx.o obj-$(CONFIG_IPMB_DEVICE_INTERFACE) += ipmb_dev_int.o +obj-$(CONFIG_SSIF_IPMI_BMC) += ssif_bmc.o +obj-$(CONFIG_ASPEED_SSIF_IPMI_BMC) += ssif_bmc_aspeed.o diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index bd4344302dc5..3cbbaa4a1b1d 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -4,6 +4,7 @@ #define pr_fmt(fmt) "clk-ast2600: " fmt +#include #include #include #include @@ -33,6 +34,17 @@ #define ASPEED_G6_CLK_SELECTION2 0x304 #define ASPEED_G6_CLK_SELECTION4 0x310 #define ASPEED_G6_CLK_SELECTION5 0x314 +#define I3C_CLK_SELECTION BIT(31) +#define I3C_CLK_SELECT_HCLK 0 +#define I3C_CLK_SELECT_APLL_DIV 1 +#define APLL_DIV_SELECTION GENMASK(30, 28) +#define APLL_DIV_2 0b001 +#define APLL_DIV_3 0b010 +#define APLL_DIV_4 0b011 +#define APLL_DIV_5 0b100 +#define APLL_DIV_6 0b101 +#define APLL_DIV_7 0b110 +#define APLL_DIV_8 0b111 #define ASPEED_HPLL_PARAM 0x200 #define ASPEED_APLL_PARAM 0x210 @@ -151,14 +163,14 @@ static struct aspeed_gate_data aspeed_g6_gates[] = { [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ /* Reserved 38 RSA: no longer used */ /* Reserved 39 */ - [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ - [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ - [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ - [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ - [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ - [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ - [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ - [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ + [ASPEED_CLK_GATE_I3CDMACLK] = { 39, ASPEED_RESET_I3C, "i3cclk-gate", NULL, 0 }, /* I3C_DMA */ + [ASPEED_CLK_GATE_I3C0CLK] = { 40, ASPEED_RESET_I3C0, "i3c0clk-gate", "i3cclk", 0 }, + [ASPEED_CLK_GATE_I3C1CLK] = { 41, ASPEED_RESET_I3C1, "i3c1clk-gate", "i3cclk", 0 }, + [ASPEED_CLK_GATE_I3C2CLK] = { 42, ASPEED_RESET_I3C2, "i3c2clk-gate", "i3cclk", 0 }, + [ASPEED_CLK_GATE_I3C3CLK] = { 43, ASPEED_RESET_I3C3, "i3c3clk-gate", "i3cclk", 0 }, + [ASPEED_CLK_GATE_I3C4CLK] = { 44, ASPEED_RESET_I3C4, "i3c4clk-gate", "i3cclk", 0 }, + [ASPEED_CLK_GATE_I3C5CLK] = { 45, ASPEED_RESET_I3C5, "i3c5clk-gate", "i3cclk", 0 }, + [ASPEED_CLK_GATE_RESERVED44] = { 46, ASPEED_RESET_RESERVED46, "reserved-46", NULL, 0 }, [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uxclk", CLK_IS_CRITICAL }, /* UART1 */ [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uxclk", CLK_IS_CRITICAL }, /* UART2 */ [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uxclk", 0 }, /* UART3 */ @@ -964,6 +976,21 @@ static void __init aspeed_g6_cc(struct regmap *map) hw = clk_hw_register_fixed_factor(NULL, "huxclk", "uartx", 0, mult, div); aspeed_g6_clk_data->hws[ASPEED_CLK_HUXCLK] = hw; + /* i3c clock */ + regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val); + if (FIELD_GET(I3C_CLK_SELECTION, val) == I3C_CLK_SELECT_APLL_DIV) { + val = FIELD_GET(APLL_DIV_SELECTION, val); + if (val) + div = val + 1; + else + div = val + 2; + hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, + div); + } else { + hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "ahb", 0, 1, + 1); + } + aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw; }; static void __init aspeed_g6_cc_init(struct device_node *np) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index f00a1b93d327..2f1d8f3d797a 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -51,15 +51,14 @@ #define ASPEED_CLK_GATE_SDCLK 35 #define ASPEED_CLK_GATE_EMMCCLK 36 -#define ASPEED_CLK_GATE_I3C0CLK 37 -#define ASPEED_CLK_GATE_I3C1CLK 38 -#define ASPEED_CLK_GATE_I3C2CLK 39 -#define ASPEED_CLK_GATE_I3C3CLK 40 -#define ASPEED_CLK_GATE_I3C4CLK 41 -#define ASPEED_CLK_GATE_I3C5CLK 42 -#define ASPEED_CLK_GATE_I3C6CLK 43 -#define ASPEED_CLK_GATE_I3C7CLK 44 - +#define ASPEED_CLK_GATE_I3CDMACLK 37 +#define ASPEED_CLK_GATE_I3C0CLK 38 +#define ASPEED_CLK_GATE_I3C1CLK 39 +#define ASPEED_CLK_GATE_I3C2CLK 40 +#define ASPEED_CLK_GATE_I3C3CLK 41 +#define ASPEED_CLK_GATE_I3C4CLK 42 +#define ASPEED_CLK_GATE_I3C5CLK 43 +#define ASPEED_CLK_GATE_RESERVED44 44 #define ASPEED_CLK_GATE_FSICLK 45 #define ASPEED_CLK_HPLL 46