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scsi: ufs: rockchip: Initial support for UFS
RK3576 SoC contains a UFS controller, add initial support for it. The features are: 1. support UFS 2.0 features 2. High speed up to HS-G3 3. 2RX-2TX lanes 4. auto H8 entry and exit Software limitation: 1. HCE procedure: enable controller->enable intr->dme_reset->dme_enable 2. disable unipro timeout values before power mode change [mkp: fix build errors] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1738736156-119203-7-git-send-email-shawn.lin@rock-chips.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Shawn Lin
committed by
Martin K. Petersen
Martin K. Petersen
parent
6b070711b7
commit
d3cbe455d6
@@ -142,3 +142,15 @@ config SCSI_UFS_SPRD
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Select this if you have UFS controller on Unisoc chipset.
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If unsure, say N.
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config SCSI_UFS_ROCKCHIP
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tristate "Rockchip UFS host controller driver"
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depends on SCSI_UFSHCD_PLATFORM && (ARCH_ROCKCHIP || COMPILE_TEST)
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help
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This selects the Rockchip specific additions to UFSHCD platform driver.
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UFS host on Rockchip needs some vendor specific configuration before
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accessing the hardware which includes PHY configuration and vendor
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specific registers.
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Select this if you have UFS controller on Rockchip chipset.
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If unsure, say N.
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@@ -10,5 +10,6 @@ obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
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obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
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obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
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obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
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obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o
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obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o
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obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
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354
drivers/ufs/host/ufs-rockchip.c
Normal file
354
drivers/ufs/host/ufs-rockchip.c
Normal file
@@ -0,0 +1,354 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2025 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_wakeup.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <ufs/ufshcd.h>
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#include <ufs/unipro.h>
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#include "ufshcd-pltfrm.h"
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#include "ufs-rockchip.h"
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static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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if (status == POST_CHANGE) {
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err = ufshcd_dme_reset(hba);
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if (err)
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return err;
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err = ufshcd_dme_enable(hba);
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if (err)
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return err;
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return ufshcd_vops_phy_initialization(hba);
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}
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return 0;
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}
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static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba)
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{
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hba->rpm_lvl = UFS_PM_LVL_5;
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hba->spm_lvl = UFS_PM_LVL_5;
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}
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static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
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/* enable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE);
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for (int i = 0; i < 2; i++) {
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/* Configuration M - TX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, SEL_TX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_VALUE, SEL_TX_LANE0 + i), 0x44);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, SEL_TX_LANE0 + i), 0xe6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, SEL_TX_LANE0 + i), 0x07);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_TASE_VALUE, SEL_TX_LANE0 + i), 0x93);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_BASE_NVALUE, SEL_TX_LANE0 + i), 0xc9);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_POWER_SAVING_CTRL, SEL_TX_LANE0 + i), 0x00);
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/* Configuration M - RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, SEL_RX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, SEL_RX_LANE0 + i), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE, SEL_RX_LANE0 + i), 0x58);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE1, SEL_RX_LANE0 + i), 0x8c);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE2, SEL_RX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_OPTION, SEL_RX_LANE0 + i), 0xf6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_POWER_SAVING_CTRL, SEL_RX_LANE0 + i), 0x69);
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}
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/* disable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_DISABLE);
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ufs_sys_writel(host->mphy_base, 0x80, CMN_REG23);
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ufs_sys_writel(host->mphy_base, 0xB5, TRSV0_REG14);
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ufs_sys_writel(host->mphy_base, 0xB5, TRSV1_REG14);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG15);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG15);
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ufs_sys_writel(host->mphy_base, 0x38, TRSV0_REG08);
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ufs_sys_writel(host->mphy_base, 0x38, TRSV1_REG08);
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ufs_sys_writel(host->mphy_base, 0x50, TRSV0_REG29);
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ufs_sys_writel(host->mphy_base, 0x50, TRSV1_REG29);
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ufs_sys_writel(host->mphy_base, 0x80, TRSV0_REG2E);
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ufs_sys_writel(host->mphy_base, 0x80, TRSV1_REG2E);
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ufs_sys_writel(host->mphy_base, 0x18, TRSV0_REG3C);
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ufs_sys_writel(host->mphy_base, 0x18, TRSV1_REG3C);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG16);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG16);
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ufs_sys_writel(host->mphy_base, 0x20, TRSV0_REG17);
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ufs_sys_writel(host->mphy_base, 0x20, TRSV1_REG17);
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ufs_sys_writel(host->mphy_base, 0xC0, TRSV0_REG18);
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ufs_sys_writel(host->mphy_base, 0xC0, TRSV1_REG18);
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ufs_sys_writel(host->mphy_base, 0x03, CMN_REG25);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG3D);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG3D);
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ufs_sys_writel(host->mphy_base, 0xC0, CMN_REG23);
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udelay(1);
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ufs_sys_writel(host->mphy_base, 0x00, CMN_REG23);
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usleep_range(200, 250);
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/* start link up */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
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return 0;
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}
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static int ufs_rockchip_common_init(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct ufs_rockchip_host *host;
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int err;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf");
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if (IS_ERR(host->ufs_sys_ctrl))
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return dev_err_probe(dev, PTR_ERR(host->ufs_sys_ctrl),
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"Failed to map HCI system control registers\n");
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host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf");
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if (IS_ERR(host->ufs_phy_ctrl))
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return dev_err_probe(dev, PTR_ERR(host->ufs_phy_ctrl),
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"Failed to map mphy system control registers\n");
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host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy");
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if (IS_ERR(host->mphy_base))
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return dev_err_probe(dev, PTR_ERR(host->mphy_base),
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"Failed to map mphy base registers\n");
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host->rst = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(host->rst))
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return dev_err_probe(dev, PTR_ERR(host->rst),
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"failed to get reset control\n");
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reset_control_assert(host->rst);
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udelay(1);
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reset_control_deassert(host->rst);
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host->ref_out_clk = devm_clk_get_enabled(dev, "ref_out");
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if (IS_ERR(host->ref_out_clk))
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return dev_err_probe(dev, PTR_ERR(host->ref_out_clk),
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"ref_out clock unavailable\n");
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host->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(host->rst_gpio))
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return dev_err_probe(dev, PTR_ERR(host->rst_gpio),
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"failed to get reset gpio\n");
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err = devm_clk_bulk_get_all_enabled(dev, &host->clks);
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if (err)
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return dev_err_probe(dev, err, "failed to enable clocks\n");
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host->hba = hba;
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ufshcd_set_variant(hba, host);
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return 0;
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}
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static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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int ret;
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hba->quirks = UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
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/* Enable BKOPS when suspend */
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hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
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/* Enable putting device into deep sleep */
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hba->caps |= UFSHCD_CAP_DEEPSLEEP;
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/* Enable devfreq of UFS */
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hba->caps |= UFSHCD_CAP_CLK_SCALING;
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/* Enable WriteBooster */
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hba->caps |= UFSHCD_CAP_WB_EN;
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/* Set the default desired pm level in case no users set via sysfs */
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ufs_rockchip_set_pm_lvl(hba);
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ret = ufs_rockchip_common_init(hba);
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if (ret)
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return dev_err_probe(dev, ret, "ufs common init fail\n");
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return 0;
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}
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static int ufs_rockchip_device_reset(struct ufs_hba *hba)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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gpiod_set_value_cansleep(host->rst_gpio, 1);
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usleep_range(20, 25);
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gpiod_set_value_cansleep(host->rst_gpio, 0);
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usleep_range(20, 25);
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return 0;
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}
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static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = {
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.name = "rk3576",
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.init = ufs_rockchip_rk3576_init,
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.device_reset = ufs_rockchip_device_reset,
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.hce_enable_notify = ufs_rockchip_hce_enable_notify,
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.phy_initialization = ufs_rockchip_rk3576_phy_init,
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};
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static const struct of_device_id ufs_rockchip_of_match[] = {
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{ .compatible = "rockchip,rk3576-ufshc", .data = &ufs_hba_rk3576_vops },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match);
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static int ufs_rockchip_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct ufs_hba_variant_ops *vops;
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int err;
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vops = device_get_match_data(dev);
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if (!vops)
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return dev_err_probe(dev, -ENODATA, "ufs_hba_variant_ops not defined.\n");
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err = ufshcd_pltfrm_init(pdev, vops);
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if (err)
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return dev_err_probe(dev, err, "ufshcd_pltfrm_init failed\n");
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return 0;
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}
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static void ufs_rockchip_remove(struct platform_device *pdev)
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{
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ufshcd_pltfrm_remove(pdev);
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}
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#ifdef CONFIG_PM
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static int ufs_rockchip_runtime_suspend(struct device *dev)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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clk_disable_unprepare(host->ref_out_clk);
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/* Do not power down the genpd if rpm_lvl is less than level 5 */
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dev_pm_genpd_rpm_always_on(dev, hba->rpm_lvl < UFS_PM_LVL_5 ? true : false);
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return ufshcd_runtime_suspend(dev);
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}
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static int ufs_rockchip_runtime_resume(struct device *dev)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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int err;
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err = clk_prepare_enable(host->ref_out_clk);
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if (err) {
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dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
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return err;
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}
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reset_control_assert(host->rst);
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udelay(1);
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reset_control_deassert(host->rst);
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return ufshcd_runtime_resume(dev);
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}
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#endif
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#ifdef CONFIG_PM_SLEEP
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static int ufs_rockchip_system_suspend(struct device *dev)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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int err;
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/*
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* If spm_lvl is less than level 5, it means we need to keep the host
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* controller in powered-on state. So device_set_awake_path() is
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* calling pm core to notify the genpd provider to meet this requirement
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*/
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if (hba->spm_lvl < UFS_PM_LVL_5)
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device_set_awake_path(dev);
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err = ufshcd_system_suspend(dev);
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if (err) {
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dev_err(hba->dev, "UFSHCD system susped failed %d\n", err);
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return err;
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}
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clk_disable_unprepare(host->ref_out_clk);
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return 0;
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}
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static int ufs_rockchip_system_resume(struct device *dev)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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int err;
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err = clk_prepare_enable(host->ref_out_clk);
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if (err) {
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dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
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return err;
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}
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return ufshcd_system_resume(dev);
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}
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#endif
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static const struct dev_pm_ops ufs_rockchip_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(ufs_rockchip_system_suspend, ufs_rockchip_system_resume)
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SET_RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL)
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.prepare = ufshcd_suspend_prepare,
|
||||
.complete = ufshcd_resume_complete,
|
||||
};
|
||||
|
||||
static struct platform_driver ufs_rockchip_pltform = {
|
||||
.probe = ufs_rockchip_probe,
|
||||
.remove = ufs_rockchip_remove,
|
||||
.driver = {
|
||||
.name = "ufshcd-rockchip",
|
||||
.pm = &ufs_rockchip_pm_ops,
|
||||
.of_match_table = ufs_rockchip_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(ufs_rockchip_pltform);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Rockchip UFS Host Driver");
|
||||
90
drivers/ufs/host/ufs-rockchip.h
Normal file
90
drivers/ufs/host/ufs-rockchip.h
Normal file
@@ -0,0 +1,90 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Rockchip UFS Host Controller driver
|
||||
*
|
||||
* Copyright (C) 2025 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _UFS_ROCKCHIP_H_
|
||||
#define _UFS_ROCKCHIP_H_
|
||||
|
||||
#define SEL_TX_LANE0 0x0
|
||||
#define SEL_TX_LANE1 0x1
|
||||
#define SEL_TX_LANE2 0x2
|
||||
#define SEL_TX_LANE3 0x3
|
||||
#define SEL_RX_LANE0 0x4
|
||||
#define SEL_RX_LANE1 0x5
|
||||
#define SEL_RX_LANE2 0x6
|
||||
#define SEL_RX_LANE3 0x7
|
||||
|
||||
#define VND_TX_CLK_PRD 0xAA
|
||||
#define VND_TX_CLK_PRD_EN 0xA9
|
||||
#define VND_TX_LINERESET_PVALUE2 0xAB
|
||||
#define VND_TX_LINERESET_PVALUE1 0xAC
|
||||
#define VND_TX_LINERESET_VALUE 0xAD
|
||||
#define VND_TX_BASE_NVALUE 0x93
|
||||
#define VND_TX_TASE_VALUE 0x94
|
||||
#define VND_TX_POWER_SAVING_CTRL 0x7F
|
||||
#define VND_RX_CLK_PRD 0x12
|
||||
#define VND_RX_CLK_PRD_EN 0x11
|
||||
#define VND_RX_LINERESET_PVALUE2 0x1B
|
||||
#define VND_RX_LINERESET_PVALUE1 0x1C
|
||||
#define VND_RX_LINERESET_VALUE 0x1D
|
||||
#define VND_RX_LINERESET_OPTION 0x25
|
||||
#define VND_RX_POWER_SAVING_CTRL 0x2F
|
||||
#define VND_RX_SAVE_DET_CTRL 0x1E
|
||||
|
||||
#define CMN_REG23 0x8C
|
||||
#define CMN_REG25 0x94
|
||||
#define TRSV0_REG08 0xE0
|
||||
#define TRSV1_REG08 0x220
|
||||
#define TRSV0_REG14 0x110
|
||||
#define TRSV1_REG14 0x250
|
||||
#define TRSV0_REG15 0x134
|
||||
#define TRSV1_REG15 0x274
|
||||
#define TRSV0_REG16 0x128
|
||||
#define TRSV1_REG16 0x268
|
||||
#define TRSV0_REG17 0x12C
|
||||
#define TRSV1_REG17 0x26c
|
||||
#define TRSV0_REG18 0x120
|
||||
#define TRSV1_REG18 0x260
|
||||
#define TRSV0_REG29 0x164
|
||||
#define TRSV1_REG29 0x2A4
|
||||
#define TRSV0_REG2E 0x178
|
||||
#define TRSV1_REG2E 0x2B8
|
||||
#define TRSV0_REG3C 0x1B0
|
||||
#define TRSV1_REG3C 0x2F0
|
||||
#define TRSV0_REG3D 0x1B4
|
||||
#define TRSV1_REG3D 0x2F4
|
||||
|
||||
#define MPHY_CFG 0x200
|
||||
#define MPHY_CFG_ENABLE 0x40
|
||||
#define MPHY_CFG_DISABLE 0x0
|
||||
|
||||
#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022
|
||||
#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023
|
||||
|
||||
struct ufs_rockchip_host {
|
||||
struct ufs_hba *hba;
|
||||
void __iomem *ufs_phy_ctrl;
|
||||
void __iomem *ufs_sys_ctrl;
|
||||
void __iomem *mphy_base;
|
||||
struct gpio_desc *rst_gpio;
|
||||
struct reset_control *rst;
|
||||
struct clk *ref_out_clk;
|
||||
struct clk_bulk_data *clks;
|
||||
uint64_t caps;
|
||||
};
|
||||
|
||||
#define ufs_sys_writel(base, val, reg) \
|
||||
writel((val), (base) + (reg))
|
||||
#define ufs_sys_readl(base, reg) readl((base) + (reg))
|
||||
#define ufs_sys_set_bits(base, mask, reg) \
|
||||
ufs_sys_writel( \
|
||||
(base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
|
||||
#define ufs_sys_ctrl_clr_bits(base, mask, reg) \
|
||||
ufs_sys_writel((base), \
|
||||
((~(mask)) & (ufs_sys_readl((base), (reg)))), \
|
||||
(reg))
|
||||
|
||||
#endif /* _UFS_ROCKCHIP_H_ */
|
||||
Reference in New Issue
Block a user