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riscv: dts: sophgo: add zfh for sg2042

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sg2042 support Zfh ISA extension [1].

Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/bcaf5684c614959f49a9770bf3cd41096cee5fe6.1751698574.git.rabenda.cn@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Han Gao
2025-07-05 15:00:14 +08:00
committed by Inochi Amaoto
parent 6ebff712f4
commit cb074bed11
1 changed files with 64 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

128
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
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@@ -260,7 +260,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
@@ -287,7 +287,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
@@ -314,7 +314,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
@@ -341,7 +341,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
@@ -368,7 +368,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <4>;
@@ -395,7 +395,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <5>;
@@ -422,7 +422,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <6>;
@@ -449,7 +449,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <7>;
@@ -476,7 +476,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <8>;
@@ -503,7 +503,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <9>;
@@ -530,7 +530,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <10>;
@@ -557,7 +557,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <11>;
@@ -584,7 +584,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <12>;
@@ -611,7 +611,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <13>;
@@ -638,7 +638,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <14>;
@@ -665,7 +665,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <15>;
@@ -692,7 +692,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <16>;
@@ -719,7 +719,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <17>;
@@ -746,7 +746,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <18>;
@@ -773,7 +773,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <19>;
@@ -800,7 +800,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <20>;
@@ -827,7 +827,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <21>;
@@ -854,7 +854,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <22>;
@@ -881,7 +881,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <23>;
@@ -908,7 +908,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <24>;
@@ -935,7 +935,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <25>;
@@ -962,7 +962,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <26>;
@@ -989,7 +989,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <27>;
@@ -1016,7 +1016,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <28>;
@@ -1043,7 +1043,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <29>;
@@ -1070,7 +1070,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <30>;
@@ -1097,7 +1097,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <31>;
@@ -1124,7 +1124,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <32>;
@@ -1151,7 +1151,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <33>;
@@ -1178,7 +1178,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <34>;
@@ -1205,7 +1205,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <35>;
@@ -1232,7 +1232,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <36>;
@@ -1259,7 +1259,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <37>;
@@ -1286,7 +1286,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <38>;
@@ -1313,7 +1313,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <39>;
@@ -1340,7 +1340,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <40>;
@@ -1367,7 +1367,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <41>;
@@ -1394,7 +1394,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <42>;
@@ -1421,7 +1421,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <43>;
@@ -1448,7 +1448,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <44>;
@@ -1475,7 +1475,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <45>;
@@ -1502,7 +1502,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <46>;
@@ -1529,7 +1529,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <47>;
@@ -1556,7 +1556,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <48>;
@@ -1583,7 +1583,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <49>;
@@ -1610,7 +1610,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <50>;
@@ -1637,7 +1637,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <51>;
@@ -1664,7 +1664,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <52>;
@@ -1691,7 +1691,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <53>;
@@ -1718,7 +1718,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <54>;
@@ -1745,7 +1745,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <55>;
@@ -1772,7 +1772,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <56>;
@@ -1799,7 +1799,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <57>;
@@ -1826,7 +1826,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <58>;
@@ -1853,7 +1853,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <59>;
@@ -1880,7 +1880,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <60>;
@@ -1907,7 +1907,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <61>;
@@ -1934,7 +1934,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <62>;
@@ -1961,7 +1961,7 @@
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <63>;