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dt-bindings: display: bridge: renesas,dsi-csi2-tx: Allow panel@ subnode
This controller can have both bridges and panels connected to it. In order to describe panels properly in DT, pull in dsi-controller.yaml and disallow only unevaluatedProperties, because the panel node is optional. Include example binding with panel. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250904210147.186728-4-marek.vasut+renesas@mailbox.org
This commit is contained in:
committed by
Tomi Valkeinen
parent
c1a7cc00cd
commit
c376a69437
@@ -14,6 +14,9 @@ description: |
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R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
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R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
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to four data lanes.
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to four data lanes.
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allOf:
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- $ref: /schemas/display/dsi-controller.yaml#
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properties:
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properties:
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compatible:
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compatible:
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enum:
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enum:
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@@ -80,14 +83,14 @@ required:
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- resets
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- resets
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- ports
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- ports
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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examples:
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- |
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- |
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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#include <dt-bindings/power/r8a779a0-sysc.h>
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#include <dt-bindings/power/r8a779a0-sysc.h>
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dsi0: dsi-encoder@fed80000 {
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dsi@fed80000 {
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compatible = "renesas,r8a779a0-dsi-csi2-tx";
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compatible = "renesas,r8a779a0-dsi-csi2-tx";
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reg = <0xfed80000 0x10000>;
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reg = <0xfed80000 0x10000>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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@@ -117,4 +120,50 @@ examples:
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};
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};
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};
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};
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};
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};
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- |
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#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
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#include <dt-bindings/power/r8a779g0-sysc.h>
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dsi@fed80000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,r8a779g0-dsi-csi2-tx";
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reg = <0xfed80000 0x10000>;
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clocks = <&cpg CPG_MOD 415>,
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<&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
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<&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
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clock-names = "fck", "dsi", "pll";
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power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
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resets = <&cpg 415>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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dsi0port1_out: endpoint {
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remote-endpoint = <&panel_in>;
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data-lanes = <1 2>;
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};
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};
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};
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panel@0 {
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reg = <0>;
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compatible = "raspberrypi,dsi-7inch";
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port {
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panel_in: endpoint {
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remote-endpoint = <&dsi0port1_out>;
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};
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};
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};
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};
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...
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...
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