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ARM: dts: st: spear: split interrupts per cells
Each interrupt should be in its own cell. This is much more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20230730111536.98164-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
committed by
Arnd Bergmann
parent
8be4ee0ee0
commit
a3265be854
@@ -63,8 +63,8 @@
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compatible = "snps,designware-i2s";
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compatible = "snps,designware-i2s";
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reg = <0xb2400000 0x10000>;
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reg = <0xb2400000 0x10000>;
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interrupt-names = "play_irq";
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interrupt-names = "play_irq";
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interrupts = <0 98 0x4
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interrupts = <0 98 0x4>,
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0 99 0x4>;
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<0 99 0x4>;
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play;
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play;
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channel = <8>;
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channel = <8>;
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status = "disabled";
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status = "disabled";
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@@ -74,8 +74,8 @@
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compatible = "snps,designware-i2s";
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compatible = "snps,designware-i2s";
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reg = <0xb2000000 0x10000>;
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reg = <0xb2000000 0x10000>;
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interrupt-names = "record_irq";
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interrupt-names = "record_irq";
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interrupts = <0 100 0x4
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interrupts = <0 100 0x4>,
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0 101 0x4>;
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<0 101 0x4>;
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record;
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record;
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channel = <8>;
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channel = <8>;
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status = "disabled";
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status = "disabled";
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@@ -39,8 +39,8 @@
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pmu {
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pmu {
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compatible = "arm,cortex-a9-pmu";
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 6 0x04
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interrupts = <0 6 0x04>,
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0 7 0x04>;
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<0 7 0x04>;
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};
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};
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L2: cache-controller {
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L2: cache-controller {
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@@ -141,10 +141,10 @@
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0xb0820000 0x0010 /* NAND Base ADDR */
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0xb0820000 0x0010 /* NAND Base ADDR */
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0xb0810000 0x0010>; /* NAND Base CMD */
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0xb0810000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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interrupts = <0 20 0x4
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interrupts = <0 20 0x4>,
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0 21 0x4
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<0 21 0x4>,
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0 22 0x4
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<0 22 0x4>,
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0 23 0x4>;
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<0 23 0x4>;
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st,mode = <2>;
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st,mode = <2>;
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status = "disabled";
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status = "disabled";
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};
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};
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@@ -152,8 +152,8 @@
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gmac0: eth@e2000000 {
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gmac0: eth@e2000000 {
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compatible = "st,spear600-gmac";
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compatible = "st,spear600-gmac";
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reg = <0xe2000000 0x8000>;
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reg = <0xe2000000 0x8000>;
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interrupts = <0 33 0x4
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interrupts = <0 33 0x4>,
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0 34 0x4>;
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<0 34 0x4>;
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interrupt-names = "macirq", "eth_wake_irq";
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interrupt-names = "macirq", "eth_wake_irq";
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status = "disabled";
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status = "disabled";
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};
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};
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@@ -263,8 +263,8 @@
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compatible = "st,designware-i2s";
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compatible = "st,designware-i2s";
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reg = <0xe0180000 0x1000>;
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reg = <0xe0180000 0x1000>;
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interrupt-names = "play_irq", "record_irq";
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interrupt-names = "play_irq", "record_irq";
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interrupts = <0 10 0x4
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interrupts = <0 10 0x4>,
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0 11 0x4 >;
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<0 11 0x4>;
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status = "disabled";
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status = "disabled";
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};
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};
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@@ -272,8 +272,8 @@
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compatible = "st,designware-i2s";
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compatible = "st,designware-i2s";
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reg = <0xe0200000 0x1000>;
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reg = <0xe0200000 0x1000>;
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interrupt-names = "play_irq", "record_irq";
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interrupt-names = "play_irq", "record_irq";
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interrupts = <0 26 0x4
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interrupts = <0 26 0x4>,
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0 53 0x4>;
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<0 53 0x4>;
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status = "disabled";
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status = "disabled";
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};
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};
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