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arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528

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Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Jonas Karlman
2025-02-28 06:40:10 +00:00
committed by Heiko Stuebner
parent ac32ad07a9
commit a31fad19ae
2 changed files with 1479 additions and 0 deletions
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1397
arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi Normal file
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File diff suppressed because it is too large Load Diff

82
arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -4,8 +4,10 @@
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
/ {
@@ -16,6 +18,11 @@
#size-cells = <2>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -165,6 +172,11 @@
#reset-cells = <1>;
};
ioc_grf: syscon@ff540000 {
compatible = "rockchip,rk3528-ioc-grf", "syscon";
reg = <0x0 0xff540000 0x0 0x40000>;
};
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
@@ -251,5 +263,75 @@
reg-shift = <2>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@ff610000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff610000 0x0 0x200>;
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@ffaf0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xffaf0000 0x0 0x200>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@ffb00000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xffb00000 0x0 0x200>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 64 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@ffb10000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xffb10000 0x0 0x200>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 96 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@ffb20000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xffb20000 0x0 0x200>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 128 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
};
#include "rk3528-pinctrl.dtsi"