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drm/i915/wcl: C10 phy connected to port A and B

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WCL added a c10 phy connected to port B. PTL code is currently
restricting c10 to phy_a only.

PTL doesn't have a PHY connected to PORT B; as such,there will
never be a case where PTL uses PHY B.
WCL uses PORT A and B with the C10 PHY.Reusing the condition
for WCL and extending it for PORT B should not cause any issues
for PTL.

-v2: Reuse and extend PTL condition for WCL (Matt)

Bspec: 73944
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20250613193146.3549862-9-dnyaneshwar.bhadane@intel.com
This commit is contained in:
Dnyaneshwar Bhadane
2025-06-14 01:01:45 +05:30
committed by Matt Roper
parent 3d77a3280d
commit 9d10de78a3
1 changed files with 7 additions and 1 deletions
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8
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@@ -39,7 +39,13 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
if (display->platform.pantherlake && phy == PHY_A)
/* PTL doesn't have a PHY connected to PORT B; as such,
* there will never be a case where PTL uses PHY B.
* WCL uses PORT A and B with the C10 PHY.
* Reusing the condition for WCL and extending it for PORT B
* should not cause any issues for PTL.
*/
if (display->platform.pantherlake && phy < PHY_C)
return true;
if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)