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drm/amdgpu: adapt reset function for pmfw eeprom

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adapt reset function for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gangliang Xie
2025-09-04 18:04:33 +08:00
committed by Alex Deucher
parent f903b85ed0
commit 9ce015e5fd
1 changed files with 36 additions and 25 deletions
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61
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
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@@ -444,40 +444,51 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
u32 erase_res = 0;
u8 csum; u8 csum;
int res; int res;
mutex_lock(&control->ras_tbl_mutex); mutex_lock(&control->ras_tbl_mutex);
hdr->header = RAS_TABLE_HDR_VAL; if (!amdgpu_ras_smu_eeprom_supported(adev)) {
amdgpu_ras_set_eeprom_table_version(control); hdr->header = RAS_TABLE_HDR_VAL;
amdgpu_ras_set_eeprom_table_version(control);
if (hdr->version >= RAS_TABLE_VER_V2_1) { if (hdr->version >= RAS_TABLE_VER_V2_1) {
hdr->first_rec_offset = RAS_RECORD_START_V2_1; hdr->first_rec_offset = RAS_RECORD_START_V2_1;
hdr->tbl_size = RAS_TABLE_HEADER_SIZE + hdr->tbl_size = RAS_TABLE_HEADER_SIZE +
RAS_TABLE_V2_1_INFO_SIZE; RAS_TABLE_V2_1_INFO_SIZE;
rai->rma_status = GPU_HEALTH_USABLE; rai->rma_status = GPU_HEALTH_USABLE;
/** /**
* GPU health represented as a percentage. * GPU health represented as a percentage.
* 0 means worst health, 100 means fully health. * 0 means worst health, 100 means fully health.
*/ */
rai->health_percent = 100; rai->health_percent = 100;
/* ecc_page_threshold = 0 means disable bad page retirement */ /* ecc_page_threshold = 0 means disable bad page retirement */
rai->ecc_page_threshold = con->bad_page_cnt_threshold; rai->ecc_page_threshold = con->bad_page_cnt_threshold;
} else {
hdr->first_rec_offset = RAS_RECORD_START;
hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
}
csum = __calc_hdr_byte_sum(control);
if (hdr->version >= RAS_TABLE_VER_V2_1)
csum += __calc_ras_info_byte_sum(control);
csum = -csum;
hdr->checksum = csum;
res = __write_table_header(control);
if (!res && hdr->version > RAS_TABLE_VER_V1)
res = __write_table_ras_info(control);
} else { } else {
hdr->first_rec_offset = RAS_RECORD_START; res = amdgpu_ras_smu_erase_ras_table(adev, &erase_res);
hdr->tbl_size = RAS_TABLE_HEADER_SIZE; if (res || erase_res) {
dev_warn(adev->dev, "RAS EEPROM reset failed, res:%d result:%d",
res, erase_res);
if (!res)
res = -EIO;
}
} }
csum = __calc_hdr_byte_sum(control);
if (hdr->version >= RAS_TABLE_VER_V2_1)
csum += __calc_ras_info_byte_sum(control);
csum = -csum;
hdr->checksum = csum;
res = __write_table_header(control);
if (!res && hdr->version > RAS_TABLE_VER_V1)
res = __write_table_ras_info(control);
control->ras_num_recs = 0; control->ras_num_recs = 0;
control->ras_num_bad_pages = 0; control->ras_num_bad_pages = 0;
control->ras_num_mca_recs = 0; control->ras_num_mca_recs = 0;