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mt76: mt7915: update mac timing settings
1. EIFS has been divided into OFDM/CCK fields after 11ax generation. 2. For 5G/6G SIFS setting, hardware counts extra 6us for OFDM. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@@ -1572,17 +1572,12 @@ void mt7915_mac_set_timing(struct mt7915_phy *phy)
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
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u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
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u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
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int sifs, offset;
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int offset;
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bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
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bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
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if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
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if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
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return;
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return;
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if (is_5ghz)
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sifs = 16;
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else
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sifs = 10;
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if (ext_phy) {
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if (ext_phy) {
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coverage_class = max_t(s16, dev->phy.coverage_class,
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coverage_class = max_t(s16, dev->phy.coverage_class,
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coverage_class);
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coverage_class);
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@@ -1604,11 +1599,14 @@ void mt7915_mac_set_timing(struct mt7915_phy *phy)
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mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset);
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mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset);
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mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset);
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mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset);
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mt76_wr(dev, MT_TMAC_ICR0(ext_phy),
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mt76_wr(dev, MT_TMAC_ICR0(ext_phy),
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FIELD_PREP(MT_IFS_EIFS, 360) |
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FIELD_PREP(MT_IFS_EIFS_OFDM, is_5ghz ? 84 : 78) |
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FIELD_PREP(MT_IFS_RIFS, 2) |
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FIELD_PREP(MT_IFS_RIFS, 2) |
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FIELD_PREP(MT_IFS_SIFS, sifs) |
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FIELD_PREP(MT_IFS_SIFS, 10) |
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FIELD_PREP(MT_IFS_SLOT, phy->slottime));
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FIELD_PREP(MT_IFS_SLOT, phy->slottime));
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mt76_wr(dev, MT_TMAC_ICR1(ext_phy),
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FIELD_PREP(MT_IFS_EIFS_CCK, 314));
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if (phy->slottime < 20 || is_5ghz)
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if (phy->slottime < 20 || is_5ghz)
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val = MT7915_CFEND_RATE_DEFAULT;
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val = MT7915_CFEND_RATE_DEFAULT;
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else
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else
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@@ -72,11 +72,14 @@
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#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
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#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
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#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
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#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
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#define MT_IFS_EIFS GENMASK(8, 0)
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#define MT_IFS_EIFS_OFDM GENMASK(8, 0)
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#define MT_IFS_RIFS GENMASK(14, 10)
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#define MT_IFS_RIFS GENMASK(14, 10)
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#define MT_IFS_SIFS GENMASK(22, 16)
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#define MT_IFS_SIFS GENMASK(22, 16)
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#define MT_IFS_SLOT GENMASK(30, 24)
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#define MT_IFS_SLOT GENMASK(30, 24)
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#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x0b4)
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#define MT_IFS_EIFS_CCK GENMASK(8, 0)
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#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
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#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
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#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
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#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
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#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
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#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
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