From c6d0c9cae7eea0a029b5961d896c016d1467d03d Mon Sep 17 00:00:00 2001 From: Vivek BalachandharTN Date: Sat, 4 Oct 2025 22:21:28 +0000 Subject: [PATCH 001/304] w1: use sysfs_emit() in sysfs show() callbacks Replace sprintf in sysfs show() paths with sysfs_emit(), per Documentation/filesystems/sysfs.rst. Signed-off-by: Vivek BalachandharTN Signed-off-by: Krzysztof Kozlowski --- drivers/w1/w1.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c index d0474a0532ec..002d2639aa12 100644 --- a/drivers/w1/w1.c +++ b/drivers/w1/w1.c @@ -86,7 +86,7 @@ static ssize_t name_show(struct device *dev, struct device_attribute *attr, char { struct w1_slave *sl = dev_to_w1_slave(dev); - return sprintf(buf, "%s\n", sl->name); + return sysfs_emit(buf, "%s\n", sl->name); } static DEVICE_ATTR_RO(name); @@ -207,7 +207,7 @@ static ssize_t w1_master_attribute_show_name(struct device *dev, struct device_a ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "%s\n", md->name); + count = sysfs_emit(buf, "%s\n", md->name); mutex_unlock(&md->mutex); return count; @@ -243,7 +243,7 @@ static ssize_t w1_master_attribute_show_search(struct device *dev, ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "%d\n", md->search_count); + count = sysfs_emit(buf, "%d\n", md->search_count); mutex_unlock(&md->mutex); return count; @@ -276,7 +276,7 @@ static ssize_t w1_master_attribute_show_pullup(struct device *dev, ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "%d\n", md->enable_pullup); + count = sysfs_emit(buf, "%d\n", md->enable_pullup); mutex_unlock(&md->mutex); return count; @@ -288,20 +288,20 @@ static ssize_t w1_master_attribute_show_pointer(struct device *dev, struct devic ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "0x%p\n", md->bus_master); + count = sysfs_emit(buf, "0x%p\n", md->bus_master); mutex_unlock(&md->mutex); return count; } static ssize_t w1_master_attribute_show_timeout(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", w1_timeout); + return sysfs_emit(buf, "%d\n", w1_timeout); } static ssize_t w1_master_attribute_show_timeout_us(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", w1_timeout_us); + return sysfs_emit(buf, "%d\n", w1_timeout_us); } static ssize_t w1_master_attribute_store_max_slave_count(struct device *dev, @@ -328,7 +328,7 @@ static ssize_t w1_master_attribute_show_max_slave_count(struct device *dev, stru ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "%d\n", md->max_slave_count); + count = sysfs_emit(buf, "%d\n", md->max_slave_count); mutex_unlock(&md->mutex); return count; } @@ -339,7 +339,7 @@ static ssize_t w1_master_attribute_show_attempts(struct device *dev, struct devi ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "%lu\n", md->attempts); + count = sysfs_emit(buf, "%lu\n", md->attempts); mutex_unlock(&md->mutex); return count; } @@ -350,7 +350,7 @@ static ssize_t w1_master_attribute_show_slave_count(struct device *dev, struct d ssize_t count; mutex_lock(&md->mutex); - count = sprintf(buf, "%d\n", md->slave_count); + count = sysfs_emit(buf, "%d\n", md->slave_count); mutex_unlock(&md->mutex); return count; } From f3c6353d801a9826e234ad477af08b09a98d888b Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Thu, 9 Oct 2025 19:45:12 +0200 Subject: [PATCH 002/304] w1: ds28e17: Replace deprecated strcpy + strcat in w1_f19_add_slave strcpy() is deprecated and using strcat() is discouraged. Replace them with scnprintf(). No functional changes. Link: https://github.com/KSPP/linux/issues/88 Signed-off-by: Thorsten Blum Signed-off-by: Krzysztof Kozlowski --- drivers/w1/slaves/w1_ds28e17.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/w1/slaves/w1_ds28e17.c b/drivers/w1/slaves/w1_ds28e17.c index 5738cbce1a37..e53bc41bde3c 100644 --- a/drivers/w1/slaves/w1_ds28e17.c +++ b/drivers/w1/slaves/w1_ds28e17.c @@ -719,8 +719,8 @@ static int w1_f19_add_slave(struct w1_slave *sl) data->adapter.owner = THIS_MODULE; data->adapter.algo = &w1_f19_i2c_algorithm; data->adapter.algo_data = sl; - strcpy(data->adapter.name, "w1-"); - strcat(data->adapter.name, sl->name); + scnprintf(data->adapter.name, sizeof(data->adapter.name), "w1-%s", + sl->name); data->adapter.dev.parent = &sl->dev; data->adapter.quirks = &w1_f19_i2c_adapter_quirks; From 5f31df5075a7f8967401ded5d54be04f62b172a2 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 17 Sep 2025 18:03:17 -0500 Subject: [PATCH 003/304] iio: adc: ad7124: add debugfs to disable single cycle mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a boolean debugfs attribute to allow disabling the SINGLE_CYCLE bit in the FILTER registers. This causes data to be read on every conversion instead of doing the usual 3 or 4 conversions per sample (depending on the filter). This is only needed for very specific use cases, such as validating the performance of the ADC. So we just expose this feature through debugfs for the rare cases where it is needed by people who really know what they are doing. Signed-off-by: David Lechner Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 910b40393f77..ad6edbc792db 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -223,6 +224,7 @@ struct ad7124_state { */ unsigned int gain_default; DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); + bool enable_single_cycle; }; static const struct ad7124_chip_info ad7124_4_chip_info = { @@ -560,13 +562,15 @@ static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_co * sampling frequency even when only one channel is enabled in a * buffered read. If it was not set, the N in ad7124_set_channel_odr() * would be 1 and we would get a faster sampling frequency than what - * was requested. + * was requested. It may only be disabled through debugfs for testing + * purposes. */ return ad_sd_write_reg(&st->sd, AD7124_FILTER(cfg->cfg_slot), 3, FIELD_PREP(AD7124_FILTER_FILTER, filter) | FIELD_PREP(AD7124_FILTER_REJ60, rej60) | FIELD_PREP(AD7124_FILTER_POST_FILTER, post) | - AD7124_FILTER_SINGLE_CYCLE | + FIELD_PREP(AD7124_FILTER_SINGLE_CYCLE, + st->enable_single_cycle) | FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits)); } @@ -1609,6 +1613,18 @@ static void ad7124_reg_disable(void *r) regulator_disable(r); } +static void ad7124_debugfs_init(struct iio_dev *indio_dev) +{ + struct dentry *dentry = iio_get_debugfs_dentry(indio_dev); + struct ad7124_state *st = iio_priv(indio_dev); + + if (!IS_ENABLED(CONFIG_DEBUG_FS)) + return; + + debugfs_create_bool("enable_single_cycle", 0644, dentry, + &st->enable_single_cycle); +} + static int ad7124_probe(struct spi_device *spi) { const struct ad7124_chip_info *info; @@ -1629,6 +1645,9 @@ static int ad7124_probe(struct spi_device *spi) st->chip_info = info; + /* Only disabled for debug/testing purposes. */ + st->enable_single_cycle = true; + indio_dev->name = st->chip_info->name; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &ad7124_info; @@ -1686,6 +1705,8 @@ static int ad7124_probe(struct spi_device *spi) if (ret < 0) return dev_err_probe(dev, ret, "Failed to register iio device\n"); + ad7124_debugfs_init(indio_dev); + return 0; } From 0b02af932b7e7777074d78203e8e336a9dc30400 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 17 Sep 2025 15:39:22 -0500 Subject: [PATCH 004/304] iio: adc: ad7124: inline ad7124_enable_channel() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Inline ad7124_enable_channel() at the only call site. This simplifies the code by avoiding a bit of extra indirection. ch->nr is replaced by address as that is the same value and avoids more indirection. Signed-off-by: David Lechner Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index ad6edbc792db..f4f445e28630 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -631,14 +631,6 @@ static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_con return ad7124_write_config(st, cfg, free_cfg_slot); } -static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch) -{ - ch->cfg.live = true; - return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain | - FIELD_PREP(AD7124_CHANNEL_SETUP, ch->cfg.cfg_slot) | - AD7124_CHANNEL_ENABLE); -} - static int ad7124_prepare_read(struct ad7124_state *st, int address) { struct ad7124_channel_config *cfg = &st->channels[address].cfg; @@ -658,7 +650,11 @@ static int ad7124_prepare_read(struct ad7124_state *st, int address) } /* point channel to the config slot and enable */ - return ad7124_enable_channel(st, &st->channels[address]); + cfg->live = true; + return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(address), 2, + st->channels[address].ain | + FIELD_PREP(AD7124_CHANNEL_SETUP, cfg->cfg_slot) | + AD7124_CHANNEL_ENABLE); } static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) @@ -1559,7 +1555,7 @@ static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio * after full-scale calibration because the next * ad_sd_calibrate() call overwrites this via * ad_sigma_delta_set_channel() -> ad7124_set_channel() - * ... -> ad7124_enable_channel(). + * -> ad7124_prepare_read(). */ ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(st->channels[i].cfg.cfg_slot), 3, &st->channels[i].cfg.calibration_gain); From 4a579c175aad6d1b5d2288f4db366261c5c4f60b Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 17 Sep 2025 15:39:23 -0500 Subject: [PATCH 005/304] iio: adc: ad7124: remove unused `nr` field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unused `nr` field from the `ad7124_channel` struct. There are no more users of this field (it is only assigned to but never read) so can be removed. Signed-off-by: David Lechner Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index f4f445e28630..950abdb75e6d 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -200,7 +200,6 @@ struct ad7124_channel_config { }; struct ad7124_channel { - unsigned int nr; struct ad7124_channel_config cfg; unsigned int ain; unsigned int slot; @@ -1305,7 +1304,6 @@ static int ad7124_parse_channel_config(struct iio_dev *indio_dev, return dev_err_probe(dev, -EINVAL, "diff-channels property of %pfwP contains invalid data\n", child); - st->channels[channel].nr = channel; st->channels[channel].ain = FIELD_PREP(AD7124_CHANNEL_AINP, ain[0]) | FIELD_PREP(AD7124_CHANNEL_AINM, ain[1]); @@ -1332,7 +1330,6 @@ static int ad7124_parse_channel_config(struct iio_dev *indio_dev, if (num_channels < AD7124_MAX_CHANNELS) { st->channels[num_channels] = (struct ad7124_channel) { - .nr = num_channels, .ain = FIELD_PREP(AD7124_CHANNEL_AINP, AD7124_CHANNEL_AINx_TEMPSENSOR) | FIELD_PREP(AD7124_CHANNEL_AINM, AD7124_CHANNEL_AINx_AVSS), .cfg = { From b8579b7c6e484f399f14bca2a9d2ca83a3c9b483 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 17 Sep 2025 09:17:23 -0500 Subject: [PATCH 006/304] iio: adc: ad7124: use AD7124_MAX_CHANNELS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use AD7124_MAX_CHANNELS macro instead of hardcoding 16 in ad7124_disable_all(). We already have the macro, so we should use it. Signed-off-by: David Lechner Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 950abdb75e6d..b13a7824ae01 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -708,7 +708,7 @@ static int ad7124_disable_all(struct ad_sigma_delta *sd) int ret; int i; - for (i = 0; i < 16; i++) { + for (i = 0; i < AD7124_MAX_CHANNELS; i++) { ret = ad7124_disable_one(sd, i); if (ret < 0) return ret; From 0b028373f87a354ad5f7665034f71007b8f3d9e2 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 17 Sep 2025 10:22:30 -0500 Subject: [PATCH 007/304] iio: adc: ad7124: use devm_mutex_init() Use devm_mutex_init() to initialize the mutex to handle automatically freeing in debug builds. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index b13a7824ae01..dff935360e6d 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -1486,7 +1486,10 @@ static int ad7124_setup(struct ad7124_state *st) st->adc_control &= ~AD7124_ADC_CONTROL_MODE; st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, AD_SD_MODE_IDLE); - mutex_init(&st->cfgs_lock); + ret = devm_mutex_init(dev, &st->cfgs_lock); + if (ret) + return ret; + INIT_KFIFO(st->live_cfgs_fifo); for (i = 0; i < st->num_channels; i++) { struct ad7124_channel_config *cfg = &st->channels[i].cfg; From 97c8b5dedb407d389e7a947b8c037087a919aadc Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:39:39 -0500 Subject: [PATCH 008/304] iio: adc: ad7124: remove __ad7124_set_channel() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove __ad7124_set_channel() wrapper function. This just added an unnecessary layer of indirection with an extra call to container_of(). Signed-off-by: David Lechner Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index dff935360e6d..374e39736584 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -656,20 +656,13 @@ static int ad7124_prepare_read(struct ad7124_state *st, int address) AD7124_CHANNEL_ENABLE); } -static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) -{ - struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); - - return ad7124_prepare_read(st, channel); -} - static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) { struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); int ret; mutex_lock(&st->cfgs_lock); - ret = __ad7124_set_channel(sd, channel); + ret = ad7124_prepare_read(st, channel); mutex_unlock(&st->cfgs_lock); return ret; @@ -964,7 +957,7 @@ static int ad7124_update_scan_mode(struct iio_dev *indio_dev, for (i = 0; i < st->num_channels; i++) { bit_set = test_bit(i, scan_mask); if (bit_set) - ret = __ad7124_set_channel(&st->sd, i); + ret = ad7124_prepare_read(st, i); else ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_ENABLE, 0, 2); From 6b166e815cdcf2ddb755ca5311a5343635ff9610 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:51 -0500 Subject: [PATCH 009/304] iio: buffer: document iio_push_to_buffers_with_ts_unaligned() may sleep Add Context: documentation comment that iio_push_to_buffers_with_ts_unaligned() may sleep because it calls devm_krealloc(). Also document Return: value while here. Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-buffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index a80f7cc25a27..7da43a1f2f75 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -2401,6 +2401,9 @@ EXPORT_SYMBOL_GPL(iio_push_to_buffers); * not require space for the timestamp, or 8 byte alignment of data. * It does however require an allocation on first call and additional * copies on all calls, so should be avoided if possible. + * + * Context: May sleep. + * Return: 0 on success, negative error code on failure. */ int iio_push_to_buffers_with_ts_unaligned(struct iio_dev *indio_dev, const void *data, From a8c8aad411554755ab59621dc6961db8a4c8af7a Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:52 -0500 Subject: [PATCH 010/304] iio: buffer: iio_push_to_buffers_with_ts_unaligned() might_sleep() Call might_sleep() in iio_push_to_buffers_with_ts_unaligned() since it can allocate memory, which may sleep. Suggested-by: Andy Shevchenko Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index 7da43a1f2f75..5599fa37b698 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -2412,6 +2412,8 @@ int iio_push_to_buffers_with_ts_unaligned(struct iio_dev *indio_dev, { struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); + might_sleep(); + /* * Conservative estimate - we can always safely copy the minimum * of either the data provided or the length of the destination buffer. From 536bf30d282a6b2f676c6106587f0e1946449aca Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:53 -0500 Subject: [PATCH 011/304] iio: buffer: document iio_push_to_buffers_with_ts() Document the iio_push_to_buffers_with_ts() function. This is copied and slightly cleaned up from iio_push_to_buffers_with_timestamp(). Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- include/linux/iio/buffer.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/linux/iio/buffer.h b/include/linux/iio/buffer.h index 5c84ec4a9810..e46b818981aa 100644 --- a/include/linux/iio/buffer.h +++ b/include/linux/iio/buffer.h @@ -45,6 +45,22 @@ static inline int iio_push_to_buffers_with_timestamp(struct iio_dev *indio_dev, return iio_push_to_buffers(indio_dev, data); } +/** + * iio_push_to_buffers_with_ts() - push data and timestamp to buffers + * @indio_dev: iio_dev structure for device. + * @data: Pointer to sample data buffer. + * @data_total_len: The size of @data in bytes. + * @timestamp: Timestamp for the sample data. + * + * Pushes data to the IIO device's buffers. If timestamps are enabled for the + * device the function will store the supplied timestamp as the last element in + * the sample data buffer before pushing it to the device buffers. The sample + * data buffer needs to be large enough to hold the additional timestamp + * (usually the buffer should be at least indio->scan_bytes bytes large). + * + * Context: Any context. + * Return: 0 on success, a negative error code otherwise. + */ static inline int iio_push_to_buffers_with_ts(struct iio_dev *indio_dev, void *data, size_t data_total_len, s64 timestamp) From 4992ce003b76ee1629ad4e7332a49ea2619e7523 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:54 -0500 Subject: [PATCH 012/304] iio: buffer: deprecated iio_push_to_buffers_with_timestamp() Replace the documentation of iio_push_to_buffers_with_timestamp() with a deprecation notice pointing to the preferred alternative. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- include/linux/iio/buffer.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/linux/iio/buffer.h b/include/linux/iio/buffer.h index e46b818981aa..d37f82678f71 100644 --- a/include/linux/iio/buffer.h +++ b/include/linux/iio/buffer.h @@ -26,11 +26,7 @@ int iio_pop_from_buffer(struct iio_buffer *buffer, void *data); * @data: sample data * @timestamp: timestamp for the sample data * - * Pushes data to the IIO device's buffers. If timestamps are enabled for the - * device the function will store the supplied timestamp as the last element in - * the sample data buffer before pushing it to the device buffers. The sample - * data buffer needs to be large enough to hold the additional timestamp - * (usually the buffer should be indio->scan_bytes bytes large). + * DEPRECATED: Use iio_push_to_buffers_with_ts() instead. * * Returns 0 on success, a negative error code otherwise. */ From d87b03ced9e989a516cc000e1e65f4eb4d6d46aa Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:55 -0500 Subject: [PATCH 013/304] iio: buffer: document iio_push_to_buffers() calling context Document that iio_push_to_buffers() can be called from any context. Also document the Return: value while here. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-buffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index 5599fa37b698..f1448ae1b843 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -2372,6 +2372,9 @@ static int iio_push_to_buffer(struct iio_buffer *buffer, const void *data) * iio_push_to_buffers() - push to a registered buffer. * @indio_dev: iio_dev structure for device. * @data: Full scan. + * + * Context: Any context. + * Return: 0 on success, negative error code on failure. */ int iio_push_to_buffers(struct iio_dev *indio_dev, const void *data) { From 748ed9fc8596015e7e136877465919b89c7d08d6 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:56 -0500 Subject: [PATCH 014/304] iio: buffer: document store_to() callback may be called in any context Document that the struct iio_buffer_access_funcs.store_to() callback must be safe to call from any context since it is called from iio_push_to_buffer() which may be called from any context. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- include/linux/iio/buffer_impl.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/iio/buffer_impl.h b/include/linux/iio/buffer_impl.h index e72552e026f3..0daff9ff20ce 100644 --- a/include/linux/iio/buffer_impl.h +++ b/include/linux/iio/buffer_impl.h @@ -24,7 +24,8 @@ struct sg_table; /** * struct iio_buffer_access_funcs - access functions for buffers. - * @store_to: actually store stuff to the buffer + * @store_to: actually store stuff to the buffer - must be safe to + * call from any context (e.g. must not sleep). * @read: try to get a specified number of bytes (must exist) * @data_available: indicates how much data is available for reading from * the buffer. From 592ae0ccecfac9af8f67444cab11cbb11770f571 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 16 Sep 2025 16:02:57 -0500 Subject: [PATCH 015/304] iio: buffer: document that buffer callback must be context safe Document that the callback registered with iio_channel_get_all_cb() must be safe to call from any context since it is called from by iio_push_to_buffer() which can be called in any context. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/buffer/industrialio-buffer-cb.c | 1 + include/linux/iio/consumer.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iio/buffer/industrialio-buffer-cb.c b/drivers/iio/buffer/industrialio-buffer-cb.c index 3e27385069ed..f4ebff968493 100644 --- a/drivers/iio/buffer/industrialio-buffer-cb.c +++ b/drivers/iio/buffer/industrialio-buffer-cb.c @@ -13,6 +13,7 @@ struct iio_cb_buffer { struct iio_buffer buffer; + /* Must be safe to call from any context (e.g. must not sleep). */ int (*cb)(const void *data, void *private); void *private; struct iio_channel *channels; diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h index a38b277c2c02..5039558267e4 100644 --- a/include/linux/iio/consumer.h +++ b/include/linux/iio/consumer.h @@ -131,7 +131,8 @@ struct iio_cb_buffer; /** * iio_channel_get_all_cb() - register callback for triggered capture * @dev: Pointer to client device. - * @cb: Callback function. + * @cb: Callback function. Must be safe to call from any context + * (e.g. must not sleep). * @private: Private data passed to callback. * * NB right now we have no ability to mux data from multiple devices. From b8af83efd67c2d36142bb411ff5218f02eaf0deb Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sat, 13 Sep 2025 18:39:22 +0300 Subject: [PATCH 016/304] dt-bindings: iio: accel: bosch,bma220 cleanup typo Cleanup typo present in the title. Acked-by: Krzysztof Kozlowski Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml index ec643de031a3..da047258aca3 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/accel/bosch,bma220.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bosch BMA220 Trixial Acceleration Sensor +title: Bosch BMA220 Triaxial Acceleration Sensor maintainers: - Jonathan Cameron From b8719569a0971f971a117c67c462360d7bbc0fcc Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sat, 13 Sep 2025 18:39:23 +0300 Subject: [PATCH 017/304] dt-bindings: iio: accel: bosch,bma220 setup SPI clock mode Assert CPOL for a high-idle clock signal and CPHA for sampling on the trailing (rising) edge. Quoting from the datasheet: "During the transitions on CSB, SCK must be high. SDI and SDO are driven at the falling edge of SCK and should be captured at the rising edge of SCK." The sensor does not function with the default SPI clock mode. Fixes: 7dbd479425d2 ("dt-bindings:iio:accel:bosch,bma220 device tree binding documentation") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/accel/bosch,bma220.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml index da047258aca3..0e27ec74065a 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml @@ -20,6 +20,9 @@ properties: interrupts: maxItems: 1 + spi-cpha: true + spi-cpol: true + vdda-supply: true vddd-supply: true vddio-supply: true @@ -44,6 +47,8 @@ examples: compatible = "bosch,bma220"; reg = <0>; spi-max-frequency = <2500000>; + spi-cpol; + spi-cpha; interrupt-parent = <&gpio0>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; From 92c7ae3486143a44ecc974531704b905d22a784a Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sat, 13 Sep 2025 18:39:24 +0300 Subject: [PATCH 018/304] dt-bindings: iio: accel: bosch,bma220 set irq type in example block Set the interrupt type to rising edge within the example block in order to match the new driver. The entry that got replaced was not in use by the original driver. Signed-off-by: Petre Rodan Acked-by: Krzysztof Kozlowski Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml index 0e27ec74065a..8c820c27f781 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml @@ -50,7 +50,7 @@ examples: spi-cpol; spi-cpha; interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; }; }; ... From a58b20aa3f890a4fe3e2ad38649359997161dd91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Fri, 19 Sep 2025 07:44:08 +0000 Subject: [PATCH 019/304] bus: mhi: ep: Make mhi_ep_bus_type const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the mhi_ep_bus_type to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Signed-off-by: Manivannan Sadhasivam Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250919074408.868220-1-abarnas@google.com --- drivers/bus/mhi/ep/internal.h | 2 +- drivers/bus/mhi/ep/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/bus/mhi/ep/internal.h b/drivers/bus/mhi/ep/internal.h index 577965f95fda..512da7482acc 100644 --- a/drivers/bus/mhi/ep/internal.h +++ b/drivers/bus/mhi/ep/internal.h @@ -11,7 +11,7 @@ #include "../common.h" -extern struct bus_type mhi_ep_bus_type; +extern const struct bus_type mhi_ep_bus_type; #define MHI_REG_OFFSET 0x100 #define BHI_REG_OFFSET 0x200 diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index cdea24e92919..86e003bc44e0 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -1703,7 +1703,7 @@ static int mhi_ep_match(struct device *dev, const struct device_driver *drv) return 0; }; -struct bus_type mhi_ep_bus_type = { +const struct bus_type mhi_ep_bus_type = { .name = "mhi_ep", .dev_name = "mhi_ep", .match = mhi_ep_match, From 6eaee77923ddf04beedb832c06f983679586361c Mon Sep 17 00:00:00 2001 From: Daniele Palmas Date: Wed, 15 Oct 2025 12:20:59 +0200 Subject: [PATCH 020/304] bus: mhi: host: pci_generic: Add Telit FE990B40 modem support Add SDX72 based modem Telit FE990B40, reusing FN920C04 configuration. 01:00.0 Unassigned class [ff00]: Qualcomm Device 0309 Subsystem: Device 1c5d:2025 Signed-off-by: Daniele Palmas Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251015102059.1781001-1-dnlplm@gmail.com --- drivers/bus/mhi/host/pci_generic.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index b188bbf7de04..3d8c9729fcfc 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -877,6 +877,16 @@ static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = { .edl_trigger = true, }; +static const struct mhi_pci_dev_info mhi_telit_fe990b40_info = { + .name = "telit-fe990b40", + .config = &modem_telit_fn920c04_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .sideband_wake = false, + .mru_default = 32768, + .edl_trigger = true, +}; + static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { .name = "netprisma-lcur57", .edl = "qcom/prog_firehose_sdx24.mbn", @@ -933,6 +943,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* Telit FN990B40 (sdx72) */ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a), .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info }, + /* Telit FE990B40 (sdx72) */ + { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x2025), + .driver_data = (kernel_ulong_t) &mhi_telit_fe990b40_info }, { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, /* QDU100, x100-DU */ From 3c2a24f7e807fda3078e3f87839b09c5ce93c90b Mon Sep 17 00:00:00 2001 From: Gustavo Silva Date: Tue, 16 Sep 2025 20:38:23 -0300 Subject: [PATCH 021/304] iio: imu: bmi270: add support for motion events Any-motion event can be enabled on a per-axis basis and triggers a combined event when motion is detected on any axis. No-motion event is triggered if the rate of change on all axes falls below a specified threshold for a configurable duration. A fake channel is used to report this event. Threshold and duration can be configured from userspace. Signed-off-by: Gustavo Silva Signed-off-by: Jonathan Cameron --- drivers/iio/imu/bmi270/bmi270_core.c | 381 +++++++++++++++++++++++++-- 1 file changed, 361 insertions(+), 20 deletions(-) diff --git a/drivers/iio/imu/bmi270/bmi270_core.c b/drivers/iio/imu/bmi270/bmi270_core.c index 519f1c9d466d..2ad230788532 100644 --- a/drivers/iio/imu/bmi270/bmi270_core.c +++ b/drivers/iio/imu/bmi270/bmi270_core.c @@ -31,6 +31,8 @@ #define BMI270_INT_STATUS_0_REG 0x1c #define BMI270_INT_STATUS_0_STEP_CNT_MSK BIT(1) +#define BMI270_INT_STATUS_0_NOMOTION_MSK BIT(5) +#define BMI270_INT_STATUS_0_MOTION_MSK BIT(6) #define BMI270_INT_STATUS_1_REG 0x1d #define BMI270_INT_STATUS_1_ACC_GYR_DRDY_MSK GENMASK(7, 6) @@ -81,6 +83,8 @@ #define BMI270_INT1_MAP_FEAT_REG 0x56 #define BMI270_INT2_MAP_FEAT_REG 0x57 #define BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK BIT(1) +#define BMI270_INT_MAP_FEAT_NOMOTION_MSK BIT(5) +#define BMI270_INT_MAP_FEAT_ANYMOTION_MSK BIT(6) #define BMI270_INT_MAP_DATA_REG 0x58 #define BMI270_INT_MAP_DATA_DRDY_INT1_MSK BIT(2) @@ -106,6 +110,25 @@ #define BMI270_STEP_SC26_RST_CNT_MSK BIT(10) #define BMI270_STEP_SC26_EN_CNT_MSK BIT(12) +#define BMI270_FEAT_MOTION_DURATION_MSK GENMASK(12, 0) +#define BMI270_FEAT_MOTION_X_EN_MSK BIT(13) +#define BMI270_FEAT_MOTION_Y_EN_MSK BIT(14) +#define BMI270_FEAT_MOTION_Z_EN_MSK BIT(15) +#define BMI270_FEAT_MOTION_XYZ_EN_MSK GENMASK(15, 13) +#define BMI270_FEAT_MOTION_THRESHOLD_MSK GENMASK(10, 0) +#define BMI270_FEAT_MOTION_OUT_CONF_MSK GENMASK(14, 11) +#define BMI270_FEAT_MOTION_ENABLE_MSK BIT(15) + +#define BMI270_MOTION_XYZ_MSK GENMASK(2, 0) + +/* See pages 92 and 93 of the datasheet */ +#define BMI270_MOTION_THRES_FULL_SCALE GENMASK(10, 0) +#define BMI270_MOTION_DURAT_SCALE 50 +#define BMI270_MOTION_DURAT_MAX 162 + +/* 9.81 * 1000000 m/s^2 */ +#define BMI270_G_MICRO_M_S_2 9810000 + /* See datasheet section 4.6.14, Temperature Sensor */ #define BMI270_TEMP_OFFSET 11776 #define BMI270_TEMP_SCALE 1953125 @@ -114,6 +137,11 @@ #define BMI270_STEP_COUNTER_FACTOR 20 #define BMI270_STEP_COUNTER_MAX 20460 +#define BMI270_INT_MICRO_TO_RAW(val, val2, scale) \ + ((val) * (scale) + ((val2) * (scale)) / MEGA) +#define BMI270_RAW_TO_MICRO(raw, scale) \ + ((((raw) % (scale)) * MEGA) / scale) + #define BMI260_INIT_DATA_FILE "bmi260-init-data.fw" #define BMI270_INIT_DATA_FILE "bmi270-init-data.fw" @@ -309,6 +337,13 @@ static const struct bmi270_odr_item bmi270_odr_table[] = { }; enum bmi270_feature_reg_id { + /* Page 1 registers */ + BMI270_ANYMO1_REG, + BMI270_ANYMO2_REG, + /* Page 2 registers */ + BMI270_NOMO1_REG, + BMI270_NOMO2_REG, + /* Page 6 registers */ BMI270_SC_26_REG, }; @@ -318,6 +353,22 @@ struct bmi270_feature_reg { }; static const struct bmi270_feature_reg bmi270_feature_regs[] = { + [BMI270_ANYMO1_REG] = { + .page = 1, + .addr = 0x3c, + }, + [BMI270_ANYMO2_REG] = { + .page = 1, + .addr = 0x3e, + }, + [BMI270_NOMO1_REG] = { + .page = 2, + .addr = 0x30, + }, + [BMI270_NOMO2_REG] = { + .page = 2, + .addr = 0x32, + }, [BMI270_SC_26_REG] = { .page = 6, .addr = 0x32, @@ -439,6 +490,121 @@ static int bmi270_step_wtrmrk_en(struct bmi270_data *data, bool state) state)); } +static int bmi270_motion_reg(enum iio_event_type type, enum iio_event_info info) +{ + switch (info) { + case IIO_EV_INFO_PERIOD: + switch (type) { + case IIO_EV_TYPE_MAG_ADAPTIVE: + return BMI270_ANYMO1_REG; + case IIO_EV_TYPE_ROC: + return BMI270_NOMO1_REG; + default: + return -EINVAL; + } + case IIO_EV_INFO_VALUE: + switch (type) { + case IIO_EV_TYPE_MAG_ADAPTIVE: + return BMI270_ANYMO2_REG; + case IIO_EV_TYPE_ROC: + return BMI270_NOMO2_REG; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int bmi270_anymotion_event_en(struct bmi270_data *data, + struct iio_chan_spec const *chan, + bool state) +{ + u16 axis_msk, axis_field_val, regval; + int ret, irq_reg; + bool axis_en; + + irq_reg = bmi270_int_map_reg(data->irq_pin); + if (irq_reg < 0) + return irq_reg; + + guard(mutex)(&data->mutex); + + ret = bmi270_read_feature_reg(data, BMI270_ANYMO1_REG, ®val); + if (ret) + return ret; + + switch (chan->channel2) { + case IIO_MOD_X: + axis_msk = BMI270_FEAT_MOTION_X_EN_MSK; + axis_field_val = FIELD_PREP(BMI270_FEAT_MOTION_X_EN_MSK, state); + axis_en = FIELD_GET(BMI270_FEAT_MOTION_Y_EN_MSK, regval) | + FIELD_GET(BMI270_FEAT_MOTION_Z_EN_MSK, regval); + break; + case IIO_MOD_Y: + axis_msk = BMI270_FEAT_MOTION_Y_EN_MSK; + axis_field_val = FIELD_PREP(BMI270_FEAT_MOTION_Y_EN_MSK, state); + axis_en = FIELD_GET(BMI270_FEAT_MOTION_X_EN_MSK, regval) | + FIELD_GET(BMI270_FEAT_MOTION_Z_EN_MSK, regval); + break; + case IIO_MOD_Z: + axis_msk = BMI270_FEAT_MOTION_Z_EN_MSK; + axis_field_val = FIELD_PREP(BMI270_FEAT_MOTION_Z_EN_MSK, state); + axis_en = FIELD_GET(BMI270_FEAT_MOTION_X_EN_MSK, regval) | + FIELD_GET(BMI270_FEAT_MOTION_Y_EN_MSK, regval); + break; + default: + return -EINVAL; + } + + ret = bmi270_update_feature_reg(data, BMI270_ANYMO1_REG, axis_msk, + axis_field_val); + if (ret) + return ret; + + ret = bmi270_update_feature_reg(data, BMI270_ANYMO2_REG, + BMI270_FEAT_MOTION_ENABLE_MSK, + FIELD_PREP(BMI270_FEAT_MOTION_ENABLE_MSK, + state || axis_en)); + if (ret) + return ret; + + return regmap_update_bits(data->regmap, irq_reg, + BMI270_INT_MAP_FEAT_ANYMOTION_MSK, + FIELD_PREP(BMI270_INT_MAP_FEAT_ANYMOTION_MSK, + state || axis_en)); +} + +static int bmi270_nomotion_event_en(struct bmi270_data *data, bool state) +{ + int ret, irq_reg; + + irq_reg = bmi270_int_map_reg(data->irq_pin); + if (irq_reg < 0) + return irq_reg; + + guard(mutex)(&data->mutex); + + ret = bmi270_update_feature_reg(data, BMI270_NOMO1_REG, + BMI270_FEAT_MOTION_XYZ_EN_MSK, + FIELD_PREP(BMI270_FEAT_MOTION_XYZ_EN_MSK, + state ? BMI270_MOTION_XYZ_MSK : 0)); + if (ret) + return ret; + + ret = bmi270_update_feature_reg(data, BMI270_NOMO2_REG, + BMI270_FEAT_MOTION_ENABLE_MSK, + FIELD_PREP(BMI270_FEAT_MOTION_ENABLE_MSK, + state)); + if (ret) + return ret; + + return regmap_update_bits(data->regmap, irq_reg, + BMI270_INT_MAP_FEAT_NOMOTION_MSK, + FIELD_PREP(BMI270_INT_MAP_FEAT_NOMOTION_MSK, + state)); +} + static int bmi270_set_scale(struct bmi270_data *data, int chan_type, int uscale) { int i; @@ -479,8 +645,6 @@ static int bmi270_get_scale(struct bmi270_data *data, int chan_type, int *scale, unsigned int val; struct bmi270_scale_item bmi270_scale_item; - guard(mutex)(&data->mutex); - switch (chan_type) { case IIO_ACCEL: ret = regmap_read(data->regmap, BMI270_ACC_CONF_RANGE_REG, &val); @@ -614,6 +778,20 @@ static irqreturn_t bmi270_irq_thread_handler(int irq, void *private) if (FIELD_GET(BMI270_INT_STATUS_1_ACC_GYR_DRDY_MSK, status1)) iio_trigger_poll_nested(data->trig); + if (FIELD_GET(BMI270_INT_STATUS_0_MOTION_MSK, status0)) + iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + IIO_MOD_X_OR_Y_OR_Z, + IIO_EV_TYPE_MAG_ADAPTIVE, + IIO_EV_DIR_RISING), + timestamp); + + if (FIELD_GET(BMI270_INT_STATUS_0_NOMOTION_MSK, status0)) + iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + IIO_MOD_X_AND_Y_AND_Z, + IIO_EV_TYPE_ROC, + IIO_EV_DIR_RISING), + timestamp); + if (FIELD_GET(BMI270_INT_STATUS_0_STEP_CNT_MSK, status0)) iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_STEPS, 0, IIO_EV_TYPE_CHANGE, @@ -827,6 +1005,39 @@ static int bmi270_read_avail(struct iio_dev *indio_dev, } } +static ssize_t in_accel_value_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct bmi270_data *data = iio_priv(indio_dev); + int ret, scale, uscale; + unsigned int step, max; + + ret = bmi270_get_scale(data, IIO_ACCEL, &scale, &uscale); + if (ret) + return ret; + + max = BMI270_G_MICRO_M_S_2 / uscale; + step = max / BMI270_MOTION_THRES_FULL_SCALE; + + return sysfs_emit(buf, "[0 %u %u]\n", step, max); +} + +static IIO_DEVICE_ATTR_RO(in_accel_value_available, 0); + +static IIO_CONST_ATTR(in_accel_period_available, "[0.0 0.02 162.0]"); + +static struct attribute *bmi270_event_attributes[] = { + &iio_dev_attr_in_accel_value_available.dev_attr.attr, + &iio_const_attr_in_accel_period_available.dev_attr.attr, + NULL +}; + +static const struct attribute_group bmi270_event_attribute_group = { + .attrs = bmi270_event_attributes, +}; + static int bmi270_write_event_config(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, @@ -835,6 +1046,10 @@ static int bmi270_write_event_config(struct iio_dev *indio_dev, struct bmi270_data *data = iio_priv(indio_dev); switch (type) { + case IIO_EV_TYPE_MAG_ADAPTIVE: + return bmi270_anymotion_event_en(data, chan, state); + case IIO_EV_TYPE_ROC: + return bmi270_nomotion_event_en(data, state); case IIO_EV_TYPE_CHANGE: return bmi270_step_wtrmrk_en(data, state); default: @@ -848,21 +1063,55 @@ static int bmi270_read_event_config(struct iio_dev *indio_dev, enum iio_event_direction dir) { struct bmi270_data *data = iio_priv(indio_dev); + bool feat_en, axis_en; int ret, reg, regval; + u16 motion_reg; guard(mutex)(&data->mutex); + reg = bmi270_int_map_reg(data->irq_pin); + if (reg < 0) + return reg; + + ret = regmap_read(data->regmap, reg, ®val); + if (ret) + return ret; + switch (chan->type) { case IIO_STEPS: - reg = bmi270_int_map_reg(data->irq_pin); - if (reg) - return reg; + return !!FIELD_GET(BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK, regval); + case IIO_ACCEL: + switch (type) { + case IIO_EV_TYPE_ROC: + return !!FIELD_GET(BMI270_INT_MAP_FEAT_NOMOTION_MSK, regval); + case IIO_EV_TYPE_MAG_ADAPTIVE: + ret = bmi270_read_feature_reg(data, BMI270_ANYMO1_REG, + &motion_reg); + if (ret) + return ret; - ret = regmap_read(data->regmap, reg, ®val); - if (ret) - return ret; - return FIELD_GET(BMI270_INT_MAP_FEAT_STEP_CNT_WTRMRK_MSK, - regval) ? 1 : 0; + feat_en = FIELD_GET(BMI270_INT_MAP_FEAT_ANYMOTION_MSK, + regval); + switch (chan->channel2) { + case IIO_MOD_X: + axis_en = FIELD_GET(BMI270_FEAT_MOTION_X_EN_MSK, + motion_reg); + break; + case IIO_MOD_Y: + axis_en = FIELD_GET(BMI270_FEAT_MOTION_Y_EN_MSK, + motion_reg); + break; + case IIO_MOD_Z: + axis_en = FIELD_GET(BMI270_FEAT_MOTION_Z_EN_MSK, + motion_reg); + break; + default: + return -EINVAL; + } + return axis_en && feat_en; + default: + return -EINVAL; + } default: return -EINVAL; } @@ -876,20 +1125,50 @@ static int bmi270_write_event_value(struct iio_dev *indio_dev, int val, int val2) { struct bmi270_data *data = iio_priv(indio_dev); - unsigned int raw; + unsigned int raw, mask, regval; + int ret, reg, scale, uscale; + u64 tmp; guard(mutex)(&data->mutex); - switch (type) { - case IIO_EV_TYPE_CHANGE: + if (type == IIO_EV_TYPE_CHANGE) { if (!in_range(val, 0, BMI270_STEP_COUNTER_MAX + 1)) return -EINVAL; raw = val / BMI270_STEP_COUNTER_FACTOR; - return bmi270_update_feature_reg(data, BMI270_SC_26_REG, - BMI270_STEP_SC26_WTRMRK_MSK, - FIELD_PREP(BMI270_STEP_SC26_WTRMRK_MSK, - raw)); + mask = BMI270_STEP_SC26_WTRMRK_MSK; + regval = FIELD_PREP(BMI270_STEP_SC26_WTRMRK_MSK, raw); + return bmi270_update_feature_reg(data, BMI270_SC_26_REG, mask, + regval); + } + + reg = bmi270_motion_reg(type, info); + if (reg < 0) + return reg; + + switch (info) { + case IIO_EV_INFO_VALUE: + ret = bmi270_get_scale(data, IIO_ACCEL, &scale, &uscale); + if (ret) + return ret; + + if (!in_range(val, 0, (BMI270_G_MICRO_M_S_2 / uscale) + 1)) + return -EINVAL; + + tmp = (u64)val * BMI270_MOTION_THRES_FULL_SCALE * uscale; + raw = DIV_ROUND_CLOSEST_ULL(tmp, BMI270_G_MICRO_M_S_2); + mask = BMI270_FEAT_MOTION_THRESHOLD_MSK; + regval = FIELD_PREP(BMI270_FEAT_MOTION_THRESHOLD_MSK, raw); + return bmi270_update_feature_reg(data, reg, mask, regval); + case IIO_EV_INFO_PERIOD: + if (!in_range(val, 0, BMI270_MOTION_DURAT_MAX + 1)) + return -EINVAL; + + raw = BMI270_INT_MICRO_TO_RAW(val, val2, + BMI270_MOTION_DURAT_SCALE); + mask = BMI270_FEAT_MOTION_DURATION_MSK; + regval = FIELD_PREP(BMI270_FEAT_MOTION_DURATION_MSK, raw); + return bmi270_update_feature_reg(data, reg, mask, regval); default: return -EINVAL; } @@ -903,14 +1182,14 @@ static int bmi270_read_event_value(struct iio_dev *indio_dev, int *val, int *val2) { struct bmi270_data *data = iio_priv(indio_dev); + int ret, reg, scale, uscale; unsigned int raw; u16 regval; - int ret; + u64 tmp; guard(mutex)(&data->mutex); - switch (type) { - case IIO_EV_TYPE_CHANGE: + if (type == IIO_EV_TYPE_CHANGE) { ret = bmi270_read_feature_reg(data, BMI270_SC_26_REG, ®val); if (ret) return ret; @@ -918,6 +1197,36 @@ static int bmi270_read_event_value(struct iio_dev *indio_dev, raw = FIELD_GET(BMI270_STEP_SC26_WTRMRK_MSK, regval); *val = raw * BMI270_STEP_COUNTER_FACTOR; return IIO_VAL_INT; + } + + reg = bmi270_motion_reg(type, info); + if (reg < 0) + return reg; + + switch (info) { + case IIO_EV_INFO_VALUE: + ret = bmi270_read_feature_reg(data, reg, ®val); + if (ret) + return ret; + + ret = bmi270_get_scale(data, IIO_ACCEL, &scale, &uscale); + if (ret) + return ret; + + raw = FIELD_GET(BMI270_FEAT_MOTION_THRESHOLD_MSK, regval); + tmp = (u64)raw * BMI270_G_MICRO_M_S_2; + *val = DIV_ROUND_CLOSEST_ULL(tmp, + BMI270_MOTION_THRES_FULL_SCALE * uscale); + return IIO_VAL_INT; + case IIO_EV_INFO_PERIOD: + ret = bmi270_read_feature_reg(data, reg, ®val); + if (ret) + return ret; + + raw = FIELD_GET(BMI270_FEAT_MOTION_DURATION_MSK, regval); + *val = raw / BMI270_MOTION_DURAT_SCALE; + *val2 = BMI270_RAW_TO_MICRO(raw, BMI270_MOTION_DURAT_SCALE); + return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; } @@ -929,6 +1238,20 @@ static const struct iio_event_spec bmi270_step_wtrmrk_event = { .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE), }; +static const struct iio_event_spec bmi270_anymotion_event = { + .type = IIO_EV_TYPE_MAG_ADAPTIVE, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_PERIOD), +}; + +static const struct iio_event_spec bmi270_nomotion_event = { + .type = IIO_EV_TYPE_ROC, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_PERIOD), +}; + static const struct iio_info bmi270_info = { .read_raw = bmi270_read_raw, .write_raw = bmi270_write_raw, @@ -937,6 +1260,7 @@ static const struct iio_info bmi270_info = { .read_event_config = bmi270_read_event_config, .write_event_value = bmi270_write_event_value, .read_event_value = bmi270_read_event_value, + .event_attrs = &bmi270_event_attribute_group, }; #define BMI270_ACCEL_CHANNEL(_axis) { \ @@ -956,6 +1280,8 @@ static const struct iio_info bmi270_info = { .storagebits = 16, \ .endianness = IIO_LE, \ }, \ + .event_spec = &bmi270_anymotion_event, \ + .num_event_specs = 1, \ } #define BMI270_ANG_VEL_CHANNEL(_axis) { \ @@ -1000,6 +1326,14 @@ static const struct iio_chan_spec bmi270_channels[] = { .num_event_specs = 1, }, IIO_CHAN_SOFT_TIMESTAMP(BMI270_SCAN_TIMESTAMP), + { + .type = IIO_ACCEL, + .modified = 1, + .channel2 = IIO_MOD_X_AND_Y_AND_Z, + .scan_index = -1, /* Fake channel */ + .event_spec = &bmi270_nomotion_event, + .num_event_specs = 1, + }, }; static int bmi270_int_pin_config(struct bmi270_data *data, @@ -1107,6 +1441,13 @@ static int bmi270_trigger_probe(struct bmi270_data *data, return dev_err_probe(data->dev, ret, "Trigger registration failed\n"); + /* Disable axes for motion events */ + ret = bmi270_update_feature_reg(data, BMI270_ANYMO1_REG, + BMI270_FEAT_MOTION_XYZ_EN_MSK, + FIELD_PREP(BMI270_FEAT_MOTION_XYZ_EN_MSK, 0)); + if (ret) + return ret; + data->irq_pin = irq_pin; return 0; From 4f816702d5bf2d32a425957bec09dd99381223a0 Mon Sep 17 00:00:00 2001 From: Gustavo Silva Date: Tue, 16 Sep 2025 20:38:24 -0300 Subject: [PATCH 022/304] iio: ABI: document accelerometer event attributes Add ABI documentation for accelerometer event-related sysfs attributes exposed by the bmi270 driver. These include threshold, period, and enable controls for adaptive magnitude (any-motion) and rate of change (no-motion) event detection. Signed-off-by: Gustavo Silva Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 89b4740dcfa1..352ab7b8476c 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -926,6 +926,7 @@ What: /sys/.../iio:deviceX/events/in_accel_y_roc_rising_en What: /sys/.../iio:deviceX/events/in_accel_y_roc_falling_en What: /sys/.../iio:deviceX/events/in_accel_z_roc_rising_en What: /sys/.../iio:deviceX/events/in_accel_z_roc_falling_en +What: /sys/.../iio:deviceX/events/in_accel_x&y&z_roc_rising_en What: /sys/.../iio:deviceX/events/in_anglvel_x_roc_rising_en What: /sys/.../iio:deviceX/events/in_anglvel_x_roc_falling_en What: /sys/.../iio:deviceX/events/in_anglvel_y_roc_rising_en @@ -1001,6 +1002,7 @@ Description: to the raw signal, allowing slow tracking to resume and the adaptive threshold event detection to function as expected. +What: /sys/.../events/in_accel_mag_adaptive_rising_value What: /sys/.../events/in_accel_thresh_rising_value What: /sys/.../events/in_accel_thresh_falling_value What: /sys/.../events/in_accel_x_raw_thresh_rising_value @@ -1147,6 +1149,7 @@ Description: will get activated once in_voltage0_raw goes above 1200 and will become deactivated again once the value falls below 1150. +What: /sys/.../events/in_accel_roc_rising_value What: /sys/.../events/in_accel_x_raw_roc_rising_value What: /sys/.../events/in_accel_x_raw_roc_falling_value What: /sys/.../events/in_accel_y_raw_roc_rising_value @@ -1193,6 +1196,8 @@ Description: value is in raw device units or in processed units (as _raw and _input do on sysfs direct channel read attributes). +What: /sys/.../events/in_accel_mag_adaptive_rising_period +What: /sys/.../events/in_accel_roc_rising_period What: /sys/.../events/in_accel_x_thresh_rising_period What: /sys/.../events/in_accel_x_thresh_falling_period What: /sys/.../events/in_accel_x_roc_rising_period @@ -1362,6 +1367,15 @@ Description: number or direction is not specified, applies to all channels of this type. +What: /sys/.../iio:deviceX/events/in_accel_x_mag_adaptive_rising_en +What: /sys/.../iio:deviceX/events/in_accel_y_mag_adaptive_rising_en +What: /sys/.../iio:deviceX/events/in_accel_z_mag_adaptive_rising_en +KernelVersion: 2.6.37 +Contact: linux-iio@vger.kernel.org +Description: + Similar to in_accel_x_thresh[_rising|_falling]_en, but here the + magnitude of the channel is compared to the adaptive threshold. + What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_en What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_rising_en What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_falling_en @@ -2422,3 +2436,23 @@ Description: Value representing the user's attention to the system expressed in units as percentage. This usually means if the user is looking at the screen or not. + +What: /sys/.../events/in_accel_value_available +KernelVersion: 6.18 +Contact: linux-iio@vger.kernel.org +Description: + List of available threshold values for acceleration event + generation. Applies to all event types on in_accel channels. + Units after application of scale and offset are m/s^2. + Expressed as: + + - a range specified as "[min step max]" + +What: /sys/.../events/in_accel_period_available +KernelVersion: 6.18 +Contact: linux-iio@vger.kernel.org +Description: + List of available periods for accelerometer event detection in + seconds, expressed as: + + - a range specified as "[min step max]" From adb729f677bd7e5b849386a0d4778a270a7041eb Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Mon, 22 Sep 2025 13:37:54 +0700 Subject: [PATCH 023/304] Documentation: iio: ade9000, adis*, adx*: Convert IIO subsystem cross-references Cross-references to iio_tools.rst (IIO Interfacing Tools) and iio_devbuf.rst (Industrial IIO device buffers) are shown in inline code instead. Convert them to proper cross-references. Signed-off-by: Bagas Sanjaya Reviewed-by: Randy Dunlap Tested-by: Randy Dunlap Signed-off-by: Jonathan Cameron --- Documentation/iio/ade9000.rst | 2 +- Documentation/iio/adis16475.rst | 4 ++-- Documentation/iio/adis16480.rst | 4 ++-- Documentation/iio/adis16550.rst | 4 ++-- Documentation/iio/adxl345.rst | 4 ++-- Documentation/iio/adxl380.rst | 4 ++-- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/iio/ade9000.rst b/Documentation/iio/ade9000.rst index 43d4b8dc1cb7..c9ff702a4251 100644 --- a/Documentation/iio/ade9000.rst +++ b/Documentation/iio/ade9000.rst @@ -264,5 +264,5 @@ Configure RMS voltage event thresholds (requires interrupts): 8. IIO Interfacing Tools ======================== -See ``Documentation/iio/iio_tools.rst`` for the description of the available IIO +See Documentation/iio/iio_tools.rst for the description of the available IIO interfacing tools. diff --git a/Documentation/iio/adis16475.rst b/Documentation/iio/adis16475.rst index 4bf0998be36e..89a388490ab7 100644 --- a/Documentation/iio/adis16475.rst +++ b/Documentation/iio/adis16475.rst @@ -374,11 +374,11 @@ Obtain buffered data: 00001740 01 1a 00 00 ff ff fe 31 00 00 46 aa 00 03 37 f7 |.......1..F...7.| ... -See ``Documentation/iio/iio_devbuf.rst`` for more information about how buffered +See Documentation/iio/iio_devbuf.rst for more information about how buffered data is structured. 4. IIO Interfacing Tools ======================== -See ``Documentation/iio/iio_tools.rst`` for the description of the available IIO +See Documentation/iio/iio_tools.rst for the description of the available IIO interfacing tools. diff --git a/Documentation/iio/adis16480.rst b/Documentation/iio/adis16480.rst index 4a2d40e0daa7..cce5f3e01741 100644 --- a/Documentation/iio/adis16480.rst +++ b/Documentation/iio/adis16480.rst @@ -436,11 +436,11 @@ Obtain buffered data:: 00006b60 09 63 00 00 00 00 1b 13 00 00 22 2f 00 03 23 91 |.c........"/..#.| ... -See ``Documentation/iio/iio_devbuf.rst`` for more information about how buffered +See Documentation/iio/iio_devbuf.rst for more information about how buffered data is structured. 4. IIO Interfacing Tools ======================== -See ``Documentation/iio/iio_tools.rst`` for the description of the available IIO +See Documentation/iio/iio_tools.rst for the description of the available IIO interfacing tools. diff --git a/Documentation/iio/adis16550.rst b/Documentation/iio/adis16550.rst index 25db7b8060c4..c9bbc0a857b0 100644 --- a/Documentation/iio/adis16550.rst +++ b/Documentation/iio/adis16550.rst @@ -366,11 +366,11 @@ Obtain buffered data: 0000ceb0 00 00 0d 2f 00 00 05 25 00 00 07 8d 00 00 a2 ce |.../...%........| ... -See ``Documentation/iio/iio_devbuf.rst`` for more information about how buffered +See Documentation/iio/iio_devbuf.rst for more information about how buffered data is structured. 4. IIO Interfacing Tools ======================== -See ``Documentation/iio/iio_tools.rst`` for the description of the available IIO +See Documentation/iio/iio_tools.rst for the description of the available IIO interfacing tools. diff --git a/Documentation/iio/adxl345.rst b/Documentation/iio/adxl345.rst index afdb35f8b72e..bb19d64f67c3 100644 --- a/Documentation/iio/adxl345.rst +++ b/Documentation/iio/adxl345.rst @@ -433,11 +433,11 @@ Obtain buffered data: 00000f0 00004 00014 00015 00005 00012 00011 00005 00012 ... -See ``Documentation/iio/iio_devbuf.rst`` for more information about how buffered +See Documentation/iio/iio_devbuf.rst for more information about how buffered data is structured. 4. IIO Interfacing Tools ======================== -See ``Documentation/iio/iio_tools.rst`` for the description of the available IIO +See Documentation/iio/iio_tools.rst for the description of the available IIO interfacing tools. diff --git a/Documentation/iio/adxl380.rst b/Documentation/iio/adxl380.rst index 66c8a4d4f767..61cafa2f98bf 100644 --- a/Documentation/iio/adxl380.rst +++ b/Documentation/iio/adxl380.rst @@ -223,11 +223,11 @@ Obtain buffered data: 002bc3c0 f7 fd 00 cb fb 94 24 80 f7 e3 00 f2 fb b8 24 80 |......$.......$.| ... -See ``Documentation/iio/iio_devbuf.rst`` for more information about how buffered +See Documentation/iio/iio_devbuf.rst for more information about how buffered data is structured. 4. IIO Interfacing Tools ======================== -See ``Documentation/iio/iio_tools.rst`` for the description of the available IIO +See Documentation/iio/iio_tools.rst for the description of the available IIO interfacing tools. From 620636f497337a9faedba336d3388091c9a540e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 23 Sep 2025 09:41:47 +0100 Subject: [PATCH 024/304] iio: dac: ltc2688: make use of devm_mutex_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use devm_mutex_init() since it brings some benefits when CONFIG_DEBUG_MUTEXES is enabled. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ltc2688.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iio/dac/ltc2688.c b/drivers/iio/dac/ltc2688.c index 7a2ee26a7d68..57028d422868 100644 --- a/drivers/iio/dac/ltc2688.c +++ b/drivers/iio/dac/ltc2688.c @@ -953,7 +953,9 @@ static int ltc2688_probe(struct spi_device *spi) /* Just write this once. No need to do it in every regmap read. */ st->tx_data[3] = LTC2688_CMD_NOOP; - mutex_init(&st->lock); + ret = devm_mutex_init(dev, &st->lock); + if (ret) + return ret; st->regmap = devm_regmap_init(dev, <c2688_regmap_bus, st, <c2688_regmap_config); From 0649002e842000872c69caceff0d20da48b2cc44 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 23 Sep 2025 15:33:18 -0500 Subject: [PATCH 025/304] iio: adc: ad7124: add ext attributes to temperature channel Use the same .ext_info for the temperature channel as for the voltage channels. In the ADC, these all go though a mux to select the source and otherwise operate the same. These attributes probably won't be used much, but since it is trivial to add this, we might as well include them. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 374e39736584..7ed31399a875 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -1348,6 +1348,7 @@ static int ad7124_parse_channel_config(struct iio_dev *indio_dev, }, .address = num_channels, .scan_index = num_channels, + .ext_info = ad7124_calibsys_ext_info, }; } From 9065197e0d41b0beb4bf15b72b91fa81b14455ad Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 23 Sep 2025 16:48:04 -0500 Subject: [PATCH 026/304] iio: adc: ad7124: change setup reg allocation strategy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the allocation strategy of the 8 SETUP registers from a least- recently-used (LRU) to a first-come-first-served basis. The AD7124 chips can have up to 16 channels enabled at a time in the sequencer for buffered reads, but only have 8 SETUP configurations (namely the OFFSET, GAIN, CONFIG and FILTER registers) that must be shared among the 16 channels. This means some of the channels must use the exact same configuration parameters so that they can share a single SETUP group of registers. The previous LRU strategy did not keep track of how many different configurations were requested at the same time, so if there were more than 8 different configurations requested, some channels would end up using the incorrect configuration because the slot assigned to them would also be assigned to a different configuration that wrote over it later. Adding such tracking to solve this would make an already complex algorithm even more complex. Instead we can replace it with a simpler first-come-first-serve strategy. This makes it easy to track how many different configurations are being requested at the same time. This comes at the expense of slightly longer setup times for buffered reads since all setup registers must be written each time when a buffered read is enabled. But this is generally not considered a hot path where performance is critical, so should be acceptable. This new strategy also makes hardware debugging easier since SETUPs are now assigned in a deterministic manner and in a logical order. Signed-off-by: David Lechner Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 233 +++++++++++++++++---------------------- 1 file changed, 100 insertions(+), 133 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 7ed31399a875..9d58ced7371d 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -111,6 +111,8 @@ #define AD7124_FILTER_SINGLE_CYCLE BIT(16) #define AD7124_FILTER_FS GENMASK(10, 0) +#define AD7124_CFG_SLOT_UNASSIGNED ~0U + #define AD7124_MAX_CONFIGS 8 #define AD7124_MAX_CHANNELS 16 @@ -176,14 +178,13 @@ enum ad7124_filter_type { }; struct ad7124_channel_config { - bool live; unsigned int cfg_slot; unsigned int requested_odr; unsigned int requested_odr_micro; /* * Following fields are used to compare for equality. If you * make adaptations in it, you most likely also have to adapt - * ad7124_find_similar_live_cfg(), too. + * ad7124_config_equal(), too. */ struct_group(config_props, enum ad7124_ref_sel refsel; @@ -215,14 +216,13 @@ struct ad7124_state { unsigned int adc_control; unsigned int num_channels; struct mutex cfgs_lock; /* lock for configs access */ - unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */ + u8 cfg_slot_use_count[AD7124_MAX_CONFIGS]; /* * Stores the power-on reset value for the GAIN(x) registers which are * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0) */ unsigned int gain_default; - DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); bool enable_single_cycle; }; @@ -367,9 +367,6 @@ static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel cfg->requested_odr_micro * factor / MICRO; odr_sel_bits = clamp(DIV_ROUND_CLOSEST(fclk, divisor), 1, 2047); - if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits) - st->channels[channel].cfg.live = false; - st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; } @@ -404,61 +401,6 @@ static int ad7124_get_3db_filter_factor(struct ad7124_state *st, } } -static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st, - struct ad7124_channel_config *cfg) -{ - struct ad7124_channel_config *cfg_aux; - int i; - - /* - * This is just to make sure that the comparison is adapted after - * struct ad7124_channel_config was changed. - */ - static_assert(sizeof_field(struct ad7124_channel_config, config_props) == - sizeof(struct { - enum ad7124_ref_sel refsel; - bool bipolar; - bool buf_positive; - bool buf_negative; - unsigned int vref_mv; - unsigned int pga_bits; - unsigned int odr_sel_bits; - enum ad7124_filter_type filter_type; - unsigned int calibration_offset; - unsigned int calibration_gain; - })); - - for (i = 0; i < st->num_channels; i++) { - cfg_aux = &st->channels[i].cfg; - - if (cfg_aux->live && - cfg->refsel == cfg_aux->refsel && - cfg->bipolar == cfg_aux->bipolar && - cfg->buf_positive == cfg_aux->buf_positive && - cfg->buf_negative == cfg_aux->buf_negative && - cfg->vref_mv == cfg_aux->vref_mv && - cfg->pga_bits == cfg_aux->pga_bits && - cfg->odr_sel_bits == cfg_aux->odr_sel_bits && - cfg->filter_type == cfg_aux->filter_type && - cfg->calibration_offset == cfg_aux->calibration_offset && - cfg->calibration_gain == cfg_aux->calibration_gain) - return cfg_aux; - } - - return NULL; -} - -static int ad7124_find_free_config_slot(struct ad7124_state *st) -{ - unsigned int free_cfg_slot; - - free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS); - if (free_cfg_slot == AD7124_MAX_CONFIGS) - return -1; - - return free_cfg_slot; -} - /* Only called during probe, so dev_err_probe() can be used */ static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg) { @@ -487,6 +429,21 @@ static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channe } } +static bool ad7124_config_equal(struct ad7124_channel_config *a, + struct ad7124_channel_config *b) +{ + return a->refsel == b->refsel && + a->bipolar == b->bipolar && + a->buf_positive == b->buf_positive && + a->buf_negative == b->buf_negative && + a->vref_mv == b->vref_mv && + a->pga_bits == b->pga_bits && + a->odr_sel_bits == b->odr_sel_bits && + a->filter_type == b->filter_type && + a->calibration_offset == b->calibration_offset && + a->calibration_gain == b->calibration_gain; +} + static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg, unsigned int cfg_slot) { @@ -495,13 +452,13 @@ static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_co unsigned int post = 0; int ret; - cfg->cfg_slot = cfg_slot; - - ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg->cfg_slot), 3, cfg->calibration_offset); + ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg_slot), 3, + cfg->calibration_offset); if (ret) return ret; - ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg->cfg_slot), 3, cfg->calibration_gain); + ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg_slot), 3, + cfg->calibration_gain); if (ret) return ret; @@ -511,7 +468,7 @@ static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_co (cfg->buf_negative ? AD7124_CONFIG_AIN_BUFM : 0) | FIELD_PREP(AD7124_CONFIG_PGA, cfg->pga_bits); - ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val); + ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg_slot), 2, val); if (ret < 0) return ret; @@ -564,7 +521,7 @@ static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_co * was requested. It may only be disabled through debugfs for testing * purposes. */ - return ad_sd_write_reg(&st->sd, AD7124_FILTER(cfg->cfg_slot), 3, + return ad_sd_write_reg(&st->sd, AD7124_FILTER(cfg_slot), 3, FIELD_PREP(AD7124_FILTER_FILTER, filter) | FIELD_PREP(AD7124_FILTER_REJ60, rej60) | FIELD_PREP(AD7124_FILTER_POST_FILTER, post) | @@ -573,83 +530,86 @@ static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_co FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits)); } -static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st) +/** + * ad7124_request_config_slot() - Request a config slot for a given config + * @st: Driver instance + * @channel: Channel to request a slot for + * + * Tries to find a matching config already in use, otherwise finds a free + * slot. If this function returns successfully, the use count for the slot is + * increased and the slot number is stored in cfg->cfg_slot. + * + * The slot must be released again with ad7124_release_config_slot() when no + * longer needed. + * + * Returns: 0 if a slot was successfully assigned, -EUSERS if no slot is + * available or other error if SPI communication fails. + */ +static int ad7124_request_config_slot(struct ad7124_state *st, u8 channel) { - struct ad7124_channel_config *lru_cfg; - struct ad7124_channel_config *cfg; - int ret; - int i; + unsigned int other, slot; + int last_used_slot = -1; - /* - * Pop least recently used config from the fifo - * in order to make room for the new one - */ - ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg); - if (ret <= 0) - return NULL; + /* Find another channel with a matching config, if any. */ + for (other = 0; other < st->num_channels; other++) { + if (other == channel) + continue; - lru_cfg->live = false; + if (st->channels[other].cfg.cfg_slot == AD7124_CFG_SLOT_UNASSIGNED) + continue; - /* mark slot as free */ - assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0); + last_used_slot = max_t(int, last_used_slot, + st->channels[other].cfg.cfg_slot); - /* invalidate all other configs that pointed to this one */ - for (i = 0; i < st->num_channels; i++) { - cfg = &st->channels[i].cfg; + if (!ad7124_config_equal(&st->channels[other].cfg, + &st->channels[channel].cfg)) + continue; - if (cfg->cfg_slot == lru_cfg->cfg_slot) - cfg->live = false; + /* Found a match, re-use that slot. */ + slot = st->channels[other].cfg.cfg_slot; + st->cfg_slot_use_count[slot]++; + st->channels[channel].cfg.cfg_slot = slot; + + return 0; } - return lru_cfg; + /* No match, use next free slot. */ + slot = last_used_slot + 1; + if (slot >= AD7124_MAX_CONFIGS) + return -EUSERS; + + st->cfg_slot_use_count[slot]++; + st->channels[channel].cfg.cfg_slot = slot; + + return ad7124_write_config(st, &st->channels[channel].cfg, slot); } -static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg) +static void ad7124_release_config_slot(struct ad7124_state *st, u8 channel) { - struct ad7124_channel_config *lru_cfg; - int free_cfg_slot; + unsigned int slot = st->channels[channel].cfg.cfg_slot; - free_cfg_slot = ad7124_find_free_config_slot(st); - if (free_cfg_slot >= 0) { - /* push the new config in configs queue */ - kfifo_put(&st->live_cfgs_fifo, cfg); - } else { - /* pop one config to make room for the new one */ - lru_cfg = ad7124_pop_config(st); - if (!lru_cfg) - return -EINVAL; + /* + * All of these conditions can happen at probe when all channels are + * disabled. Otherwise, they should not happen normally. + */ + if (channel >= st->num_channels || slot == AD7124_CFG_SLOT_UNASSIGNED || + st->cfg_slot_use_count[slot] == 0) + return; - /* push the new config in configs queue */ - free_cfg_slot = lru_cfg->cfg_slot; - kfifo_put(&st->live_cfgs_fifo, cfg); - } - - /* mark slot as used */ - assign_bit(free_cfg_slot, &st->cfg_slots_status, 1); - - return ad7124_write_config(st, cfg, free_cfg_slot); + st->cfg_slot_use_count[slot]--; + st->channels[channel].cfg.cfg_slot = AD7124_CFG_SLOT_UNASSIGNED; } static int ad7124_prepare_read(struct ad7124_state *st, int address) { struct ad7124_channel_config *cfg = &st->channels[address].cfg; - struct ad7124_channel_config *live_cfg; + int ret; - /* - * Before doing any reads assign the channel a configuration. - * Check if channel's config is on the device - */ - if (!cfg->live) { - /* check if config matches another one */ - live_cfg = ad7124_find_similar_live_cfg(st, cfg); - if (!live_cfg) - ad7124_push_config(st, cfg); - else - cfg->cfg_slot = live_cfg->cfg_slot; - } + ret = ad7124_request_config_slot(st, address); + if (ret) + return ret; /* point channel to the config slot and enable */ - cfg->live = true; return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(address), 2, st->channels[address].ain | FIELD_PREP(AD7124_CHANNEL_SETUP, cfg->cfg_slot) | @@ -692,6 +652,8 @@ static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan) { struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); + ad7124_release_config_slot(st, chan); + /* The relevant thing here is that AD7124_CHANNEL_ENABLE is cleared. */ return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0); } @@ -913,9 +875,6 @@ static int ad7124_write_raw(struct iio_dev *indio_dev, gain = DIV_ROUND_CLOSEST(res, val2); res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain); - if (st->channels[chan->address].cfg.pga_bits != res) - st->channels[chan->address].cfg.live = false; - st->channels[chan->address].cfg.pga_bits = res; return 0; default: @@ -1058,7 +1017,11 @@ static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan if (ret < 0) return ret; - ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(ch->cfg.cfg_slot), 3, + /* + * Making the assumption that a single conversion will always + * use configuration slot 0 for the OFFSET/GAIN registers. + */ + ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(0), 3, &ch->cfg.calibration_offset); if (ret < 0) return ret; @@ -1073,7 +1036,7 @@ static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan if (ret < 0) return ret; - ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(ch->cfg.cfg_slot), 3, + ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &ch->cfg.calibration_gain); if (ret < 0) return ret; @@ -1164,7 +1127,6 @@ static int ad7124_set_filter_type_attr(struct iio_dev *dev, guard(mutex)(&st->cfgs_lock); - cfg->live = false; cfg->filter_type = value; ad7124_set_channel_odr(st, chan->address); @@ -1484,7 +1446,6 @@ static int ad7124_setup(struct ad7124_state *st) if (ret) return ret; - INIT_KFIFO(st->live_cfgs_fifo); for (i = 0; i < st->num_channels; i++) { struct ad7124_channel_config *cfg = &st->channels[i].cfg; @@ -1492,6 +1453,8 @@ static int ad7124_setup(struct ad7124_state *st) if (ret < 0) return ret; + cfg->cfg_slot = AD7124_CFG_SLOT_UNASSIGNED; + /* Default filter type on the ADC after reset. */ cfg->filter_type = AD7124_FILTER_TYPE_SINC4; @@ -1551,7 +1514,7 @@ static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio * ad_sigma_delta_set_channel() -> ad7124_set_channel() * -> ad7124_prepare_read(). */ - ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(st->channels[i].cfg.cfg_slot), 3, + ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->channels[i].cfg.calibration_gain); if (ret < 0) return ret; @@ -1561,7 +1524,11 @@ static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio if (ret < 0) return ret; - ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(st->channels[i].cfg.cfg_slot), 3, + /* + * Making the assumption that a single conversion will always + * use configuration slot 0 for the OFFSET/GAIN registers. + */ + ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(0), 3, &st->channels[i].cfg.calibration_offset); if (ret < 0) return ret; From f11e4374b44777aa2b51205999469a057f6f7faa Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Thu, 2 Oct 2025 22:02:02 +0200 Subject: [PATCH 027/304] dt-bindings: iio: pressure: add binding for mpl3115 MPL3115 is an I2C pressure and temperature sensor. It features 2 interrupt lines which can be configured to indicate events such as data ready or pressure/temperature threshold reached. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- .../bindings/iio/pressure/fsl,mpl3115.yaml | 71 +++++++++++++++++++ .../devicetree/bindings/trivial-devices.yaml | 2 - 2 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/pressure/fsl,mpl3115.yaml diff --git a/Documentation/devicetree/bindings/iio/pressure/fsl,mpl3115.yaml b/Documentation/devicetree/bindings/iio/pressure/fsl,mpl3115.yaml new file mode 100644 index 000000000000..2933c2e10695 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/pressure/fsl,mpl3115.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/fsl,mpl3115.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MPL3115 precision pressure sensor with altimetry + +maintainers: + - Antoni Pokusinski + +description: | + MPL3115 is a pressure/altitude and temperature sensor with I2C interface. + It features two programmable interrupt lines which indicate events such as + data ready or pressure/temperature threshold reached. + https://www.nxp.com/docs/en/data-sheet/MPL3115A2.pdf + +properties: + compatible: + const: fsl,mpl3115 + + reg: + maxItems: 1 + + vdd-supply: true + + vddio-supply: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 + + drive-open-drain: + type: boolean + description: + set if the specified interrupt pins should be configured as + open drain. If not set, defaults to push-pull. + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pressure@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT2"; + }; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 58ff948d93c9..2be5fb41b410 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -113,8 +113,6 @@ properties: - fsl,mma7660 # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer - fsl,mma8450 - # MPL3115: Absolute Digital Pressure Sensor - - fsl,mpl3115 # MPR121: Proximity Capacitive Touch Sensor Controller - fsl,mpr121 # Honeywell Humidicon HIH-6130 humidity/temperature sensor From f692f0bfdf471b6afad0aa759ce215cb087c9b81 Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Thu, 2 Oct 2025 22:02:03 +0200 Subject: [PATCH 028/304] iio: mpl3115: add separate function for triggered buffer data collection Factor out the code responsible for collecting data for the triggered buffer from the trigger handler into a separate function. Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/mpl3115.c | 56 +++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index 579da60ef441..1da78081ca7e 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -148,6 +148,33 @@ static int mpl3115_read_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int mpl3115_fill_trig_buffer(struct iio_dev *indio_dev, u8 *buffer) +{ + struct mpl3115_data *data = iio_priv(indio_dev); + int ret, pos = 0; + + ret = mpl3115_request(data); + if (ret < 0) + return ret; + + if (test_bit(0, indio_dev->active_scan_mask)) { + ret = i2c_smbus_read_i2c_block_data(data->client, + MPL3115_OUT_PRESS, 3, &buffer[pos]); + if (ret < 0) + return ret; + pos += 4; + } + + if (test_bit(1, indio_dev->active_scan_mask)) { + ret = i2c_smbus_read_i2c_block_data(data->client, + MPL3115_OUT_TEMP, 2, &buffer[pos]); + if (ret < 0) + return ret; + } + + return 0; +} + static irqreturn_t mpl3115_trigger_handler(int irq, void *p) { struct iio_poll_func *pf = p; @@ -161,34 +188,13 @@ static irqreturn_t mpl3115_trigger_handler(int irq, void *p) * use a simple structure definition to express this data layout. */ u8 buffer[16] __aligned(8) = { }; - int ret, pos = 0; + int ret; mutex_lock(&data->lock); - ret = mpl3115_request(data); - if (ret < 0) { - mutex_unlock(&data->lock); - goto done; - } - - if (test_bit(0, indio_dev->active_scan_mask)) { - ret = i2c_smbus_read_i2c_block_data(data->client, - MPL3115_OUT_PRESS, 3, &buffer[pos]); - if (ret < 0) { - mutex_unlock(&data->lock); - goto done; - } - pos += 4; - } - - if (test_bit(1, indio_dev->active_scan_mask)) { - ret = i2c_smbus_read_i2c_block_data(data->client, - MPL3115_OUT_TEMP, 2, &buffer[pos]); - if (ret < 0) { - mutex_unlock(&data->lock); - goto done; - } - } + ret = mpl3115_fill_trig_buffer(indio_dev, buffer); mutex_unlock(&data->lock); + if (ret) + goto done; iio_push_to_buffers_with_ts(indio_dev, buffer, sizeof(buffer), iio_get_time_ns(indio_dev)); From b4105b20312a48a7723ad13fe180fbe6c066ac34 Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Thu, 2 Oct 2025 22:02:04 +0200 Subject: [PATCH 029/304] iio: mpl3115: rename CTRL_REG1 field macros Rename the bitfield macros of CTRL_REG1, so that their names clearly indicate their relation to CTRL_REG1. This is a preparation for introducing the support for the DRDY interrupt which requires the usage of other control registers. Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/mpl3115.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index 1da78081ca7e..61830edd959b 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -30,10 +30,10 @@ #define MPL3115_STATUS_PRESS_RDY BIT(2) #define MPL3115_STATUS_TEMP_RDY BIT(1) -#define MPL3115_CTRL_RESET BIT(2) /* software reset */ -#define MPL3115_CTRL_OST BIT(1) /* initiate measurement */ -#define MPL3115_CTRL_ACTIVE BIT(0) /* continuous measurement */ -#define MPL3115_CTRL_OS_258MS (BIT(5) | BIT(4)) /* 64x oversampling */ +#define MPL3115_CTRL1_RESET BIT(2) /* software reset */ +#define MPL3115_CTRL1_OST BIT(1) /* initiate measurement */ +#define MPL3115_CTRL1_ACTIVE BIT(0) /* continuous measurement */ +#define MPL3115_CTRL1_OS_258MS GENMASK(5, 4) /* 64x oversampling */ struct mpl3115_data { struct i2c_client *client; @@ -47,7 +47,7 @@ static int mpl3115_request(struct mpl3115_data *data) /* trigger measurement */ ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1, - data->ctrl_reg1 | MPL3115_CTRL_OST); + data->ctrl_reg1 | MPL3115_CTRL1_OST); if (ret < 0) return ret; @@ -56,7 +56,7 @@ static int mpl3115_request(struct mpl3115_data *data) if (ret < 0) return ret; /* wait for data ready, i.e. OST cleared */ - if (!(ret & MPL3115_CTRL_OST)) + if (!(ret & MPL3115_CTRL1_OST)) break; msleep(20); } @@ -268,10 +268,10 @@ static int mpl3115_probe(struct i2c_client *client) /* software reset, I2C transfer is aborted (fails) */ i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1, - MPL3115_CTRL_RESET); + MPL3115_CTRL1_RESET); msleep(50); - data->ctrl_reg1 = MPL3115_CTRL_OS_258MS; + data->ctrl_reg1 = MPL3115_CTRL1_OS_258MS; ret = i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1, data->ctrl_reg1); if (ret < 0) @@ -295,7 +295,7 @@ buffer_cleanup: static int mpl3115_standby(struct mpl3115_data *data) { return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1, - data->ctrl_reg1 & ~MPL3115_CTRL_ACTIVE); + data->ctrl_reg1 & ~MPL3115_CTRL1_ACTIVE); } static void mpl3115_remove(struct i2c_client *client) From 8464f61099c2a6a434a995fecd565f12cdec21d5 Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Thu, 2 Oct 2025 22:02:05 +0200 Subject: [PATCH 030/304] iio: mpl3115: add support for DRDY interrupt MPL3115 sensor features a "data ready" interrupt which indicates the presence of new measurements. Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/mpl3115.c | 183 +++++++++++++++++++++++++++++++-- 1 file changed, 175 insertions(+), 8 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index 61830edd959b..e1b2c9f2bb43 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -7,40 +7,66 @@ * (7-bit I2C slave address 0x60) * * TODO: FIFO buffer, altimeter mode, oversampling, continuous mode, - * interrupts, user offset correction, raw mode + * user offset correction, raw mode */ -#include +#include +#include #include +#include +#include + +#include #include #include -#include -#include #include -#include +#include +#include #define MPL3115_STATUS 0x00 #define MPL3115_OUT_PRESS 0x01 /* MSB first, 20 bit */ #define MPL3115_OUT_TEMP 0x04 /* MSB first, 12 bit */ #define MPL3115_WHO_AM_I 0x0c +#define MPL3115_INT_SOURCE 0x12 +#define MPL3115_PT_DATA_CFG 0x13 #define MPL3115_CTRL_REG1 0x26 +#define MPL3115_CTRL_REG3 0x28 +#define MPL3115_CTRL_REG4 0x29 +#define MPL3115_CTRL_REG5 0x2a #define MPL3115_DEVICE_ID 0xc4 #define MPL3115_STATUS_PRESS_RDY BIT(2) #define MPL3115_STATUS_TEMP_RDY BIT(1) +#define MPL3115_INT_SRC_DRDY BIT(7) + +#define MPL3115_PT_DATA_EVENT_ALL GENMASK(2, 0) + #define MPL3115_CTRL1_RESET BIT(2) /* software reset */ #define MPL3115_CTRL1_OST BIT(1) /* initiate measurement */ #define MPL3115_CTRL1_ACTIVE BIT(0) /* continuous measurement */ #define MPL3115_CTRL1_OS_258MS GENMASK(5, 4) /* 64x oversampling */ +#define MPL3115_CTRL3_IPOL1 BIT(5) +#define MPL3115_CTRL3_IPOL2 BIT(1) + +#define MPL3115_CTRL4_INT_EN_DRDY BIT(7) + +#define MPL3115_CTRL5_INT_CFG_DRDY BIT(7) + struct mpl3115_data { struct i2c_client *client; + struct iio_trigger *drdy_trig; struct mutex lock; u8 ctrl_reg1; }; +enum mpl3115_irq_pin { + MPL3115_IRQ_INT1, + MPL3115_IRQ_INT2, +}; + static int mpl3115_request(struct mpl3115_data *data) { int ret, tries = 15; @@ -153,9 +179,11 @@ static int mpl3115_fill_trig_buffer(struct iio_dev *indio_dev, u8 *buffer) struct mpl3115_data *data = iio_priv(indio_dev); int ret, pos = 0; - ret = mpl3115_request(data); - if (ret < 0) - return ret; + if (!(data->ctrl_reg1 & MPL3115_CTRL1_ACTIVE)) { + ret = mpl3115_request(data); + if (ret < 0) + return ret; + } if (test_bit(0, indio_dev->active_scan_mask)) { ret = i2c_smbus_read_i2c_block_data(data->client, @@ -234,10 +262,145 @@ static const struct iio_chan_spec mpl3115_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(2), }; +static irqreturn_t mpl3115_interrupt_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct mpl3115_data *data = iio_priv(indio_dev); + int ret; + + ret = i2c_smbus_read_byte_data(data->client, MPL3115_INT_SOURCE); + if (ret < 0) + return IRQ_HANDLED; + + if (!(ret & MPL3115_INT_SRC_DRDY)) + return IRQ_NONE; + + iio_trigger_poll_nested(data->drdy_trig); + + return IRQ_HANDLED; +} + +static int mpl3115_config_interrupt(struct mpl3115_data *data, + u8 ctrl_reg1, u8 ctrl_reg4) +{ + int ret; + + ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1, + ctrl_reg1); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG4, + ctrl_reg4); + if (ret < 0) + goto reg1_cleanup; + + data->ctrl_reg1 = ctrl_reg1; + + return 0; + +reg1_cleanup: + i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1, + data->ctrl_reg1); + return ret; +} + +static int mpl3115_set_trigger_state(struct iio_trigger *trig, bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct mpl3115_data *data = iio_priv(indio_dev); + u8 ctrl_reg1 = data->ctrl_reg1; + u8 ctrl_reg4 = state ? MPL3115_CTRL4_INT_EN_DRDY : 0; + + if (state) + ctrl_reg1 |= MPL3115_CTRL1_ACTIVE; + else + ctrl_reg1 &= ~MPL3115_CTRL1_ACTIVE; + + guard(mutex)(&data->lock); + + return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4); +} + +static const struct iio_trigger_ops mpl3115_trigger_ops = { + .set_trigger_state = mpl3115_set_trigger_state, +}; + static const struct iio_info mpl3115_info = { .read_raw = &mpl3115_read_raw, }; +static int mpl3115_trigger_probe(struct mpl3115_data *data, + struct iio_dev *indio_dev) +{ + struct fwnode_handle *fwnode = dev_fwnode(&data->client->dev); + int ret, irq, irq_type, irq_pin = MPL3115_IRQ_INT1; + + irq = fwnode_irq_get_byname(fwnode, "INT1"); + if (irq < 0) { + irq = fwnode_irq_get_byname(fwnode, "INT2"); + if (irq < 0) + return 0; + + irq_pin = MPL3115_IRQ_INT2; + } + + irq_type = irq_get_trigger_type(irq); + if (irq_type != IRQF_TRIGGER_RISING && irq_type != IRQF_TRIGGER_FALLING) + return -EINVAL; + + ret = i2c_smbus_write_byte_data(data->client, MPL3115_PT_DATA_CFG, + MPL3115_PT_DATA_EVENT_ALL); + if (ret < 0) + return ret; + + if (irq_pin == MPL3115_IRQ_INT1) { + ret = i2c_smbus_write_byte_data(data->client, + MPL3115_CTRL_REG5, + MPL3115_CTRL5_INT_CFG_DRDY); + if (ret) + return ret; + + if (irq_type == IRQF_TRIGGER_RISING) { + ret = i2c_smbus_write_byte_data(data->client, + MPL3115_CTRL_REG3, + MPL3115_CTRL3_IPOL1); + if (ret) + return ret; + } + } else if (irq_type == IRQF_TRIGGER_RISING) { + ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG3, + MPL3115_CTRL3_IPOL2); + if (ret) + return ret; + } + + data->drdy_trig = devm_iio_trigger_alloc(&data->client->dev, + "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!data->drdy_trig) + return -ENOMEM; + + data->drdy_trig->ops = &mpl3115_trigger_ops; + iio_trigger_set_drvdata(data->drdy_trig, indio_dev); + + ret = devm_request_threaded_irq(&data->client->dev, irq, NULL, + mpl3115_interrupt_handler, + IRQF_ONESHOT, + "mpl3115_irq", indio_dev); + if (ret) + return ret; + + ret = devm_iio_trigger_register(&data->client->dev, data->drdy_trig); + if (ret) + return ret; + + indio_dev->trig = iio_trigger_get(data->drdy_trig); + + return 0; +} + static int mpl3115_probe(struct i2c_client *client) { const struct i2c_device_id *id = i2c_client_get_device_id(client); @@ -277,6 +440,10 @@ static int mpl3115_probe(struct i2c_client *client) if (ret < 0) return ret; + ret = mpl3115_trigger_probe(data, indio_dev); + if (ret) + return ret; + ret = iio_triggered_buffer_setup(indio_dev, NULL, mpl3115_trigger_handler, NULL); if (ret < 0) From 1d09cf18cc91d29f650ad9811ed4868d9304d6c7 Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Thu, 2 Oct 2025 22:02:06 +0200 Subject: [PATCH 031/304] iio: mpl3115: add support for sampling frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the device is in ACTIVE mode the temperature and pressure measurements are collected with a frequency determined by the ST[3:0] bits of CTRL_REG2 register. Reviewed-by: Nuno Sá Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/mpl3115.c | 82 ++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index e1b2c9f2bb43..c212dfdf59ff 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -10,6 +10,7 @@ * user offset correction, raw mode */ +#include #include #include #include @@ -30,6 +31,7 @@ #define MPL3115_INT_SOURCE 0x12 #define MPL3115_PT_DATA_CFG 0x13 #define MPL3115_CTRL_REG1 0x26 +#define MPL3115_CTRL_REG2 0x27 #define MPL3115_CTRL_REG3 0x28 #define MPL3115_CTRL_REG4 0x29 #define MPL3115_CTRL_REG5 0x2a @@ -48,6 +50,8 @@ #define MPL3115_CTRL1_ACTIVE BIT(0) /* continuous measurement */ #define MPL3115_CTRL1_OS_258MS GENMASK(5, 4) /* 64x oversampling */ +#define MPL3115_CTRL2_ST GENMASK(3, 0) + #define MPL3115_CTRL3_IPOL1 BIT(5) #define MPL3115_CTRL3_IPOL2 BIT(1) @@ -55,6 +59,25 @@ #define MPL3115_CTRL5_INT_CFG_DRDY BIT(7) +static const unsigned int mpl3115_samp_freq_table[][2] = { + { 1, 0 }, + { 0, 500000 }, + { 0, 250000 }, + { 0, 125000 }, + { 0, 62500 }, + { 0, 31250 }, + { 0, 15625 }, + { 0, 7812 }, + { 0, 3906 }, + { 0, 1953 }, + { 0, 976 }, + { 0, 488 }, + { 0, 244 }, + { 0, 122 }, + { 0, 61 }, + { 0, 30 }, +}; + struct mpl3115_data { struct i2c_client *client; struct iio_trigger *drdy_trig; @@ -170,10 +193,61 @@ static int mpl3115_read_raw(struct iio_dev *indio_dev, default: return -EINVAL; } + case IIO_CHAN_INFO_SAMP_FREQ: + ret = i2c_smbus_read_byte_data(data->client, MPL3115_CTRL_REG2); + if (ret < 0) + return ret; + + ret = FIELD_GET(MPL3115_CTRL2_ST, ret); + + *val = mpl3115_samp_freq_table[ret][0]; + *val2 = mpl3115_samp_freq_table[ret][1]; + return IIO_VAL_INT_PLUS_MICRO; } return -EINVAL; } +static int mpl3115_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + if (mask != IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + *type = IIO_VAL_INT_PLUS_MICRO; + *length = ARRAY_SIZE(mpl3115_samp_freq_table) * 2; + *vals = (int *)mpl3115_samp_freq_table; + return IIO_AVAIL_LIST; +} + +static int mpl3115_write_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int val, int val2, long mask) +{ + struct mpl3115_data *data = iio_priv(indio_dev); + int i, ret; + + if (mask != IIO_CHAN_INFO_SAMP_FREQ) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(mpl3115_samp_freq_table); i++) + if (val == mpl3115_samp_freq_table[i][0] && + val2 == mpl3115_samp_freq_table[i][1]) + break; + + if (i == ARRAY_SIZE(mpl3115_samp_freq_table)) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG2, + FIELD_PREP(MPL3115_CTRL2_ST, i)); + iio_device_release_direct(indio_dev); + return ret; +} + static int mpl3115_fill_trig_buffer(struct iio_dev *indio_dev, u8 *buffer) { struct mpl3115_data *data = iio_priv(indio_dev); @@ -237,6 +311,9 @@ static const struct iio_chan_spec mpl3115_channels[] = { .type = IIO_PRESSURE, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all_available = + BIT(IIO_CHAN_INFO_SAMP_FREQ), .scan_index = 0, .scan_type = { .sign = 'u', @@ -250,6 +327,9 @@ static const struct iio_chan_spec mpl3115_channels[] = { .type = IIO_TEMP, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all_available = + BIT(IIO_CHAN_INFO_SAMP_FREQ), .scan_index = 1, .scan_type = { .sign = 's', @@ -328,6 +408,8 @@ static const struct iio_trigger_ops mpl3115_trigger_ops = { static const struct iio_info mpl3115_info = { .read_raw = &mpl3115_read_raw, + .read_avail = &mpl3115_read_avail, + .write_raw = &mpl3115_write_raw, }; static int mpl3115_trigger_probe(struct mpl3115_data *data, From 67f31f0b5f27ed10cb7976c8140c52b0235e3d68 Mon Sep 17 00:00:00 2001 From: Sameeksha Sankpal Date: Fri, 3 Oct 2025 23:14:25 +0530 Subject: [PATCH 032/304] iio: light: ltr390: Fix typo in variable name Corrected a spelling mistake in the ltr390 driver: 'recieve_buffer' was renamed to 'receive_buffer'. This improves code readibility without changing functionality. Signed-off-by: Sameeksha Sankpal Signed-off-by: Jonathan Cameron --- drivers/iio/light/ltr390.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/light/ltr390.c b/drivers/iio/light/ltr390.c index a2b804e9089a..fc387426fa87 100644 --- a/drivers/iio/light/ltr390.c +++ b/drivers/iio/light/ltr390.c @@ -160,16 +160,16 @@ static int ltr390_register_read(struct ltr390_data *data, u8 register_address) { struct device *dev = &data->client->dev; int ret; - u8 recieve_buffer[3]; + u8 receive_buffer[3]; - ret = regmap_bulk_read(data->regmap, register_address, recieve_buffer, - sizeof(recieve_buffer)); + ret = regmap_bulk_read(data->regmap, register_address, receive_buffer, + sizeof(receive_buffer)); if (ret) { dev_err(dev, "failed to read measurement data"); return ret; } - return get_unaligned_le24(recieve_buffer); + return get_unaligned_le24(receive_buffer); } static int ltr390_set_mode(struct ltr390_data *data, enum ltr390_mode mode) From ed1a82401bc08b43efbf1c10e653b8775a000ae1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:10 +0100 Subject: [PATCH 033/304] iio: adc: ad4030: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ad4030_read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4030.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 1bc2f9a22470..4393160c7c77 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -852,8 +852,8 @@ static int ad4030_read_label(struct iio_dev *indio_dev, char *label) { if (chan->differential) - return sprintf(label, "differential%lu\n", chan->address); - return sprintf(label, "common-mode%lu\n", chan->address); + return sysfs_emit(label, "differential%lu\n", chan->address); + return sysfs_emit(label, "common-mode%lu\n", chan->address); } static int ad4030_get_current_scan_type(const struct iio_dev *indio_dev, From 69911a64ba24c1077a38f3083202f93248e1c970 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:11 +0100 Subject: [PATCH 034/304] iio: adc: ad7768-1: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ad7768_read_label() function to use sysfs_emit(() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7768-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 872c88d0c86c..d96802b7847a 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -899,7 +899,7 @@ static int ad7768_read_label(struct iio_dev *indio_dev, { struct ad7768_state *st = iio_priv(indio_dev); - return sprintf(label, "%s\n", st->labels[chan->channel]); + return sysfs_emit(label, "%s\n", st->labels[chan->channel]); } static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, From 08be56ebe994d8038751cc52a4a02e0135df34bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:12 +0100 Subject: [PATCH 035/304] iio: adc: mcp3564: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the mcp3564_read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Reviewed-by: Marius Cristea Signed-off-by: Jonathan Cameron --- drivers/iio/adc/mcp3564.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/mcp3564.c b/drivers/iio/adc/mcp3564.c index cd679ff10a97..fcdf13f49c48 100644 --- a/drivers/iio/adc/mcp3564.c +++ b/drivers/iio/adc/mcp3564.c @@ -987,7 +987,7 @@ static int mcp3564_read_label(struct iio_dev *indio_dev, { struct mcp3564_state *adc = iio_priv(indio_dev); - return sprintf(label, "%s\n", adc->labels[chan->scan_index]); + return sysfs_emit(label, "%s\n", adc->labels[chan->scan_index]); } static int mcp3564_parse_fw_children(struct iio_dev *indio_dev) From f24a5ef74c350ec5432037f1d270b6ec4d56d269 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:13 +0100 Subject: [PATCH 036/304] iio: adc: meson_saradc: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/meson_saradc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index f7e7172ef4f6..47cd350498a0 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -1181,12 +1181,12 @@ static int read_label(struct iio_dev *indio_dev, char *label) { if (chan->type == IIO_TEMP) - return sprintf(label, "temp-sensor\n"); + return sysfs_emit(label, "temp-sensor\n"); if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS) - return sprintf(label, "%s\n", + return sysfs_emit(label, "%s\n", chan7_mux_names[chan->channel - NUM_MUX_0_VSS]); if (chan->type == IIO_VOLTAGE) - return sprintf(label, "channel-%d\n", chan->channel); + return sysfs_emit(label, "channel-%d\n", chan->channel); return 0; } From 31ab988b9f2f6c4ef0b3782bebc8c662bb0ce257 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:14 +0100 Subject: [PATCH 037/304] iio: adc: mt6360-adc: replace snprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the mt6360_adc_read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/mt6360-adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/mt6360-adc.c b/drivers/iio/adc/mt6360-adc.c index 69b3569c90e5..e0e4df418612 100644 --- a/drivers/iio/adc/mt6360-adc.c +++ b/drivers/iio/adc/mt6360-adc.c @@ -216,7 +216,7 @@ static const char *mt6360_channel_labels[MT6360_CHAN_MAX] = { static int mt6360_adc_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, char *label) { - return snprintf(label, PAGE_SIZE, "%s\n", mt6360_channel_labels[chan->channel]); + return sysfs_emit(label, "%s\n", mt6360_channel_labels[chan->channel]); } static const struct iio_info mt6360_adc_iio_info = { From 4367d24b156313b4b75a290ea5162328dbaa8e61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:15 +0100 Subject: [PATCH 038/304] iio: adc: pac1921: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the pac1921_read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/pac1921.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/pac1921.c b/drivers/iio/adc/pac1921.c index 35433250b008..a0227b57f238 100644 --- a/drivers/iio/adc/pac1921.c +++ b/drivers/iio/adc/pac1921.c @@ -672,13 +672,13 @@ static int pac1921_read_label(struct iio_dev *indio_dev, { switch (chan->channel) { case PAC1921_CHAN_VBUS: - return sprintf(label, "vbus\n"); + return sysfs_emit(label, "vbus\n"); case PAC1921_CHAN_VSENSE: - return sprintf(label, "vsense\n"); + return sysfs_emit(label, "vsense\n"); case PAC1921_CHAN_CURRENT: - return sprintf(label, "current\n"); + return sysfs_emit(label, "current\n"); case PAC1921_CHAN_POWER: - return sprintf(label, "power\n"); + return sysfs_emit(label, "power\n"); default: return -EINVAL; } From fdc9719a630fea1a2304529aa8f1b929a3e7ea75 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:16 +0100 Subject: [PATCH 039/304] iio: adc: qcom-spmi-rradc: replace snprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the rradc_read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/adc/qcom-spmi-rradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c index f61ad0510f04..b245416bae12 100644 --- a/drivers/iio/adc/qcom-spmi-rradc.c +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -769,7 +769,7 @@ static int rradc_read_raw(struct iio_dev *indio_dev, static int rradc_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, char *label) { - return snprintf(label, PAGE_SIZE, "%s\n", + return sysfs_emit(label, "%s\n", rradc_chans[chan->address].label); } From dd72a3880fc46fa383bff349033e96debcd401bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:17 +0100 Subject: [PATCH 040/304] iio: position: hid-sensor-custom-intel-hinge: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the hinge_read_label() function to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Acked-by: Srinivas Pandruvada Signed-off-by: Jonathan Cameron --- drivers/iio/position/hid-sensor-custom-intel-hinge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/position/hid-sensor-custom-intel-hinge.c b/drivers/iio/position/hid-sensor-custom-intel-hinge.c index bff7039690ac..a26d391661fd 100644 --- a/drivers/iio/position/hid-sensor-custom-intel-hinge.c +++ b/drivers/iio/position/hid-sensor-custom-intel-hinge.c @@ -176,7 +176,7 @@ static int hinge_read_label(struct iio_dev *indio_dev, { struct hinge_state *st = iio_priv(indio_dev); - return sprintf(label, "%s\n", st->labels[chan->channel]); + return sysfs_emit(label, "%s\n", st->labels[chan->channel]); } static const struct iio_info hinge_info = { From 7798b50e002591c14bd4492b794f2d1b7addb5be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 30 Sep 2025 16:33:18 +0100 Subject: [PATCH 041/304] iio: resolver: ad2s1210: replace sprintf() with sysfs_emit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ad2s1210_read_label() and ad2s1210_read_event_label() functions to use sysfs_emit() for generating labels. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/resolver/ad2s1210.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/iio/resolver/ad2s1210.c b/drivers/iio/resolver/ad2s1210.c index 9b028c8bb1db..06d9c784f93e 100644 --- a/drivers/iio/resolver/ad2s1210.c +++ b/drivers/iio/resolver/ad2s1210.c @@ -1132,23 +1132,23 @@ static int ad2s1210_read_label(struct iio_dev *indio_dev, { if (chan->type == IIO_ANGL) { if (chan->channel == 0) - return sprintf(label, "position\n"); + return sysfs_emit(label, "position\n"); if (chan->channel == 1) - return sprintf(label, "tracking error\n"); + return sysfs_emit(label, "tracking error\n"); } if (chan->type == IIO_ANGL_VEL) - return sprintf(label, "velocity\n"); + return sysfs_emit(label, "velocity\n"); if (chan->type == IIO_PHASE) - return sprintf(label, "synthetic reference\n"); + return sysfs_emit(label, "synthetic reference\n"); if (chan->type == IIO_ALTVOLTAGE) { if (chan->output) - return sprintf(label, "excitation\n"); + return sysfs_emit(label, "excitation\n"); if (chan->channel == 0) - return sprintf(label, "monitor signal\n"); + return sysfs_emit(label, "monitor signal\n"); if (chan->channel == 1) - return sprintf(label, "cosine\n"); + return sysfs_emit(label, "cosine\n"); if (chan->channel == 2) - return sprintf(label, "sine\n"); + return sysfs_emit(label, "sine\n"); } return -EINVAL; @@ -1239,24 +1239,24 @@ static int ad2s1210_read_event_label(struct iio_dev *indio_dev, char *label) { if (chan->type == IIO_ANGL) - return sprintf(label, "LOT\n"); + return sysfs_emit(label, "LOT\n"); if (chan->type == IIO_ANGL_VEL) - return sprintf(label, "max tracking rate\n"); + return sysfs_emit(label, "max tracking rate\n"); if (chan->type == IIO_PHASE) - return sprintf(label, "phase lock\n"); + return sysfs_emit(label, "phase lock\n"); if (chan->type == IIO_ALTVOLTAGE) { if (chan->channel == 0) { if (type == IIO_EV_TYPE_THRESH && dir == IIO_EV_DIR_FALLING) - return sprintf(label, "LOS\n"); + return sysfs_emit(label, "LOS\n"); if (type == IIO_EV_TYPE_THRESH && dir == IIO_EV_DIR_RISING) - return sprintf(label, "DOS overrange\n"); + return sysfs_emit(label, "DOS overrange\n"); if (type == IIO_EV_TYPE_MAG) - return sprintf(label, "DOS mismatch\n"); + return sysfs_emit(label, "DOS mismatch\n"); } if (chan->channel == 1 || chan->channel == 2) - return sprintf(label, "clipped\n"); + return sysfs_emit(label, "clipped\n"); } return -EINVAL; From 70fde04883609dcfd785bfe94649317c88a9840f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Mon, 29 Sep 2025 14:35:32 +0100 Subject: [PATCH 042/304] iio: dac: ltc2688: use the auto lock API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make use of the cleanup API so that we can simplify some code paths. Signed-off-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ltc2688.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/iio/dac/ltc2688.c b/drivers/iio/dac/ltc2688.c index 57028d422868..02f408229681 100644 --- a/drivers/iio/dac/ltc2688.c +++ b/drivers/iio/dac/ltc2688.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -208,12 +209,12 @@ static int ltc2688_dac_code_write(struct ltc2688_state *st, u32 chan, u32 input, code = FIELD_PREP(LTC2688_DITHER_RAW_MASK, code); } - mutex_lock(&st->lock); + guard(mutex)(&st->lock); /* select the correct input register to read from */ ret = regmap_update_bits(st->regmap, LTC2688_CMD_A_B_SELECT, BIT(chan), input << chan); if (ret) - goto out_unlock; + return ret; /* * If in dither/toggle mode the dac should be updated by an @@ -224,10 +225,7 @@ static int ltc2688_dac_code_write(struct ltc2688_state *st, u32 chan, u32 input, else reg = LTC2688_CMD_CH_CODE(chan); - ret = regmap_write(st->regmap, reg, code); -out_unlock: - mutex_unlock(&st->lock); - return ret; + return regmap_write(st->regmap, reg, code); } static int ltc2688_dac_code_read(struct ltc2688_state *st, u32 chan, u32 input, @@ -236,20 +234,20 @@ static int ltc2688_dac_code_read(struct ltc2688_state *st, u32 chan, u32 input, struct ltc2688_chan *c = &st->channels[chan]; int ret; - mutex_lock(&st->lock); + guard(mutex)(&st->lock); ret = regmap_update_bits(st->regmap, LTC2688_CMD_A_B_SELECT, BIT(chan), input << chan); if (ret) - goto out_unlock; + return ret; ret = regmap_read(st->regmap, LTC2688_CMD_CH_CODE(chan), code); -out_unlock: - mutex_unlock(&st->lock); + if (ret) + return ret; if (!c->toggle_chan && input == LTC2688_INPUT_B) *code = FIELD_GET(LTC2688_DITHER_RAW_MASK, *code); - return ret; + return 0; } static const int ltc2688_raw_range[] = {0, 1, U16_MAX}; @@ -359,17 +357,15 @@ static ssize_t ltc2688_dither_toggle_set(struct iio_dev *indio_dev, if (ret) return ret; - mutex_lock(&st->lock); + guard(mutex)(&st->lock); ret = regmap_update_bits(st->regmap, LTC2688_CMD_TOGGLE_DITHER_EN, BIT(chan->channel), en << chan->channel); if (ret) - goto out_unlock; + return ret; c->mode = en ? LTC2688_MODE_DITHER_TOGGLE : LTC2688_MODE_DEFAULT; -out_unlock: - mutex_unlock(&st->lock); - return ret ?: len; + return len; } static ssize_t ltc2688_reg_bool_get(struct iio_dev *indio_dev, From 4d8d58987cb57b3fe9721590888a99310a0e2cda Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 5 Oct 2025 14:13:17 +0300 Subject: [PATCH 043/304] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Document the A/D 12-Bit successive approximation converters found in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Signed-off-by: Cosmin Tanislav Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Signed-off-by: Jonathan Cameron --- .../iio/adc/renesas,r9a09g077-adc.yaml | 135 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml new file mode 100644 index 000000000000..dc0206b28231 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H / RZ/N2H ADC12 + +maintainers: + - Cosmin Tanislav + +description: | + A/D Converter block is a successive approximation analog-to-digital converter + with a 12-bit accuracy. Up to 16 analog input channels can be selected. + Conversions can be performed in single or continuous mode. Result of the ADC + is stored in a 16-bit data register corresponding to each channel. + +properties: + compatible: + oneOf: + - items: + - const: renesas,r9a09g087-adc # RZ/N2H + - const: renesas,r9a09g077-adc # RZ/T2H + - items: + - const: renesas,r9a09g077-adc # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: A/D scan end interrupt + - description: A/D scan end interrupt for Group B + - description: A/D scan end interrupt for Group C + - description: Window A compare match + - description: Window B compare match + - description: Compare match + - description: Compare mismatch + + interrupt-names: + items: + - const: adi + - const: gbadi + - const: gcadi + - const: cmpai + - const: cmpbi + - const: wcmpm + - const: wcmpum + + clocks: + items: + - description: Converter clock + - description: Peripheral clock + + clock-names: + items: + - const: adclk + - const: pclk + + power-domains: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#io-channel-cells": + const: 1 + +patternProperties: + "^channel@[0-9a-f]$": + $ref: adc.yaml + type: object + description: The external channels which are connected to the ADC. + + properties: + reg: + description: The channel number. + maximum: 15 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + + adc@80008000 { + compatible = "renesas,r9a09g077-adc"; + reg = <0x80008000 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@0 { + reg = <0x0>; + }; + channel@1 { + reg = <0x1>; + }; + channel@2 { + reg = <0x2>; + }; + channel@3 { + reg = <0x3>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..5c10d4df8279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21853,6 +21853,13 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c +RENESAS RZ/T2H / RZ/N2H A/D DRIVER +M: Cosmin Tanislav +L: linux-iio@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml + RENESAS RTCA-3 RTC DRIVER M: Claudiu Beznea L: linux-rtc@vger.kernel.org From fc3b97dd71ab428d6cf6a49c7f67b7067feb6456 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 5 Oct 2025 14:13:18 +0300 Subject: [PATCH 044/304] iio: adc: add RZ/T2H / RZ/N2H ADC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the A/D 12-Bit successive approximation converters found in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Conversions can be performed in single or continuous mode. Result of the conversion is stored in a 16-bit data register corresponding to each channel. The conversions can be started by a software trigger, a synchronous trigger (from MTU or from ELC) or an asynchronous external trigger (from ADTRGn# pin). Only single mode with software trigger is supported for now. Signed-off-by: Cosmin Tanislav Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzt2h_adc.c | 304 ++++++++++++++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 drivers/iio/adc/rzt2h_adc.c diff --git a/MAINTAINERS b/MAINTAINERS index 5c10d4df8279..08fcce3208cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21859,6 +21859,7 @@ L: linux-iio@vger.kernel.org L: linux-renesas-soc@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml +F: drivers/iio/adc/rzt2h_adc.c RENESAS RTCA-3 RTC DRIVER M: Claudiu Beznea diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58a14e6833f6..b0580fcefef5 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1403,6 +1403,17 @@ config RZG2L_ADC To compile this driver as a module, choose M here: the module will be called rzg2l_adc. +config RZT2H_ADC + tristate "Renesas RZ/T2H / RZ/N2H ADC driver" + depends on ARCH_RENESAS || COMPILE_TEST + select IIO_ADC_HELPER + help + Say yes here to build support for the ADC found in Renesas + RZ/T2H / RZ/N2H SoCs. + + To compile this driver as a module, choose M here: the + module will be called rzt2h_adc. + config SC27XX_ADC tristate "Spreadtrum SC27xx series PMICs ADC" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d008f78dc010..ed647a734c51 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o +obj-$(CONFIG_RZT2H_ADC) += rzt2h_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o obj-$(CONFIG_SOPHGO_CV1800B_ADC) += sophgo-cv1800b-adc.o diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c new file mode 100644 index 000000000000..33ce5cc44ff4 --- /dev/null +++ b/drivers/iio/adc/rzt2h_adc.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZT2H_ADCSR_REG 0x00 +#define RZT2H_ADCSR_ADIE_MASK BIT(12) +#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13) +#define RZT2H_ADCSR_ADCS_SINGLE 0b00 +#define RZT2H_ADCSR_ADST_MASK BIT(15) + +#define RZT2H_ADANSA0_REG 0x04 +#define RZT2H_ADANSA0_CH_MASK(x) BIT(x) + +#define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x)) + +#define RZT2H_ADCALCTL_REG 0x1f0 +#define RZT2H_ADCALCTL_CAL_MASK BIT(0) +#define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1) +#define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2) + +#define RZT2H_ADC_MAX_CHANNELS 16 + +struct rzt2h_adc { + void __iomem *base; + struct device *dev; + + struct completion completion; + /* lock to protect against multiple access to the device */ + struct mutex lock; + + const struct iio_chan_spec *channels; + unsigned int num_channels; + unsigned int max_channels; +}; + +static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int conversion_type) +{ + u16 reg; + + reg = readw(adc->base + RZT2H_ADCSR_REG); + + /* Set conversion type */ + FIELD_MODIFY(RZT2H_ADCSR_ADCS_MASK, ®, conversion_type); + + /* Set end of conversion interrupt and start bit. */ + reg |= RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK; + + writew(reg, adc->base + RZT2H_ADCSR_REG); +} + +static void rzt2h_adc_stop(struct rzt2h_adc *adc) +{ + u16 reg; + + reg = readw(adc->base + RZT2H_ADCSR_REG); + + /* Clear end of conversion interrupt and start bit. */ + reg &= ~(RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK); + + writew(reg, adc->base + RZT2H_ADCSR_REG); +} + +static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, int *val) +{ + int ret; + + ret = pm_runtime_resume_and_get(adc->dev); + if (ret) + return ret; + + mutex_lock(&adc->lock); + + reinit_completion(&adc->completion); + + /* Enable a single channel */ + writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG); + + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE); + + /* + * Datasheet Page 2770, Table 41.1: + * 0.32us per channel when sample-and-hold circuits are not in use. + */ + ret = wait_for_completion_timeout(&adc->completion, usecs_to_jiffies(1)); + if (!ret) { + ret = -ETIMEDOUT; + goto disable; + } + + *val = readw(adc->base + RZT2H_ADDR_REG(ch)); + ret = IIO_VAL_INT; + +disable: + rzt2h_adc_stop(adc); + + mutex_unlock(&adc->lock); + + pm_runtime_put_autosuspend(adc->dev); + + return ret; +} + +static void rzt2h_adc_set_cal(struct rzt2h_adc *adc, bool cal) +{ + u16 val; + + val = readw(adc->base + RZT2H_ADCALCTL_REG); + if (cal) + val |= RZT2H_ADCALCTL_CAL_MASK; + else + val &= ~RZT2H_ADCALCTL_CAL_MASK; + + writew(val, adc->base + RZT2H_ADCALCTL_REG); +} + +static int rzt2h_adc_calibrate(struct rzt2h_adc *adc) +{ + u16 val; + int ret; + + rzt2h_adc_set_cal(adc, true); + + ret = read_poll_timeout(readw, val, val & RZT2H_ADCALCTL_CAL_RDY_MASK, + 200, 1000, true, adc->base + RZT2H_ADCALCTL_REG); + if (ret) { + dev_err(adc->dev, "Calibration timed out: %d\n", ret); + return ret; + } + + rzt2h_adc_set_cal(adc, false); + + if (val & RZT2H_ADCALCTL_CAL_ERR_MASK) { + dev_err(adc->dev, "Calibration failed\n"); + return -EINVAL; + } + + return 0; +} + +static int rzt2h_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct rzt2h_adc *adc = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + return rzt2h_adc_read_single(adc, chan->channel, val); + case IIO_CHAN_INFO_SCALE: + *val = 1800; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info rzt2h_adc_iio_info = { + .read_raw = rzt2h_adc_read_raw, +}; + +static irqreturn_t rzt2h_adc_isr(int irq, void *private) +{ + struct rzt2h_adc *adc = private; + + complete(&adc->completion); + + return IRQ_HANDLED; +} + +static const struct iio_chan_spec rzt2h_adc_chan_template = { + .indexed = 1, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .type = IIO_VOLTAGE, +}; + +static int rzt2h_adc_parse_properties(struct rzt2h_adc *adc) +{ + struct iio_chan_spec *chan_array; + unsigned int i; + int ret; + + ret = devm_iio_adc_device_alloc_chaninfo_se(adc->dev, + &rzt2h_adc_chan_template, + RZT2H_ADC_MAX_CHANNELS - 1, + &chan_array); + if (ret < 0) + return dev_err_probe(adc->dev, ret, "Failed to read channel info"); + + adc->num_channels = ret; + adc->channels = chan_array; + + for (i = 0; i < adc->num_channels; i++) + if (chan_array[i].channel + 1 > adc->max_channels) + adc->max_channels = chan_array[i].channel + 1; + + return 0; +} + +static int rzt2h_adc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rzt2h_adc *adc; + int ret, irq; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + adc->dev = dev; + init_completion(&adc->completion); + + ret = devm_mutex_init(dev, &adc->lock); + if (ret) + return ret; + + platform_set_drvdata(pdev, adc); + + ret = rzt2h_adc_parse_properties(adc); + if (ret) + return ret; + + adc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(adc->base)) + return PTR_ERR(adc->base); + + pm_runtime_set_autosuspend_delay(dev, 300); + pm_runtime_use_autosuspend(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + irq = platform_get_irq_byname(pdev, "adi"); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, rzt2h_adc_isr, 0, dev_name(dev), adc); + if (ret) + return ret; + + indio_dev->name = "rzt2h-adc"; + indio_dev->info = &rzt2h_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = adc->channels; + indio_dev->num_channels = adc->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rzt2h_adc_match[] = { + { .compatible = "renesas,r9a09g077-adc" }, + { } +}; +MODULE_DEVICE_TABLE(of, rzt2h_adc_match); + +static int rzt2h_adc_pm_runtime_resume(struct device *dev) +{ + struct rzt2h_adc *adc = dev_get_drvdata(dev); + + /* + * Datasheet Page 2810, Section 41.5.6: + * After release from the module-stop state, wait for at least + * 0.5 µs before starting A/D conversion. + */ + fsleep(1); + + return rzt2h_adc_calibrate(adc); +} + +static const struct dev_pm_ops rzt2h_adc_pm_ops = { + RUNTIME_PM_OPS(NULL, rzt2h_adc_pm_runtime_resume, NULL) +}; + +static struct platform_driver rzt2h_adc_driver = { + .probe = rzt2h_adc_probe, + .driver = { + .name = "rzt2h-adc", + .of_match_table = rzt2h_adc_match, + .pm = pm_ptr(&rzt2h_adc_pm_ops), + }, +}; + +module_platform_driver(rzt2h_adc_driver); + +MODULE_AUTHOR("Cosmin Tanislav "); +MODULE_DESCRIPTION("Renesas RZ/T2H / RZ/N2H ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DRIVER"); From 9cc2d6566f0bac8efd4e9f75a07c11c1a12b20ba Mon Sep 17 00:00:00 2001 From: Taimoor Zaeem Date: Mon, 6 Oct 2025 14:40:24 +0500 Subject: [PATCH 045/304] staging: iio: ad9834: remove empty ad9834.h file Remove drivers/staging/iio/frequency/ad9834.h header file because it contains nothing except the include guards. Signed-off-by: Taimoor Zaeem Signed-off-by: Jonathan Cameron --- drivers/staging/iio/frequency/ad9834.c | 3 +-- drivers/staging/iio/frequency/ad9834.h | 10 ---------- 2 files changed, 1 insertion(+), 12 deletions(-) delete mode 100644 drivers/staging/iio/frequency/ad9834.h diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c index 0038eb234d40..d339d5e8e043 100644 --- a/drivers/staging/iio/frequency/ad9834.c +++ b/drivers/staging/iio/frequency/ad9834.c @@ -21,9 +21,8 @@ #include #include -#include "dds.h" -#include "ad9834.h" +#include "dds.h" /* Registers */ diff --git a/drivers/staging/iio/frequency/ad9834.h b/drivers/staging/iio/frequency/ad9834.h deleted file mode 100644 index 521943aa0e61..000000000000 --- a/drivers/staging/iio/frequency/ad9834.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * AD9833/AD9834/AD9837/AD9838 SPI DDS driver - * - * Copyright 2010-2011 Analog Devices Inc. - */ -#ifndef IIO_DDS_AD9834_H_ -#define IIO_DDS_AD9834_H_ - -#endif /* IIO_DDS_AD9834_H_ */ From 679bf18ec0497ed2a8acb9d6a7acf56a341f3f9f Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:10 +0300 Subject: [PATCH 046/304] iio: accel: bma220: remove incorrect kernel-doc marking Remove incorrect use of kernel-doc marking. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 01592eebf05b..505ad7091257 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -223,7 +223,7 @@ static int bma220_power(struct spi_device *spi, bool up) { int i, ret; - /** + /* * The chip can be suspended/woken up by a simple register read. * So, we need up to 2 register reads of the suspend register * to make sure that the device is in the desired state. From f3f42da58803e606d50b01d6ae63454a4f0cfa2b Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:11 +0300 Subject: [PATCH 047/304] iio: accel: bma220: relax constraints during probe() Do not return error if the chip id being read is not the expected one. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_spi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 505ad7091257..02ee6b4d51c0 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -202,10 +202,15 @@ static const struct iio_info bma220_info = { static int bma220_init(struct spi_device *spi) { int ret; + struct device *dev = &spi->dev; ret = bma220_read_reg(spi, BMA220_REG_ID); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to read chip id register\n"); + if (ret != BMA220_CHIP_ID) - return -ENODEV; + dev_info(dev, "Unknown chip found: 0x%02x\n", ret); /* Make sure the chip is powered on */ ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); From b4cecec7dc0b09b8e7260abd0d45ec58214dfa9a Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:12 +0300 Subject: [PATCH 048/304] iio: accel: bma220: cleanup license string Fix checkpatch warning about use of "GPL v2" license: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity") Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 02ee6b4d51c0..8c313debc1df 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -332,4 +332,4 @@ module_spi_driver(bma220_driver); MODULE_AUTHOR("Tiberiu Breana "); MODULE_DESCRIPTION("BMA220 acceleration sensor driver"); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); From 5dbac275dcb909b281b9f68727aace0e350e3ab3 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:13 +0300 Subject: [PATCH 049/304] iio: accel: bma220: shorten spi->dev calls Provide functions easier access to device struct. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_spi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 8c313debc1df..a5d2906321ae 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -258,8 +258,9 @@ static int bma220_probe(struct spi_device *spi) int ret; struct iio_dev *indio_dev; struct bma220_data *data; + struct device *dev = &spi->dev; - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data)); + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); if (!indio_dev) return -ENOMEM; @@ -278,19 +279,19 @@ static int bma220_probe(struct spi_device *spi) if (ret) return ret; - ret = devm_add_action_or_reset(&spi->dev, bma220_deinit, spi); + ret = devm_add_action_or_reset(dev, bma220_deinit, spi); if (ret) return ret; - ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, iio_pollfunc_store_time, bma220_trigger_handler, NULL); if (ret < 0) { - dev_err(&spi->dev, "iio triggered buffer setup failed\n"); + dev_err(dev, "iio triggered buffer setup failed\n"); return ret; } - return devm_iio_device_register(&spi->dev, indio_dev); + return devm_iio_device_register(dev, indio_dev); } static int bma220_suspend(struct device *dev) From a9865410f4deec4db752941b87c8b387152aa103 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:14 +0300 Subject: [PATCH 050/304] iio: accel: bma220: move bma220_power function Move bma220_power() before bma220_init() as a precursor to a patch that removes code duplication. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_spi.c | 49 +++++++++++++++++----------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index a5d2906321ae..45ac0d7ee27d 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -199,6 +199,31 @@ static const struct iio_info bma220_info = { .read_avail = bma220_read_avail, }; +static int bma220_power(struct spi_device *spi, bool up) +{ + int ret; + unsigned int i; + + /* + * The chip can be suspended/woken up by a simple register read. + * So, we need up to 2 register reads of the suspend register + * to make sure that the device is in the desired state. + */ + for (i = 0; i < 2; i++) { + ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); + if (ret < 0) + return ret; + + if (up && ret == BMA220_SUSPEND_SLEEP) + return 0; + + if (!up && ret == BMA220_SUSPEND_WAKE) + return 0; + } + + return -EBUSY; +} + static int bma220_init(struct spi_device *spi) { int ret; @@ -224,30 +249,6 @@ static int bma220_init(struct spi_device *spi) return 0; } -static int bma220_power(struct spi_device *spi, bool up) -{ - int i, ret; - - /* - * The chip can be suspended/woken up by a simple register read. - * So, we need up to 2 register reads of the suspend register - * to make sure that the device is in the desired state. - */ - for (i = 0; i < 2; i++) { - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); - if (ret < 0) - return ret; - - if (up && ret == BMA220_SUSPEND_SLEEP) - return 0; - - if (!up && ret == BMA220_SUSPEND_WAKE) - return 0; - } - - return -EBUSY; -} - static void bma220_deinit(void *spi) { bma220_power(spi, false); From 7fe8e142f1edc770bb90aa0559c5c9ae6c17ffdf Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:15 +0300 Subject: [PATCH 051/304] iio: accel: bma220: cleanup includes Tweak includes based on requirements. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron #added linux/errno.h --- drivers/iio/accel/bma220_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 45ac0d7ee27d..bf78fb052812 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -6,9 +6,11 @@ */ #include -#include +#include #include #include +#include +#include #include #include From c785d9803b861ad1ebf52386c7ac2fa6ee54d355 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:16 +0300 Subject: [PATCH 052/304] iio: accel: bma220: split original driver In preparation for the i2c module, move the original code into multiple source files without any other functional change. Create the additional bma220_core module which currently is not providing an abstracted bus type (this will change with the regmap patch). Fix a few includes in the context of this patch. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/Kconfig | 8 +- drivers/iio/accel/Makefile | 3 +- drivers/iio/accel/bma220.h | 19 ++ drivers/iio/accel/bma220_core.c | 320 ++++++++++++++++++++++++++++++++ drivers/iio/accel/bma220_spi.c | 310 +------------------------------ 5 files changed, 356 insertions(+), 304 deletions(-) create mode 100644 drivers/iio/accel/bma220.h create mode 100644 drivers/iio/accel/bma220_core.c diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig index 8c3f7cf55d5f..4648be329917 100644 --- a/drivers/iio/accel/Kconfig +++ b/drivers/iio/accel/Kconfig @@ -221,12 +221,18 @@ config BMA220 depends on SPI select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select BMA220_SPI if SPI help Say yes here to add support for the Bosch BMA220 triaxial acceleration sensor. To compile this driver as a module, choose M here: the - module will be called bma220_spi. + module will be called bma220_core and you will also get + bma220_spi if SPI is enabled. + +config BMA220_SPI + tristate + depends on BMA220 config BMA400 tristate "Bosch BMA400 3-Axis Accelerometer Driver" diff --git a/drivers/iio/accel/Makefile b/drivers/iio/accel/Makefile index ca8569e25aba..56a9f848f7f9 100644 --- a/drivers/iio/accel/Makefile +++ b/drivers/iio/accel/Makefile @@ -25,7 +25,8 @@ obj-$(CONFIG_ADXL380) += adxl380.o obj-$(CONFIG_ADXL380_I2C) += adxl380_i2c.o obj-$(CONFIG_ADXL380_SPI) += adxl380_spi.o obj-$(CONFIG_BMA180) += bma180.o -obj-$(CONFIG_BMA220) += bma220_spi.o +obj-$(CONFIG_BMA220) += bma220_core.o +obj-$(CONFIG_BMA220_SPI) += bma220_spi.o obj-$(CONFIG_BMA400) += bma400_core.o obj-$(CONFIG_BMA400_I2C) += bma400_i2c.o obj-$(CONFIG_BMA400_SPI) += bma400_spi.o diff --git a/drivers/iio/accel/bma220.h b/drivers/iio/accel/bma220.h new file mode 100644 index 000000000000..b181f2b510fd --- /dev/null +++ b/drivers/iio/accel/bma220.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Forward declarations needed by the bma220 sources. + * + * Copyright 2025 Petre Rodan + */ + +#ifndef _BMA220_H +#define _BMA220_H + +#include + +struct spi_device; + +extern const struct dev_pm_ops bma220_pm_ops; + +int bma220_common_probe(struct spi_device *dev); + +#endif diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c new file mode 100644 index 000000000000..050282f20d90 --- /dev/null +++ b/drivers/iio/accel/bma220_core.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * BMA220 Digital triaxial acceleration sensor driver + * + * Copyright (c) 2016,2020 Intel Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "bma220.h" + +#define BMA220_REG_ID 0x00 +#define BMA220_REG_ACCEL_X 0x02 +#define BMA220_REG_ACCEL_Y 0x03 +#define BMA220_REG_ACCEL_Z 0x04 +#define BMA220_REG_RANGE 0x11 +#define BMA220_REG_SUSPEND 0x18 + +#define BMA220_CHIP_ID 0xDD +#define BMA220_READ_MASK BIT(7) +#define BMA220_RANGE_MASK GENMASK(1, 0) +#define BMA220_SUSPEND_SLEEP 0xFF +#define BMA220_SUSPEND_WAKE 0x00 + +#define BMA220_DEVICE_NAME "bma220" + +#define BMA220_ACCEL_CHANNEL(index, reg, axis) { \ + .type = IIO_ACCEL, \ + .address = reg, \ + .modified = 1, \ + .channel2 = IIO_MOD_##axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 6, \ + .storagebits = 8, \ + .shift = 2, \ + .endianness = IIO_CPU, \ + }, \ +} + +enum bma220_axis { + AXIS_X, + AXIS_Y, + AXIS_Z, +}; + +static const int bma220_scale_table[][2] = { + {0, 623000}, {1, 248000}, {2, 491000}, {4, 983000}, +}; + +struct bma220_data { + struct spi_device *spi_device; + struct mutex lock; + struct { + s8 chans[3]; + /* Ensure timestamp is naturally aligned. */ + aligned_s64 timestamp; + } scan; + u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); +}; + +static const struct iio_chan_spec bma220_channels[] = { + BMA220_ACCEL_CHANNEL(0, BMA220_REG_ACCEL_X, X), + BMA220_ACCEL_CHANNEL(1, BMA220_REG_ACCEL_Y, Y), + BMA220_ACCEL_CHANNEL(2, BMA220_REG_ACCEL_Z, Z), + IIO_CHAN_SOFT_TIMESTAMP(3), +}; + +static inline int bma220_read_reg(struct spi_device *spi, u8 reg) +{ + return spi_w8r8(spi, reg | BMA220_READ_MASK); +} + +static const unsigned long bma220_accel_scan_masks[] = { + BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), + 0 +}; + +static irqreturn_t bma220_trigger_handler(int irq, void *p) +{ + int ret; + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct bma220_data *data = iio_priv(indio_dev); + struct spi_device *spi = data->spi_device; + + mutex_lock(&data->lock); + data->tx_buf[0] = BMA220_REG_ACCEL_X | BMA220_READ_MASK; + ret = spi_write_then_read(spi, data->tx_buf, 1, &data->scan.chans, + ARRAY_SIZE(bma220_channels) - 1); + if (ret < 0) + goto err; + + iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan), + pf->timestamp); +err: + mutex_unlock(&data->lock); + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int bma220_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + int ret; + u8 range_idx; + struct bma220_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = bma220_read_reg(data->spi_device, chan->address); + if (ret < 0) + return -EINVAL; + *val = sign_extend32(ret >> chan->scan_type.shift, + chan->scan_type.realbits - 1); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + ret = bma220_read_reg(data->spi_device, BMA220_REG_RANGE); + if (ret < 0) + return ret; + range_idx = ret & BMA220_RANGE_MASK; + *val = bma220_scale_table[range_idx][0]; + *val2 = bma220_scale_table[range_idx][1]; + return IIO_VAL_INT_PLUS_MICRO; + } + + return -EINVAL; +} + +static int bma220_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + int i; + int ret; + int index = -1; + struct bma220_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + for (i = 0; i < ARRAY_SIZE(bma220_scale_table); i++) + if (val == bma220_scale_table[i][0] && + val2 == bma220_scale_table[i][1]) { + index = i; + break; + } + if (index < 0) + return -EINVAL; + + mutex_lock(&data->lock); + data->tx_buf[0] = BMA220_REG_RANGE; + data->tx_buf[1] = index; + ret = spi_write(data->spi_device, data->tx_buf, + sizeof(data->tx_buf)); + if (ret < 0) + return ret; + mutex_unlock(&data->lock); + + return 0; + } + + return -EINVAL; +} + +static int bma220_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = (int *)bma220_scale_table; + *type = IIO_VAL_INT_PLUS_MICRO; + *length = ARRAY_SIZE(bma220_scale_table) * 2; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static const struct iio_info bma220_info = { + .read_raw = bma220_read_raw, + .write_raw = bma220_write_raw, + .read_avail = bma220_read_avail, +}; + +static int bma220_power(struct spi_device *spi, bool up) +{ + int ret; + unsigned int i; + + /* + * The chip can be suspended/woken up by a simple register read. + * So, we need up to 2 register reads of the suspend register + * to make sure that the device is in the desired state. + */ + for (i = 0; i < 2; i++) { + ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); + if (ret < 0) + return ret; + + if (up && ret == BMA220_SUSPEND_SLEEP) + return 0; + + if (!up && ret == BMA220_SUSPEND_WAKE) + return 0; + } + + return -EBUSY; +} + +static int bma220_init(struct spi_device *spi) +{ + int ret; + struct device *dev = &spi->dev; + + ret = bma220_read_reg(spi, BMA220_REG_ID); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to read chip id register\n"); + + if (ret != BMA220_CHIP_ID) + dev_info(dev, "Unknown chip found: 0x%02x\n", ret); + + /* Make sure the chip is powered on */ + ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); + if (ret == BMA220_SUSPEND_WAKE) + ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); + if (ret < 0) + return ret; + if (ret == BMA220_SUSPEND_WAKE) + return -EBUSY; + + return 0; +} + +static void bma220_deinit(void *spi) +{ + bma220_power(spi, false); +} + +int bma220_common_probe(struct spi_device *spi) +{ + int ret; + struct iio_dev *indio_dev; + struct bma220_data *data; + struct device *dev = &spi->dev; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + data->spi_device = spi; + mutex_init(&data->lock); + + indio_dev->info = &bma220_info; + indio_dev->name = BMA220_DEVICE_NAME; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = bma220_channels; + indio_dev->num_channels = ARRAY_SIZE(bma220_channels); + indio_dev->available_scan_masks = bma220_accel_scan_masks; + + ret = bma220_init(data->spi_device); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, bma220_deinit, spi); + if (ret) + return ret; + + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + bma220_trigger_handler, NULL); + if (ret < 0) { + dev_err(dev, "iio triggered buffer setup failed\n"); + return ret; + } + + return devm_iio_device_register(dev, indio_dev); +} +EXPORT_SYMBOL_NS(bma220_common_probe, "IIO_BOSCH_BMA220"); + +static int bma220_suspend(struct device *dev) +{ + struct spi_device *spi = to_spi_device(dev); + + return bma220_power(spi, false); +} + +static int bma220_resume(struct device *dev) +{ + struct spi_device *spi = to_spi_device(dev); + + return bma220_power(spi, true); +} +EXPORT_NS_SIMPLE_DEV_PM_OPS(bma220_pm_ops, bma220_suspend, bma220_resume, + IIO_BOSCH_BMA220); + +MODULE_AUTHOR("Tiberiu Breana "); +MODULE_DESCRIPTION("BMA220 acceleration sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index bf78fb052812..761f475a5942 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -5,313 +5,18 @@ * Copyright (c) 2016,2020 Intel Corporation. */ -#include -#include #include #include -#include -#include #include #include -#include -#include -#include -#include -#include +#include "bma220.h" -#define BMA220_REG_ID 0x00 -#define BMA220_REG_ACCEL_X 0x02 -#define BMA220_REG_ACCEL_Y 0x03 -#define BMA220_REG_ACCEL_Z 0x04 -#define BMA220_REG_RANGE 0x11 -#define BMA220_REG_SUSPEND 0x18 - -#define BMA220_CHIP_ID 0xDD -#define BMA220_READ_MASK BIT(7) -#define BMA220_RANGE_MASK GENMASK(1, 0) -#define BMA220_SUSPEND_SLEEP 0xFF -#define BMA220_SUSPEND_WAKE 0x00 - -#define BMA220_DEVICE_NAME "bma220" - -#define BMA220_ACCEL_CHANNEL(index, reg, axis) { \ - .type = IIO_ACCEL, \ - .address = reg, \ - .modified = 1, \ - .channel2 = IIO_MOD_##axis, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ - .scan_index = index, \ - .scan_type = { \ - .sign = 's', \ - .realbits = 6, \ - .storagebits = 8, \ - .shift = 2, \ - .endianness = IIO_CPU, \ - }, \ -} - -enum bma220_axis { - AXIS_X, - AXIS_Y, - AXIS_Z, -}; - -static const int bma220_scale_table[][2] = { - {0, 623000}, {1, 248000}, {2, 491000}, {4, 983000}, -}; - -struct bma220_data { - struct spi_device *spi_device; - struct mutex lock; - struct { - s8 chans[3]; - /* Ensure timestamp is naturally aligned. */ - aligned_s64 timestamp; - } scan; - u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); -}; - -static const struct iio_chan_spec bma220_channels[] = { - BMA220_ACCEL_CHANNEL(0, BMA220_REG_ACCEL_X, X), - BMA220_ACCEL_CHANNEL(1, BMA220_REG_ACCEL_Y, Y), - BMA220_ACCEL_CHANNEL(2, BMA220_REG_ACCEL_Z, Z), - IIO_CHAN_SOFT_TIMESTAMP(3), -}; - -static inline int bma220_read_reg(struct spi_device *spi, u8 reg) +static int bma220_spi_probe(struct spi_device *spi) { - return spi_w8r8(spi, reg | BMA220_READ_MASK); + return bma220_common_probe(spi); } -static const unsigned long bma220_accel_scan_masks[] = { - BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), - 0 -}; - -static irqreturn_t bma220_trigger_handler(int irq, void *p) -{ - int ret; - struct iio_poll_func *pf = p; - struct iio_dev *indio_dev = pf->indio_dev; - struct bma220_data *data = iio_priv(indio_dev); - struct spi_device *spi = data->spi_device; - - mutex_lock(&data->lock); - data->tx_buf[0] = BMA220_REG_ACCEL_X | BMA220_READ_MASK; - ret = spi_write_then_read(spi, data->tx_buf, 1, &data->scan.chans, - ARRAY_SIZE(bma220_channels) - 1); - if (ret < 0) - goto err; - - iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan), - pf->timestamp); -err: - mutex_unlock(&data->lock); - iio_trigger_notify_done(indio_dev->trig); - - return IRQ_HANDLED; -} - -static int bma220_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, int *val2, long mask) -{ - int ret; - u8 range_idx; - struct bma220_data *data = iio_priv(indio_dev); - - switch (mask) { - case IIO_CHAN_INFO_RAW: - ret = bma220_read_reg(data->spi_device, chan->address); - if (ret < 0) - return -EINVAL; - *val = sign_extend32(ret >> chan->scan_type.shift, - chan->scan_type.realbits - 1); - return IIO_VAL_INT; - case IIO_CHAN_INFO_SCALE: - ret = bma220_read_reg(data->spi_device, BMA220_REG_RANGE); - if (ret < 0) - return ret; - range_idx = ret & BMA220_RANGE_MASK; - *val = bma220_scale_table[range_idx][0]; - *val2 = bma220_scale_table[range_idx][1]; - return IIO_VAL_INT_PLUS_MICRO; - } - - return -EINVAL; -} - -static int bma220_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, int val2, long mask) -{ - int i; - int ret; - int index = -1; - struct bma220_data *data = iio_priv(indio_dev); - - switch (mask) { - case IIO_CHAN_INFO_SCALE: - for (i = 0; i < ARRAY_SIZE(bma220_scale_table); i++) - if (val == bma220_scale_table[i][0] && - val2 == bma220_scale_table[i][1]) { - index = i; - break; - } - if (index < 0) - return -EINVAL; - - mutex_lock(&data->lock); - data->tx_buf[0] = BMA220_REG_RANGE; - data->tx_buf[1] = index; - ret = spi_write(data->spi_device, data->tx_buf, - sizeof(data->tx_buf)); - if (ret < 0) - dev_err(&data->spi_device->dev, - "failed to set measurement range\n"); - mutex_unlock(&data->lock); - - return 0; - } - - return -EINVAL; -} - -static int bma220_read_avail(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - const int **vals, int *type, int *length, - long mask) -{ - switch (mask) { - case IIO_CHAN_INFO_SCALE: - *vals = (int *)bma220_scale_table; - *type = IIO_VAL_INT_PLUS_MICRO; - *length = ARRAY_SIZE(bma220_scale_table) * 2; - return IIO_AVAIL_LIST; - default: - return -EINVAL; - } -} - -static const struct iio_info bma220_info = { - .read_raw = bma220_read_raw, - .write_raw = bma220_write_raw, - .read_avail = bma220_read_avail, -}; - -static int bma220_power(struct spi_device *spi, bool up) -{ - int ret; - unsigned int i; - - /* - * The chip can be suspended/woken up by a simple register read. - * So, we need up to 2 register reads of the suspend register - * to make sure that the device is in the desired state. - */ - for (i = 0; i < 2; i++) { - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); - if (ret < 0) - return ret; - - if (up && ret == BMA220_SUSPEND_SLEEP) - return 0; - - if (!up && ret == BMA220_SUSPEND_WAKE) - return 0; - } - - return -EBUSY; -} - -static int bma220_init(struct spi_device *spi) -{ - int ret; - struct device *dev = &spi->dev; - - ret = bma220_read_reg(spi, BMA220_REG_ID); - if (ret < 0) - return dev_err_probe(dev, ret, - "Failed to read chip id register\n"); - - if (ret != BMA220_CHIP_ID) - dev_info(dev, "Unknown chip found: 0x%02x\n", ret); - - /* Make sure the chip is powered on */ - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); - if (ret == BMA220_SUSPEND_WAKE) - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); - if (ret < 0) - return ret; - if (ret == BMA220_SUSPEND_WAKE) - return -EBUSY; - - return 0; -} - -static void bma220_deinit(void *spi) -{ - bma220_power(spi, false); -} - -static int bma220_probe(struct spi_device *spi) -{ - int ret; - struct iio_dev *indio_dev; - struct bma220_data *data; - struct device *dev = &spi->dev; - - indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); - if (!indio_dev) - return -ENOMEM; - - data = iio_priv(indio_dev); - data->spi_device = spi; - mutex_init(&data->lock); - - indio_dev->info = &bma220_info; - indio_dev->name = BMA220_DEVICE_NAME; - indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = bma220_channels; - indio_dev->num_channels = ARRAY_SIZE(bma220_channels); - indio_dev->available_scan_masks = bma220_accel_scan_masks; - - ret = bma220_init(data->spi_device); - if (ret) - return ret; - - ret = devm_add_action_or_reset(dev, bma220_deinit, spi); - if (ret) - return ret; - - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - bma220_trigger_handler, NULL); - if (ret < 0) { - dev_err(dev, "iio triggered buffer setup failed\n"); - return ret; - } - - return devm_iio_device_register(dev, indio_dev); -} - -static int bma220_suspend(struct device *dev) -{ - struct spi_device *spi = to_spi_device(dev); - - return bma220_power(spi, false); -} - -static int bma220_resume(struct device *dev) -{ - struct spi_device *spi = to_spi_device(dev); - - return bma220_power(spi, true); -} -static DEFINE_SIMPLE_DEV_PM_OPS(bma220_pm_ops, bma220_suspend, bma220_resume); - static const struct spi_device_id bma220_spi_id[] = { {"bma220", 0}, { } @@ -323,17 +28,18 @@ static const struct acpi_device_id bma220_acpi_id[] = { }; MODULE_DEVICE_TABLE(spi, bma220_spi_id); -static struct spi_driver bma220_driver = { +static struct spi_driver bma220_spi_driver = { .driver = { .name = "bma220_spi", .pm = pm_sleep_ptr(&bma220_pm_ops), .acpi_match_table = bma220_acpi_id, }, - .probe = bma220_probe, + .probe = bma220_spi_probe, .id_table = bma220_spi_id, }; -module_spi_driver(bma220_driver); +module_spi_driver(bma220_spi_driver); MODULE_AUTHOR("Tiberiu Breana "); -MODULE_DESCRIPTION("BMA220 acceleration sensor driver"); +MODULE_DESCRIPTION("BMA220 triaxial acceleration sensor spi driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_BOSCH_BMA220"); From 4a719f182674d30f060dde7414ba7d265fb0388c Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:17 +0300 Subject: [PATCH 053/304] iio: accel: bma220: add open firmware table Add open firmware entry to the spi driver. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_spi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 761f475a5942..e1c25f48d9b3 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -28,10 +28,17 @@ static const struct acpi_device_id bma220_acpi_id[] = { }; MODULE_DEVICE_TABLE(spi, bma220_spi_id); +static const struct of_device_id bma220_of_spi_match[] = { + { .compatible = "bosch,bma220" }, + { } +}; +MODULE_DEVICE_TABLE(of, bma220_of_spi_match); + static struct spi_driver bma220_spi_driver = { .driver = { .name = "bma220_spi", .pm = pm_sleep_ptr(&bma220_pm_ops), + .of_match_table = bma220_of_spi_match, .acpi_match_table = bma220_acpi_id, }, .probe = bma220_spi_probe, From dfea5f181c9238bead123f777d5f3b401dae432e Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:18 +0300 Subject: [PATCH 054/304] iio: accel: bma220: turn power supplies on Add devm_regulator_bulk_get_enable() to device probe(). Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 050282f20d90..31fbea971230 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -231,6 +232,12 @@ static int bma220_init(struct spi_device *spi) { int ret; struct device *dev = &spi->dev; + static const char * const regulator_names[] = { "vddd", "vddio", "vdda" }; + + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names), + regulator_names); + if (ret) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); ret = bma220_read_reg(spi, BMA220_REG_ID); if (ret < 0) From 2027b1a201eafe1697b34a5d87c41127864eb4f9 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:19 +0300 Subject: [PATCH 055/304] iio: accel: bma220: reset registers during init stage Bring all configuration registers to default values during device probe(). Remove trivial code duplication regarding bma220_power() in _init() Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 44 +++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 31fbea971230..c2ed789f9658 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -29,12 +29,15 @@ #define BMA220_REG_ACCEL_Z 0x04 #define BMA220_REG_RANGE 0x11 #define BMA220_REG_SUSPEND 0x18 +#define BMA220_REG_SOFTRESET 0x19 #define BMA220_CHIP_ID 0xDD #define BMA220_READ_MASK BIT(7) #define BMA220_RANGE_MASK GENMASK(1, 0) #define BMA220_SUSPEND_SLEEP 0xFF #define BMA220_SUSPEND_WAKE 0x00 +#define BMA220_RESET_MODE 0xFF +#define BMA220_NONRESET_MODE 0x00 #define BMA220_DEVICE_NAME "bma220" @@ -203,6 +206,31 @@ static const struct iio_info bma220_info = { .read_avail = bma220_read_avail, }; +static int bma220_reset(struct spi_device *spi, bool up) +{ + int ret; + unsigned int i; + + /* + * The chip can be reset by a simple register read. + * We need up to 2 register reads of the softreset register + * to make sure that the device is in the desired state. + */ + for (i = 0; i < 2; i++) { + ret = bma220_read_reg(spi, BMA220_REG_SOFTRESET); + if (ret < 0) + return ret; + + if (up && ret == BMA220_RESET_MODE) + return 0; + + if (!up && ret == BMA220_NONRESET_MODE) + return 0; + } + + return -EBUSY; +} + static int bma220_power(struct spi_device *spi, bool up) { int ret; @@ -247,14 +275,14 @@ static int bma220_init(struct spi_device *spi) if (ret != BMA220_CHIP_ID) dev_info(dev, "Unknown chip found: 0x%02x\n", ret); - /* Make sure the chip is powered on */ - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); - if (ret == BMA220_SUSPEND_WAKE) - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); - if (ret < 0) - return ret; - if (ret == BMA220_SUSPEND_WAKE) - return -EBUSY; + /* Make sure the chip is powered on and config registers are reset */ + ret = bma220_power(spi, true); + if (ret) + return dev_err_probe(dev, ret, "Failed to power-on chip\n"); + + ret = bma220_reset(spi, true); + if (ret) + return dev_err_probe(dev, ret, "Failed to soft reset chip\n"); return 0; } From 5c27f1332282522de8da839bbdd2d1b2f0a6c960 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:20 +0300 Subject: [PATCH 056/304] iio: accel: bma220: migrate to regmap API Switch to regmap API. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/Kconfig | 2 + drivers/iio/accel/bma220.h | 6 +- drivers/iio/accel/bma220_core.c | 231 ++++++++++++++++++++++---------- drivers/iio/accel/bma220_spi.c | 10 +- 4 files changed, 172 insertions(+), 77 deletions(-) diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig index 4648be329917..988fe4b1f9a5 100644 --- a/drivers/iio/accel/Kconfig +++ b/drivers/iio/accel/Kconfig @@ -219,6 +219,7 @@ config BMA180 config BMA220 tristate "Bosch BMA220 3-Axis Accelerometer Driver" depends on SPI + select REGMAP select IIO_BUFFER select IIO_TRIGGERED_BUFFER select BMA220_SPI if SPI @@ -232,6 +233,7 @@ config BMA220 config BMA220_SPI tristate + select REGMAP_SPI depends on BMA220 config BMA400 diff --git a/drivers/iio/accel/bma220.h b/drivers/iio/accel/bma220.h index b181f2b510fd..695f491bc5a0 100644 --- a/drivers/iio/accel/bma220.h +++ b/drivers/iio/accel/bma220.h @@ -9,11 +9,13 @@ #define _BMA220_H #include +#include -struct spi_device; +struct device; +extern const struct regmap_config bma220_spi_regmap_config; extern const struct dev_pm_ops bma220_pm_ops; -int bma220_common_probe(struct spi_device *dev); +int bma220_common_probe(struct device *dev, struct regmap *regmap, int irq); #endif diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index c2ed789f9658..9a9fc98186a0 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -3,17 +3,21 @@ * BMA220 Digital triaxial acceleration sensor driver * * Copyright (c) 2016,2020 Intel Corporation. + * Copyright (c) 2025 Petre Rodan */ #include +#include +#include +#include #include #include #include #include #include +#include #include #include -#include #include #include @@ -24,16 +28,63 @@ #include "bma220.h" #define BMA220_REG_ID 0x00 +#define BMA220_REG_REVISION_ID 0x01 #define BMA220_REG_ACCEL_X 0x02 #define BMA220_REG_ACCEL_Y 0x03 #define BMA220_REG_ACCEL_Z 0x04 +#define BMA220_REG_CONF0 0x05 +#define BMA220_HIGH_DUR_MSK GENMASK(5, 0) +#define BMA220_HIGH_HY_MSK GENMASK(7, 6) +#define BMA220_REG_CONF1 0x06 +#define BMA220_HIGH_TH_MSK GENMASK(3, 0) +#define BMA220_LOW_TH_MSK GENMASK(7, 4) +#define BMA220_REG_CONF2 0x07 +#define BMA220_LOW_DUR_MSK GENMASK(5, 0) +#define BMA220_LOW_HY_MSK GENMASK(7, 6) +#define BMA220_REG_CONF3 0x08 +#define BMA220_TT_DUR_MSK GENMASK(2, 0) +#define BMA220_TT_TH_MSK GENMASK(6, 3) +#define BMA220_REG_CONF4 0x09 +#define BMA220_SLOPE_DUR_MSK GENMASK(1, 0) +#define BMA220_SLOPE_TH_MSK GENMASK(5, 2) +#define BMA220_REG_CONF5 0x0a +#define BMA220_TIP_EN_MSK BIT(4) +#define BMA220_REG_IF0 0x0b +#define BMA220_REG_IF1 0x0c +#define BMA220_IF_SLOPE BIT(0) +#define BMA220_IF_DRDY BIT(1) +#define BMA220_IF_HIGH BIT(2) +#define BMA220_IF_LOW BIT(3) +#define BMA220_IF_TT BIT(4) +#define BMA220_REG_IE0 0x0d +#define BMA220_INT_EN_TAP_Z_MSK BIT(0) +#define BMA220_INT_EN_TAP_Y_MSK BIT(1) +#define BMA220_INT_EN_TAP_X_MSK BIT(2) +#define BMA220_INT_EN_SLOPE_Z_MSK BIT(3) +#define BMA220_INT_EN_SLOPE_Y_MSK BIT(4) +#define BMA220_INT_EN_SLOPE_X_MSK BIT(5) +#define BMA220_INT_EN_DRDY_MSK BIT(7) +#define BMA220_REG_IE1 0x0e +#define BMA220_INT_EN_HIGH_Z_MSK BIT(0) +#define BMA220_INT_EN_HIGH_Y_MSK BIT(1) +#define BMA220_INT_EN_HIGH_X_MSK BIT(2) +#define BMA220_INT_EN_LOW_MSK BIT(3) +#define BMA220_INT_LATCH_MSK GENMASK(6, 4) +#define BMA220_INT_RST_MSK BIT(7) +#define BMA220_REG_IE2 0x0f +#define BMA220_REG_FILTER 0x10 +#define BMA220_FILTER_MASK GENMASK(3, 0) #define BMA220_REG_RANGE 0x11 +#define BMA220_RANGE_MASK GENMASK(1, 0) +#define BMA220_REG_WDT 0x17 +#define BMA220_WDT_MASK GENMASK(2, 1) +#define BMA220_WDT_OFF 0x0 +#define BMA220_WDT_1MS 0x2 +#define BMA220_WDT_10MS 0x3 #define BMA220_REG_SUSPEND 0x18 #define BMA220_REG_SOFTRESET 0x19 #define BMA220_CHIP_ID 0xDD -#define BMA220_READ_MASK BIT(7) -#define BMA220_RANGE_MASK GENMASK(1, 0) #define BMA220_SUSPEND_SLEEP 0xFF #define BMA220_SUSPEND_WAKE 0x00 #define BMA220_RESET_MODE 0xFF @@ -69,14 +120,14 @@ static const int bma220_scale_table[][2] = { }; struct bma220_data { - struct spi_device *spi_device; + struct regmap *regmap; struct mutex lock; + u8 range_idx; struct { s8 chans[3]; /* Ensure timestamp is naturally aligned. */ aligned_s64 timestamp; - } scan; - u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); + } scan __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec bma220_channels[] = { @@ -86,35 +137,57 @@ static const struct iio_chan_spec bma220_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(3), }; -static inline int bma220_read_reg(struct spi_device *spi, u8 reg) -{ - return spi_w8r8(spi, reg | BMA220_READ_MASK); -} - static const unsigned long bma220_accel_scan_masks[] = { BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0 }; +static bool bma220_is_writable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case BMA220_REG_CONF0: + case BMA220_REG_CONF1: + case BMA220_REG_CONF2: + case BMA220_REG_CONF3: + case BMA220_REG_CONF4: + case BMA220_REG_CONF5: + case BMA220_REG_IE0: + case BMA220_REG_IE1: + case BMA220_REG_IE2: + case BMA220_REG_FILTER: + case BMA220_REG_RANGE: + case BMA220_REG_WDT: + return true; + default: + return false; + } +} + +const struct regmap_config bma220_spi_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .read_flag_mask = BIT(7), + .max_register = BMA220_REG_SOFTRESET, + .cache_type = REGCACHE_NONE, + .writeable_reg = bma220_is_writable_reg, +}; +EXPORT_SYMBOL_NS_GPL(bma220_spi_regmap_config, "IIO_BOSCH_BMA220"); + static irqreturn_t bma220_trigger_handler(int irq, void *p) { int ret; struct iio_poll_func *pf = p; struct iio_dev *indio_dev = pf->indio_dev; struct bma220_data *data = iio_priv(indio_dev); - struct spi_device *spi = data->spi_device; - mutex_lock(&data->lock); - data->tx_buf[0] = BMA220_REG_ACCEL_X | BMA220_READ_MASK; - ret = spi_write_then_read(spi, data->tx_buf, 1, &data->scan.chans, - ARRAY_SIZE(bma220_channels) - 1); + ret = regmap_bulk_read(data->regmap, BMA220_REG_ACCEL_X, + &data->scan.chans, + sizeof(data->scan.chans)); if (ret < 0) - goto err; + return IRQ_NONE; iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan), pf->timestamp); -err: - mutex_unlock(&data->lock); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; @@ -125,24 +198,24 @@ static int bma220_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { int ret; - u8 range_idx; + u8 index; + unsigned int reg; struct bma220_data *data = iio_priv(indio_dev); + guard(mutex)(&data->lock); + switch (mask) { case IIO_CHAN_INFO_RAW: - ret = bma220_read_reg(data->spi_device, chan->address); + ret = regmap_read(data->regmap, chan->address, ®); if (ret < 0) return -EINVAL; - *val = sign_extend32(ret >> chan->scan_type.shift, + *val = sign_extend32(reg >> chan->scan_type.shift, chan->scan_type.realbits - 1); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - ret = bma220_read_reg(data->spi_device, BMA220_REG_RANGE); - if (ret < 0) - return ret; - range_idx = ret & BMA220_RANGE_MASK; - *val = bma220_scale_table[range_idx][0]; - *val2 = bma220_scale_table[range_idx][1]; + index = data->range_idx; + *val = bma220_scale_table[index][0]; + *val2 = bma220_scale_table[index][1]; return IIO_VAL_INT_PLUS_MICRO; } @@ -158,6 +231,8 @@ static int bma220_write_raw(struct iio_dev *indio_dev, int index = -1; struct bma220_data *data = iio_priv(indio_dev); + guard(mutex)(&data->lock); + switch (mask) { case IIO_CHAN_INFO_SCALE: for (i = 0; i < ARRAY_SIZE(bma220_scale_table); i++) @@ -169,14 +244,12 @@ static int bma220_write_raw(struct iio_dev *indio_dev, if (index < 0) return -EINVAL; - mutex_lock(&data->lock); - data->tx_buf[0] = BMA220_REG_RANGE; - data->tx_buf[1] = index; - ret = spi_write(data->spi_device, data->tx_buf, - sizeof(data->tx_buf)); + ret = regmap_update_bits(data->regmap, BMA220_REG_RANGE, + BMA220_RANGE_MASK, + FIELD_PREP(BMA220_RANGE_MASK, index)); if (ret < 0) return ret; - mutex_unlock(&data->lock); + data->range_idx = index; return 0; } @@ -206,10 +279,10 @@ static const struct iio_info bma220_info = { .read_avail = bma220_read_avail, }; -static int bma220_reset(struct spi_device *spi, bool up) +static int bma220_reset(struct bma220_data *data, bool up) { int ret; - unsigned int i; + unsigned int i, val; /* * The chip can be reset by a simple register read. @@ -217,24 +290,24 @@ static int bma220_reset(struct spi_device *spi, bool up) * to make sure that the device is in the desired state. */ for (i = 0; i < 2; i++) { - ret = bma220_read_reg(spi, BMA220_REG_SOFTRESET); + ret = regmap_read(data->regmap, BMA220_REG_SOFTRESET, &val); if (ret < 0) return ret; - if (up && ret == BMA220_RESET_MODE) + if (up && val == BMA220_RESET_MODE) return 0; - if (!up && ret == BMA220_NONRESET_MODE) + if (!up && val == BMA220_NONRESET_MODE) return 0; } return -EBUSY; } -static int bma220_power(struct spi_device *spi, bool up) +static int bma220_power(struct bma220_data *data, bool up) { int ret; - unsigned int i; + unsigned int i, val; /* * The chip can be suspended/woken up by a simple register read. @@ -242,70 +315,84 @@ static int bma220_power(struct spi_device *spi, bool up) * to make sure that the device is in the desired state. */ for (i = 0; i < 2; i++) { - ret = bma220_read_reg(spi, BMA220_REG_SUSPEND); + ret = regmap_read(data->regmap, BMA220_REG_SUSPEND, &val); if (ret < 0) return ret; - if (up && ret == BMA220_SUSPEND_SLEEP) + if (up && val == BMA220_SUSPEND_SLEEP) return 0; - if (!up && ret == BMA220_SUSPEND_WAKE) + if (!up && val == BMA220_SUSPEND_WAKE) return 0; } return -EBUSY; } -static int bma220_init(struct spi_device *spi) +static int bma220_init(struct device *dev, struct bma220_data *data) { int ret; - struct device *dev = &spi->dev; + unsigned int val; static const char * const regulator_names[] = { "vddd", "vddio", "vdda" }; - ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names), + ret = devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(regulator_names), regulator_names); if (ret) return dev_err_probe(dev, ret, "Failed to get regulators\n"); - ret = bma220_read_reg(spi, BMA220_REG_ID); - if (ret < 0) + ret = regmap_read(data->regmap, BMA220_REG_ID, &val); + if (ret) return dev_err_probe(dev, ret, "Failed to read chip id register\n"); - if (ret != BMA220_CHIP_ID) - dev_info(dev, "Unknown chip found: 0x%02x\n", ret); + if (val != BMA220_CHIP_ID) + dev_info(dev, "Unknown chip found: 0x%02x\n", val); - /* Make sure the chip is powered on and config registers are reset */ - ret = bma220_power(spi, true); + ret = bma220_power(data, true); if (ret) return dev_err_probe(dev, ret, "Failed to power-on chip\n"); - ret = bma220_reset(spi, true); + ret = bma220_reset(data, true); if (ret) return dev_err_probe(dev, ret, "Failed to soft reset chip\n"); return 0; } -static void bma220_deinit(void *spi) +static void bma220_deinit(void *data_ptr) { - bma220_power(spi, false); + struct bma220_data *data = data_ptr; + int ret; + struct device *dev = regmap_get_device(data->regmap); + + ret = bma220_power(data, false); + if (ret) + dev_warn(dev, + "Failed to put device into suspend mode (%pe)\n", + ERR_PTR(ret)); } -int bma220_common_probe(struct spi_device *spi) +int bma220_common_probe(struct device *dev, struct regmap *regmap, int irq) { int ret; struct iio_dev *indio_dev; struct bma220_data *data; - struct device *dev = &spi->dev; indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); if (!indio_dev) return -ENOMEM; data = iio_priv(indio_dev); - data->spi_device = spi; - mutex_init(&data->lock); + data->regmap = regmap; + + ret = bma220_init(dev, data); + if (ret) + return ret; + + ret = devm_mutex_init(dev, &data->lock); + if (ret) + return ret; indio_dev->info = &bma220_info; indio_dev->name = BMA220_DEVICE_NAME; @@ -314,38 +401,34 @@ int bma220_common_probe(struct spi_device *spi) indio_dev->num_channels = ARRAY_SIZE(bma220_channels); indio_dev->available_scan_masks = bma220_accel_scan_masks; - ret = bma220_init(data->spi_device); - if (ret) - return ret; - - ret = devm_add_action_or_reset(dev, bma220_deinit, spi); + ret = devm_add_action_or_reset(dev, bma220_deinit, data); if (ret) return ret; ret = devm_iio_triggered_buffer_setup(dev, indio_dev, iio_pollfunc_store_time, bma220_trigger_handler, NULL); - if (ret < 0) { - dev_err(dev, "iio triggered buffer setup failed\n"); - return ret; - } + if (ret < 0) + dev_err_probe(dev, ret, "iio triggered buffer setup failed\n"); return devm_iio_device_register(dev, indio_dev); } -EXPORT_SYMBOL_NS(bma220_common_probe, "IIO_BOSCH_BMA220"); +EXPORT_SYMBOL_NS_GPL(bma220_common_probe, "IIO_BOSCH_BMA220"); static int bma220_suspend(struct device *dev) { - struct spi_device *spi = to_spi_device(dev); + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct bma220_data *data = iio_priv(indio_dev); - return bma220_power(spi, false); + return bma220_power(data, false); } static int bma220_resume(struct device *dev) { - struct spi_device *spi = to_spi_device(dev); + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct bma220_data *data = iio_priv(indio_dev); - return bma220_power(spi, true); + return bma220_power(data, true); } EXPORT_NS_SIMPLE_DEV_PM_OPS(bma220_pm_ops, bma220_suspend, bma220_resume, IIO_BOSCH_BMA220); diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index e1c25f48d9b3..7aced4017373 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -7,6 +7,7 @@ #include #include +#include #include #include @@ -14,7 +15,14 @@ static int bma220_spi_probe(struct spi_device *spi) { - return bma220_common_probe(spi); + struct regmap *regmap; + + regmap = devm_regmap_init_spi(spi, &bma220_spi_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(regmap), + "failed to create regmap\n"); + + return bma220_common_probe(&spi->dev, regmap, spi->irq); } static const struct spi_device_id bma220_spi_id[] = { From 480f08a6892e3de415c8063121d5e198c4120ed7 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:21 +0300 Subject: [PATCH 057/304] iio: accel: bma220: populate buffer ts in trigger handler Populate buffer timestamps in trigger handler since not all triggers can run the top half handler that provides pf->timestamp. Fixes failing unit test that triggers based on the INT signal. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 9a9fc98186a0..6975076802a2 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -187,7 +187,7 @@ static irqreturn_t bma220_trigger_handler(int irq, void *p) return IRQ_NONE; iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan), - pf->timestamp); + iio_get_time_ns(indio_dev)); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; @@ -405,8 +405,7 @@ int bma220_common_probe(struct device *dev, struct regmap *regmap, int irq) if (ret) return ret; - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, bma220_trigger_handler, NULL); if (ret < 0) dev_err_probe(dev, ret, "iio triggered buffer setup failed\n"); From 0e3c7fd44244a1dbb925ade1a87e699bdea03dab Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:22 +0300 Subject: [PATCH 058/304] iio: accel: bma220: use find_match_table fct Clean up the code a bit by using a find_match_table function. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 6975076802a2..404fea26e3f7 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -222,11 +222,23 @@ static int bma220_read_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int bma220_find_match_2dt(const int (*tbl)[2], const int n, + const int val, const int val2) +{ + int i; + + for (i = 0; i < n; i++) { + if (tbl[i][0] == val && tbl[i][1] == val2) + return i; + } + + return -EINVAL; +} + static int bma220_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { - int i; int ret; int index = -1; struct bma220_data *data = iio_priv(indio_dev); @@ -235,12 +247,9 @@ static int bma220_write_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_SCALE: - for (i = 0; i < ARRAY_SIZE(bma220_scale_table); i++) - if (val == bma220_scale_table[i][0] && - val2 == bma220_scale_table[i][1]) { - index = i; - break; - } + index = bma220_find_match_2dt(bma220_scale_table, + ARRAY_SIZE(bma220_scale_table), + val, val2); if (index < 0) return -EINVAL; From 7a23e6d922efc77e783084c4f3b2859c2a0bc7f3 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:23 +0300 Subject: [PATCH 059/304] iio: accel: bma220: add i2c module Add the bma220_i2c module. Note that this kernel module transparently shifts all register addresses 1 bit to the left, so all functions will operate based on the SPI memory map. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/Kconfig | 11 +++++-- drivers/iio/accel/Makefile | 1 + drivers/iio/accel/bma220.h | 1 + drivers/iio/accel/bma220_core.c | 18 ++++++++++ drivers/iio/accel/bma220_i2c.c | 58 +++++++++++++++++++++++++++++++++ 5 files changed, 87 insertions(+), 2 deletions(-) create mode 100644 drivers/iio/accel/bma220_i2c.c diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig index 988fe4b1f9a5..76911278fb21 100644 --- a/drivers/iio/accel/Kconfig +++ b/drivers/iio/accel/Kconfig @@ -218,10 +218,11 @@ config BMA180 config BMA220 tristate "Bosch BMA220 3-Axis Accelerometer Driver" - depends on SPI + depends on I2C || SPI select REGMAP select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select BMA220_I2C if I2C select BMA220_SPI if SPI help Say yes here to add support for the Bosch BMA220 triaxial @@ -229,7 +230,13 @@ config BMA220 To compile this driver as a module, choose M here: the module will be called bma220_core and you will also get - bma220_spi if SPI is enabled. + bma220_i2c if I2C is enabled and bma220_spi if SPI is + enabled. + +config BMA220_I2C + tristate + select REGMAP_I2C + depends on BMA220 config BMA220_SPI tristate diff --git a/drivers/iio/accel/Makefile b/drivers/iio/accel/Makefile index 56a9f848f7f9..fa440a859283 100644 --- a/drivers/iio/accel/Makefile +++ b/drivers/iio/accel/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_ADXL380_I2C) += adxl380_i2c.o obj-$(CONFIG_ADXL380_SPI) += adxl380_spi.o obj-$(CONFIG_BMA180) += bma180.o obj-$(CONFIG_BMA220) += bma220_core.o +obj-$(CONFIG_BMA220_I2C) += bma220_i2c.o obj-$(CONFIG_BMA220_SPI) += bma220_spi.o obj-$(CONFIG_BMA400) += bma400_core.o obj-$(CONFIG_BMA400_I2C) += bma400_i2c.o diff --git a/drivers/iio/accel/bma220.h b/drivers/iio/accel/bma220.h index 695f491bc5a0..e53ca63de54b 100644 --- a/drivers/iio/accel/bma220.h +++ b/drivers/iio/accel/bma220.h @@ -13,6 +13,7 @@ struct device; +extern const struct regmap_config bma220_i2c_regmap_config; extern const struct regmap_config bma220_spi_regmap_config; extern const struct dev_pm_ops bma220_pm_ops; diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 404fea26e3f7..050827bfb9e6 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -173,6 +173,24 @@ const struct regmap_config bma220_spi_regmap_config = { }; EXPORT_SYMBOL_NS_GPL(bma220_spi_regmap_config, "IIO_BOSCH_BMA220"); +/* + * Based on the datasheet the memory map differs between the SPI and the I2C + * implementations. I2C register addresses are simply shifted to the left + * by 1 bit yet the register size remains unchanged. + * This driver employs the SPI memory map to correlate register names to + * addresses regardless of the bus type. + */ + +const struct regmap_config bma220_i2c_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .reg_shift = -1, + .max_register = BMA220_REG_SOFTRESET, + .cache_type = REGCACHE_NONE, + .writeable_reg = bma220_is_writable_reg, +}; +EXPORT_SYMBOL_NS_GPL(bma220_i2c_regmap_config, "IIO_BOSCH_BMA220"); + static irqreturn_t bma220_trigger_handler(int irq, void *p) { int ret; diff --git a/drivers/iio/accel/bma220_i2c.c b/drivers/iio/accel/bma220_i2c.c new file mode 100644 index 000000000000..5dc7c38f53b3 --- /dev/null +++ b/drivers/iio/accel/bma220_i2c.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Bosch triaxial acceleration sensor + * + * Copyright (c) 2025 Petre Rodan + * + * Datasheet: https://media.digikey.com/pdf/Data%20Sheets/Bosch/BMA220.pdf + * I2C address is either 0x0b or 0x0a depending on CSB (pin 10) + */ + +#include +#include +#include +#include +#include +#include + +#include "bma220.h" + +static int bma220_i2c_probe(struct i2c_client *client) +{ + struct regmap *regmap; + + regmap = devm_regmap_init_i2c(client, &bma220_i2c_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(&client->dev, PTR_ERR(regmap), + "failed to create regmap\n"); + + return bma220_common_probe(&client->dev, regmap, client->irq); +} + +static const struct of_device_id bma220_i2c_match[] = { + { .compatible = "bosch,bma220" }, + { } +}; +MODULE_DEVICE_TABLE(of, bma220_i2c_match); + +static const struct i2c_device_id bma220_i2c_id[] = { + { "bma220" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, bma220_i2c_id); + +static struct i2c_driver bma220_i2c_driver = { + .driver = { + .name = "bma220_i2c", + .pm = pm_sleep_ptr(&bma220_pm_ops), + .of_match_table = bma220_i2c_match, + }, + .probe = bma220_i2c_probe, + .id_table = bma220_i2c_id, +}; +module_i2c_driver(bma220_i2c_driver); + +MODULE_AUTHOR("Petre Rodan "); +MODULE_DESCRIPTION("Bosch triaxial acceleration sensor i2c driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_BOSCH_BMA220"); From 3499375209ca839a741e775d579f8bb9b85529d5 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:24 +0300 Subject: [PATCH 060/304] iio: accel: bma220: add i2c watchdog feature Sometimes the sensor gets stuck and enters a condition in which it pulls SDA low, thus making the entire i2c bus unusable. This problem is mitigated by activating a 1ms watchdog implemented in the sensor. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 050827bfb9e6..38a2f36783cd 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -356,6 +357,12 @@ static int bma220_power(struct bma220_data *data, bool up) return -EBUSY; } +static int bma220_set_wdt(struct bma220_data *data, const u8 val) +{ + return regmap_update_bits(data->regmap, BMA220_REG_WDT, BMA220_WDT_MASK, + FIELD_PREP(BMA220_WDT_MASK, val)); +} + static int bma220_init(struct device *dev, struct bma220_data *data) { int ret; @@ -384,6 +391,13 @@ static int bma220_init(struct device *dev, struct bma220_data *data) if (ret) return dev_err_probe(dev, ret, "Failed to soft reset chip\n"); + if (i2c_verify_client(dev)) { + ret = bma220_set_wdt(data, BMA220_WDT_1MS); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set i2c watchdog\n"); + } + return 0; } From b7e17ca107931c83c4b4edc8a02118121fe8ab9e Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:25 +0300 Subject: [PATCH 061/304] iio: accel: bma220: add interrupt trigger Add interrupt trigger. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 58 +++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 38a2f36783cd..08c4dec67d5e 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -124,6 +125,7 @@ struct bma220_data { struct regmap *regmap; struct mutex lock; u8 range_idx; + struct iio_trigger *trig; struct { s8 chans[3]; /* Ensure timestamp is naturally aligned. */ @@ -192,6 +194,22 @@ const struct regmap_config bma220_i2c_regmap_config = { }; EXPORT_SYMBOL_NS_GPL(bma220_i2c_regmap_config, "IIO_BOSCH_BMA220"); +static int bma220_data_rdy_trigger_set_state(struct iio_trigger *trig, + bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct bma220_data *data = iio_priv(indio_dev); + + return regmap_update_bits(data->regmap, BMA220_REG_IE0, + BMA220_INT_EN_DRDY_MSK, + FIELD_PREP(BMA220_INT_EN_DRDY_MSK, state)); +} + +static const struct iio_trigger_ops bma220_trigger_ops = { + .set_trigger_state = &bma220_data_rdy_trigger_set_state, + .validate_device = &iio_trigger_validate_own_device, +}; + static irqreturn_t bma220_trigger_handler(int irq, void *p) { int ret; @@ -414,6 +432,23 @@ static void bma220_deinit(void *data_ptr) ERR_PTR(ret)); } +static irqreturn_t bma220_irq_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct bma220_data *data = iio_priv(indio_dev); + int ret; + unsigned int bma220_reg_if1; + + ret = regmap_read(data->regmap, BMA220_REG_IF1, &bma220_reg_if1); + if (ret) + return IRQ_NONE; + + if (FIELD_GET(BMA220_IF_DRDY, bma220_reg_if1)) + iio_trigger_poll_nested(data->trig); + + return IRQ_HANDLED; +} + int bma220_common_probe(struct device *dev, struct regmap *regmap, int irq) { int ret; @@ -442,6 +477,29 @@ int bma220_common_probe(struct device *dev, struct regmap *regmap, int irq) indio_dev->num_channels = ARRAY_SIZE(bma220_channels); indio_dev->available_scan_masks = bma220_accel_scan_masks; + if (irq > 0) { + data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!data->trig) + return -ENOMEM; + + data->trig->ops = &bma220_trigger_ops; + iio_trigger_set_drvdata(data->trig, indio_dev); + + ret = devm_iio_trigger_register(dev, data->trig); + if (ret) + return dev_err_probe(dev, ret, + "iio trigger register fail\n"); + indio_dev->trig = iio_trigger_get(data->trig); + ret = devm_request_threaded_irq(dev, irq, NULL, + &bma220_irq_handler, IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return dev_err_probe(dev, ret, + "request irq %d failed\n", irq); + } + ret = devm_add_action_or_reset(dev, bma220_deinit, data); if (ret) return ret; From 59a212d3c3d4cf239f4d1c71a19b47c0e72eca2d Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:26 +0300 Subject: [PATCH 062/304] iio: accel: bma220: add LPF cut-off frequency mapping Add mapping for the low pass filter cut-off frequency. Make valid values visible for both the cut-off frequency and the scale. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 59 ++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 08c4dec67d5e..0ceffc412664 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -94,13 +94,23 @@ #define BMA220_DEVICE_NAME "bma220" +#define BMA220_COF_1000Hz 0x0 +#define BMA220_COF_500Hz 0x1 +#define BMA220_COF_250Hz 0x2 +#define BMA220_COF_125Hz 0x3 +#define BMA220_COF_64Hz 0x4 +#define BMA220_COF_32Hz 0x5 + #define BMA220_ACCEL_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .address = reg, \ .modified = 1, \ .channel2 = IIO_MOD_##axis, \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) |\ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ .scan_index = index, \ .scan_type = { \ .sign = 's', \ @@ -124,6 +134,7 @@ static const int bma220_scale_table[][2] = { struct bma220_data { struct regmap *regmap; struct mutex lock; + u8 lpf_3dB_freq_idx; u8 range_idx; struct iio_trigger *trig; struct { @@ -140,6 +151,16 @@ static const struct iio_chan_spec bma220_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(3), }; +/* Available cut-off frequencies of the low pass filter in Hz. */ +static const int bma220_lpf_3dB_freq_Hz_table[] = { + [BMA220_COF_1000Hz] = 1000, + [BMA220_COF_500Hz] = 500, + [BMA220_COF_250Hz] = 250, + [BMA220_COF_125Hz] = 125, + [BMA220_COF_64Hz] = 64, + [BMA220_COF_32Hz] = 32, +}; + static const unsigned long bma220_accel_scan_masks[] = { BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0 @@ -254,6 +275,10 @@ static int bma220_read_raw(struct iio_dev *indio_dev, *val = bma220_scale_table[index][0]; *val2 = bma220_scale_table[index][1]; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + index = data->lpf_3dB_freq_idx; + *val = bma220_lpf_3dB_freq_Hz_table[index]; + return IIO_VAL_INT; } return -EINVAL; @@ -272,6 +297,18 @@ static int bma220_find_match_2dt(const int (*tbl)[2], const int n, return -EINVAL; } +static int bma220_find_match(const int *arr, const int n, const int val) +{ + int i; + + for (i = 0; i < n; i++) { + if (arr[i] == val) + return i; + } + + return -EINVAL; +} + static int bma220_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) @@ -297,6 +334,21 @@ static int bma220_write_raw(struct iio_dev *indio_dev, return ret; data->range_idx = index; + return 0; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + index = bma220_find_match(bma220_lpf_3dB_freq_Hz_table, + ARRAY_SIZE(bma220_lpf_3dB_freq_Hz_table), + val); + if (index < 0) + return -EINVAL; + + ret = regmap_update_bits(data->regmap, BMA220_REG_FILTER, + BMA220_FILTER_MASK, + FIELD_PREP(BMA220_FILTER_MASK, index)); + if (ret < 0) + return ret; + data->lpf_3dB_freq_idx = index; + return 0; } @@ -314,6 +366,11 @@ static int bma220_read_avail(struct iio_dev *indio_dev, *type = IIO_VAL_INT_PLUS_MICRO; *length = ARRAY_SIZE(bma220_scale_table) * 2; return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + *vals = (const int *)bma220_lpf_3dB_freq_Hz_table; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(bma220_lpf_3dB_freq_Hz_table); + return IIO_AVAIL_LIST; default: return -EINVAL; } From c3ee72998b33a5c9fc9ffc99b660a0f33c380af3 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:27 +0300 Subject: [PATCH 063/304] iio: accel: bma220: add debugfs reg access Allow read/write access to sensor registers for use in unit-tests. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 0ceffc412664..2531d6a54ff0 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -376,10 +376,21 @@ static int bma220_read_avail(struct iio_dev *indio_dev, } } +static int bma220_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct bma220_data *data = iio_priv(indio_dev); + + if (readval) + return regmap_read(data->regmap, reg, readval); + return regmap_write(data->regmap, reg, writeval); +} + static const struct iio_info bma220_info = { .read_raw = bma220_read_raw, .write_raw = bma220_write_raw, .read_avail = bma220_read_avail, + .debugfs_reg_access = &bma220_reg_access, }; static int bma220_reset(struct bma220_data *data, bool up) From efbce18231b4b78959bb562906728e515ab17463 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Sun, 5 Oct 2025 16:12:28 +0300 Subject: [PATCH 064/304] iio: accel: bma220: add maintainer Add maintainer for this driver. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 08fcce3208cf..3760f14493b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4467,6 +4467,13 @@ F: include/net/bond* F: include/uapi/linux/if_bonding.h F: tools/testing/selftests/drivers/net/bonding/ +BOSCH SENSORTEC BMA220 ACCELEROMETER IIO DRIVER +M: Petre Rodan +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml +F: drivers/iio/accel/bma220* + BOSCH SENSORTEC BMA400 ACCELEROMETER IIO DRIVER M: Dan Robertson L: linux-iio@vger.kernel.org From 95f934b2dd518016747aefbaecff8017e65f835d Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 7 Oct 2025 14:16:12 -0500 Subject: [PATCH 065/304] dt-bindings: iio: Add Infineon DPS310 sensor documentation The DPS310 is a barometric pressure and temperature sensor with an I2C interface. Remove it from trivial-devices.yaml and add its own documentation to allow for consumers of this device such as the iio/hwmon bridge. Signed-off-by: Eddie James Reviewed-by: Rob Herring (Arm) Signed-off-by: Jonathan Cameron --- .../iio/pressure/infineon,dps310.yaml | 54 +++++++++++++++++++ .../devicetree/bindings/trivial-devices.yaml | 2 - MAINTAINERS | 1 + 3 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/pressure/infineon,dps310.yaml diff --git a/Documentation/devicetree/bindings/iio/pressure/infineon,dps310.yaml b/Documentation/devicetree/bindings/iio/pressure/infineon,dps310.yaml new file mode 100644 index 000000000000..e5d1e6c48939 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/pressure/infineon,dps310.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/infineon,dps310.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon DPS310 barometric pressure and temperature sensor + +maintainers: + - Eddie James + +description: + The DPS310 is a barometric pressure and temperature sensor with an I2C + interface. + +properties: + compatible: + enum: + - infineon,dps310 + + reg: + maxItems: 1 + + "#io-channel-cells": + const: 0 + + vdd-supply: + description: + Voltage supply for the chip's analog blocks. + + vddio-supply: + description: + Digital voltage supply for the chip's digital blocks and I/O interface. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dps: pressure-sensor@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + vdd-supply = <&vref1>; + vddio-supply = <&vref2>; + }; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 2be5fb41b410..8a10b0a9ccc5 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -125,8 +125,6 @@ properties: - ibm,cffps2 # IBM On-Chip Controller hwmon device - ibm,p8-occ-hwmon - # Infineon barometric pressure and temperature sensor - - infineon,dps310 # Infineon IR36021 digital POL buck controller - infineon,ir36021 # Infineon IRPS5401 Voltage Regulator (PMIC) diff --git a/MAINTAINERS b/MAINTAINERS index 3760f14493b9..371ac55d0edc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12228,6 +12228,7 @@ INFINEON DPS310 Driver M: Eddie James L: linux-iio@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/iio/pressure/infineon,dps310.yaml F: drivers/iio/pressure/dps310.c INFINEON PEB2466 ASoC CODEC From 7d55d00185ddfba53b66efbbde33b8cf87fe7a1d Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:02 +0000 Subject: [PATCH 066/304] dt-bindings: iio: imu: Add inv_icm45600 Document the ICM-45600 devices devicetree bindings. Specific variants of the device are defined because of their differences in terms of FSR or advanced features like eDMP. Signed-off-by: Remi Buisson Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- .../bindings/iio/imu/invensense,icm45600.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/imu/invensense,icm45600.yaml diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm45600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm45600.yaml new file mode 100644 index 000000000000..e0b78d14420f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm45600.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/invensense,icm45600.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: InvenSense ICM-45600 Inertial Measurement Unit + +maintainers: + - Remi Buisson + +description: | + 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis + accelerometer. + + It has a configurable host interface that supports I3C, I2C and SPI serial + communication, features up to 8kB FIFO and 2 programmable interrupts with + ultra-low-power wake-on-motion support to minimize system power consumption. + + Other industry-leading features include InvenSense on-chip APEX Motion + Processing engine for gesture recognition, activity classification, and + pedometer, along with programmable digital filters, and an embedded + temperature sensor. + + https://invensense.tdk.com/wp-content/uploads/documentation/DS-000576_ICM-45605.pdf + +properties: + compatible: + enum: + - invensense,icm45605 + - invensense,icm45606 + - invensense,icm45608 + - invensense,icm45634 + - invensense,icm45686 + - invensense,icm45687 + - invensense,icm45688p + - invensense,icm45689 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - enum: [int1, int2] + - const: int2 + description: Choose chip interrupt pin to be used as interrupt input. + + drive-open-drain: + type: boolean + + vdd-supply: true + + vddio-supply: true + + mount-matrix: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imu@68 { + compatible = "invensense,icm45605"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupt-names = "int1"; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; + }; From 7ff021a3faca4233d53c994d7bc85823caa714db Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:03 +0000 Subject: [PATCH 067/304] iio: imu: inv_icm45600: add new inv_icm45600 driver Core component of a new driver for InvenSense ICM-45600 devices. It includes registers definition, main probe/setup, and device utility functions. ICM-456xx devices are latest generation of 6-axis IMU, gyroscope+accelerometer and temperature sensor. This device includes a 8K FIFO, supports I2C/I3C/SPI, and provides intelligent motion features like pedometer, tilt detection, and tap detection. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/Kconfig | 1 + drivers/iio/imu/Makefile | 1 + drivers/iio/imu/inv_icm45600/Kconfig | 5 + drivers/iio/imu/inv_icm45600/Makefile | 4 + drivers/iio/imu/inv_icm45600/inv_icm45600.h | 331 ++++++++++ .../iio/imu/inv_icm45600/inv_icm45600_core.c | 621 ++++++++++++++++++ 6 files changed, 963 insertions(+) create mode 100644 drivers/iio/imu/inv_icm45600/Kconfig create mode 100644 drivers/iio/imu/inv_icm45600/Makefile create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600.h create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_core.c diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig index 15612f0f189b..9d732bed9fcd 100644 --- a/drivers/iio/imu/Kconfig +++ b/drivers/iio/imu/Kconfig @@ -109,6 +109,7 @@ config KMX61 be called kmx61. source "drivers/iio/imu/inv_icm42600/Kconfig" +source "drivers/iio/imu/inv_icm45600/Kconfig" source "drivers/iio/imu/inv_mpu6050/Kconfig" config SMI240 diff --git a/drivers/iio/imu/Makefile b/drivers/iio/imu/Makefile index e901aea498d3..2ae6344f8469 100644 --- a/drivers/iio/imu/Makefile +++ b/drivers/iio/imu/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_FXOS8700_I2C) += fxos8700_i2c.o obj-$(CONFIG_FXOS8700_SPI) += fxos8700_spi.o obj-y += inv_icm42600/ +obj-y += inv_icm45600/ obj-y += inv_mpu6050/ obj-$(CONFIG_KMX61) += kmx61.o diff --git a/drivers/iio/imu/inv_icm45600/Kconfig b/drivers/iio/imu/inv_icm45600/Kconfig new file mode 100644 index 000000000000..8cb5543e0a58 --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config INV_ICM45600 + tristate + select IIO_INV_SENSORS_TIMESTAMP diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile new file mode 100644 index 000000000000..4f442b61896e --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-$(CONFIG_INV_ICM45600) += inv-icm45600.o +inv-icm45600-y += inv_icm45600_core.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600.h b/drivers/iio/imu/inv_icm45600/inv_icm45600.h new file mode 100644 index 000000000000..5f637e2f2ec8 --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2025 Invensense, Inc. */ + +#ifndef INV_ICM45600_H_ +#define INV_ICM45600_H_ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define INV_ICM45600_REG_BANK_MASK GENMASK(15, 8) +#define INV_ICM45600_REG_ADDR_MASK GENMASK(7, 0) + +enum inv_icm45600_sensor_mode { + INV_ICM45600_SENSOR_MODE_OFF, + INV_ICM45600_SENSOR_MODE_STANDBY, + INV_ICM45600_SENSOR_MODE_LOW_POWER, + INV_ICM45600_SENSOR_MODE_LOW_NOISE, + INV_ICM45600_SENSOR_MODE_MAX +}; + +/* gyroscope fullscale values */ +enum inv_icm45600_gyro_fs { + INV_ICM45600_GYRO_FS_2000DPS, + INV_ICM45600_GYRO_FS_1000DPS, + INV_ICM45600_GYRO_FS_500DPS, + INV_ICM45600_GYRO_FS_250DPS, + INV_ICM45600_GYRO_FS_125DPS, + INV_ICM45600_GYRO_FS_62_5DPS, + INV_ICM45600_GYRO_FS_31_25DPS, + INV_ICM45600_GYRO_FS_15_625DPS, + INV_ICM45600_GYRO_FS_MAX +}; + +enum inv_icm45686_gyro_fs { + INV_ICM45686_GYRO_FS_4000DPS, + INV_ICM45686_GYRO_FS_2000DPS, + INV_ICM45686_GYRO_FS_1000DPS, + INV_ICM45686_GYRO_FS_500DPS, + INV_ICM45686_GYRO_FS_250DPS, + INV_ICM45686_GYRO_FS_125DPS, + INV_ICM45686_GYRO_FS_62_5DPS, + INV_ICM45686_GYRO_FS_31_25DPS, + INV_ICM45686_GYRO_FS_15_625DPS, + INV_ICM45686_GYRO_FS_MAX +}; + +/* accelerometer fullscale values */ +enum inv_icm45600_accel_fs { + INV_ICM45600_ACCEL_FS_16G, + INV_ICM45600_ACCEL_FS_8G, + INV_ICM45600_ACCEL_FS_4G, + INV_ICM45600_ACCEL_FS_2G, + INV_ICM45600_ACCEL_FS_MAX +}; + +enum inv_icm45686_accel_fs { + INV_ICM45686_ACCEL_FS_32G, + INV_ICM45686_ACCEL_FS_16G, + INV_ICM45686_ACCEL_FS_8G, + INV_ICM45686_ACCEL_FS_4G, + INV_ICM45686_ACCEL_FS_2G, + INV_ICM45686_ACCEL_FS_MAX +}; + +/* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ +enum inv_icm45600_odr { + INV_ICM45600_ODR_6400HZ_LN = 0x03, + INV_ICM45600_ODR_3200HZ_LN, + INV_ICM45600_ODR_1600HZ_LN, + INV_ICM45600_ODR_800HZ_LN, + INV_ICM45600_ODR_400HZ, + INV_ICM45600_ODR_200HZ, + INV_ICM45600_ODR_100HZ, + INV_ICM45600_ODR_50HZ, + INV_ICM45600_ODR_25HZ, + INV_ICM45600_ODR_12_5HZ, + INV_ICM45600_ODR_6_25HZ_LP, + INV_ICM45600_ODR_3_125HZ_LP, + INV_ICM45600_ODR_1_5625HZ_LP, + INV_ICM45600_ODR_MAX +}; + +struct inv_icm45600_sensor_conf { + u8 mode; + u8 fs; + u8 odr; + u8 filter; +}; + +struct inv_icm45600_conf { + struct inv_icm45600_sensor_conf gyro; + struct inv_icm45600_sensor_conf accel; +}; + +struct inv_icm45600_suspended { + enum inv_icm45600_sensor_mode gyro; + enum inv_icm45600_sensor_mode accel; +}; + +struct inv_icm45600_chip_info { + u8 whoami; + const char *name; + const struct inv_icm45600_conf *conf; +}; + +/** + * struct inv_icm45600_state - driver state variables + * @lock: lock for serializing multiple registers access. + * @map: regmap pointer. + * @vddio_supply: I/O voltage regulator for the chip. + * @orientation: sensor chip orientation relative to main hardware. + * @conf: chip sensors configurations. + * @suspended: suspended sensors configuration. + * @indio_gyro: gyroscope IIO device. + * @indio_accel: accelerometer IIO device. + * @chip_info: chip driver data. + * @timestamp: interrupt timestamps. + * @buffer: data transfer buffer aligned for DMA. + */ +struct inv_icm45600_state { + struct mutex lock; + struct regmap *map; + struct regulator *vddio_supply; + struct iio_mount_matrix orientation; + struct inv_icm45600_conf conf; + struct inv_icm45600_suspended suspended; + struct iio_dev *indio_gyro; + struct iio_dev *indio_accel; + const struct inv_icm45600_chip_info *chip_info; + struct { + s64 gyro; + s64 accel; + } timestamp; + union { + u8 buff[2]; + __le16 u16; + u8 ireg[3]; + } buffer __aligned(IIO_DMA_MINALIGN); +}; + +/** + * struct inv_icm45600_sensor_state - sensor state variables + * @scales: table of scales. + * @scales_len: length (nb of items) of the scales table. + * @power_mode: sensor requested power mode (for common frequencies) + * @ts: timestamp module states. + */ +struct inv_icm45600_sensor_state { + const int *scales; + size_t scales_len; + enum inv_icm45600_sensor_mode power_mode; + struct inv_sensors_timestamp ts; +}; + +/* Virtual register addresses: @bank on MSB (16 bits), @address on LSB */ + +/* Indirect register access */ +#define INV_ICM45600_REG_IREG_ADDR 0x7C +#define INV_ICM45600_REG_IREG_DATA 0x7E + +/* Direct acces registers */ +#define INV_ICM45600_REG_MISC2 0x007F +#define INV_ICM45600_MISC2_SOFT_RESET BIT(1) + +#define INV_ICM45600_REG_DRIVE_CONFIG0 0x0032 +#define INV_ICM45600_DRIVE_CONFIG0_SPI_MASK GENMASK(3, 1) +#define INV_ICM45600_SPI_SLEW_RATE_0_5NS 6 +#define INV_ICM45600_SPI_SLEW_RATE_4NS 5 +#define INV_ICM45600_SPI_SLEW_RATE_5NS 4 +#define INV_ICM45600_SPI_SLEW_RATE_7NS 3 +#define INV_ICM45600_SPI_SLEW_RATE_10NS 2 +#define INV_ICM45600_SPI_SLEW_RATE_14NS 1 +#define INV_ICM45600_SPI_SLEW_RATE_38NS 0 + +#define INV_ICM45600_REG_INT1_CONFIG2 0x0018 +#define INV_ICM45600_INT1_CONFIG2_PUSH_PULL BIT(2) +#define INV_ICM45600_INT1_CONFIG2_LATCHED BIT(1) +#define INV_ICM45600_INT1_CONFIG2_ACTIVE_HIGH BIT(0) +#define INV_ICM45600_INT1_CONFIG2_ACTIVE_LOW 0x00 + +#define INV_ICM45600_REG_FIFO_CONFIG0 0x001D +#define INV_ICM45600_FIFO_CONFIG0_MODE_MASK GENMASK(7, 6) +#define INV_ICM45600_FIFO_CONFIG0_MODE_BYPASS 0 +#define INV_ICM45600_FIFO_CONFIG0_MODE_STREAM 1 +#define INV_ICM45600_FIFO_CONFIG0_MODE_STOP_ON_FULL 2 +#define INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MAX 0x1F + +#define INV_ICM45600_REG_FIFO_CONFIG2 0x0020 +#define INV_ICM45600_REG_FIFO_CONFIG2_FIFO_FLUSH BIT(7) +#define INV_ICM45600_REG_FIFO_CONFIG2_WM_GT_TH BIT(3) + +#define INV_ICM45600_REG_FIFO_CONFIG3 0x0021 +#define INV_ICM45600_FIFO_CONFIG3_ES1_EN BIT(5) +#define INV_ICM45600_FIFO_CONFIG3_ES0_EN BIT(4) +#define INV_ICM45600_FIFO_CONFIG3_HIRES_EN BIT(3) +#define INV_ICM45600_FIFO_CONFIG3_GYRO_EN BIT(2) +#define INV_ICM45600_FIFO_CONFIG3_ACCEL_EN BIT(1) +#define INV_ICM45600_FIFO_CONFIG3_IF_EN BIT(0) + +#define INV_ICM45600_REG_FIFO_CONFIG4 0x0022 +#define INV_ICM45600_FIFO_CONFIG4_COMP_EN BIT(2) +#define INV_ICM45600_FIFO_CONFIG4_TMST_FSYNC_EN BIT(1) +#define INV_ICM45600_FIFO_CONFIG4_ES0_9B BIT(0) + +/* all sensor data are 16 bits (2 registers wide) in big-endian */ +#define INV_ICM45600_REG_TEMP_DATA 0x000C +#define INV_ICM45600_REG_ACCEL_DATA_X 0x0000 +#define INV_ICM45600_REG_ACCEL_DATA_Y 0x0002 +#define INV_ICM45600_REG_ACCEL_DATA_Z 0x0004 +#define INV_ICM45600_REG_GYRO_DATA_X 0x0006 +#define INV_ICM45600_REG_GYRO_DATA_Y 0x0008 +#define INV_ICM45600_REG_GYRO_DATA_Z 0x000A + +#define INV_ICM45600_REG_INT_STATUS 0x0019 +#define INV_ICM45600_INT_STATUS_RESET_DONE BIT(7) +#define INV_ICM45600_INT_STATUS_AUX1_AGC_RDY BIT(6) +#define INV_ICM45600_INT_STATUS_AP_AGC_RDY BIT(5) +#define INV_ICM45600_INT_STATUS_AP_FSYNC BIT(4) +#define INV_ICM45600_INT_STATUS_AUX1_DRDY BIT(3) +#define INV_ICM45600_INT_STATUS_DATA_RDY BIT(2) +#define INV_ICM45600_INT_STATUS_FIFO_THS BIT(1) +#define INV_ICM45600_INT_STATUS_FIFO_FULL BIT(0) + +/* + * FIFO access registers + * FIFO count is 16 bits (2 registers) + * FIFO data is a continuous read register to read FIFO content + */ +#define INV_ICM45600_REG_FIFO_COUNT 0x0012 +#define INV_ICM45600_REG_FIFO_DATA 0x0014 + +#define INV_ICM45600_REG_PWR_MGMT0 0x0010 +#define INV_ICM45600_PWR_MGMT0_GYRO_MODE_MASK GENMASK(3, 2) +#define INV_ICM45600_PWR_MGMT0_ACCEL_MODE_MASK GENMASK(1, 0) + +#define INV_ICM45600_REG_ACCEL_CONFIG0 0x001B +#define INV_ICM45600_ACCEL_CONFIG0_FS_MASK GENMASK(6, 4) +#define INV_ICM45600_ACCEL_CONFIG0_ODR_MASK GENMASK(3, 0) +#define INV_ICM45600_REG_GYRO_CONFIG0 0x001C +#define INV_ICM45600_GYRO_CONFIG0_FS_MASK GENMASK(7, 4) +#define INV_ICM45600_GYRO_CONFIG0_ODR_MASK GENMASK(3, 0) + +#define INV_ICM45600_REG_SMC_CONTROL_0 0xA258 +#define INV_ICM45600_SMC_CONTROL_0_ACCEL_LP_CLK_SEL BIT(4) +#define INV_ICM45600_SMC_CONTROL_0_TMST_EN BIT(0) + +/* FIFO watermark is 16 bits (2 registers wide) in little-endian */ +#define INV_ICM45600_REG_FIFO_WATERMARK 0x001E + +/* FIFO is configured for 8kb */ +#define INV_ICM45600_FIFO_SIZE_MAX SZ_8K + +#define INV_ICM45600_REG_INT1_CONFIG0 0x0016 +#define INV_ICM45600_INT1_CONFIG0_RESET_DONE_EN BIT(7) +#define INV_ICM45600_INT1_CONFIG0_AUX1_AGC_RDY_EN BIT(6) +#define INV_ICM45600_INT1_CONFIG0_AP_AGC_RDY_EN BIT(5) +#define INV_ICM45600_INT1_CONFIG0_AP_FSYNC_EN BIT(4) +#define INV_ICM45600_INT1_CONFIG0_AUX1_DRDY_EN BIT(3) +#define INV_ICM45600_INT1_CONFIG0_DRDY_EN BIT(2) +#define INV_ICM45600_INT1_CONFIG0_FIFO_THS_EN BIT(1) +#define INV_ICM45600_INT1_CONFIG0_FIFO_FULL_EN BIT(0) + +#define INV_ICM45600_REG_WHOAMI 0x0072 +#define INV_ICM45600_WHOAMI_ICM45605 0xE5 +#define INV_ICM45600_WHOAMI_ICM45686 0xE9 +#define INV_ICM45600_WHOAMI_ICM45688P 0xE7 +#define INV_ICM45600_WHOAMI_ICM45608 0x81 +#define INV_ICM45600_WHOAMI_ICM45634 0x82 +#define INV_ICM45600_WHOAMI_ICM45689 0x83 +#define INV_ICM45600_WHOAMI_ICM45606 0x84 +#define INV_ICM45600_WHOAMI_ICM45687 0x85 + +/* Gyro USER offset */ +#define INV_ICM45600_IPREG_SYS1_REG_42 0xA42A +#define INV_ICM45600_IPREG_SYS1_REG_56 0xA438 +#define INV_ICM45600_IPREG_SYS1_REG_70 0xA446 +#define INV_ICM45600_GYRO_OFFUSER_MASK GENMASK(13, 0) +/* Gyro Averaging filter */ +#define INV_ICM45600_IPREG_SYS1_REG_170 0xA4AA +#define INV_ICM45600_IPREG_SYS1_170_GYRO_LP_AVG_MASK GENMASK(4, 1) +#define INV_ICM45600_GYRO_LP_AVG_SEL_8X 5 +#define INV_ICM45600_GYRO_LP_AVG_SEL_2X 1 +/* Accel USER offset */ +#define INV_ICM45600_IPREG_SYS2_REG_24 0xA518 +#define INV_ICM45600_IPREG_SYS2_REG_32 0xA520 +#define INV_ICM45600_IPREG_SYS2_REG_40 0xA528 +#define INV_ICM45600_ACCEL_OFFUSER_MASK GENMASK(13, 0) +/* Accel averaging filter */ +#define INV_ICM45600_IPREG_SYS2_REG_129 0xA581 +#define INV_ICM45600_ACCEL_LP_AVG_SEL_1X 0x0000 +#define INV_ICM45600_ACCEL_LP_AVG_SEL_4X 0x0002 + +/* Sleep times required by the driver */ +#define INV_ICM45600_ACCEL_STARTUP_TIME_MS 60 +#define INV_ICM45600_GYRO_STARTUP_TIME_MS 60 +#define INV_ICM45600_GYRO_STOP_TIME_MS 150 +#define INV_ICM45600_IREG_DELAY_US 4 + +typedef int (*inv_icm45600_bus_setup)(struct inv_icm45600_state *); + +extern const struct dev_pm_ops inv_icm45600_pm_ops; + +const struct iio_mount_matrix * +inv_icm45600_get_mount_matrix(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan); + +u32 inv_icm45600_odr_to_period(enum inv_icm45600_odr odr); + +int inv_icm45600_set_accel_conf(struct inv_icm45600_state *st, + struct inv_icm45600_sensor_conf *conf, + unsigned int *sleep_ms); + +int inv_icm45600_set_gyro_conf(struct inv_icm45600_state *st, + struct inv_icm45600_sensor_conf *conf, + unsigned int *sleep_ms); + +int inv_icm45600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval); + +int inv_icm45600_core_probe(struct regmap *regmap, + const struct inv_icm45600_chip_info *chip_info, + bool reset, inv_icm45600_bus_setup bus_setup); + +#endif diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c new file mode 100644 index 000000000000..280cdd40f86b --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2025 Invensense, Inc. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "inv_icm45600.h" + +static int inv_icm45600_ireg_read(struct regmap *map, unsigned int reg, + u8 *data, size_t count) +{ + const struct device *dev = regmap_get_device(map); + struct inv_icm45600_state *st = dev_get_drvdata(dev); + unsigned int d; + size_t i; + int ret; + + st->buffer.ireg[0] = FIELD_GET(INV_ICM45600_REG_BANK_MASK, reg); + st->buffer.ireg[1] = FIELD_GET(INV_ICM45600_REG_ADDR_MASK, reg); + + /* Burst write address. */ + ret = regmap_bulk_write(map, INV_ICM45600_REG_IREG_ADDR, st->buffer.ireg, 2); + /* + * Wait while the device is busy processing the address. + * Datasheet: 13.3 MINIMUM WAIT TIME-GAP + */ + fsleep(INV_ICM45600_IREG_DELAY_US); + if (ret) + return ret; + + /* Read the data. */ + for (i = 0; i < count; i++) { + ret = regmap_read(map, INV_ICM45600_REG_IREG_DATA, &d); + /* + * Wait while the device is busy processing the address. + * Datasheet: 13.3 MINIMUM WAIT TIME-GAP + */ + fsleep(INV_ICM45600_IREG_DELAY_US); + if (ret) + return ret; + data[i] = d; + } + + return 0; +} + +static int inv_icm45600_ireg_write(struct regmap *map, unsigned int reg, + const u8 *data, size_t count) +{ + const struct device *dev = regmap_get_device(map); + struct inv_icm45600_state *st = dev_get_drvdata(dev); + size_t i; + int ret; + + st->buffer.ireg[0] = FIELD_GET(INV_ICM45600_REG_BANK_MASK, reg); + st->buffer.ireg[1] = FIELD_GET(INV_ICM45600_REG_ADDR_MASK, reg); + st->buffer.ireg[2] = data[0]; + + /* Burst write address and first byte. */ + ret = regmap_bulk_write(map, INV_ICM45600_REG_IREG_ADDR, st->buffer.ireg, 3); + /* + * Wait while the device is busy processing the address. + * Datasheet: 13.3 MINIMUM WAIT TIME-GAP + */ + fsleep(INV_ICM45600_IREG_DELAY_US); + if (ret) + return ret; + + /* Write the remaining bytes. */ + for (i = 1; i < count; i++) { + ret = regmap_write(map, INV_ICM45600_REG_IREG_DATA, data[i]); + /* + * Wait while the device is busy processing the address. + * Datasheet: 13.3 MINIMUM WAIT TIME-GAP + */ + fsleep(INV_ICM45600_IREG_DELAY_US); + if (ret) + return ret; + } + + return 0; +} + +static int inv_icm45600_read(void *context, const void *reg_buf, size_t reg_size, + void *val_buf, size_t val_size) +{ + unsigned int reg = be16_to_cpup(reg_buf); + struct regmap *map = context; + + if (FIELD_GET(INV_ICM45600_REG_BANK_MASK, reg)) + return inv_icm45600_ireg_read(map, reg, val_buf, val_size); + + return regmap_bulk_read(map, FIELD_GET(INV_ICM45600_REG_ADDR_MASK, reg), + val_buf, val_size); +} + +static int inv_icm45600_write(void *context, const void *data, size_t count) +{ + const u8 *d = data; + unsigned int reg = be16_to_cpup(data); + struct regmap *map = context; + + if (FIELD_GET(INV_ICM45600_REG_BANK_MASK, reg)) + return inv_icm45600_ireg_write(map, reg, d + 2, count - 2); + + return regmap_bulk_write(map, FIELD_GET(INV_ICM45600_REG_ADDR_MASK, reg), + d + 2, count - 2); +} + +static const struct regmap_bus inv_icm45600_regmap_bus = { + .read = inv_icm45600_read, + .write = inv_icm45600_write, +}; + +static const struct regmap_config inv_icm45600_regmap_config = { + .reg_bits = 16, + .val_bits = 8, +}; + +const struct iio_mount_matrix * +inv_icm45600_get_mount_matrix(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + const struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + + return &st->orientation; +} + +u32 inv_icm45600_odr_to_period(enum inv_icm45600_odr odr) +{ + static const u32 odr_periods[INV_ICM45600_ODR_MAX] = { + /* 3 first values are reserved, left to 0 */ + [INV_ICM45600_ODR_6400HZ_LN] = 156250, + [INV_ICM45600_ODR_3200HZ_LN] = 312500, + [INV_ICM45600_ODR_1600HZ_LN] = 625000, + [INV_ICM45600_ODR_800HZ_LN] = 1250000, + [INV_ICM45600_ODR_400HZ] = 2500000, + [INV_ICM45600_ODR_200HZ] = 5000000, + [INV_ICM45600_ODR_100HZ] = 10000000, + [INV_ICM45600_ODR_50HZ] = 20000000, + [INV_ICM45600_ODR_25HZ] = 40000000, + [INV_ICM45600_ODR_12_5HZ] = 80000000, + [INV_ICM45600_ODR_6_25HZ_LP] = 160000000, + [INV_ICM45600_ODR_3_125HZ_LP] = 320000000, + [INV_ICM45600_ODR_1_5625HZ_LP] = 640000000, + }; + + return odr_periods[odr]; +} + +static int inv_icm45600_set_pwr_mgmt0(struct inv_icm45600_state *st, + enum inv_icm45600_sensor_mode gyro, + enum inv_icm45600_sensor_mode accel, + unsigned int *sleep_ms) +{ + enum inv_icm45600_sensor_mode oldgyro = st->conf.gyro.mode; + enum inv_icm45600_sensor_mode oldaccel = st->conf.accel.mode; + unsigned int sleepval; + unsigned int val; + int ret; + + /* if nothing changed, exit */ + if (gyro == oldgyro && accel == oldaccel) + return 0; + + val = FIELD_PREP(INV_ICM45600_PWR_MGMT0_GYRO_MODE_MASK, gyro) | + FIELD_PREP(INV_ICM45600_PWR_MGMT0_ACCEL_MODE_MASK, accel); + ret = regmap_write(st->map, INV_ICM45600_REG_PWR_MGMT0, val); + if (ret) + return ret; + + st->conf.gyro.mode = gyro; + st->conf.accel.mode = accel; + + /* Compute the required wait time for sensors to stabilize. */ + sleepval = 0; + if (accel != oldaccel && oldaccel == INV_ICM45600_SENSOR_MODE_OFF) + sleepval = max(sleepval, INV_ICM45600_ACCEL_STARTUP_TIME_MS); + + if (gyro != oldgyro) { + if (oldgyro == INV_ICM45600_SENSOR_MODE_OFF) + sleepval = max(sleepval, INV_ICM45600_GYRO_STARTUP_TIME_MS); + else if (gyro == INV_ICM45600_SENSOR_MODE_OFF) + sleepval = max(sleepval, INV_ICM45600_GYRO_STOP_TIME_MS); + } + + /* Deferred sleep value if sleep pointer is provided or direct sleep */ + if (sleep_ms) + *sleep_ms = sleepval; + else if (sleepval) + msleep(sleepval); + + return 0; +} + +static void inv_icm45600_set_default_conf(struct inv_icm45600_sensor_conf *conf, + struct inv_icm45600_sensor_conf *oldconf) +{ + /* Sanitize missing values with current values. */ + if (conf->mode == U8_MAX) + conf->mode = oldconf->mode; + if (conf->fs == U8_MAX) + conf->fs = oldconf->fs; + if (conf->odr == U8_MAX) + conf->odr = oldconf->odr; + if (conf->filter == U8_MAX) + conf->filter = oldconf->filter; +} + +int inv_icm45600_set_accel_conf(struct inv_icm45600_state *st, + struct inv_icm45600_sensor_conf *conf, + unsigned int *sleep_ms) +{ + struct inv_icm45600_sensor_conf *oldconf = &st->conf.accel; + unsigned int val; + int ret; + + inv_icm45600_set_default_conf(conf, oldconf); + + /* Force the power mode against the ODR when sensor is on. */ + if (conf->mode > INV_ICM45600_SENSOR_MODE_STANDBY) { + if (conf->odr <= INV_ICM45600_ODR_800HZ_LN) { + conf->mode = INV_ICM45600_SENSOR_MODE_LOW_NOISE; + } else { + conf->mode = INV_ICM45600_SENSOR_MODE_LOW_POWER; + /* sanitize averaging value depending on ODR for low-power mode */ + /* maximum 1x @400Hz */ + if (conf->odr == INV_ICM45600_ODR_400HZ) + conf->filter = INV_ICM45600_ACCEL_LP_AVG_SEL_1X; + else + conf->filter = INV_ICM45600_ACCEL_LP_AVG_SEL_4X; + } + } + + /* Set accel fullscale & odr. */ + if (conf->fs != oldconf->fs || conf->odr != oldconf->odr) { + val = FIELD_PREP(INV_ICM45600_ACCEL_CONFIG0_FS_MASK, conf->fs) | + FIELD_PREP(INV_ICM45600_ACCEL_CONFIG0_ODR_MASK, conf->odr); + ret = regmap_write(st->map, INV_ICM45600_REG_ACCEL_CONFIG0, val); + if (ret) + return ret; + oldconf->fs = conf->fs; + oldconf->odr = conf->odr; + } + + /* Set accel low-power average filter. */ + if (conf->filter != oldconf->filter) { + ret = regmap_write(st->map, INV_ICM45600_IPREG_SYS2_REG_129, + conf->filter); + if (ret) + return ret; + oldconf->filter = conf->filter; + } + + /* Update the sensor accel mode. */ + return inv_icm45600_set_pwr_mgmt0(st, st->conf.gyro.mode, conf->mode, + sleep_ms); +} + +int inv_icm45600_set_gyro_conf(struct inv_icm45600_state *st, + struct inv_icm45600_sensor_conf *conf, + unsigned int *sleep_ms) +{ + struct inv_icm45600_sensor_conf *oldconf = &st->conf.gyro; + unsigned int val; + int ret; + + inv_icm45600_set_default_conf(conf, oldconf); + + /* Force the power mode against ODR when sensor is on. */ + if (conf->mode > INV_ICM45600_SENSOR_MODE_STANDBY) { + if (conf->odr >= INV_ICM45600_ODR_6_25HZ_LP) { + conf->mode = INV_ICM45600_SENSOR_MODE_LOW_POWER; + conf->filter = INV_ICM45600_GYRO_LP_AVG_SEL_8X; + } else { + conf->mode = INV_ICM45600_SENSOR_MODE_LOW_NOISE; + } + } + + /* Set gyro fullscale & odr. */ + if (conf->fs != oldconf->fs || conf->odr != oldconf->odr) { + val = FIELD_PREP(INV_ICM45600_GYRO_CONFIG0_FS_MASK, conf->fs) | + FIELD_PREP(INV_ICM45600_GYRO_CONFIG0_ODR_MASK, conf->odr); + ret = regmap_write(st->map, INV_ICM45600_REG_GYRO_CONFIG0, val); + if (ret) + return ret; + oldconf->fs = conf->fs; + oldconf->odr = conf->odr; + } + + /* Set gyro low-power average filter. */ + if (conf->filter != oldconf->filter) { + val = FIELD_PREP(INV_ICM45600_IPREG_SYS1_170_GYRO_LP_AVG_MASK, conf->filter); + ret = regmap_update_bits(st->map, INV_ICM45600_IPREG_SYS1_REG_170, + INV_ICM45600_IPREG_SYS1_170_GYRO_LP_AVG_MASK, val); + if (ret) + return ret; + oldconf->filter = conf->filter; + } + + /* Update the sensor gyro mode. */ + return inv_icm45600_set_pwr_mgmt0(st, conf->mode, st->conf.accel.mode, + sleep_ms); +} + +int inv_icm45600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + + guard(mutex)(&st->lock); + + if (readval) + return regmap_read(st->map, reg, readval); + else + return regmap_write(st->map, reg, writeval); +} + +static int inv_icm45600_set_conf(struct inv_icm45600_state *st, + const struct inv_icm45600_conf *conf) +{ + unsigned int val; + int ret; + + val = FIELD_PREP(INV_ICM45600_PWR_MGMT0_GYRO_MODE_MASK, conf->gyro.mode) | + FIELD_PREP(INV_ICM45600_PWR_MGMT0_ACCEL_MODE_MASK, conf->accel.mode); + ret = regmap_write(st->map, INV_ICM45600_REG_PWR_MGMT0, val); + if (ret) + return ret; + + val = FIELD_PREP(INV_ICM45600_GYRO_CONFIG0_FS_MASK, conf->gyro.fs) | + FIELD_PREP(INV_ICM45600_GYRO_CONFIG0_ODR_MASK, conf->gyro.odr); + ret = regmap_write(st->map, INV_ICM45600_REG_GYRO_CONFIG0, val); + if (ret) + return ret; + + val = FIELD_PREP(INV_ICM45600_ACCEL_CONFIG0_FS_MASK, conf->accel.fs) | + FIELD_PREP(INV_ICM45600_ACCEL_CONFIG0_ODR_MASK, conf->accel.odr); + ret = regmap_write(st->map, INV_ICM45600_REG_ACCEL_CONFIG0, val); + if (ret) + return ret; + + /* Save configuration. */ + st->conf = *conf; + + return 0; +} + +/** + * inv_icm45600_setup() - check and setup chip + * @st: driver internal state + * @chip_info: detected chip description + * @reset: define whether a reset is required or not + * @bus_setup: callback for setting up bus specific registers + * + * Returns: 0 on success, a negative error code otherwise. + */ +static int inv_icm45600_setup(struct inv_icm45600_state *st, + const struct inv_icm45600_chip_info *chip_info, + bool reset, inv_icm45600_bus_setup bus_setup) +{ + const struct device *dev = regmap_get_device(st->map); + unsigned int val; + int ret; + + /* Set chip bus configuration if specified. */ + if (bus_setup) { + ret = bus_setup(st); + if (ret) + return ret; + } + + /* Check chip self-identification value. */ + ret = regmap_read(st->map, INV_ICM45600_REG_WHOAMI, &val); + if (ret) + return ret; + if (val != chip_info->whoami) { + /* + * SPI interface has no ack mechanism. + * 0xFF or 0x00 whoami means no response from the device. + */ + if (val == U8_MAX || val == 0) + return dev_err_probe(dev, -ENODEV, + "Invalid whoami %#02x expected %#02x (%s)\n", + val, chip_info->whoami, chip_info->name); + + dev_warn(dev, "Unexpected whoami %#02x expected %#02x (%s)\n", + val, chip_info->whoami, chip_info->name); + } + + st->chip_info = chip_info; + + if (reset) { + /* Reset previous state. */ + ret = regmap_write(st->map, INV_ICM45600_REG_MISC2, + INV_ICM45600_MISC2_SOFT_RESET); + if (ret) + return ret; + /* + * IMU reset time. + * Datasheet: 16.84 REG_MISC2 + */ + fsleep(USEC_PER_MSEC); + + if (bus_setup) { + ret = bus_setup(st); + if (ret) + return ret; + } + + ret = regmap_read(st->map, INV_ICM45600_REG_INT_STATUS, &val); + if (ret) + return ret; + if (!(val & INV_ICM45600_INT_STATUS_RESET_DONE)) { + dev_err(dev, "reset error, reset done bit not set\n"); + return -ENODEV; + } + } + + return inv_icm45600_set_conf(st, chip_info->conf); +} + +static int inv_icm45600_timestamp_setup(struct inv_icm45600_state *st) +{ + /* Enable timestamps. */ + return regmap_set_bits(st->map, INV_ICM45600_REG_SMC_CONTROL_0, + INV_ICM45600_SMC_CONTROL_0_TMST_EN); +} + +static int inv_icm45600_enable_regulator_vddio(struct inv_icm45600_state *st) +{ + int ret; + + ret = regulator_enable(st->vddio_supply); + if (ret) + return ret; + + /* + * Wait a little for supply ramp. + * Duration is empirically defined. + */ + fsleep(3 * USEC_PER_MSEC); + + return 0; +} + +static void inv_icm45600_disable_vddio_reg(void *_data) +{ + struct inv_icm45600_state *st = _data; + struct device *dev = regmap_get_device(st->map); + + if (pm_runtime_status_suspended(dev)) + return; + + regulator_disable(st->vddio_supply); +} + +int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chip_info *chip_info, + bool reset, inv_icm45600_bus_setup bus_setup) +{ + struct device *dev = regmap_get_device(regmap); + struct inv_icm45600_state *st; + struct regmap *regmap_custom; + int ret; + + regmap_custom = devm_regmap_init(dev, &inv_icm45600_regmap_bus, regmap, + &inv_icm45600_regmap_config); + if (IS_ERR(regmap_custom)) + return dev_err_probe(dev, PTR_ERR(regmap_custom), "Failed to register regmap\n"); + + st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + dev_set_drvdata(dev, st); + + ret = devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + st->map = regmap_custom; + + ret = iio_read_mount_matrix(dev, &st->orientation); + if (ret) + return dev_err_probe(dev, ret, "Failed to retrieve mounting matrix\n"); + + st->vddio_supply = devm_regulator_get(dev, "vddio"); + if (IS_ERR(st->vddio_supply)) + return PTR_ERR(st->vddio_supply); + + ret = devm_regulator_get_enable(dev, "vdd"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get vdd regulator\n"); + + /* + * Supply ramp time + Start-up time. + * Datasheet: 3.3.2 A.C. Electrical Characteristics + */ + fsleep(5 * USEC_PER_MSEC); + + ret = inv_icm45600_enable_regulator_vddio(st); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, inv_icm45600_disable_vddio_reg, st); + if (ret) + return ret; + + ret = inv_icm45600_setup(st, chip_info, reset, bus_setup); + if (ret) + return ret; + + ret = inv_icm45600_timestamp_setup(st); + if (ret) + return ret; + + ret = devm_pm_runtime_set_active_enabled(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_autosuspend_delay(dev, 2 * USEC_PER_MSEC); + pm_runtime_use_autosuspend(dev); + pm_runtime_put(dev); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(inv_icm45600_core_probe, "IIO_ICM45600"); + +/* + * Suspend saves sensors state and turns everything off. + */ +static int inv_icm45600_suspend(struct device *dev) +{ + struct inv_icm45600_state *st = dev_get_drvdata(dev); + + scoped_guard(mutex, &st->lock) { + /* Save sensors states */ + st->suspended.gyro = st->conf.gyro.mode; + st->suspended.accel = st->conf.accel.mode; + } + + return pm_runtime_force_suspend(dev); +} + +/* + * System resume gets the system back on and restores the sensors state. + * Manually put runtime power management in system active state. + */ +static int inv_icm45600_resume(struct device *dev) +{ + struct inv_icm45600_state *st = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) { + /* Restore sensors state. */ + ret = inv_icm45600_set_pwr_mgmt0(st, st->suspended.gyro, + st->suspended.accel, NULL); + } + + return ret; +} + +/* Runtime suspend will turn off sensors that are enabled by iio devices. */ +static int inv_icm45600_runtime_suspend(struct device *dev) +{ + struct inv_icm45600_state *st = dev_get_drvdata(dev); + int ret; + + guard(mutex)(&st->lock); + + /* disable all sensors */ + ret = inv_icm45600_set_pwr_mgmt0(st, INV_ICM45600_SENSOR_MODE_OFF, + INV_ICM45600_SENSOR_MODE_OFF, NULL); + if (ret) + return ret; + + regulator_disable(st->vddio_supply); + + return 0; +} + +/* Sensors are enabled by iio devices, no need to turn them back on here. */ +static int inv_icm45600_runtime_resume(struct device *dev) +{ + struct inv_icm45600_state *st = dev_get_drvdata(dev); + + guard(mutex)(&st->lock); + + return inv_icm45600_enable_regulator_vddio(st); +} + +EXPORT_NS_GPL_DEV_PM_OPS(inv_icm45600_pm_ops, IIO_ICM45600) = { + SYSTEM_SLEEP_PM_OPS(inv_icm45600_suspend, inv_icm45600_resume) + RUNTIME_PM_OPS(inv_icm45600_runtime_suspend, + inv_icm45600_runtime_resume, NULL) +}; + +MODULE_AUTHOR("InvenSense, Inc."); +MODULE_DESCRIPTION("InvenSense ICM-456xx device driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_INV_SENSORS_TIMESTAMP"); From 06674a72cf7afa540b4d8c5a4ee41d547988fd78 Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:04 +0000 Subject: [PATCH 068/304] iio: imu: inv_icm45600: add buffer support in iio devices Add FIFO control functions. Support hwfifo watermark by multiplexing gyro and accel settings. Support hwfifo flush. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/Makefile | 1 + drivers/iio/imu/inv_icm45600/inv_icm45600.h | 8 + .../imu/inv_icm45600/inv_icm45600_buffer.c | 483 ++++++++++++++++++ .../imu/inv_icm45600/inv_icm45600_buffer.h | 98 ++++ .../iio/imu/inv_icm45600/inv_icm45600_core.c | 158 ++++++ 5 files changed, 748 insertions(+) create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile index 4f442b61896e..72f95bc30d99 100644 --- a/drivers/iio/imu/inv_icm45600/Makefile +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_INV_ICM45600) += inv-icm45600.o inv-icm45600-y += inv_icm45600_core.o +inv-icm45600-y += inv_icm45600_buffer.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600.h b/drivers/iio/imu/inv_icm45600/inv_icm45600.h index 5f637e2f2ec8..aac8cd852c12 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600.h +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600.h @@ -5,6 +5,7 @@ #define INV_ICM45600_H_ #include +#include #include #include #include @@ -14,6 +15,8 @@ #include #include +#include "inv_icm45600_buffer.h" + #define INV_ICM45600_REG_BANK_MASK GENMASK(15, 8) #define INV_ICM45600_REG_ADDR_MASK GENMASK(7, 0) @@ -94,6 +97,8 @@ struct inv_icm45600_sensor_conf { u8 filter; }; +#define INV_ICM45600_SENSOR_CONF_KEEP_VALUES { U8_MAX, U8_MAX, U8_MAX, U8_MAX } + struct inv_icm45600_conf { struct inv_icm45600_sensor_conf gyro; struct inv_icm45600_sensor_conf accel; @@ -122,6 +127,7 @@ struct inv_icm45600_chip_info { * @indio_accel: accelerometer IIO device. * @chip_info: chip driver data. * @timestamp: interrupt timestamps. + * @fifo: FIFO management structure. * @buffer: data transfer buffer aligned for DMA. */ struct inv_icm45600_state { @@ -138,6 +144,7 @@ struct inv_icm45600_state { s64 gyro; s64 accel; } timestamp; + struct inv_icm45600_fifo fifo; union { u8 buff[2]; __le16 u16; @@ -190,6 +197,7 @@ struct inv_icm45600_sensor_state { #define INV_ICM45600_FIFO_CONFIG0_MODE_BYPASS 0 #define INV_ICM45600_FIFO_CONFIG0_MODE_STREAM 1 #define INV_ICM45600_FIFO_CONFIG0_MODE_STOP_ON_FULL 2 +#define INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MASK GENMASK(5, 0) #define INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MAX 0x1F #define INV_ICM45600_REG_FIFO_CONFIG2 0x0020 diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c new file mode 100644 index 000000000000..5542ad8af2a6 --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2025 Invensense, Inc. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "inv_icm45600_buffer.h" +#include "inv_icm45600.h" + +/* FIFO header: 1 byte */ +#define INV_ICM45600_FIFO_EXT_HEADER BIT(7) +#define INV_ICM45600_FIFO_HEADER_ACCEL BIT(6) +#define INV_ICM45600_FIFO_HEADER_GYRO BIT(5) +#define INV_ICM45600_FIFO_HEADER_HIGH_RES BIT(4) +#define INV_ICM45600_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2) +#define INV_ICM45600_FIFO_HEADER_ODR_ACCEL BIT(1) +#define INV_ICM45600_FIFO_HEADER_ODR_GYRO BIT(0) + +struct inv_icm45600_fifo_1sensor_packet { + u8 header; + struct inv_icm45600_fifo_sensor_data data; + s8 temp; +} __packed; + +struct inv_icm45600_fifo_2sensors_packet { + u8 header; + struct inv_icm45600_fifo_sensor_data accel; + struct inv_icm45600_fifo_sensor_data gyro; + s8 temp; + __le16 timestamp; +} __packed; + +ssize_t inv_icm45600_fifo_decode_packet(const void *packet, + const struct inv_icm45600_fifo_sensor_data **accel, + const struct inv_icm45600_fifo_sensor_data **gyro, + const s8 **temp, + const __le16 **timestamp, unsigned int *odr) +{ + const struct inv_icm45600_fifo_1sensor_packet *pack1 = packet; + const struct inv_icm45600_fifo_2sensors_packet *pack2 = packet; + u8 header = *((const u8 *)packet); + + /* FIFO extended header */ + if (header & INV_ICM45600_FIFO_EXT_HEADER) { + /* Not yet supported */ + return 0; + } + + /* handle odr flags. */ + *odr = 0; + if (header & INV_ICM45600_FIFO_HEADER_ODR_GYRO) + *odr |= INV_ICM45600_SENSOR_GYRO; + if (header & INV_ICM45600_FIFO_HEADER_ODR_ACCEL) + *odr |= INV_ICM45600_SENSOR_ACCEL; + + /* Accel + Gyro data are present. */ + if ((header & INV_ICM45600_FIFO_HEADER_ACCEL) && + (header & INV_ICM45600_FIFO_HEADER_GYRO)) { + *accel = &pack2->accel; + *gyro = &pack2->gyro; + *temp = &pack2->temp; + *timestamp = &pack2->timestamp; + return sizeof(*pack2); + } + + /* Accel data only. */ + if (header & INV_ICM45600_FIFO_HEADER_ACCEL) { + *accel = &pack1->data; + *gyro = NULL; + *temp = &pack1->temp; + *timestamp = NULL; + return sizeof(*pack1); + } + + /* Gyro data only. */ + if (header & INV_ICM45600_FIFO_HEADER_GYRO) { + *accel = NULL; + *gyro = &pack1->data; + *temp = &pack1->temp; + *timestamp = NULL; + return sizeof(*pack1); + } + + /* Invalid packet if here. */ + return -EINVAL; +} + +void inv_icm45600_buffer_update_fifo_period(struct inv_icm45600_state *st) +{ + u32 period_gyro, period_accel; + + if (st->fifo.en & INV_ICM45600_SENSOR_GYRO) + period_gyro = inv_icm45600_odr_to_period(st->conf.gyro.odr); + else + period_gyro = U32_MAX; + + if (st->fifo.en & INV_ICM45600_SENSOR_ACCEL) + period_accel = inv_icm45600_odr_to_period(st->conf.accel.odr); + else + period_accel = U32_MAX; + + st->fifo.period = min(period_gyro, period_accel); +} + +int inv_icm45600_buffer_set_fifo_en(struct inv_icm45600_state *st, + unsigned int fifo_en) +{ + unsigned int mask; + int ret; + + mask = INV_ICM45600_FIFO_CONFIG3_GYRO_EN | + INV_ICM45600_FIFO_CONFIG3_ACCEL_EN; + + ret = regmap_assign_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3, mask, + (fifo_en & INV_ICM45600_SENSOR_GYRO) || + (fifo_en & INV_ICM45600_SENSOR_ACCEL)); + if (ret) + return ret; + + st->fifo.en = fifo_en; + inv_icm45600_buffer_update_fifo_period(st); + + return 0; +} + +static unsigned int inv_icm45600_wm_truncate(unsigned int watermark, size_t packet_size, + unsigned int fifo_period) +{ + size_t watermark_max, grace_samples; + + /* Keep 20ms for processing FIFO.*/ + grace_samples = (20U * NSEC_PER_MSEC) / fifo_period; + if (grace_samples < 1) + grace_samples = 1; + + watermark_max = INV_ICM45600_FIFO_SIZE_MAX / packet_size; + watermark_max -= grace_samples; + + return min(watermark, watermark_max); +} + +/** + * inv_icm45600_buffer_update_watermark - update watermark FIFO threshold + * @st: driver internal state + * + * FIFO watermark threshold is computed based on the required watermark values + * set for gyro and accel sensors. Since watermark is all about acceptable data + * latency, use the smallest setting between the 2. It means choosing the + * smallest latency but this is not as simple as choosing the smallest watermark + * value. Latency depends on watermark and ODR. It requires several steps: + * 1) compute gyro and accel latencies and choose the smallest value. + * 2) adapt the chosen latency so that it is a multiple of both gyro and accel + * ones. Otherwise it is possible that you don't meet a requirement. (for + * example with gyro @100Hz wm 4 and accel @100Hz with wm 6, choosing the + * value of 4 will not meet accel latency requirement because 6 is not a + * multiple of 4. You need to use the value 2.) + * 3) Since all periods are multiple of each others, watermark is computed by + * dividing this computed latency by the smallest period, which corresponds + * to the FIFO frequency. + * + * Returns: 0 on success, a negative error code otherwise. + */ +int inv_icm45600_buffer_update_watermark(struct inv_icm45600_state *st) +{ + const size_t packet_size = sizeof(struct inv_icm45600_fifo_2sensors_packet); + unsigned int wm_gyro, wm_accel, watermark; + u32 period_gyro, period_accel, period; + u32 latency_gyro, latency_accel, latency; + + /* Compute sensors latency, depending on sensor watermark and odr. */ + wm_gyro = inv_icm45600_wm_truncate(st->fifo.watermark.gyro, packet_size, + st->fifo.period); + wm_accel = inv_icm45600_wm_truncate(st->fifo.watermark.accel, packet_size, + st->fifo.period); + /* Use us for odr to avoid overflow using 32 bits values. */ + period_gyro = inv_icm45600_odr_to_period(st->conf.gyro.odr) / NSEC_PER_USEC; + period_accel = inv_icm45600_odr_to_period(st->conf.accel.odr) / NSEC_PER_USEC; + latency_gyro = period_gyro * wm_gyro; + latency_accel = period_accel * wm_accel; + + /* 0 value for watermark means that the sensor is turned off. */ + if (wm_gyro == 0 && wm_accel == 0) + return 0; + + if (latency_gyro == 0) { + watermark = wm_accel; + st->fifo.watermark.eff_accel = wm_accel; + } else if (latency_accel == 0) { + watermark = wm_gyro; + st->fifo.watermark.eff_gyro = wm_gyro; + } else { + /* Compute the smallest latency that is a multiple of both. */ + if (latency_gyro <= latency_accel) + latency = latency_gyro - (latency_accel % latency_gyro); + else + latency = latency_accel - (latency_gyro % latency_accel); + /* Use the shortest period. */ + period = min(period_gyro, period_accel); + /* All this works because periods are multiple of each others. */ + watermark = max(latency / period, 1); + /* Update effective watermark. */ + st->fifo.watermark.eff_gyro = max(latency / period_gyro, 1); + st->fifo.watermark.eff_accel = max(latency / period_accel, 1); + } + + st->buffer.u16 = cpu_to_le16(watermark); + return regmap_bulk_write(st->map, INV_ICM45600_REG_FIFO_WATERMARK, + &st->buffer.u16, sizeof(st->buffer.u16)); +} + +static int inv_icm45600_buffer_preenable(struct iio_dev *indio_dev) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct device *dev = regmap_get_device(st->map); + struct inv_icm45600_sensor_state *sensor_st = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = &sensor_st->ts; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + guard(mutex)(&st->lock); + inv_sensors_timestamp_reset(ts); + + return 0; +} + +/* + * Update_scan_mode callback is turning sensors on and setting data FIFO enable + * bits. + */ +static int inv_icm45600_buffer_postenable(struct iio_dev *indio_dev) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + unsigned int val; + int ret; + + guard(mutex)(&st->lock); + + /* Exit if FIFO is already on. */ + if (st->fifo.on) { + st->fifo.on++; + return 0; + } + + ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG2, + INV_ICM45600_REG_FIFO_CONFIG2_FIFO_FLUSH); + if (ret) + return ret; + + ret = regmap_set_bits(st->map, INV_ICM45600_REG_INT1_CONFIG0, + INV_ICM45600_INT1_CONFIG0_FIFO_THS_EN | + INV_ICM45600_INT1_CONFIG0_FIFO_FULL_EN); + if (ret) + return ret; + + val = FIELD_PREP(INV_ICM45600_FIFO_CONFIG0_MODE_MASK, + INV_ICM45600_FIFO_CONFIG0_MODE_STREAM); + ret = regmap_update_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG0, + INV_ICM45600_FIFO_CONFIG0_MODE_MASK, val); + if (ret) + return ret; + + /* Enable writing sensor data to FIFO. */ + ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3, + INV_ICM45600_FIFO_CONFIG3_IF_EN); + if (ret) + return ret; + + st->fifo.on++; + return 0; +} + +static int inv_icm45600_buffer_predisable(struct iio_dev *indio_dev) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + unsigned int val; + int ret; + + guard(mutex)(&st->lock); + + /* Exit if there are several sensors using the FIFO. */ + if (st->fifo.on > 1) { + st->fifo.on--; + return 0; + } + + /* Disable writing sensor data to FIFO. */ + ret = regmap_clear_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3, + INV_ICM45600_FIFO_CONFIG3_IF_EN); + if (ret) + return ret; + + val = FIELD_PREP(INV_ICM45600_FIFO_CONFIG0_MODE_MASK, + INV_ICM45600_FIFO_CONFIG0_MODE_BYPASS); + ret = regmap_update_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG0, + INV_ICM45600_FIFO_CONFIG0_MODE_MASK, val); + if (ret) + return ret; + + ret = regmap_clear_bits(st->map, INV_ICM45600_REG_INT1_CONFIG0, + INV_ICM45600_INT1_CONFIG0_FIFO_THS_EN | + INV_ICM45600_INT1_CONFIG0_FIFO_FULL_EN); + if (ret) + return ret; + + ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG2, + INV_ICM45600_REG_FIFO_CONFIG2_FIFO_FLUSH); + if (ret) + return ret; + + st->fifo.on--; + return 0; +} + +static int _inv_icm45600_buffer_postdisable(struct inv_icm45600_state *st, + unsigned int sensor, unsigned int *watermark, + unsigned int *sleep) +{ + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + ret = inv_icm45600_buffer_set_fifo_en(st, st->fifo.en & ~sensor); + if (ret) + return ret; + + *watermark = 0; + ret = inv_icm45600_buffer_update_watermark(st); + if (ret) + return ret; + + conf.mode = INV_ICM45600_SENSOR_MODE_OFF; + if (sensor == INV_ICM45600_SENSOR_GYRO) + return inv_icm45600_set_gyro_conf(st, &conf, sleep); + else + return inv_icm45600_set_accel_conf(st, &conf, sleep); +} + +static int inv_icm45600_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int sensor; + unsigned int *watermark; + unsigned int sleep; + int ret; + + if (indio_dev == st->indio_gyro) { + sensor = INV_ICM45600_SENSOR_GYRO; + watermark = &st->fifo.watermark.gyro; + } else if (indio_dev == st->indio_accel) { + sensor = INV_ICM45600_SENSOR_ACCEL; + watermark = &st->fifo.watermark.accel; + } else { + return -EINVAL; + } + + scoped_guard(mutex, &st->lock) + ret = _inv_icm45600_buffer_postdisable(st, sensor, watermark, &sleep); + + /* Sleep required time. */ + if (sleep) + msleep(sleep); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +const struct iio_buffer_setup_ops inv_icm45600_buffer_ops = { + .preenable = inv_icm45600_buffer_preenable, + .postenable = inv_icm45600_buffer_postenable, + .predisable = inv_icm45600_buffer_predisable, + .postdisable = inv_icm45600_buffer_postdisable, +}; + +int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st) +{ + const ssize_t packet_size = sizeof(struct inv_icm45600_fifo_2sensors_packet); + __le16 *raw_fifo_count; + size_t fifo_nb, i; + ssize_t size; + const struct inv_icm45600_fifo_sensor_data *accel, *gyro; + const __le16 *timestamp; + const s8 *temp; + unsigned int odr; + int ret; + + /* Reset all samples counters. */ + st->fifo.count = 0; + st->fifo.nb.gyro = 0; + st->fifo.nb.accel = 0; + st->fifo.nb.total = 0; + + raw_fifo_count = &st->buffer.u16; + ret = regmap_bulk_read(st->map, INV_ICM45600_REG_FIFO_COUNT, + raw_fifo_count, sizeof(*raw_fifo_count)); + if (ret) + return ret; + + /* Check and limit number of samples if requested. */ + fifo_nb = le16_to_cpup(raw_fifo_count); + if (fifo_nb == 0) + return 0; + + /* Try to read all FIFO data in internal buffer. */ + st->fifo.count = fifo_nb * packet_size; + ret = regmap_noinc_read(st->map, INV_ICM45600_REG_FIFO_DATA, + st->fifo.data, st->fifo.count); + if (ret == -ENOTSUPP || ret == -EFBIG) { + /* Read full fifo is not supported, read samples one by one. */ + ret = 0; + for (i = 0; i < st->fifo.count && ret == 0; i += packet_size) + ret = regmap_noinc_read(st->map, INV_ICM45600_REG_FIFO_DATA, + &st->fifo.data[i], packet_size); + } + if (ret) + return ret; + + for (i = 0; i < st->fifo.count; i += size) { + size = inv_icm45600_fifo_decode_packet(&st->fifo.data[i], &accel, &gyro, + &temp, ×tamp, &odr); + if (size <= 0) + /* No more sample in buffer */ + break; + if (gyro && inv_icm45600_fifo_is_data_valid(gyro)) + st->fifo.nb.gyro++; + if (accel && inv_icm45600_fifo_is_data_valid(accel)) + st->fifo.nb.accel++; + st->fifo.nb.total++; + } + + return 0; +} + +int inv_icm45600_buffer_init(struct inv_icm45600_state *st) +{ + int ret; + unsigned int val; + + st->fifo.watermark.eff_gyro = 1; + st->fifo.watermark.eff_accel = 1; + + /* Disable all FIFO EN bits. */ + ret = regmap_write(st->map, INV_ICM45600_REG_FIFO_CONFIG3, 0); + if (ret) + return ret; + + /* Disable FIFO and set depth. */ + val = FIELD_PREP(INV_ICM45600_FIFO_CONFIG0_MODE_MASK, + INV_ICM45600_FIFO_CONFIG0_MODE_BYPASS) | + FIELD_PREP(INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MASK, + INV_ICM45600_FIFO_CONFIG0_FIFO_DEPTH_MAX); + + ret = regmap_write(st->map, INV_ICM45600_REG_FIFO_CONFIG0, val); + if (ret) + return ret; + + /* Enable only timestamp in fifo, disable compression. */ + ret = regmap_write(st->map, INV_ICM45600_REG_FIFO_CONFIG4, + INV_ICM45600_FIFO_CONFIG4_TMST_FSYNC_EN); + if (ret) + return ret; + + /* Enable FIFO continuous watermark interrupt. */ + return regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG2, + INV_ICM45600_REG_FIFO_CONFIG2_WM_GT_TH); +} diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h new file mode 100644 index 000000000000..b4c700fa4e9f --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2025 Invensense, Inc. */ + +#ifndef INV_ICM45600_BUFFER_H_ +#define INV_ICM45600_BUFFER_H_ + +#include +#include +#include + +#include + +#include + +struct inv_icm45600_state; + +#define INV_ICM45600_SENSOR_GYRO BIT(0) +#define INV_ICM45600_SENSOR_ACCEL BIT(1) +#define INV_ICM45600_SENSOR_TEMP BIT(2) + +/** + * struct inv_icm45600_fifo - FIFO state variables + * @on: reference counter for FIFO on. + * @en: bits field of INV_ICM45600_SENSOR_* for FIFO EN bits. + * @period: FIFO internal period. + * @watermark: watermark configuration values for accel and gyro. + * @watermark.gyro: requested watermark for gyro. + * @watermark.accel: requested watermark for accel. + * @watermark.eff_gyro: effective watermark for gyro. + * @watermark.eff_accel: effective watermark for accel. + * @count: number of bytes in the FIFO data buffer. + * @nb: gyro, accel and total samples in the FIFO data buffer. + * @data: FIFO data buffer aligned for DMA (8kB) + */ +struct inv_icm45600_fifo { + unsigned int on; + unsigned int en; + u32 period; + struct { + unsigned int gyro; + unsigned int accel; + unsigned int eff_gyro; + unsigned int eff_accel; + } watermark; + size_t count; + struct { + size_t gyro; + size_t accel; + size_t total; + } nb; + u8 *data; +}; + +/* FIFO data packet */ +struct inv_icm45600_fifo_sensor_data { + __le16 x; + __le16 y; + __le16 z; +} __packed; +#define INV_ICM45600_DATA_INVALID S16_MIN + +static inline bool +inv_icm45600_fifo_is_data_valid(const struct inv_icm45600_fifo_sensor_data *s) +{ + s16 x, y, z; + + x = le16_to_cpu(s->x); + y = le16_to_cpu(s->y); + z = le16_to_cpu(s->z); + + return (x != INV_ICM45600_DATA_INVALID || + y != INV_ICM45600_DATA_INVALID || + z != INV_ICM45600_DATA_INVALID); +} + +ssize_t inv_icm45600_fifo_decode_packet(const void *packet, + const struct inv_icm45600_fifo_sensor_data **accel, + const struct inv_icm45600_fifo_sensor_data **gyro, + const s8 **temp, + const __le16 **timestamp, unsigned int *odr); + +extern const struct iio_buffer_setup_ops inv_icm45600_buffer_ops; + +int inv_icm45600_buffer_init(struct inv_icm45600_state *st); + +void inv_icm45600_buffer_update_fifo_period(struct inv_icm45600_state *st); + +int inv_icm45600_buffer_set_fifo_en(struct inv_icm45600_state *st, + unsigned int fifo_en); + +int inv_icm45600_buffer_update_watermark(struct inv_icm45600_state *st); + +int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st); + +int inv_icm45600_buffer_hwfifo_flush(struct inv_icm45600_state *st, + unsigned int count); + +#endif diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c index 280cdd40f86b..118450b3c9f9 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c @@ -5,11 +5,14 @@ #include #include #include +#include +#include #include #include #include #include #include +#include #include #include #include @@ -19,6 +22,7 @@ #include +#include "inv_icm45600_buffer.h" #include "inv_icm45600.h" static int inv_icm45600_ireg_read(struct regmap *map, unsigned int reg, @@ -435,6 +439,94 @@ static int inv_icm45600_setup(struct inv_icm45600_state *st, return inv_icm45600_set_conf(st, chip_info->conf); } +static irqreturn_t inv_icm45600_irq_timestamp(int irq, void *_data) +{ + struct inv_icm45600_state *st = _data; + + st->timestamp.gyro = iio_get_time_ns(st->indio_gyro); + st->timestamp.accel = iio_get_time_ns(st->indio_accel); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t inv_icm45600_irq_handler(int irq, void *_data) +{ + struct inv_icm45600_state *st = _data; + struct device *dev = regmap_get_device(st->map); + unsigned int mask, status; + int ret; + + guard(mutex)(&st->lock); + + ret = regmap_read(st->map, INV_ICM45600_REG_INT_STATUS, &status); + if (ret) + return IRQ_HANDLED; + + /* Read the FIFO data. */ + mask = INV_ICM45600_INT_STATUS_FIFO_THS | INV_ICM45600_INT_STATUS_FIFO_FULL; + if (status & mask) { + ret = inv_icm45600_buffer_fifo_read(st); + if (ret) { + dev_err(dev, "FIFO read error %d\n", ret); + return IRQ_HANDLED; + } + } + + /* FIFO full warning. */ + if (status & INV_ICM45600_INT_STATUS_FIFO_FULL) + dev_warn(dev, "FIFO full possible data lost!\n"); + + return IRQ_HANDLED; +} + +/** + * inv_icm45600_irq_init() - initialize int pin and interrupt handler + * @st: driver internal state + * @irq: irq number + * @irq_type: irq trigger type + * @open_drain: true if irq is open drain, false for push-pull + * + * Returns: 0 on success, a negative error code otherwise. + */ +static int inv_icm45600_irq_init(struct inv_icm45600_state *st, int irq, + int irq_type, bool open_drain) +{ + struct device *dev = regmap_get_device(st->map); + unsigned int val; + int ret; + + /* Configure INT1 interrupt: default is active low on edge. */ + switch (irq_type) { + case IRQF_TRIGGER_RISING: + case IRQF_TRIGGER_HIGH: + val = INV_ICM45600_INT1_CONFIG2_ACTIVE_HIGH; + break; + default: + val = INV_ICM45600_INT1_CONFIG2_ACTIVE_LOW; + break; + } + + switch (irq_type) { + case IRQF_TRIGGER_LOW: + case IRQF_TRIGGER_HIGH: + val |= INV_ICM45600_INT1_CONFIG2_LATCHED; + break; + default: + break; + } + + if (!open_drain) + val |= INV_ICM45600_INT1_CONFIG2_PUSH_PULL; + + ret = regmap_write(st->map, INV_ICM45600_REG_INT1_CONFIG2, val); + if (ret) + return ret; + + return devm_request_threaded_irq(dev, irq, inv_icm45600_irq_timestamp, + inv_icm45600_irq_handler, irq_type | IRQF_ONESHOT, + "inv_icm45600", st); +} + static int inv_icm45600_timestamp_setup(struct inv_icm45600_state *st) { /* Enable timestamps. */ @@ -476,8 +568,21 @@ int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chi struct device *dev = regmap_get_device(regmap); struct inv_icm45600_state *st; struct regmap *regmap_custom; + struct fwnode_handle *fwnode; + int irq, irq_type; + bool open_drain; int ret; + /* Get INT1 only supported interrupt. */ + fwnode = dev_fwnode(dev); + irq = fwnode_irq_get_byname(fwnode, "int1"); + if (irq < 0) + return dev_err_probe(dev, irq, "Missing int1 interrupt\n"); + + irq_type = irq_get_trigger_type(irq); + + open_drain = device_property_read_bool(dev, "drive-open-drain"); + regmap_custom = devm_regmap_init(dev, &inv_icm45600_regmap_bus, regmap, &inv_icm45600_regmap_config); if (IS_ERR(regmap_custom)) @@ -489,6 +594,10 @@ int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chi dev_set_drvdata(dev, st); + st->fifo.data = devm_kzalloc(dev, 8192, GFP_KERNEL); + if (!st->fifo.data) + return -ENOMEM; + ret = devm_mutex_init(dev, &st->lock); if (ret) return ret; @@ -529,6 +638,14 @@ int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chi if (ret) return ret; + ret = inv_icm45600_buffer_init(st); + if (ret) + return ret; + + ret = inv_icm45600_irq_init(st, irq, irq_type, open_drain); + if (ret) + return ret; + ret = devm_pm_runtime_set_active_enabled(dev); if (ret) return ret; @@ -548,8 +665,26 @@ EXPORT_SYMBOL_NS_GPL(inv_icm45600_core_probe, "IIO_ICM45600"); static int inv_icm45600_suspend(struct device *dev) { struct inv_icm45600_state *st = dev_get_drvdata(dev); + int ret; scoped_guard(mutex, &st->lock) { + /* Disable FIFO data streaming. */ + if (st->fifo.on) { + unsigned int val; + + /* Clear FIFO_CONFIG3_IF_EN before changing the FIFO configuration */ + ret = regmap_clear_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3, + INV_ICM45600_FIFO_CONFIG3_IF_EN); + if (ret) + return ret; + val = FIELD_PREP(INV_ICM45600_FIFO_CONFIG0_MODE_MASK, + INV_ICM45600_FIFO_CONFIG0_MODE_BYPASS); + ret = regmap_update_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG0, + INV_ICM45600_FIFO_CONFIG0_MODE_MASK, val); + if (ret) + return ret; + } + /* Save sensors states */ st->suspended.gyro = st->conf.gyro.mode; st->suspended.accel = st->conf.accel.mode; @@ -575,6 +710,29 @@ static int inv_icm45600_resume(struct device *dev) /* Restore sensors state. */ ret = inv_icm45600_set_pwr_mgmt0(st, st->suspended.gyro, st->suspended.accel, NULL); + if (ret) + return ret; + + /* Restore FIFO data streaming. */ + if (st->fifo.on) { + struct inv_icm45600_sensor_state *gyro_st = iio_priv(st->indio_gyro); + struct inv_icm45600_sensor_state *accel_st = iio_priv(st->indio_accel); + unsigned int val; + + inv_sensors_timestamp_reset(&gyro_st->ts); + inv_sensors_timestamp_reset(&accel_st->ts); + val = FIELD_PREP(INV_ICM45600_FIFO_CONFIG0_MODE_MASK, + INV_ICM45600_FIFO_CONFIG0_MODE_STREAM); + ret = regmap_update_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG0, + INV_ICM45600_FIFO_CONFIG0_MODE_MASK, val); + if (ret) + return ret; + /* FIFO_CONFIG3_IF_EN must only be set at end of FIFO the configuration */ + ret = regmap_set_bits(st->map, INV_ICM45600_REG_FIFO_CONFIG3, + INV_ICM45600_FIFO_CONFIG3_IF_EN); + if (ret) + return ret; + } } return ret; From 27e072bc34d12857cfd9f8a8424450c2aa6ecd47 Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:05 +0000 Subject: [PATCH 069/304] iio: imu: inv_icm45600: add IMU IIO gyroscope device Add IIO device for gyroscope sensor with data polling interface and FIFO parsing. Attributes: raw, scale, sampling_frequency, calibbias. Temperature is available as a processed channel. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/Kconfig | 2 + drivers/iio/imu/inv_icm45600/Makefile | 1 + drivers/iio/imu/inv_icm45600/inv_icm45600.h | 38 + .../imu/inv_icm45600/inv_icm45600_buffer.c | 56 +- .../imu/inv_icm45600/inv_icm45600_buffer.h | 5 +- .../iio/imu/inv_icm45600/inv_icm45600_core.c | 179 +++- .../iio/imu/inv_icm45600/inv_icm45600_gyro.c | 791 ++++++++++++++++++ 7 files changed, 1069 insertions(+), 3 deletions(-) create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_gyro.c diff --git a/drivers/iio/imu/inv_icm45600/Kconfig b/drivers/iio/imu/inv_icm45600/Kconfig index 8cb5543e0a58..ea0a8d20cba2 100644 --- a/drivers/iio/imu/inv_icm45600/Kconfig +++ b/drivers/iio/imu/inv_icm45600/Kconfig @@ -2,4 +2,6 @@ config INV_ICM45600 tristate + select IIO_BUFFER + select IIO_KFIFO_BUF select IIO_INV_SENSORS_TIMESTAMP diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile index 72f95bc30d99..b5954b4053c2 100644 --- a/drivers/iio/imu/inv_icm45600/Makefile +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_INV_ICM45600) += inv-icm45600.o inv-icm45600-y += inv_icm45600_core.o inv-icm45600-y += inv_icm45600_buffer.o +inv-icm45600-y += inv_icm45600_gyro.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600.h b/drivers/iio/imu/inv_icm45600/inv_icm45600.h index aac8cd852c12..674c2b4091ef 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600.h +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600.h @@ -113,8 +113,22 @@ struct inv_icm45600_chip_info { u8 whoami; const char *name; const struct inv_icm45600_conf *conf; + const int *gyro_scales; + const int gyro_scales_len; }; +extern const struct inv_icm45600_chip_info inv_icm45605_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45606_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45608_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45634_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45686_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45687_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45688p_chip_info; +extern const struct inv_icm45600_chip_info inv_icm45689_chip_info; + +extern const int inv_icm45600_gyro_scale[][2]; +extern const int inv_icm45686_gyro_scale[][2]; + /** * struct inv_icm45600_state - driver state variables * @lock: lock for serializing multiple registers access. @@ -319,6 +333,26 @@ const struct iio_mount_matrix * inv_icm45600_get_mount_matrix(const struct iio_dev *indio_dev, const struct iio_chan_spec *chan); +#define INV_ICM45600_TEMP_CHAN(_index) \ + { \ + .type = IIO_TEMP, \ + .info_mask_separate = \ + BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ + } + +int inv_icm45600_temp_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask); + u32 inv_icm45600_odr_to_period(enum inv_icm45600_odr odr); int inv_icm45600_set_accel_conf(struct inv_icm45600_state *st, @@ -336,4 +370,8 @@ int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chip_info *chip_info, bool reset, inv_icm45600_bus_setup bus_setup); +struct iio_dev *inv_icm45600_gyro_init(struct inv_icm45600_state *st); + +int inv_icm45600_gyro_parse_fifo(struct iio_dev *indio_dev); + #endif diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c index 5542ad8af2a6..2800995bfa32 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c @@ -389,7 +389,8 @@ const struct iio_buffer_setup_ops inv_icm45600_buffer_ops = { .postdisable = inv_icm45600_buffer_postdisable, }; -int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st) +int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st, + unsigned int max) { const ssize_t packet_size = sizeof(struct inv_icm45600_fifo_2sensors_packet); __le16 *raw_fifo_count; @@ -417,6 +418,8 @@ int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st) fifo_nb = le16_to_cpup(raw_fifo_count); if (fifo_nb == 0) return 0; + if (max > 0 && fifo_nb > max) + fifo_nb = max; /* Try to read all FIFO data in internal buffer. */ st->fifo.count = fifo_nb * packet_size; @@ -448,6 +451,57 @@ int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st) return 0; } +int inv_icm45600_buffer_fifo_parse(struct inv_icm45600_state *st) +{ + struct inv_icm45600_sensor_state *gyro_st = iio_priv(st->indio_gyro); + struct inv_sensors_timestamp *ts; + int ret; + + if (st->fifo.nb.total == 0) + return 0; + + /* Handle gyroscope timestamp and FIFO data parsing. */ + if (st->fifo.nb.gyro > 0) { + ts = &gyro_st->ts; + inv_sensors_timestamp_interrupt(ts, st->fifo.watermark.eff_gyro, + st->timestamp.gyro); + ret = inv_icm45600_gyro_parse_fifo(st->indio_gyro); + if (ret) + return ret; + } + + return 0; +} + +int inv_icm45600_buffer_hwfifo_flush(struct inv_icm45600_state *st, + unsigned int count) +{ + struct inv_icm45600_sensor_state *gyro_st = iio_priv(st->indio_gyro); + struct inv_sensors_timestamp *ts; + s64 gyro_ts, accel_ts; + int ret; + + gyro_ts = iio_get_time_ns(st->indio_gyro); + accel_ts = iio_get_time_ns(st->indio_accel); + + ret = inv_icm45600_buffer_fifo_read(st, count); + if (ret) + return ret; + + if (st->fifo.nb.total == 0) + return 0; + + if (st->fifo.nb.gyro > 0) { + ts = &gyro_st->ts; + inv_sensors_timestamp_interrupt(ts, st->fifo.nb.gyro, gyro_ts); + ret = inv_icm45600_gyro_parse_fifo(st->indio_gyro); + if (ret) + return ret; + } + + return 0; +} + int inv_icm45600_buffer_init(struct inv_icm45600_state *st) { int ret; diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h index b4c700fa4e9f..e047871cdbe2 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.h @@ -90,7 +90,10 @@ int inv_icm45600_buffer_set_fifo_en(struct inv_icm45600_state *st, int inv_icm45600_buffer_update_watermark(struct inv_icm45600_state *st); -int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st); +int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st, + unsigned int max); + +int inv_icm45600_buffer_fifo_parse(struct inv_icm45600_state *st); int inv_icm45600_buffer_hwfifo_flush(struct inv_icm45600_state *st, unsigned int count); diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c index 118450b3c9f9..0484e675069f 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c @@ -136,6 +136,97 @@ static const struct regmap_config inv_icm45600_regmap_config = { .val_bits = 8, }; +/* These are the chip initial default configurations (default FS value is based on icm45686) */ +static const struct inv_icm45600_conf inv_icm45600_default_conf = { + .gyro = { + .mode = INV_ICM45600_SENSOR_MODE_OFF, + .fs = INV_ICM45686_GYRO_FS_2000DPS, + .odr = INV_ICM45600_ODR_800HZ_LN, + .filter = INV_ICM45600_GYRO_LP_AVG_SEL_8X, + }, +}; + +static const struct inv_icm45600_conf inv_icm45686_default_conf = { + .gyro = { + .mode = INV_ICM45600_SENSOR_MODE_OFF, + .fs = INV_ICM45686_GYRO_FS_4000DPS, + .odr = INV_ICM45600_ODR_800HZ_LN, + .filter = INV_ICM45600_GYRO_LP_AVG_SEL_8X, + }, +}; + +const struct inv_icm45600_chip_info inv_icm45605_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45605, + .name = "icm45605", + .conf = &inv_icm45600_default_conf, + .gyro_scales = (const int *)inv_icm45600_gyro_scale, + .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45605_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45606_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45606, + .name = "icm45606", + .conf = &inv_icm45600_default_conf, + .gyro_scales = (const int *)inv_icm45600_gyro_scale, + .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45606_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45608_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45608, + .name = "icm45608", + .conf = &inv_icm45600_default_conf, + .gyro_scales = (const int *)inv_icm45600_gyro_scale, + .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45608_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45634_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45634, + .name = "icm45634", + .conf = &inv_icm45600_default_conf, + .gyro_scales = (const int *)inv_icm45600_gyro_scale, + .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45634_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45686_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45686, + .name = "icm45686", + .conf = &inv_icm45686_default_conf, + .gyro_scales = (const int *)inv_icm45686_gyro_scale, + .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45686_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45687_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45687, + .name = "icm45687", + .conf = &inv_icm45686_default_conf, + .gyro_scales = (const int *)inv_icm45686_gyro_scale, + .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45687_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45688p_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45688P, + .name = "icm45688p", + .conf = &inv_icm45686_default_conf, + .gyro_scales = (const int *)inv_icm45686_gyro_scale, + .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45688p_chip_info, "IIO_ICM45600"); + +const struct inv_icm45600_chip_info inv_icm45689_chip_info = { + .whoami = INV_ICM45600_WHOAMI_ICM45689, + .name = "icm45689", + .conf = &inv_icm45686_default_conf, + .gyro_scales = (const int *)inv_icm45686_gyro_scale, + .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, +}; +EXPORT_SYMBOL_NS_GPL(inv_icm45689_chip_info, "IIO_ICM45600"); + const struct iio_mount_matrix * inv_icm45600_get_mount_matrix(const struct iio_dev *indio_dev, const struct iio_chan_spec *chan) @@ -465,11 +556,14 @@ static irqreturn_t inv_icm45600_irq_handler(int irq, void *_data) /* Read the FIFO data. */ mask = INV_ICM45600_INT_STATUS_FIFO_THS | INV_ICM45600_INT_STATUS_FIFO_FULL; if (status & mask) { - ret = inv_icm45600_buffer_fifo_read(st); + ret = inv_icm45600_buffer_fifo_read(st, 0); if (ret) { dev_err(dev, "FIFO read error %d\n", ret); return IRQ_HANDLED; } + ret = inv_icm45600_buffer_fifo_parse(st); + if (ret) + dev_err(dev, "FIFO parsing error %d\n", ret); } /* FIFO full warning. */ @@ -642,6 +736,10 @@ int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chi if (ret) return ret; + st->indio_gyro = inv_icm45600_gyro_init(st); + if (IS_ERR(st->indio_gyro)) + return PTR_ERR(st->indio_gyro); + ret = inv_icm45600_irq_init(st, irq, irq_type, open_drain); if (ret) return ret; @@ -767,6 +865,85 @@ static int inv_icm45600_runtime_resume(struct device *dev) return inv_icm45600_enable_regulator_vddio(st); } +static int _inv_icm45600_temp_read(struct inv_icm45600_state *st, s16 *temp) +{ + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + /* Make sure a sensor is on. */ + if (st->conf.gyro.mode == INV_ICM45600_SENSOR_MODE_OFF && + st->conf.accel.mode == INV_ICM45600_SENSOR_MODE_OFF) { + conf.mode = INV_ICM45600_SENSOR_MODE_LOW_POWER; + ret = inv_icm45600_set_accel_conf(st, &conf, NULL); + if (ret) + return ret; + } + + ret = regmap_bulk_read(st->map, INV_ICM45600_REG_TEMP_DATA, + &st->buffer.u16, sizeof(st->buffer.u16)); + if (ret) + return ret; + + *temp = (s16)le16_to_cpup(&st->buffer.u16); + if (*temp == INV_ICM45600_DATA_INVALID) + return -EINVAL; + + return 0; +} + +static int inv_icm45600_temp_read(struct inv_icm45600_state *st, s16 *temp) +{ + struct device *dev = regmap_get_device(st->map); + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = _inv_icm45600_temp_read(st, temp); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +int inv_icm45600_temp_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + s16 temp; + int ret; + + if (chan->type != IIO_TEMP) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = inv_icm45600_temp_read(st, &temp); + if (ret) + return ret; + *val = temp; + return IIO_VAL_INT; + /* + * T°C = (temp / 128) + 25 + * Tm°C = 1000 * ((temp * 100 / 12800) + 25) + * scale: 100000 / 13248 = 7.8125 + * offset: 25000 + */ + case IIO_CHAN_INFO_SCALE: + *val = 7; + *val2 = 812500; + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_OFFSET: + *val = 25000; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + EXPORT_NS_GPL_DEV_PM_OPS(inv_icm45600_pm_ops, IIO_ICM45600) = { SYSTEM_SLEEP_PM_OPS(inv_icm45600_suspend, inv_icm45600_resume) RUNTIME_PM_OPS(inv_icm45600_runtime_suspend, diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_gyro.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_gyro.c new file mode 100644 index 000000000000..1e85fd0e4ea9 --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_gyro.c @@ -0,0 +1,791 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 Invensense, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "inv_icm45600_buffer.h" +#include "inv_icm45600.h" + +enum inv_icm45600_gyro_scan { + INV_ICM45600_GYRO_SCAN_X, + INV_ICM45600_GYRO_SCAN_Y, + INV_ICM45600_GYRO_SCAN_Z, + INV_ICM45600_GYRO_SCAN_TEMP, + INV_ICM45600_GYRO_SCAN_TIMESTAMP, +}; + +static const struct iio_chan_spec_ext_info inv_icm45600_gyro_ext_infos[] = { + IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, inv_icm45600_get_mount_matrix), + { } +}; + +#define INV_ICM45600_GYRO_CHAN(_modifier, _index, _ext_info) \ + { \ + .type = IIO_ANGL_VEL, \ + .modified = 1, \ + .channel2 = _modifier, \ + .info_mask_separate = \ + BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_type = \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_all = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ + .ext_info = _ext_info, \ + } + +static const struct iio_chan_spec inv_icm45600_gyro_channels[] = { + INV_ICM45600_GYRO_CHAN(IIO_MOD_X, INV_ICM45600_GYRO_SCAN_X, + inv_icm45600_gyro_ext_infos), + INV_ICM45600_GYRO_CHAN(IIO_MOD_Y, INV_ICM45600_GYRO_SCAN_Y, + inv_icm45600_gyro_ext_infos), + INV_ICM45600_GYRO_CHAN(IIO_MOD_Z, INV_ICM45600_GYRO_SCAN_Z, + inv_icm45600_gyro_ext_infos), + INV_ICM45600_TEMP_CHAN(INV_ICM45600_GYRO_SCAN_TEMP), + IIO_CHAN_SOFT_TIMESTAMP(INV_ICM45600_GYRO_SCAN_TIMESTAMP), +}; + +/* + * IIO buffer data: size must be a power of 2 and timestamp aligned + * 16 bytes: 6 bytes angular velocity, 2 bytes temperature, 8 bytes timestamp + */ +struct inv_icm45600_gyro_buffer { + struct inv_icm45600_fifo_sensor_data gyro; + s16 temp; + aligned_s64 timestamp; +}; + +static const unsigned long inv_icm45600_gyro_scan_masks[] = { + /* 3-axis gyro + temperature */ + BIT(INV_ICM45600_GYRO_SCAN_X) | + BIT(INV_ICM45600_GYRO_SCAN_Y) | + BIT(INV_ICM45600_GYRO_SCAN_Z) | + BIT(INV_ICM45600_GYRO_SCAN_TEMP), + 0 +}; + +/* enable gyroscope sensor and FIFO write */ +static int inv_icm45600_gyro_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + unsigned int fifo_en = 0; + unsigned int sleep = 0; + int ret; + + scoped_guard(mutex, &st->lock) { + if (*scan_mask & BIT(INV_ICM45600_GYRO_SCAN_TEMP)) + fifo_en |= INV_ICM45600_SENSOR_TEMP; + + if (*scan_mask & (BIT(INV_ICM45600_GYRO_SCAN_X) | + BIT(INV_ICM45600_GYRO_SCAN_Y) | + BIT(INV_ICM45600_GYRO_SCAN_Z))) { + /* enable gyro sensor */ + conf.mode = gyro_st->power_mode; + ret = inv_icm45600_set_gyro_conf(st, &conf, &sleep); + if (ret) + return ret; + fifo_en |= INV_ICM45600_SENSOR_GYRO; + } + ret = inv_icm45600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); + } + if (sleep) + msleep(sleep); + + return ret; +} + +static int _inv_icm45600_gyro_read_sensor(struct inv_icm45600_state *st, + struct inv_icm45600_sensor_state *gyro_st, + unsigned int reg, int *val) +{ + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + /* enable gyro sensor */ + conf.mode = gyro_st->power_mode; + ret = inv_icm45600_set_gyro_conf(st, &conf, NULL); + if (ret) + return ret; + + /* read gyro register data */ + ret = regmap_bulk_read(st->map, reg, &st->buffer.u16, sizeof(st->buffer.u16)); + if (ret) + return ret; + + *val = sign_extend32(le16_to_cpup(&st->buffer.u16), 15); + if (*val == INV_ICM45600_DATA_INVALID) + return -ENODATA; + + return 0; +} + +static int inv_icm45600_gyro_read_sensor(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int reg; + int ret; + + if (chan->type != IIO_ANGL_VEL) + return -EINVAL; + + switch (chan->channel2) { + case IIO_MOD_X: + reg = INV_ICM45600_REG_GYRO_DATA_X; + break; + case IIO_MOD_Y: + reg = INV_ICM45600_REG_GYRO_DATA_Y; + break; + case IIO_MOD_Z: + reg = INV_ICM45600_REG_GYRO_DATA_Z; + break; + default: + return -EINVAL; + } + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = _inv_icm45600_gyro_read_sensor(st, gyro_st, reg, val); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +/* IIO format int + nano */ +const int inv_icm45600_gyro_scale[][2] = { + /* +/- 2000dps => 0.001065264 rad/s */ + [INV_ICM45600_GYRO_FS_2000DPS] = { 0, 1065264 }, + /* +/- 1000dps => 0.000532632 rad/s */ + [INV_ICM45600_GYRO_FS_1000DPS] = { 0, 532632 }, + /* +/- 500dps => 0.000266316 rad/s */ + [INV_ICM45600_GYRO_FS_500DPS] = { 0, 266316 }, + /* +/- 250dps => 0.000133158 rad/s */ + [INV_ICM45600_GYRO_FS_250DPS] = { 0, 133158 }, + /* +/- 125dps => 0.000066579 rad/s */ + [INV_ICM45600_GYRO_FS_125DPS] = { 0, 66579 }, + /* +/- 62.5dps => 0.000033290 rad/s */ + [INV_ICM45600_GYRO_FS_62_5DPS] = { 0, 33290 }, + /* +/- 31.25dps => 0.000016645 rad/s */ + [INV_ICM45600_GYRO_FS_31_25DPS] = { 0, 16645 }, + /* +/- 15.625dps => 0.000008322 rad/s */ + [INV_ICM45600_GYRO_FS_15_625DPS] = { 0, 8322 }, +}; + +/* IIO format int + nano */ +const int inv_icm45686_gyro_scale[][2] = { + /* +/- 4000dps => 0.002130529 rad/s */ + [INV_ICM45686_GYRO_FS_4000DPS] = { 0, 2130529 }, + /* +/- 2000dps => 0.001065264 rad/s */ + [INV_ICM45686_GYRO_FS_2000DPS] = { 0, 1065264 }, + /* +/- 1000dps => 0.000532632 rad/s */ + [INV_ICM45686_GYRO_FS_1000DPS] = { 0, 532632 }, + /* +/- 500dps => 0.000266316 rad/s */ + [INV_ICM45686_GYRO_FS_500DPS] = { 0, 266316 }, + /* +/- 250dps => 0.000133158 rad/s */ + [INV_ICM45686_GYRO_FS_250DPS] = { 0, 133158 }, + /* +/- 125dps => 0.000066579 rad/s */ + [INV_ICM45686_GYRO_FS_125DPS] = { 0, 66579 }, + /* +/- 62.5dps => 0.000033290 rad/s */ + [INV_ICM45686_GYRO_FS_62_5DPS] = { 0, 33290 }, + /* +/- 31.25dps => 0.000016645 rad/s */ + [INV_ICM45686_GYRO_FS_31_25DPS] = { 0, 16645 }, + /* +/- 15.625dps => 0.000008322 rad/s */ + [INV_ICM45686_GYRO_FS_15_625DPS] = { 0, 8322 }, +}; + +static int inv_icm45600_gyro_read_scale(struct iio_dev *indio_dev, + int *val, int *val2) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + unsigned int idx; + + idx = st->conf.gyro.fs; + + /* Full scale register starts at 1 for not High FSR parts */ + if (gyro_st->scales == (const int *)&inv_icm45600_gyro_scale) + idx--; + + *val = gyro_st->scales[2 * idx]; + *val2 = gyro_st->scales[2 * idx + 1]; + return IIO_VAL_INT_PLUS_NANO; +} + +static int inv_icm45600_gyro_write_scale(struct iio_dev *indio_dev, + int val, int val2) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int idx; + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + for (idx = 0; idx < gyro_st->scales_len; idx += 2) { + if (val == gyro_st->scales[idx] && + val2 == gyro_st->scales[idx + 1]) + break; + } + if (idx == gyro_st->scales_len) + return -EINVAL; + + conf.fs = idx / 2; + + /* Full scale register starts at 1 for not High FSR parts */ + if (gyro_st->scales == (const int *)&inv_icm45600_gyro_scale) + conf.fs++; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = inv_icm45600_set_gyro_conf(st, &conf, NULL); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +/* IIO format int + micro */ +static const int inv_icm45600_gyro_odr[] = { + 1, 562500, /* 1.5625Hz */ + 3, 125000, /* 3.125Hz */ + 6, 250000, /* 6.25Hz */ + 12, 500000, /* 12.5Hz */ + 25, 0, /* 25Hz */ + 50, 0, /* 50Hz */ + 100, 0, /* 100Hz */ + 200, 0, /* 200Hz */ + 400, 0, /* 400Hz */ + 800, 0, /* 800Hz */ + 1600, 0, /* 1.6kHz */ + 3200, 0, /* 3.2kHz */ + 6400, 0, /* 6.4kHz */ +}; + +static const int inv_icm45600_gyro_odr_conv[] = { + INV_ICM45600_ODR_1_5625HZ_LP, + INV_ICM45600_ODR_3_125HZ_LP, + INV_ICM45600_ODR_6_25HZ_LP, + INV_ICM45600_ODR_12_5HZ, + INV_ICM45600_ODR_25HZ, + INV_ICM45600_ODR_50HZ, + INV_ICM45600_ODR_100HZ, + INV_ICM45600_ODR_200HZ, + INV_ICM45600_ODR_400HZ, + INV_ICM45600_ODR_800HZ_LN, + INV_ICM45600_ODR_1600HZ_LN, + INV_ICM45600_ODR_3200HZ_LN, + INV_ICM45600_ODR_6400HZ_LN, +}; + +static int inv_icm45600_gyro_read_odr(struct inv_icm45600_state *st, + int *val, int *val2) +{ + unsigned int odr; + unsigned int i; + + odr = st->conf.gyro.odr; + + for (i = 0; i < ARRAY_SIZE(inv_icm45600_gyro_odr_conv); ++i) { + if (inv_icm45600_gyro_odr_conv[i] == odr) + break; + } + if (i >= ARRAY_SIZE(inv_icm45600_gyro_odr_conv)) + return -EINVAL; + + *val = inv_icm45600_gyro_odr[2 * i]; + *val2 = inv_icm45600_gyro_odr[2 * i + 1]; + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int _inv_icm45600_gyro_write_odr(struct iio_dev *indio_dev, int odr) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = &gyro_st->ts; + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + conf.odr = odr; + ret = inv_sensors_timestamp_update_odr(ts, inv_icm45600_odr_to_period(conf.odr), + iio_buffer_enabled(indio_dev)); + if (ret) + return ret; + + if (st->conf.gyro.mode != INV_ICM45600_SENSOR_MODE_OFF) + conf.mode = gyro_st->power_mode; + + ret = inv_icm45600_set_gyro_conf(st, &conf, NULL); + if (ret) + return ret; + + inv_icm45600_buffer_update_fifo_period(st); + inv_icm45600_buffer_update_watermark(st); + + return 0; +} + +static int inv_icm45600_gyro_write_odr(struct iio_dev *indio_dev, + int val, int val2) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int idx; + int odr; + int ret; + + for (idx = 0; idx < ARRAY_SIZE(inv_icm45600_gyro_odr); idx += 2) { + if (val == inv_icm45600_gyro_odr[idx] && + val2 == inv_icm45600_gyro_odr[idx + 1]) + break; + } + if (idx >= ARRAY_SIZE(inv_icm45600_gyro_odr)) + return -EINVAL; + + odr = inv_icm45600_gyro_odr_conv[idx / 2]; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = _inv_icm45600_gyro_write_odr(indio_dev, odr); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +/* + * Calibration bias values, IIO range format int + nano. + * Value is limited to +/-62.5dps coded on 14 bits signed. Step is 7.5mdps. + */ +static int inv_icm45600_gyro_calibbias[] = { + -1, 90830336, /* min: -1.090830336 rad/s */ + 0, 133158, /* step: 0.000133158 rad/s */ + 1, 90697178, /* max: 1.090697178 rad/s */ +}; + +static int inv_icm45600_gyro_read_offset(struct inv_icm45600_state *st, + struct iio_chan_spec const *chan, + int *val, int *val2) +{ + struct device *dev = regmap_get_device(st->map); + s64 val64; + s32 bias; + unsigned int reg; + s16 offset; + int ret; + + if (chan->type != IIO_ANGL_VEL) + return -EINVAL; + + switch (chan->channel2) { + case IIO_MOD_X: + reg = INV_ICM45600_IPREG_SYS1_REG_42; + break; + case IIO_MOD_Y: + reg = INV_ICM45600_IPREG_SYS1_REG_56; + break; + case IIO_MOD_Z: + reg = INV_ICM45600_IPREG_SYS1_REG_70; + break; + default: + return -EINVAL; + } + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = regmap_bulk_read(st->map, reg, &st->buffer.u16, sizeof(st->buffer.u16)); + + pm_runtime_put_autosuspend(dev); + if (ret) + return ret; + + offset = le16_to_cpup(&st->buffer.u16) & INV_ICM45600_GYRO_OFFUSER_MASK; + /* 14 bits signed value */ + offset = sign_extend32(offset, 13); + + /* + * convert raw offset to dps then to rad/s + * 14 bits signed raw max 62.5 to dps: 625 / 81920 + * dps to rad: Pi / 180 + * result in nano (1000000000) + * (offset * 625 * Pi * 1000000000) / (81920 * 180) + */ + val64 = (s64)offset * 625LL * 3141592653LL; + /* for rounding, add + or - divisor (81920 * 180) divided by 2 */ + if (val64 >= 0) + val64 += 81920 * 180 / 2; + else + val64 -= 81920 * 180 / 2; + bias = div_s64(val64, 81920 * 180); + *val = bias / 1000000000L; + *val2 = bias % 1000000000L; + + return IIO_VAL_INT_PLUS_NANO; +} + +static int inv_icm45600_gyro_write_offset(struct inv_icm45600_state *st, + struct iio_chan_spec const *chan, + int val, int val2) +{ + struct device *dev = regmap_get_device(st->map); + s64 val64, min, max; + unsigned int reg; + s16 offset; + int ret; + + if (chan->type != IIO_ANGL_VEL) + return -EINVAL; + + switch (chan->channel2) { + case IIO_MOD_X: + reg = INV_ICM45600_IPREG_SYS1_REG_42; + break; + case IIO_MOD_Y: + reg = INV_ICM45600_IPREG_SYS1_REG_56; + break; + case IIO_MOD_Z: + reg = INV_ICM45600_IPREG_SYS1_REG_70; + break; + default: + return -EINVAL; + } + + /* inv_icm45600_gyro_calibbias: min - step - max in nano */ + min = (s64)inv_icm45600_gyro_calibbias[0] * 1000000000LL - + (s64)inv_icm45600_gyro_calibbias[1]; + max = (s64)inv_icm45600_gyro_calibbias[4] * 1000000000LL + + (s64)inv_icm45600_gyro_calibbias[5]; + val64 = (s64)val * 1000000000LL; + if (val >= 0) + val64 += (s64)val2; + else + val64 -= (s64)val2; + if (val64 < min || val64 > max) + return -EINVAL; + + /* + * convert rad/s to dps then to raw value + * rad to dps: 180 / Pi + * dps to raw 14 bits signed, max 62.5: 8192 / 62.5 + * val in nano (1000000000) + * val * 180 * 8192 / (Pi * 1000000000 * 62.5) + */ + val64 = val64 * 180LL * 8192; + /* for rounding, add + or - divisor (314159265 * 625) divided by 2 */ + if (val64 >= 0) + val64 += 314159265LL * 625LL / 2LL; + else + val64 -= 314159265LL * 625LL / 2LL; + offset = div64_s64(val64, 314159265LL * 625LL); + + /* clamp value limited to 14 bits signed */ + offset = clamp(offset, -8192, 8191); + + st->buffer.u16 = cpu_to_le16(offset & INV_ICM45600_GYRO_OFFUSER_MASK); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = regmap_bulk_write(st->map, reg, &st->buffer.u16, sizeof(st->buffer.u16)); + + pm_runtime_put_autosuspend(dev); + return ret; +} + +static int inv_icm45600_gyro_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + int ret; + + switch (chan->type) { + case IIO_ANGL_VEL: + break; + case IIO_TEMP: + return inv_icm45600_temp_read_raw(indio_dev, chan, val, val2, mask); + default: + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = inv_icm45600_gyro_read_sensor(indio_dev, chan, val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + return inv_icm45600_gyro_read_scale(indio_dev, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + return inv_icm45600_gyro_read_odr(st, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return inv_icm45600_gyro_read_offset(st, chan, val, val2); + default: + return -EINVAL; + } +} + +static int inv_icm45600_gyro_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, + int *type, int *length, long mask) +{ + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + + if (chan->type != IIO_ANGL_VEL) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = gyro_st->scales; + *type = IIO_VAL_INT_PLUS_NANO; + *length = gyro_st->scales_len; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SAMP_FREQ: + *vals = inv_icm45600_gyro_odr; + *type = IIO_VAL_INT_PLUS_MICRO; + *length = ARRAY_SIZE(inv_icm45600_gyro_odr); + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CALIBBIAS: + *vals = inv_icm45600_gyro_calibbias; + *type = IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_RANGE; + default: + return -EINVAL; + } +} + +static int inv_icm45600_gyro_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + int ret; + + if (chan->type != IIO_ANGL_VEL) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = inv_icm45600_gyro_write_scale(indio_dev, val, val2); + iio_device_release_direct(indio_dev); + return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + return inv_icm45600_gyro_write_odr(indio_dev, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = inv_icm45600_gyro_write_offset(st, chan, val, val2); + iio_device_release_direct(indio_dev); + return ret; + default: + return -EINVAL; + } +} + +static int inv_icm45600_gyro_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + if (chan->type != IIO_ANGL_VEL) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + case IIO_CHAN_INFO_SAMP_FREQ: + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_CALIBBIAS: + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + +static int inv_icm45600_gyro_hwfifo_set_watermark(struct iio_dev *indio_dev, + unsigned int val) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + + guard(mutex)(&st->lock); + + st->fifo.watermark.gyro = val; + return inv_icm45600_buffer_update_watermark(st); +} + +static int inv_icm45600_gyro_hwfifo_flush(struct iio_dev *indio_dev, + unsigned int count) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + int ret; + + if (count == 0) + return 0; + + guard(mutex)(&st->lock); + + ret = inv_icm45600_buffer_hwfifo_flush(st, count); + if (ret) + return ret; + + return st->fifo.nb.gyro; +} + +static const struct iio_info inv_icm45600_gyro_info = { + .read_raw = inv_icm45600_gyro_read_raw, + .read_avail = inv_icm45600_gyro_read_avail, + .write_raw = inv_icm45600_gyro_write_raw, + .write_raw_get_fmt = inv_icm45600_gyro_write_raw_get_fmt, + .debugfs_reg_access = inv_icm45600_debugfs_reg, + .update_scan_mode = inv_icm45600_gyro_update_scan_mode, + .hwfifo_set_watermark = inv_icm45600_gyro_hwfifo_set_watermark, + .hwfifo_flush_to_buffer = inv_icm45600_gyro_hwfifo_flush, +}; + +struct iio_dev *inv_icm45600_gyro_init(struct inv_icm45600_state *st) +{ + struct device *dev = regmap_get_device(st->map); + struct inv_icm45600_sensor_state *gyro_st; + struct inv_sensors_timestamp_chip ts_chip; + struct iio_dev *indio_dev; + const char *name; + int ret; + + name = devm_kasprintf(dev, GFP_KERNEL, "%s-gyro", st->chip_info->name); + if (!name) + return ERR_PTR(-ENOMEM); + + indio_dev = devm_iio_device_alloc(dev, sizeof(*gyro_st)); + if (!indio_dev) + return ERR_PTR(-ENOMEM); + gyro_st = iio_priv(indio_dev); + + gyro_st->scales = st->chip_info->gyro_scales; + gyro_st->scales_len = st->chip_info->gyro_scales_len * 2; + + /* low-noise by default at init */ + gyro_st->power_mode = INV_ICM45600_SENSOR_MODE_LOW_NOISE; + + /* + * clock period is 32kHz (31250ns) + * jitter is +/- 2% (20 per mille) + */ + ts_chip.clock_period = 31250; + ts_chip.jitter = 20; + ts_chip.init_period = inv_icm45600_odr_to_period(st->conf.gyro.odr); + inv_sensors_timestamp_init(&gyro_st->ts, &ts_chip); + + iio_device_set_drvdata(indio_dev, st); + indio_dev->name = name; + indio_dev->info = &inv_icm45600_gyro_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = inv_icm45600_gyro_channels; + indio_dev->num_channels = ARRAY_SIZE(inv_icm45600_gyro_channels); + indio_dev->available_scan_masks = inv_icm45600_gyro_scan_masks; + indio_dev->setup_ops = &inv_icm45600_buffer_ops; + + ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, + &inv_icm45600_buffer_ops); + if (ret) + return ERR_PTR(ret); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return ERR_PTR(ret); + + return indio_dev; +} + +int inv_icm45600_gyro_parse_fifo(struct iio_dev *indio_dev) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *gyro_st = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = &gyro_st->ts; + ssize_t i, size; + unsigned int no; + + /* parse all fifo packets */ + for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) { + struct inv_icm45600_gyro_buffer buffer = { }; + const struct inv_icm45600_fifo_sensor_data *accel, *gyro; + const __le16 *timestamp; + const s8 *temp; + unsigned int odr; + s64 ts_val; + + size = inv_icm45600_fifo_decode_packet(&st->fifo.data[i], + &accel, &gyro, &temp, ×tamp, &odr); + /* quit if error or FIFO is empty */ + if (size <= 0) + return size; + + /* skip packet if no gyro data or data is invalid */ + if (gyro == NULL || !inv_icm45600_fifo_is_data_valid(gyro)) + continue; + + /* update odr */ + if (odr & INV_ICM45600_SENSOR_GYRO) + inv_sensors_timestamp_apply_odr(ts, st->fifo.period, + st->fifo.nb.total, no); + + memcpy(&buffer.gyro, gyro, sizeof(buffer.gyro)); + /* convert 8 bits FIFO temperature in high resolution format */ + buffer.temp = temp ? (*temp * 64) : 0; + ts_val = inv_sensors_timestamp_pop(ts); + iio_push_to_buffers_with_ts(indio_dev, &buffer, sizeof(buffer), ts_val); + } + + return 0; +} From 1fad7b491bb1eb77aad46b873f9d433cfb26b446 Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:06 +0000 Subject: [PATCH 070/304] iio: imu: inv_icm45600: add IMU IIO accelerometer device Add IIO device for accelerometer sensor with data polling interface and FIFO parsing. Attributes: raw, scale, sampling_frequency, calibbias. Temperature is available as a processed channel. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/Makefile | 1 + drivers/iio/imu/inv_icm45600/inv_icm45600.h | 8 + .../iio/imu/inv_icm45600/inv_icm45600_accel.c | 782 ++++++++++++++++++ .../imu/inv_icm45600/inv_icm45600_buffer.c | 20 + .../iio/imu/inv_icm45600/inv_icm45600_core.c | 32 + 5 files changed, 843 insertions(+) create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_accel.c diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile index b5954b4053c2..e34553d2b74d 100644 --- a/drivers/iio/imu/inv_icm45600/Makefile +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_INV_ICM45600) += inv-icm45600.o inv-icm45600-y += inv_icm45600_core.o inv-icm45600-y += inv_icm45600_buffer.o inv-icm45600-y += inv_icm45600_gyro.o +inv-icm45600-y += inv_icm45600_accel.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600.h b/drivers/iio/imu/inv_icm45600/inv_icm45600.h index 674c2b4091ef..c5b5446f6c3b 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600.h +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600.h @@ -113,6 +113,8 @@ struct inv_icm45600_chip_info { u8 whoami; const char *name; const struct inv_icm45600_conf *conf; + const int *accel_scales; + const int accel_scales_len; const int *gyro_scales; const int gyro_scales_len; }; @@ -126,6 +128,8 @@ extern const struct inv_icm45600_chip_info inv_icm45687_chip_info; extern const struct inv_icm45600_chip_info inv_icm45688p_chip_info; extern const struct inv_icm45600_chip_info inv_icm45689_chip_info; +extern const int inv_icm45600_accel_scale[][2]; +extern const int inv_icm45686_accel_scale[][2]; extern const int inv_icm45600_gyro_scale[][2]; extern const int inv_icm45686_gyro_scale[][2]; @@ -374,4 +378,8 @@ struct iio_dev *inv_icm45600_gyro_init(struct inv_icm45600_state *st); int inv_icm45600_gyro_parse_fifo(struct iio_dev *indio_dev); +struct iio_dev *inv_icm45600_accel_init(struct inv_icm45600_state *st); + +int inv_icm45600_accel_parse_fifo(struct iio_dev *indio_dev); + #endif diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_accel.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_accel.c new file mode 100644 index 000000000000..efa22e02657f --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_accel.c @@ -0,0 +1,782 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 Invensense, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "inv_icm45600_buffer.h" +#include "inv_icm45600.h" + +enum inv_icm45600_accel_scan { + INV_ICM45600_ACCEL_SCAN_X, + INV_ICM45600_ACCEL_SCAN_Y, + INV_ICM45600_ACCEL_SCAN_Z, + INV_ICM45600_ACCEL_SCAN_TEMP, + INV_ICM45600_ACCEL_SCAN_TIMESTAMP, +}; + +static const struct iio_chan_spec_ext_info inv_icm45600_accel_ext_infos[] = { + IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, inv_icm45600_get_mount_matrix), + { } +}; + +#define INV_ICM45600_ACCEL_CHAN(_modifier, _index, _ext_info) \ + { \ + .type = IIO_ACCEL, \ + .modified = 1, \ + .channel2 = _modifier, \ + .info_mask_separate = \ + BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_type = \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_all = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ + .ext_info = _ext_info, \ + } + +static const struct iio_chan_spec inv_icm45600_accel_channels[] = { + INV_ICM45600_ACCEL_CHAN(IIO_MOD_X, INV_ICM45600_ACCEL_SCAN_X, + inv_icm45600_accel_ext_infos), + INV_ICM45600_ACCEL_CHAN(IIO_MOD_Y, INV_ICM45600_ACCEL_SCAN_Y, + inv_icm45600_accel_ext_infos), + INV_ICM45600_ACCEL_CHAN(IIO_MOD_Z, INV_ICM45600_ACCEL_SCAN_Z, + inv_icm45600_accel_ext_infos), + INV_ICM45600_TEMP_CHAN(INV_ICM45600_ACCEL_SCAN_TEMP), + IIO_CHAN_SOFT_TIMESTAMP(INV_ICM45600_ACCEL_SCAN_TIMESTAMP), +}; + +/* + * IIO buffer data: size must be a power of 2 and timestamp aligned + * 16 bytes: 6 bytes acceleration, 2 bytes temperature, 8 bytes timestamp + */ +struct inv_icm45600_accel_buffer { + struct inv_icm45600_fifo_sensor_data accel; + s16 temp; + aligned_s64 timestamp; +}; + +static const unsigned long inv_icm45600_accel_scan_masks[] = { + /* 3-axis accel + temperature */ + BIT(INV_ICM45600_ACCEL_SCAN_X) | + BIT(INV_ICM45600_ACCEL_SCAN_Y) | + BIT(INV_ICM45600_ACCEL_SCAN_Z) | + BIT(INV_ICM45600_ACCEL_SCAN_TEMP), + 0 +}; + +/* enable accelerometer sensor and FIFO write */ +static int inv_icm45600_accel_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + unsigned int fifo_en = 0; + unsigned int sleep = 0; + int ret; + + scoped_guard(mutex, &st->lock) { + if (*scan_mask & BIT(INV_ICM45600_ACCEL_SCAN_TEMP)) + fifo_en |= INV_ICM45600_SENSOR_TEMP; + + if (*scan_mask & (BIT(INV_ICM45600_ACCEL_SCAN_X) | + BIT(INV_ICM45600_ACCEL_SCAN_Y) | + BIT(INV_ICM45600_ACCEL_SCAN_Z))) { + /* enable accel sensor */ + conf.mode = accel_st->power_mode; + ret = inv_icm45600_set_accel_conf(st, &conf, &sleep); + if (ret) + return ret; + fifo_en |= INV_ICM45600_SENSOR_ACCEL; + } + + /* Update data FIFO write. */ + ret = inv_icm45600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); + } + + /* Sleep required time. */ + if (sleep) + msleep(sleep); + + return ret; +} + +static int _inv_icm45600_accel_read_sensor(struct inv_icm45600_state *st, + struct inv_icm45600_sensor_state *accel_st, + unsigned int reg, int *val) +{ + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + /* enable accel sensor */ + conf.mode = accel_st->power_mode; + ret = inv_icm45600_set_accel_conf(st, &conf, NULL); + if (ret) + return ret; + + /* read accel register data */ + ret = regmap_bulk_read(st->map, reg, &st->buffer.u16, sizeof(st->buffer.u16)); + if (ret) + return ret; + + *val = sign_extend32(le16_to_cpup(&st->buffer.u16), 15); + if (*val == INV_ICM45600_DATA_INVALID) + return -ENODATA; + + return 0; +} + +static int inv_icm45600_accel_read_sensor(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int reg; + int ret; + + if (chan->type != IIO_ACCEL) + return -EINVAL; + + switch (chan->channel2) { + case IIO_MOD_X: + reg = INV_ICM45600_REG_ACCEL_DATA_X; + break; + case IIO_MOD_Y: + reg = INV_ICM45600_REG_ACCEL_DATA_Y; + break; + case IIO_MOD_Z: + reg = INV_ICM45600_REG_ACCEL_DATA_Z; + break; + default: + return -EINVAL; + } + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = _inv_icm45600_accel_read_sensor(st, accel_st, reg, val); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +/* IIO format int + nano */ +const int inv_icm45600_accel_scale[][2] = { + /* +/- 16G => 0.004788403 m/s-2 */ + [INV_ICM45600_ACCEL_FS_16G] = { 0, 4788403 }, + /* +/- 8G => 0.002394202 m/s-2 */ + [INV_ICM45600_ACCEL_FS_8G] = { 0, 2394202 }, + /* +/- 4G => 0.001197101 m/s-2 */ + [INV_ICM45600_ACCEL_FS_4G] = { 0, 1197101 }, + /* +/- 2G => 0.000598550 m/s-2 */ + [INV_ICM45600_ACCEL_FS_2G] = { 0, 598550 }, +}; + +const int inv_icm45686_accel_scale[][2] = { + /* +/- 32G => 0.009576806 m/s-2 */ + [INV_ICM45686_ACCEL_FS_32G] = { 0, 9576806 }, + /* +/- 16G => 0.004788403 m/s-2 */ + [INV_ICM45686_ACCEL_FS_16G] = { 0, 4788403 }, + /* +/- 8G => 0.002394202 m/s-2 */ + [INV_ICM45686_ACCEL_FS_8G] = { 0, 2394202 }, + /* +/- 4G => 0.001197101 m/s-2 */ + [INV_ICM45686_ACCEL_FS_4G] = { 0, 1197101 }, + /* +/- 2G => 0.000598550 m/s-2 */ + [INV_ICM45686_ACCEL_FS_2G] = { 0, 598550 }, +}; + +static int inv_icm45600_accel_read_scale(struct iio_dev *indio_dev, + int *val, int *val2) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + unsigned int idx; + + idx = st->conf.accel.fs; + + /* Full scale register starts at 1 for not High FSR parts */ + if (accel_st->scales == (const int *)&inv_icm45600_accel_scale) + idx--; + + *val = accel_st->scales[2 * idx]; + *val2 = accel_st->scales[2 * idx + 1]; + return IIO_VAL_INT_PLUS_NANO; +} + +static int inv_icm45600_accel_write_scale(struct iio_dev *indio_dev, + int val, int val2) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int idx; + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + for (idx = 0; idx < accel_st->scales_len; idx += 2) { + if (val == accel_st->scales[idx] && + val2 == accel_st->scales[idx + 1]) + break; + } + if (idx == accel_st->scales_len) + return -EINVAL; + + conf.fs = idx / 2; + + /* Full scale register starts at 1 for not High FSR parts */ + if (accel_st->scales == (const int *)&inv_icm45600_accel_scale) + conf.fs++; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = inv_icm45600_set_accel_conf(st, &conf, NULL); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +/* IIO format int + micro */ +static const int inv_icm45600_accel_odr[] = { + 1, 562500, /* 1.5625Hz */ + 3, 125000, /* 3.125Hz */ + 6, 250000, /* 6.25Hz */ + 12, 500000, /* 12.5Hz */ + 25, 0, /* 25Hz */ + 50, 0, /* 50Hz */ + 100, 0, /* 100Hz */ + 200, 0, /* 200Hz */ + 400, 0, /* 400Hz */ + 800, 0, /* 800Hz */ + 1600, 0, /* 1.6kHz */ + 3200, 0, /* 3.2kHz */ + 6400, 0, /* 6.4kHz */ +}; + +static const int inv_icm45600_accel_odr_conv[] = { + INV_ICM45600_ODR_1_5625HZ_LP, + INV_ICM45600_ODR_3_125HZ_LP, + INV_ICM45600_ODR_6_25HZ_LP, + INV_ICM45600_ODR_12_5HZ, + INV_ICM45600_ODR_25HZ, + INV_ICM45600_ODR_50HZ, + INV_ICM45600_ODR_100HZ, + INV_ICM45600_ODR_200HZ, + INV_ICM45600_ODR_400HZ, + INV_ICM45600_ODR_800HZ_LN, + INV_ICM45600_ODR_1600HZ_LN, + INV_ICM45600_ODR_3200HZ_LN, + INV_ICM45600_ODR_6400HZ_LN, +}; + +static int inv_icm45600_accel_read_odr(struct inv_icm45600_state *st, + int *val, int *val2) +{ + unsigned int odr; + unsigned int i; + + odr = st->conf.accel.odr; + + for (i = 0; i < ARRAY_SIZE(inv_icm45600_accel_odr_conv); ++i) { + if (inv_icm45600_accel_odr_conv[i] == odr) + break; + } + if (i >= ARRAY_SIZE(inv_icm45600_accel_odr_conv)) + return -EINVAL; + + *val = inv_icm45600_accel_odr[2 * i]; + *val2 = inv_icm45600_accel_odr[2 * i + 1]; + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int _inv_icm45600_accel_write_odr(struct iio_dev *indio_dev, int odr) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = &accel_st->ts; + struct inv_icm45600_sensor_conf conf = INV_ICM45600_SENSOR_CONF_KEEP_VALUES; + int ret; + + conf.odr = odr; + ret = inv_sensors_timestamp_update_odr(ts, inv_icm45600_odr_to_period(conf.odr), + iio_buffer_enabled(indio_dev)); + if (ret) + return ret; + + if (st->conf.accel.mode != INV_ICM45600_SENSOR_MODE_OFF) + conf.mode = accel_st->power_mode; + + ret = inv_icm45600_set_accel_conf(st, &conf, NULL); + if (ret) + return ret; + + inv_icm45600_buffer_update_fifo_period(st); + inv_icm45600_buffer_update_watermark(st); + + return 0; +} + +static int inv_icm45600_accel_write_odr(struct iio_dev *indio_dev, + int val, int val2) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct device *dev = regmap_get_device(st->map); + unsigned int idx; + int odr; + int ret; + + for (idx = 0; idx < ARRAY_SIZE(inv_icm45600_accel_odr); idx += 2) { + if (val == inv_icm45600_accel_odr[idx] && + val2 == inv_icm45600_accel_odr[idx + 1]) + break; + } + if (idx >= ARRAY_SIZE(inv_icm45600_accel_odr)) + return -EINVAL; + + odr = inv_icm45600_accel_odr_conv[idx / 2]; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = _inv_icm45600_accel_write_odr(indio_dev, odr); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +/* + * Calibration bias values, IIO range format int + micro. + * Value is limited to +/-1g coded on 14 bits signed. Step is 0.125mg. + */ +static int inv_icm45600_accel_calibbias[] = { + -9, 806650, /* min: -9.806650 m/s² */ + 0, 1197, /* step: 0.001197 m/s² */ + 9, 805453, /* max: 9.805453 m/s² */ +}; + +static int inv_icm45600_accel_read_offset(struct inv_icm45600_state *st, + struct iio_chan_spec const *chan, + int *val, int *val2) +{ + struct device *dev = regmap_get_device(st->map); + s64 val64; + s32 bias; + unsigned int reg; + s16 offset; + int ret; + + if (chan->type != IIO_ACCEL) + return -EINVAL; + + switch (chan->channel2) { + case IIO_MOD_X: + reg = INV_ICM45600_IPREG_SYS2_REG_24; + break; + case IIO_MOD_Y: + reg = INV_ICM45600_IPREG_SYS2_REG_32; + break; + case IIO_MOD_Z: + reg = INV_ICM45600_IPREG_SYS2_REG_40; + break; + default: + return -EINVAL; + } + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = regmap_bulk_read(st->map, reg, &st->buffer.u16, sizeof(st->buffer.u16)); + + pm_runtime_put_autosuspend(dev); + if (ret) + return ret; + + offset = le16_to_cpup(&st->buffer.u16) & INV_ICM45600_ACCEL_OFFUSER_MASK; + /* 14 bits signed value */ + offset = sign_extend32(offset, 13); + + /* + * convert raw offset to g then to m/s² + * 14 bits signed raw step 1/8192g + * g to m/s²: 9.806650 + * result in micro (* 1000000) + * (offset * 9806650) / 8192 + */ + val64 = (s64)offset * 9806650LL; + /* for rounding, add + or - divisor (8192) divided by 2 */ + if (val64 >= 0) + val64 += 8192LL / 2LL; + else + val64 -= 8192LL / 2LL; + bias = div_s64(val64, 8192L); + *val = bias / 1000000L; + *val2 = bias % 1000000L; + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int inv_icm45600_accel_write_offset(struct inv_icm45600_state *st, + struct iio_chan_spec const *chan, + int val, int val2) +{ + struct device *dev = regmap_get_device(st->map); + s64 val64; + s32 min, max; + unsigned int reg; + s16 offset; + int ret; + + if (chan->type != IIO_ACCEL) + return -EINVAL; + + switch (chan->channel2) { + case IIO_MOD_X: + reg = INV_ICM45600_IPREG_SYS2_REG_24; + break; + case IIO_MOD_Y: + reg = INV_ICM45600_IPREG_SYS2_REG_32; + break; + case IIO_MOD_Z: + reg = INV_ICM45600_IPREG_SYS2_REG_40; + break; + default: + return -EINVAL; + } + + /* inv_icm45600_accel_calibbias: min - step - max in micro */ + min = inv_icm45600_accel_calibbias[0] * 1000000L - + inv_icm45600_accel_calibbias[1]; + max = inv_icm45600_accel_calibbias[4] * 1000000L + + inv_icm45600_accel_calibbias[5]; + val64 = (s64)val * 1000000LL; + if (val >= 0) + val64 += (s64)val2; + else + val64 -= (s64)val2; + if (val64 < min || val64 > max) + return -EINVAL; + + /* + * convert m/s² to g then to raw value + * m/s² to g: 1 / 9.806650 + * g to raw 14 bits signed, step 1/8192g: * 8192 + * val in micro (1000000) + * val * 8192 / (9.806650 * 1000000) + */ + val64 = val64 * 8192LL; + /* for rounding, add + or - divisor (9806650) divided by 2 */ + if (val64 >= 0) + val64 += 9806650 / 2; + else + val64 -= 9806650 / 2; + offset = div_s64(val64, 9806650); + + /* clamp value limited to 14 bits signed */ + offset = clamp(offset, -8192, 8191); + + st->buffer.u16 = cpu_to_le16(offset & INV_ICM45600_ACCEL_OFFUSER_MASK); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + scoped_guard(mutex, &st->lock) + ret = regmap_bulk_write(st->map, reg, &st->buffer.u16, sizeof(st->buffer.u16)); + + pm_runtime_put_autosuspend(dev); + return ret; +} + +static int inv_icm45600_accel_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + int ret; + + switch (chan->type) { + case IIO_ACCEL: + break; + case IIO_TEMP: + return inv_icm45600_temp_read_raw(indio_dev, chan, val, val2, mask); + default: + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = inv_icm45600_accel_read_sensor(indio_dev, chan, val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + return inv_icm45600_accel_read_scale(indio_dev, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + return inv_icm45600_accel_read_odr(st, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return inv_icm45600_accel_read_offset(st, chan, val, val2); + default: + return -EINVAL; + } +} + +static int inv_icm45600_accel_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, + int *type, int *length, long mask) +{ + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + + if (chan->type != IIO_ACCEL) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = accel_st->scales; + *type = IIO_VAL_INT_PLUS_NANO; + *length = accel_st->scales_len; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SAMP_FREQ: + *vals = inv_icm45600_accel_odr; + *type = IIO_VAL_INT_PLUS_MICRO; + *length = ARRAY_SIZE(inv_icm45600_accel_odr); + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CALIBBIAS: + *vals = inv_icm45600_accel_calibbias; + *type = IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_RANGE; + default: + return -EINVAL; + } +} + +static int inv_icm45600_accel_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + int ret; + + if (chan->type != IIO_ACCEL) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = inv_icm45600_accel_write_scale(indio_dev, val, val2); + iio_device_release_direct(indio_dev); + return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + return inv_icm45600_accel_write_odr(indio_dev, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = inv_icm45600_accel_write_offset(st, chan, val, val2); + iio_device_release_direct(indio_dev); + return ret; + default: + return -EINVAL; + } +} + +static int inv_icm45600_accel_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + if (chan->type != IIO_ACCEL) + return -EINVAL; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + case IIO_CHAN_INFO_SAMP_FREQ: + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_CALIBBIAS: + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int inv_icm45600_accel_hwfifo_set_watermark(struct iio_dev *indio_dev, + unsigned int val) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + + guard(mutex)(&st->lock); + + st->fifo.watermark.accel = val; + return inv_icm45600_buffer_update_watermark(st); +} + +static int inv_icm45600_accel_hwfifo_flush(struct iio_dev *indio_dev, + unsigned int count) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + int ret; + + if (count == 0) + return 0; + + guard(mutex)(&st->lock); + + ret = inv_icm45600_buffer_hwfifo_flush(st, count); + if (ret) + return ret; + + return st->fifo.nb.accel; +} + +static const struct iio_info inv_icm45600_accel_info = { + .read_raw = inv_icm45600_accel_read_raw, + .read_avail = inv_icm45600_accel_read_avail, + .write_raw = inv_icm45600_accel_write_raw, + .write_raw_get_fmt = inv_icm45600_accel_write_raw_get_fmt, + .debugfs_reg_access = inv_icm45600_debugfs_reg, + .update_scan_mode = inv_icm45600_accel_update_scan_mode, + .hwfifo_set_watermark = inv_icm45600_accel_hwfifo_set_watermark, + .hwfifo_flush_to_buffer = inv_icm45600_accel_hwfifo_flush, +}; + +struct iio_dev *inv_icm45600_accel_init(struct inv_icm45600_state *st) +{ + struct device *dev = regmap_get_device(st->map); + struct inv_icm45600_sensor_state *accel_st; + struct inv_sensors_timestamp_chip ts_chip; + struct iio_dev *indio_dev; + const char *name; + int ret; + + name = devm_kasprintf(dev, GFP_KERNEL, "%s-accel", st->chip_info->name); + if (!name) + return ERR_PTR(-ENOMEM); + + indio_dev = devm_iio_device_alloc(dev, sizeof(*accel_st)); + if (!indio_dev) + return ERR_PTR(-ENOMEM); + accel_st = iio_priv(indio_dev); + + accel_st->scales = st->chip_info->accel_scales; + accel_st->scales_len = st->chip_info->accel_scales_len * 2; + + /* low-power (LP) mode by default at init, no ULP mode */ + accel_st->power_mode = INV_ICM45600_SENSOR_MODE_LOW_POWER; + ret = regmap_set_bits(st->map, INV_ICM45600_REG_SMC_CONTROL_0, + INV_ICM45600_SMC_CONTROL_0_ACCEL_LP_CLK_SEL); + if (ret) + return ERR_PTR(ret); + + /* + * clock period is 32kHz (31250ns) + * jitter is +/- 2% (20 per mille) + */ + ts_chip.clock_period = 31250; + ts_chip.jitter = 20; + ts_chip.init_period = inv_icm45600_odr_to_period(st->conf.accel.odr); + inv_sensors_timestamp_init(&accel_st->ts, &ts_chip); + + iio_device_set_drvdata(indio_dev, st); + indio_dev->name = name; + indio_dev->info = &inv_icm45600_accel_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = inv_icm45600_accel_channels; + indio_dev->num_channels = ARRAY_SIZE(inv_icm45600_accel_channels); + indio_dev->available_scan_masks = inv_icm45600_accel_scan_masks; + + ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, + &inv_icm45600_buffer_ops); + if (ret) + return ERR_PTR(ret); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return ERR_PTR(ret); + + return indio_dev; +} + +int inv_icm45600_accel_parse_fifo(struct iio_dev *indio_dev) +{ + struct inv_icm45600_state *st = iio_device_get_drvdata(indio_dev); + struct inv_icm45600_sensor_state *accel_st = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = &accel_st->ts; + ssize_t i, size; + unsigned int no; + + /* parse all fifo packets */ + for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) { + struct inv_icm45600_accel_buffer buffer = { }; + const struct inv_icm45600_fifo_sensor_data *accel, *gyro; + const __le16 *timestamp; + const s8 *temp; + unsigned int odr; + s64 ts_val; + + size = inv_icm45600_fifo_decode_packet(&st->fifo.data[i], + &accel, &gyro, &temp, ×tamp, &odr); + /* quit if error or FIFO is empty */ + if (size <= 0) + return size; + + /* skip packet if no accel data or data is invalid */ + if (accel == NULL || !inv_icm45600_fifo_is_data_valid(accel)) + continue; + + /* update odr */ + if (odr & INV_ICM45600_SENSOR_ACCEL) + inv_sensors_timestamp_apply_odr(ts, st->fifo.period, + st->fifo.nb.total, no); + + memcpy(&buffer.accel, accel, sizeof(buffer.accel)); + /* convert 8 bits FIFO temperature in high resolution format */ + buffer.temp = temp ? (*temp * 64) : 0; + ts_val = inv_sensors_timestamp_pop(ts); + iio_push_to_buffers_with_ts(indio_dev, &buffer, sizeof(buffer), ts_val); + } + + return 0; +} diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c index 2800995bfa32..2efcc177f9d6 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c @@ -454,6 +454,7 @@ int inv_icm45600_buffer_fifo_read(struct inv_icm45600_state *st, int inv_icm45600_buffer_fifo_parse(struct inv_icm45600_state *st) { struct inv_icm45600_sensor_state *gyro_st = iio_priv(st->indio_gyro); + struct inv_icm45600_sensor_state *accel_st = iio_priv(st->indio_accel); struct inv_sensors_timestamp *ts; int ret; @@ -470,6 +471,16 @@ int inv_icm45600_buffer_fifo_parse(struct inv_icm45600_state *st) return ret; } + /* Handle accelerometer timestamp and FIFO data parsing. */ + if (st->fifo.nb.accel > 0) { + ts = &accel_st->ts; + inv_sensors_timestamp_interrupt(ts, st->fifo.watermark.eff_accel, + st->timestamp.accel); + ret = inv_icm45600_accel_parse_fifo(st->indio_accel); + if (ret) + return ret; + } + return 0; } @@ -477,6 +488,7 @@ int inv_icm45600_buffer_hwfifo_flush(struct inv_icm45600_state *st, unsigned int count) { struct inv_icm45600_sensor_state *gyro_st = iio_priv(st->indio_gyro); + struct inv_icm45600_sensor_state *accel_st = iio_priv(st->indio_accel); struct inv_sensors_timestamp *ts; s64 gyro_ts, accel_ts; int ret; @@ -499,6 +511,14 @@ int inv_icm45600_buffer_hwfifo_flush(struct inv_icm45600_state *st, return ret; } + if (st->fifo.nb.accel > 0) { + ts = &accel_st->ts; + inv_sensors_timestamp_interrupt(ts, st->fifo.nb.accel, accel_ts); + ret = inv_icm45600_accel_parse_fifo(st->indio_accel); + if (ret) + return ret; + } + return 0; } diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c index 0484e675069f..ab1cb7b9dba4 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_core.c @@ -144,6 +144,12 @@ static const struct inv_icm45600_conf inv_icm45600_default_conf = { .odr = INV_ICM45600_ODR_800HZ_LN, .filter = INV_ICM45600_GYRO_LP_AVG_SEL_8X, }, + .accel = { + .mode = INV_ICM45600_SENSOR_MODE_OFF, + .fs = INV_ICM45686_ACCEL_FS_16G, + .odr = INV_ICM45600_ODR_800HZ_LN, + .filter = INV_ICM45600_ACCEL_LP_AVG_SEL_4X, + }, }; static const struct inv_icm45600_conf inv_icm45686_default_conf = { @@ -153,12 +159,20 @@ static const struct inv_icm45600_conf inv_icm45686_default_conf = { .odr = INV_ICM45600_ODR_800HZ_LN, .filter = INV_ICM45600_GYRO_LP_AVG_SEL_8X, }, + .accel = { + .mode = INV_ICM45600_SENSOR_MODE_OFF, + .fs = INV_ICM45686_ACCEL_FS_32G, + .odr = INV_ICM45600_ODR_800HZ_LN, + .filter = INV_ICM45600_ACCEL_LP_AVG_SEL_4X, + }, }; const struct inv_icm45600_chip_info inv_icm45605_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45605, .name = "icm45605", .conf = &inv_icm45600_default_conf, + .accel_scales = (const int *)inv_icm45600_accel_scale, + .accel_scales_len = INV_ICM45600_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45600_gyro_scale, .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, }; @@ -168,6 +182,8 @@ const struct inv_icm45600_chip_info inv_icm45606_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45606, .name = "icm45606", .conf = &inv_icm45600_default_conf, + .accel_scales = (const int *)inv_icm45600_accel_scale, + .accel_scales_len = INV_ICM45600_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45600_gyro_scale, .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, }; @@ -177,6 +193,8 @@ const struct inv_icm45600_chip_info inv_icm45608_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45608, .name = "icm45608", .conf = &inv_icm45600_default_conf, + .accel_scales = (const int *)inv_icm45600_accel_scale, + .accel_scales_len = INV_ICM45600_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45600_gyro_scale, .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, }; @@ -186,6 +204,8 @@ const struct inv_icm45600_chip_info inv_icm45634_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45634, .name = "icm45634", .conf = &inv_icm45600_default_conf, + .accel_scales = (const int *)inv_icm45600_accel_scale, + .accel_scales_len = INV_ICM45600_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45600_gyro_scale, .gyro_scales_len = INV_ICM45600_GYRO_FS_MAX, }; @@ -195,6 +215,8 @@ const struct inv_icm45600_chip_info inv_icm45686_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45686, .name = "icm45686", .conf = &inv_icm45686_default_conf, + .accel_scales = (const int *)inv_icm45686_accel_scale, + .accel_scales_len = INV_ICM45686_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45686_gyro_scale, .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, }; @@ -204,6 +226,8 @@ const struct inv_icm45600_chip_info inv_icm45687_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45687, .name = "icm45687", .conf = &inv_icm45686_default_conf, + .accel_scales = (const int *)inv_icm45686_accel_scale, + .accel_scales_len = INV_ICM45686_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45686_gyro_scale, .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, }; @@ -213,6 +237,8 @@ const struct inv_icm45600_chip_info inv_icm45688p_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45688P, .name = "icm45688p", .conf = &inv_icm45686_default_conf, + .accel_scales = (const int *)inv_icm45686_accel_scale, + .accel_scales_len = INV_ICM45686_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45686_gyro_scale, .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, }; @@ -222,6 +248,8 @@ const struct inv_icm45600_chip_info inv_icm45689_chip_info = { .whoami = INV_ICM45600_WHOAMI_ICM45689, .name = "icm45689", .conf = &inv_icm45686_default_conf, + .accel_scales = (const int *)inv_icm45686_accel_scale, + .accel_scales_len = INV_ICM45686_ACCEL_FS_MAX, .gyro_scales = (const int *)inv_icm45686_gyro_scale, .gyro_scales_len = INV_ICM45686_GYRO_FS_MAX, }; @@ -740,6 +768,10 @@ int inv_icm45600_core_probe(struct regmap *regmap, const struct inv_icm45600_chi if (IS_ERR(st->indio_gyro)) return PTR_ERR(st->indio_gyro); + st->indio_accel = inv_icm45600_accel_init(st); + if (IS_ERR(st->indio_accel)) + return PTR_ERR(st->indio_accel); + ret = inv_icm45600_irq_init(st, irq, irq_type, open_drain); if (ret) return ret; From d4684c4363f947d7b10ba8bcbf2c2941a616656d Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:07 +0000 Subject: [PATCH 071/304] iio: imu: inv_icm45600: add I2C driver for inv_icm45600 driver Add I2C driver for InvenSense ICM-456000 devices. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/Kconfig | 21 ++++ drivers/iio/imu/inv_icm45600/Makefile | 3 + .../iio/imu/inv_icm45600/inv_icm45600_i2c.c | 98 +++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_i2c.c diff --git a/drivers/iio/imu/inv_icm45600/Kconfig b/drivers/iio/imu/inv_icm45600/Kconfig index ea0a8d20cba2..5b044a954e95 100644 --- a/drivers/iio/imu/inv_icm45600/Kconfig +++ b/drivers/iio/imu/inv_icm45600/Kconfig @@ -5,3 +5,24 @@ config INV_ICM45600 select IIO_BUFFER select IIO_KFIFO_BUF select IIO_INV_SENSORS_TIMESTAMP + +config INV_ICM45600_I2C + tristate "InvenSense ICM-456xx I2C driver" + depends on I2C + select INV_ICM45600 + select REGMAP_I2C + help + This driver supports the InvenSense ICM-456xx motion tracking + devices over I2C. + Supported devices: + - ICM-45605 + - ICM-45606 + - ICM-45608 + - ICM-45634 + - ICM-45686 + - ICM-45687 + - ICM-45688-P + - ICM-45689 + + This driver can be built as a module. The module will be called + inv-icm45600-i2c. diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile index e34553d2b74d..c43e5d6ad3a2 100644 --- a/drivers/iio/imu/inv_icm45600/Makefile +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -5,3 +5,6 @@ inv-icm45600-y += inv_icm45600_core.o inv-icm45600-y += inv_icm45600_buffer.o inv-icm45600-y += inv_icm45600_gyro.o inv-icm45600-y += inv_icm45600_accel.o + +obj-$(CONFIG_INV_ICM45600_I2C) += inv-icm45600-i2c.o +inv-icm45600-i2c-y += inv_icm45600_i2c.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_i2c.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_i2c.c new file mode 100644 index 000000000000..5ebc18121a11 --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_i2c.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2025 InvenSense, Inc. */ + +#include +#include +#include +#include +#include +#include + +#include "inv_icm45600.h" + +static const struct regmap_config inv_icm45600_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int inv_icm45600_probe(struct i2c_client *client) +{ + const struct inv_icm45600_chip_info *chip_info; + struct regmap *regmap; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) + return -ENODEV; + + chip_info = device_get_match_data(&client->dev); + if (!chip_info) + return -ENODEV; + + regmap = devm_regmap_init_i2c(client, &inv_icm45600_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return inv_icm45600_core_probe(regmap, chip_info, true, NULL); +} + +/* + * The device id table is used to identify which device is + * supported by this driver. + */ +static const struct i2c_device_id inv_icm45600_id[] = { + { "icm45605", (kernel_ulong_t)&inv_icm45605_chip_info }, + { "icm45606", (kernel_ulong_t)&inv_icm45606_chip_info }, + { "icm45608", (kernel_ulong_t)&inv_icm45608_chip_info }, + { "icm45634", (kernel_ulong_t)&inv_icm45634_chip_info }, + { "icm45686", (kernel_ulong_t)&inv_icm45686_chip_info }, + { "icm45687", (kernel_ulong_t)&inv_icm45687_chip_info }, + { "icm45688p", (kernel_ulong_t)&inv_icm45688p_chip_info }, + { "icm45689", (kernel_ulong_t)&inv_icm45689_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(i2c, inv_icm45600_id); + +static const struct of_device_id inv_icm45600_of_matches[] = { + { + .compatible = "invensense,icm45605", + .data = &inv_icm45605_chip_info, + }, { + .compatible = "invensense,icm45606", + .data = &inv_icm45606_chip_info, + }, { + .compatible = "invensense,icm45608", + .data = &inv_icm45608_chip_info, + }, { + .compatible = "invensense,icm45634", + .data = &inv_icm45634_chip_info, + }, { + .compatible = "invensense,icm45686", + .data = &inv_icm45686_chip_info, + }, { + .compatible = "invensense,icm45687", + .data = &inv_icm45687_chip_info, + }, { + .compatible = "invensense,icm45688p", + .data = &inv_icm45688p_chip_info, + }, { + .compatible = "invensense,icm45689", + .data = &inv_icm45689_chip_info, + }, + { } +}; +MODULE_DEVICE_TABLE(of, inv_icm45600_of_matches); + +static struct i2c_driver inv_icm45600_driver = { + .driver = { + .name = "inv-icm45600-i2c", + .of_match_table = inv_icm45600_of_matches, + .pm = pm_ptr(&inv_icm45600_pm_ops), + }, + .id_table = inv_icm45600_id, + .probe = inv_icm45600_probe, +}; +module_i2c_driver(inv_icm45600_driver); + +MODULE_AUTHOR("InvenSense, Inc."); +MODULE_DESCRIPTION("InvenSense ICM-456xx I2C driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_ICM45600"); From b27492d50d2c75ca48c893fd65e49f855300f0ac Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:08 +0000 Subject: [PATCH 072/304] iio: imu: inv_icm45600: add SPI driver for inv_icm45600 driver Add SPI driver for InvenSense ICM-456000 devices. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/Kconfig | 21 ++++ drivers/iio/imu/inv_icm45600/Makefile | 3 + .../iio/imu/inv_icm45600/inv_icm45600_spi.c | 108 ++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_spi.c diff --git a/drivers/iio/imu/inv_icm45600/Kconfig b/drivers/iio/imu/inv_icm45600/Kconfig index 5b044a954e95..01399d136a7e 100644 --- a/drivers/iio/imu/inv_icm45600/Kconfig +++ b/drivers/iio/imu/inv_icm45600/Kconfig @@ -26,3 +26,24 @@ config INV_ICM45600_I2C This driver can be built as a module. The module will be called inv-icm45600-i2c. + +config INV_ICM45600_SPI + tristate "InvenSense ICM-456xx SPI driver" + depends on SPI_MASTER + select INV_ICM45600 + select REGMAP_SPI + help + This driver supports the InvenSense ICM-456xx motion tracking + devices over SPI. + Supported devices: + - ICM-45605 + - ICM-45606 + - ICM-45608 + - ICM-45634 + - ICM-45686 + - ICM-45687 + - ICM-45688-P + - ICM-45689 + + This driver can be built as a module. The module will be called + inv-icm45600-spi. diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile index c43e5d6ad3a2..3692636d393a 100644 --- a/drivers/iio/imu/inv_icm45600/Makefile +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -8,3 +8,6 @@ inv-icm45600-y += inv_icm45600_accel.o obj-$(CONFIG_INV_ICM45600_I2C) += inv-icm45600-i2c.o inv-icm45600-i2c-y += inv_icm45600_i2c.o + +obj-$(CONFIG_INV_ICM45600_SPI) += inv-icm45600-spi.o +inv-icm45600-spi-y += inv_icm45600_spi.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_spi.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_spi.c new file mode 100644 index 000000000000..6288113a6d7c --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_spi.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2025 InvenSense, Inc. */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "inv_icm45600.h" + +static const struct regmap_config inv_icm45600_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int inv_icm45600_spi_bus_setup(struct inv_icm45600_state *st) +{ + /* Set slew rates for SPI. */ + return regmap_update_bits(st->map, INV_ICM45600_REG_DRIVE_CONFIG0, + INV_ICM45600_DRIVE_CONFIG0_SPI_MASK, + FIELD_PREP(INV_ICM45600_DRIVE_CONFIG0_SPI_MASK, + INV_ICM45600_SPI_SLEW_RATE_5NS)); +} + +static int inv_icm45600_probe(struct spi_device *spi) +{ + const struct inv_icm45600_chip_info *chip_info; + struct regmap *regmap; + + chip_info = spi_get_device_match_data(spi); + if (!chip_info) + return -ENODEV; + + /* Use SPI specific regmap. */ + regmap = devm_regmap_init_spi(spi, &inv_icm45600_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return inv_icm45600_core_probe(regmap, chip_info, true, + inv_icm45600_spi_bus_setup); +} + +/* + * The device id table is used to identify which device is + * supported by this driver. + */ +static const struct spi_device_id inv_icm45600_id[] = { + { "icm45605", (kernel_ulong_t)&inv_icm45605_chip_info }, + { "icm45606", (kernel_ulong_t)&inv_icm45606_chip_info }, + { "icm45608", (kernel_ulong_t)&inv_icm45608_chip_info }, + { "icm45634", (kernel_ulong_t)&inv_icm45634_chip_info }, + { "icm45686", (kernel_ulong_t)&inv_icm45686_chip_info }, + { "icm45687", (kernel_ulong_t)&inv_icm45687_chip_info }, + { "icm45688p", (kernel_ulong_t)&inv_icm45688p_chip_info }, + { "icm45689", (kernel_ulong_t)&inv_icm45689_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, inv_icm45600_id); + +static const struct of_device_id inv_icm45600_of_matches[] = { + { + .compatible = "invensense,icm45605", + .data = &inv_icm45605_chip_info, + }, { + .compatible = "invensense,icm45606", + .data = &inv_icm45606_chip_info, + }, { + .compatible = "invensense,icm45608", + .data = &inv_icm45608_chip_info, + }, { + .compatible = "invensense,icm45634", + .data = &inv_icm45634_chip_info, + }, { + .compatible = "invensense,icm45686", + .data = &inv_icm45686_chip_info, + }, { + .compatible = "invensense,icm45687", + .data = &inv_icm45687_chip_info, + }, { + .compatible = "invensense,icm45688p", + .data = &inv_icm45688p_chip_info, + }, { + .compatible = "invensense,icm45689", + .data = &inv_icm45689_chip_info, + }, + { } +}; +MODULE_DEVICE_TABLE(of, inv_icm45600_of_matches); + +static struct spi_driver inv_icm45600_driver = { + .driver = { + .name = "inv-icm45600-spi", + .of_match_table = inv_icm45600_of_matches, + .pm = pm_ptr(&inv_icm45600_pm_ops), + }, + .id_table = inv_icm45600_id, + .probe = inv_icm45600_probe, +}; +module_spi_driver(inv_icm45600_driver); + +MODULE_AUTHOR("InvenSense, Inc."); +MODULE_DESCRIPTION("InvenSense ICM-456xx SPI driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_ICM45600"); From 1bef24e9007e4bc5fcaf99df1c256969ba58d5e6 Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:09 +0000 Subject: [PATCH 073/304] iio: imu: inv_icm45600: add I3C driver for inv_icm45600 driver Add I3C driver for InvenSense ICM-45600 devices. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/Kconfig | 21 +++++ drivers/iio/imu/inv_icm45600/Makefile | 3 + .../iio/imu/inv_icm45600/inv_icm45600_i3c.c | 78 +++++++++++++++++++ 3 files changed, 102 insertions(+) create mode 100644 drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c diff --git a/drivers/iio/imu/inv_icm45600/Kconfig b/drivers/iio/imu/inv_icm45600/Kconfig index 01399d136a7e..dc133402f6d7 100644 --- a/drivers/iio/imu/inv_icm45600/Kconfig +++ b/drivers/iio/imu/inv_icm45600/Kconfig @@ -47,3 +47,24 @@ config INV_ICM45600_SPI This driver can be built as a module. The module will be called inv-icm45600-spi. + +config INV_ICM45600_I3C + tristate "InvenSense ICM-456xx I3C driver" + depends on I3C + select INV_ICM45600 + select REGMAP_I3C + help + This driver supports the InvenSense ICM-456xx motion tracking + devices over I3C. + Supported devices: + - ICM-45605 + - ICM-45606 + - ICM-45608 + - ICM-45634 + - ICM-45686 + - ICM-45687 + - ICM-45688-P + - ICM-45689 + + This driver can be built as a module. The module will be called + inv-icm45600-i3c. diff --git a/drivers/iio/imu/inv_icm45600/Makefile b/drivers/iio/imu/inv_icm45600/Makefile index 3692636d393a..c98b8365b467 100644 --- a/drivers/iio/imu/inv_icm45600/Makefile +++ b/drivers/iio/imu/inv_icm45600/Makefile @@ -11,3 +11,6 @@ inv-icm45600-i2c-y += inv_icm45600_i2c.o obj-$(CONFIG_INV_ICM45600_SPI) += inv-icm45600-spi.o inv-icm45600-spi-y += inv_icm45600_spi.o + +obj-$(CONFIG_INV_ICM45600_I3C) += inv-icm45600-i3c.o +inv-icm45600-i3c-y += inv_icm45600_i3c.o diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c new file mode 100644 index 000000000000..b5df06b97d44 --- /dev/null +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2025 InvenSense, Inc. */ + +#include +#include +#include +#include + +#include +#include + +#include "inv_icm45600.h" + +static const struct regmap_config inv_icm45600_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static const struct i3c_device_id inv_icm45600_i3c_ids[] = { + I3C_DEVICE_EXTRA_INFO(0x0235, 0x0000, 0x0011, (void *)NULL), + I3C_DEVICE_EXTRA_INFO(0x0235, 0x0000, 0x0084, (void *)NULL), + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i3c, inv_icm45600_i3c_ids); + +static const struct inv_icm45600_chip_info *i3c_chip_info[] = { + &inv_icm45605_chip_info, + &inv_icm45606_chip_info, + &inv_icm45608_chip_info, + &inv_icm45634_chip_info, + &inv_icm45686_chip_info, + &inv_icm45687_chip_info, + &inv_icm45688p_chip_info, + &inv_icm45689_chip_info, +}; + +static int inv_icm45600_i3c_probe(struct i3c_device *i3cdev) +{ + int ret; + unsigned int whoami; + struct regmap *regmap; + const int nb_chip = ARRAY_SIZE(i3c_chip_info); + int chip; + + regmap = devm_regmap_init_i3c(i3cdev, &inv_icm45600_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(&i3cdev->dev, PTR_ERR(regmap), + "Failed to register i3c regmap %ld\n", PTR_ERR(regmap)); + + ret = regmap_read(regmap, INV_ICM45600_REG_WHOAMI, &whoami); + if (ret) + return dev_err_probe(&i3cdev->dev, ret, "Failed to read part id %d\n", whoami); + + for (chip = 0; chip < nb_chip; chip++) { + if (whoami == i3c_chip_info[chip]->whoami) + break; + } + + if (chip == nb_chip) + dev_err_probe(&i3cdev->dev, -ENODEV, "Failed to match part id %d\n", whoami); + + return inv_icm45600_core_probe(regmap, i3c_chip_info[chip], false, NULL); +} + +static struct i3c_driver inv_icm45600_driver = { + .driver = { + .name = "inv_icm45600_i3c", + .pm = pm_sleep_ptr(&inv_icm45600_pm_ops), + }, + .probe = inv_icm45600_i3c_probe, + .id_table = inv_icm45600_i3c_ids, +}; +module_i3c_driver(inv_icm45600_driver); + +MODULE_AUTHOR("Remi Buisson "); +MODULE_DESCRIPTION("InvenSense ICM-456xx i3c driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_ICM45600"); From b73e812a82508b8ba81b7ac9f64a75ddd0be74c7 Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Tue, 7 Oct 2025 07:20:10 +0000 Subject: [PATCH 074/304] MAINTAINERS: add entry for inv_icm45600 6-axis imu sensor Add MAINTAINERS entry for InvenSense ICM-45600 IMU device. Signed-off-by: Remi Buisson Signed-off-by: Jonathan Cameron --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 371ac55d0edc..8082081ea742 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13040,6 +13040,14 @@ F: Documentation/ABI/testing/sysfs-bus-iio-inv_icm42600 F: Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml F: drivers/iio/imu/inv_icm42600/ +INVENSENSE ICM-456xx IMU DRIVER +M: Remi Buisson +L: linux-iio@vger.kernel.org +S: Maintained +W: https://invensense.tdk.com/ +F: Documentation/devicetree/bindings/iio/imu/invensense,icm45600.yaml +F: drivers/iio/imu/inv_icm45600/ + INVENSENSE MPU-3050 GYROSCOPE DRIVER M: Linus Walleij L: linux-iio@vger.kernel.org From b66cddc8be7278fd14650ff9182f3794397f8b31 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Oct 2025 11:15:20 +0000 Subject: [PATCH 075/304] iio: adc: ad4080: fix chip identification MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix AD4080 chip identification by using the correct 16-bit product ID (0x0050) instead of GENMASK(2, 0). Update the chip reading logic to use regmap_bulk_read to read both PRODUCT_ID_L and PRODUCT_ID_H registers and combine them into a 16-bit value. The original implementation was incorrectly reading only 3 bits, which would not correctly identify the AD4080 chip. Fixes: 6b31ba1811b6 ("iio: adc: ad4080: add driver support") Signed-off-by: Antoniu Miclaus Reviewed-by: Nuno Sá Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index 6e61787ed321..e15310fcd21a 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -125,7 +125,7 @@ /* Miscellaneous Definitions */ #define AD4080_SPI_READ BIT(7) -#define AD4080_CHIP_ID GENMASK(2, 0) +#define AD4080_CHIP_ID 0x0050 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 @@ -445,7 +445,8 @@ static int ad4080_setup(struct iio_dev *indio_dev) { struct ad4080_state *st = iio_priv(indio_dev); struct device *dev = regmap_get_device(st->regmap); - unsigned int id; + __le16 id_le; + u16 id; int ret; ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, @@ -458,10 +459,12 @@ static int ad4080_setup(struct iio_dev *indio_dev) if (ret) return ret; - ret = regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id); + ret = regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id_le, + sizeof(id_le)); if (ret) return ret; + id = le16_to_cpu(id_le); if (id != AD4080_CHIP_ID) dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); From 69ca4df3491a9475fa2f92ce711f5a21cd26a4a9 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Oct 2025 11:15:21 +0000 Subject: [PATCH 076/304] iio: adc: ad4080: prepare driver for multi-part support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor the ad4080 driver to support multiple ADC variants with different resolution bits and LVDS CNV clock count maximums. Changes: - Add lvds_cnv_clk_cnt_max field to chip_info structure - Create AD4080_CHANNEL_DEFINE macro for variable resolution/storage bits - Make LVDS CNV clock count configurable per chip variant - Use chip_info->product_id for chip identification comparison This prepares the infrastructure for adding support for additional ADC parts with different specifications while maintaining backward compatibility with existing AD4080 functionality. Reviewed-by: Nuno Sá Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 42 ++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index e15310fcd21a..646a4de01ca7 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -167,6 +167,7 @@ struct ad4080_chip_info { const unsigned int (*scale_table)[2]; const struct iio_chan_spec *channels; unsigned int num_channels; + unsigned int lvds_cnv_clk_cnt_max; }; struct ad4080_state { @@ -414,23 +415,25 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = { { } }; -static const struct iio_chan_spec ad4080_channel = { - .type = IIO_VOLTAGE, - .indexed = 1, - .channel = 0, - .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), - .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), - .info_mask_shared_by_all_available = - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), - .ext_info = ad4080_ext_info, - .scan_index = 0, - .scan_type = { - .sign = 's', - .realbits = 20, - .storagebits = 32, - }, -}; +#define AD4080_CHANNEL_DEFINE(bits, storage) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = 0, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .ext_info = ad4080_ext_info, \ + .scan_index = 0, \ + .scan_type = { \ + .sign = 's', \ + .realbits = (bits), \ + .storagebits = (storage), \ + }, \ +} + +static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32); static const struct ad4080_chip_info ad4080_chip_info = { .name = "ad4080", @@ -439,6 +442,7 @@ static const struct ad4080_chip_info ad4080_chip_info = { .num_scales = ARRAY_SIZE(ad4080_scale_table), .num_channels = 1, .channels = &ad4080_channel, + .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, }; static int ad4080_setup(struct iio_dev *indio_dev) @@ -465,7 +469,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) return ret; id = le16_to_cpu(id_le); - if (id != AD4080_CHIP_ID) + if (id != st->info->product_id) dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, @@ -491,7 +495,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) AD4080_REG_ADC_DATA_INTF_CONFIG_B, AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, - AD4080_LVDS_CNV_CLK_CNT_MAX)); + st->info->lvds_cnv_clk_cnt_max)); if (ret) return ret; From 1b86053ba6f818624efffa8d1b890b4c74886903 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Oct 2025 11:15:22 +0000 Subject: [PATCH 077/304] dt-bindings: iio: adc: adi,ad4080: add support for AD4084 Add device tree binding support for the AD4084 16-bit SAR ADC. Add adi,ad4084 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4084 has different resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (2 vs 7), requiring different driver configuration. Acked-by: Conor Dooley Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index ed849ba1b77b..c4c5d208f502 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -26,6 +26,7 @@ properties: compatible: enum: - adi,ad4080 + - adi,ad4084 reg: maxItems: 1 From 6c3e7265734bbde7347d44fa8e5720bcc5ad5cea Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Oct 2025 11:15:23 +0000 Subject: [PATCH 078/304] iio: adc: ad4080: add support for AD4084 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for AD4084 16-bit SAR ADC. The AD4084 differs from AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (2 vs 7). Changes: - Add AD4084_CHIP_ID definition (0x0054) - Create ad4084_channel with 16-bit resolution and storage - Add ad4084_chip_info with appropriate configuration - Register AD4084 in device ID and OF match tables Reviewed-by: Nuno Sá Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index 646a4de01ca7..d243b4336ac6 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -126,6 +126,7 @@ /* Miscellaneous Definitions */ #define AD4080_SPI_READ BIT(7) #define AD4080_CHIP_ID 0x0050 +#define AD4084_CHIP_ID 0x0054 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 @@ -435,6 +436,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = { static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32); +static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16); + static const struct ad4080_chip_info ad4080_chip_info = { .name = "ad4080", .product_id = AD4080_CHIP_ID, @@ -445,6 +448,16 @@ static const struct ad4080_chip_info ad4080_chip_info = { .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, }; +static const struct ad4080_chip_info ad4084_chip_info = { + .name = "ad4084", + .product_id = AD4084_CHIP_ID, + .scale_table = ad4080_scale_table, + .num_scales = ARRAY_SIZE(ad4080_scale_table), + .num_channels = 1, + .channels = &ad4084_channel, + .lvds_cnv_clk_cnt_max = 2, +}; + static int ad4080_setup(struct iio_dev *indio_dev) { struct ad4080_state *st = iio_priv(indio_dev); @@ -600,12 +613,14 @@ static int ad4080_probe(struct spi_device *spi) static const struct spi_device_id ad4080_id[] = { { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, + { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4080_id); static const struct of_device_id ad4080_of_match[] = { { .compatible = "adi,ad4080", &ad4080_chip_info }, + { .compatible = "adi,ad4084", &ad4084_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4080_of_match); From 83185903b4eca86e0c7145d62e55de768eeb9e7b Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Oct 2025 11:15:24 +0000 Subject: [PATCH 079/304] dt-bindings: iio: adc: adi,ad4080: add support for AD4081 Add device tree binding support for the AD4081 20-bit SAR ADC. Add adi,ad4081 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4081 has a different LVDS CNV clock count maximum (2 vs 7), requiring different driver configuration. Acked-by: Conor Dooley Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index c4c5d208f502..a9fa068189ea 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -26,6 +26,7 @@ properties: compatible: enum: - adi,ad4080 + - adi,ad4081 - adi,ad4084 reg: From d34ad6467200380c8f8337ceefee9f3d8cee5492 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Oct 2025 11:15:25 +0000 Subject: [PATCH 080/304] iio: adc: ad4080: add support for AD4081 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for AD4081 20-bit SAR ADC. The AD4081 has the same resolution as AD4080 (20-bit) but differs in LVDS CNV clock count maximum (2 vs 7). Changes: - Add AD4081_CHIP_ID definition (0x0051) - Create ad4081_channel with 20-bit resolution and 32-bit storage - Add ad4081_chip_info with lvds_cnv_clk_cnt_max = 2 - Register AD4081 in device ID and OF match tables Reviewed-by: Nuno Sá Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index d243b4336ac6..5940651655df 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -126,6 +126,7 @@ /* Miscellaneous Definitions */ #define AD4080_SPI_READ BIT(7) #define AD4080_CHIP_ID 0x0050 +#define AD4081_CHIP_ID 0x0051 #define AD4084_CHIP_ID 0x0054 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 @@ -436,6 +437,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[] = { static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32); +static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32); + static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16); static const struct ad4080_chip_info ad4080_chip_info = { @@ -448,6 +451,16 @@ static const struct ad4080_chip_info ad4080_chip_info = { .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, }; +static const struct ad4080_chip_info ad4081_chip_info = { + .name = "ad4081", + .product_id = AD4081_CHIP_ID, + .scale_table = ad4080_scale_table, + .num_scales = ARRAY_SIZE(ad4080_scale_table), + .num_channels = 1, + .channels = &ad4081_channel, + .lvds_cnv_clk_cnt_max = 2, +}; + static const struct ad4080_chip_info ad4084_chip_info = { .name = "ad4084", .product_id = AD4084_CHIP_ID, @@ -613,6 +626,7 @@ static int ad4080_probe(struct spi_device *spi) static const struct spi_device_id ad4080_id[] = { { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, + { "ad4081", (kernel_ulong_t)&ad4081_chip_info }, { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, { } }; @@ -620,6 +634,7 @@ MODULE_DEVICE_TABLE(spi, ad4080_id); static const struct of_device_id ad4080_of_match[] = { { .compatible = "adi,ad4080", &ad4080_chip_info }, + { .compatible = "adi,ad4081", &ad4081_chip_info }, { .compatible = "adi,ad4084", &ad4084_chip_info }, { } }; From f277fe2ff54aeea3b5c31aa045f03ccea612a299 Mon Sep 17 00:00:00 2001 From: Dixit Parmar Date: Sat, 11 Oct 2025 13:41:49 +0530 Subject: [PATCH 081/304] iio: adc: ti-ads131e08: return correct error code The error code returned from devm_iio_trigger_register() inturn iio_trigger_register() can be other than -ENOMEM. Hence return the same value as it was returned from the function call. This change makes devm_iio_trigger_register() handling uniform with other iio drivers. Signed-off-by: Dixit Parmar Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ti-ads131e08.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ti-ads131e08.c b/drivers/iio/adc/ti-ads131e08.c index 742acc6d8cf9..c9a20024d6b1 100644 --- a/drivers/iio/adc/ti-ads131e08.c +++ b/drivers/iio/adc/ti-ads131e08.c @@ -848,7 +848,7 @@ static int ads131e08_probe(struct spi_device *spi) ret = devm_iio_trigger_register(&spi->dev, st->trig); if (ret) { dev_err(&spi->dev, "failed to register IIO trigger\n"); - return -ENOMEM; + return ret; } indio_dev->trig = iio_trigger_get(st->trig); From 8f0072c742e37474de058a41256fb91934dd4d5d Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sat, 11 Oct 2025 22:59:09 +0200 Subject: [PATCH 082/304] dt-bindings: iio: accel: adxl345: document second interrupt The pinout of all the supported chips in this binding have two interrupt pins. Document the second one, too, even though the Linux driver currently does not support the second interrupt. Boards may have it wired nonetheless. While here, drop the dependency of interrupt-names which is already described in the core. Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/accel/adi,adxl345.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index a23a626bfab6..61d7ba89adc2 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -35,15 +35,17 @@ properties: spi-3wire: true interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupt-names: + minItems: 1 items: - enum: [INT1, INT2] + - const: INT2 dependencies: interrupts: [ interrupt-names ] - interrupt-names: [ interrupts ] required: - compatible @@ -84,7 +86,8 @@ examples: spi-cpol; spi-cpha; interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "INT2"; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1", "INT2"; }; }; From e7966a4953a3c9e40382693f578523da2b384919 Mon Sep 17 00:00:00 2001 From: Shrikant Raskar Date: Sun, 12 Oct 2025 23:00:34 +0530 Subject: [PATCH 083/304] dt-bindings: iio: health: max30100: Add LED pulse-width property The LED pulse width on the MAX30100 sensor determines how long the IR/Red LEDs are driven during each sample, directly affecting the emitted optical energy and hence the received signal amplitude. This parameter is highly dependent on the mechanical and optical integration of the sensor, such as: - The type and thickness of the optical window or lens covering the sensor. - The distance between the LED and photodiode. - The reflectivity of the target surface. For example: - A smartwatch or wearable ring with a thin glass window can operate with shorter pulses (200-400 us) to save power. - A medical-grade pulse oximeter or sensor mounted behind a thicker protective layer may require longer pulses (800-1600 us) for reliable signal amplitude. Because this configuration is determined by hardware design rather than by runtime conditions, it is appropriate to describe it in the DT. If not specified, the driver defaults to 1600 us to maintain existing behavior. Tested on: Raspberry Pi 3B + MAX30100 breakout board. Signed-off-by: Shrikant Raskar Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/health/maxim,max30100.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/health/maxim,max30100.yaml b/Documentation/devicetree/bindings/iio/health/maxim,max30100.yaml index 967778fb0ce8..d4753c85ecc3 100644 --- a/Documentation/devicetree/bindings/iio/health/maxim,max30100.yaml +++ b/Documentation/devicetree/bindings/iio/health/maxim,max30100.yaml @@ -27,6 +27,14 @@ properties: LED current whilst the engine is running. First indexed value is the configuration for the RED LED, and second value is for the IR LED. + maxim,pulse-width-us: + description: | + LED pulse width in microseconds. Appropriate pulse width depends on + factors such as optical window absorption, LED-to-sensor distance, + and expected reflectivity of the skin or contact surface. + enum: [200, 400, 800, 1600] + default: 1600 + additionalProperties: false required: From 6365d2b988aa6515983b498333d832297418563f Mon Sep 17 00:00:00 2001 From: Shrikant Raskar Date: Sun, 12 Oct 2025 23:00:35 +0530 Subject: [PATCH 084/304] iio: health: max30100: Make LED pulse-width configurable via DT The required LED pulse width depends on board-specific optical and mechanical design, which affects measurement accuracy and power use. Making it configurable via Device Tree allows each platform to define an appropriate value instead of relying on a hardcoded default. If unspecified, the driver defaults to 1600 us for backward compatibility. Tested on: Raspberry Pi 3B + MAX30100 breakout board. Reviewed-by: Nuno Sa Signed-off-by: Shrikant Raskar Signed-off-by: Jonathan Cameron --- drivers/iio/health/max30100.c | 38 ++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/iio/health/max30100.c b/drivers/iio/health/max30100.c index 814f521e47ae..3d441013893c 100644 --- a/drivers/iio/health/max30100.c +++ b/drivers/iio/health/max30100.c @@ -5,7 +5,6 @@ * Copyright (C) 2015, 2018 * Author: Matt Ranostay * - * TODO: enable pulse length controls via device tree properties */ #include @@ -18,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -52,9 +52,13 @@ #define MAX30100_REG_MODE_CONFIG_PWR BIT(7) #define MAX30100_REG_SPO2_CONFIG 0x07 +#define MAX30100_REG_SPO2_CONFIG_PW_MASK GENMASK(1, 0) +#define MAX30100_REG_SPO2_CONFIG_200US 0x0 +#define MAX30100_REG_SPO2_CONFIG_400US 0x1 +#define MAX30100_REG_SPO2_CONFIG_800US 0x2 +#define MAX30100_REG_SPO2_CONFIG_1600US 0x3 #define MAX30100_REG_SPO2_CONFIG_100HZ BIT(2) #define MAX30100_REG_SPO2_CONFIG_HI_RES_EN BIT(6) -#define MAX30100_REG_SPO2_CONFIG_1600US 0x3 #define MAX30100_REG_LED_CONFIG 0x09 #define MAX30100_REG_LED_CONFIG_LED_MASK 0x0f @@ -306,19 +310,47 @@ static int max30100_led_init(struct max30100_data *data) MAX30100_REG_LED_CONFIG_LED_MASK, reg); } +static int max30100_get_pulse_width(unsigned int pwidth_us) +{ + switch (pwidth_us) { + case 200: + return MAX30100_REG_SPO2_CONFIG_200US; + case 400: + return MAX30100_REG_SPO2_CONFIG_400US; + case 800: + return MAX30100_REG_SPO2_CONFIG_800US; + case 1600: + return MAX30100_REG_SPO2_CONFIG_1600US; + default: + return -EINVAL; + } +} + static int max30100_chip_init(struct max30100_data *data) { int ret; + int pulse_width; + /* set default LED pulse-width to 1600 us */ + unsigned int pulse_us = 1600; + struct device *dev = &data->client->dev; /* setup LED current settings */ ret = max30100_led_init(data); if (ret) return ret; + /* Read LED pulse-width-us from DT */ + device_property_read_u32(dev, "maxim,pulse-width-us", &pulse_us); + + pulse_width = max30100_get_pulse_width(pulse_us); + if (pulse_width < 0) + return dev_err_probe(dev, pulse_width, "invalid LED pulse-width %uus\n", pulse_us); + /* enable hi-res SPO2 readings at 100Hz */ ret = regmap_write(data->regmap, MAX30100_REG_SPO2_CONFIG, MAX30100_REG_SPO2_CONFIG_HI_RES_EN | - MAX30100_REG_SPO2_CONFIG_100HZ); + MAX30100_REG_SPO2_CONFIG_100HZ | + FIELD_PREP(MAX30100_REG_SPO2_CONFIG_PW_MASK, pulse_width)); if (ret) return ret; From 36bf0de9d6ec8f5ce50bdb9f2bd90150c9026d9a Mon Sep 17 00:00:00 2001 From: Akshay Jindal Date: Sun, 12 Oct 2025 23:36:08 +0530 Subject: [PATCH 085/304] iio: accel: bma400: Reorganize and rename register and field macros Reorganize register and field macros to improve consistency with the datasheet and naming style: - Move field macros next to their corresponding register macros - Reorder register macros to follow address order from the datasheet - Rename field macros to include the register name in the macro name - Add a _REG suffix to register macros where missing - Add INT_STAT register fields corresponding to used INT_CONFIG fields No functional changes are intended. Signed-off-by: Akshay Jindal Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma400.h | 117 ++++++++++-------- drivers/iio/accel/bma400_core.c | 212 ++++++++++++++++---------------- 2 files changed, 170 insertions(+), 159 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 932358b45f17..fcafd1fba57a 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -16,31 +16,44 @@ * Read-Only Registers */ +/* Chip ID of BMA 400 devices found in the chip ID register. */ +#define BMA400_ID_REG_VAL 0x90 + /* Status and ID registers */ #define BMA400_CHIP_ID_REG 0x00 #define BMA400_ERR_REG 0x02 #define BMA400_STATUS_REG 0x03 /* Acceleration registers */ -#define BMA400_X_AXIS_LSB_REG 0x04 -#define BMA400_X_AXIS_MSB_REG 0x05 -#define BMA400_Y_AXIS_LSB_REG 0x06 -#define BMA400_Y_AXIS_MSB_REG 0x07 -#define BMA400_Z_AXIS_LSB_REG 0x08 -#define BMA400_Z_AXIS_MSB_REG 0x09 +#define BMA400_ACC_X_LSB_REG 0x04 +#define BMA400_ACC_X_MSB_REG 0x05 +#define BMA400_ACC_Y_LSB_REG 0x06 +#define BMA400_ACC_Y_MSB_REG 0x07 +#define BMA400_ACC_Z_LSB_REG 0x08 +#define BMA400_ACC_Z_MSB_REG 0x09 /* Sensor time registers */ -#define BMA400_SENSOR_TIME0 0x0a -#define BMA400_SENSOR_TIME1 0x0b -#define BMA400_SENSOR_TIME2 0x0c +#define BMA400_SENSOR_TIME0_REG 0x0a +#define BMA400_SENSOR_TIME1_REG 0x0b +#define BMA400_SENSOR_TIME2_REG 0x0c /* Event and interrupt registers */ #define BMA400_EVENT_REG 0x0d + #define BMA400_INT_STAT0_REG 0x0e +#define BMA400_INT_STAT0_GEN1_MASK BIT(2) +#define BMA400_INT_STAT0_GEN2_MASK BIT(3) +#define BMA400_INT_STAT0_DRDY_MASK BIT(7) + #define BMA400_INT_STAT1_REG 0x0f +#define BMA400_INT_STAT1_STEP_INT_MASK GENMASK(9, 8) +#define BMA400_INT_STAT1_S_TAP_MASK BIT(10) +#define BMA400_INT_STAT1_D_TAP_MASK BIT(11) + #define BMA400_INT_STAT2_REG 0x10 -#define BMA400_INT12_MAP_REG 0x23 -#define BMA400_INT_ENG_OVRUN_MSK BIT(4) + +/* Bit present in all INT_STAT registers */ +#define BMA400_INT_STAT_ENG_OVRRUN_MASK BIT(4) /* Temperature register */ #define BMA400_TEMP_DATA_REG 0x11 @@ -55,70 +68,68 @@ #define BMA400_STEP_CNT1_REG 0x16 #define BMA400_STEP_CNT3_REG 0x17 #define BMA400_STEP_STAT_REG 0x18 -#define BMA400_STEP_INT_MSK BIT(0) #define BMA400_STEP_RAW_LEN 0x03 -#define BMA400_STEP_STAT_MASK GENMASK(9, 8) /* * Read-write configuration registers */ -#define BMA400_ACC_CONFIG0_REG 0x19 -#define BMA400_ACC_CONFIG1_REG 0x1a +#define BMA400_ACC_CONFIG0_REG 0x19 +#define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5) +#define BMA400_LP_OSR_SHIFT 5 + +#define BMA400_ACC_CONFIG1_REG 0x1a +#define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0) +#define BMA400_ACC_CONFIG1_ODR_MIN_RAW 0x05 +#define BMA400_ACC_CONFIG1_ODR_LP_RAW 0x06 +#define BMA400_ACC_CONFIG1_ODR_MAX_RAW 0x0b +#define BMA400_ACC_CONFIG1_ODR_MAX_HZ 800 +#define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ 25 +#define BMA400_ACC_CONFIG1_ODR_MIN_HZ 12 +#define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4) +#define BMA400_NP_OSR_SHIFT 4 +#define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6) +#define BMA400_ACC_RANGE_SHIFT 6 + #define BMA400_ACC_CONFIG2_REG 0x1b -#define BMA400_CMD_REG 0x7e /* Interrupt registers */ #define BMA400_INT_CONFIG0_REG 0x1f +#define BMA400_INT_CONFIG0_GEN1_MASK BIT(2) +#define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) +#define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) + #define BMA400_INT_CONFIG1_REG 0x20 +#define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) +#define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) +#define BMA400_INT_CONFIG1_D_TAP_MASK BIT(3) + #define BMA400_INT1_MAP_REG 0x21 +#define BMA400_INT12_MAP_REG 0x23 #define BMA400_INT_IO_CTRL_REG 0x24 -#define BMA400_INT_DRDY_MSK BIT(7) - -/* Chip ID of BMA 400 devices found in the chip ID register. */ -#define BMA400_ID_REG_VAL 0x90 - -#define BMA400_LP_OSR_SHIFT 5 -#define BMA400_NP_OSR_SHIFT 4 -#define BMA400_SCALE_SHIFT 6 #define BMA400_TWO_BITS_MASK GENMASK(1, 0) -#define BMA400_LP_OSR_MASK GENMASK(6, 5) -#define BMA400_NP_OSR_MASK GENMASK(5, 4) -#define BMA400_ACC_ODR_MASK GENMASK(3, 0) -#define BMA400_ACC_SCALE_MASK GENMASK(7, 6) - -#define BMA400_ACC_ODR_MIN_RAW 0x05 -#define BMA400_ACC_ODR_LP_RAW 0x06 -#define BMA400_ACC_ODR_MAX_RAW 0x0b - -#define BMA400_ACC_ODR_MAX_HZ 800 -#define BMA400_ACC_ODR_MIN_WHOLE_HZ 25 -#define BMA400_ACC_ODR_MIN_HZ 12 /* Generic interrupts register */ -#define BMA400_GEN1INT_CONFIG0 0x3f -#define BMA400_GEN2INT_CONFIG0 0x4A +#define BMA400_GEN1INT_CONFIG0_REG 0x3f +#define BMA400_GEN2INT_CONFIG0_REG 0x4A +#define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) + #define BMA400_GEN_CONFIG1_OFF 0x01 #define BMA400_GEN_CONFIG2_OFF 0x02 #define BMA400_GEN_CONFIG3_OFF 0x03 #define BMA400_GEN_CONFIG31_OFF 0x04 -#define BMA400_INT_GEN1_MSK BIT(2) -#define BMA400_INT_GEN2_MSK BIT(3) -#define BMA400_GEN_HYST_MSK GENMASK(1, 0) /* TAP config registers */ -#define BMA400_TAP_CONFIG 0x57 -#define BMA400_TAP_CONFIG1 0x58 -#define BMA400_S_TAP_MSK BIT(2) -#define BMA400_D_TAP_MSK BIT(3) -#define BMA400_INT_S_TAP_MSK BIT(10) -#define BMA400_INT_D_TAP_MSK BIT(11) -#define BMA400_TAP_SEN_MSK GENMASK(2, 0) -#define BMA400_TAP_TICSTH_MSK GENMASK(1, 0) -#define BMA400_TAP_QUIET_MSK GENMASK(3, 2) -#define BMA400_TAP_QUIETDT_MSK GENMASK(5, 4) +#define BMA400_TAP_CONFIG_REG 0x57 +#define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0) + +#define BMA400_TAP_CONFIG1_REG 0x58 +#define BMA400_TAP_CONFIG1_TICSTH_MASK GENMASK(1, 0) +#define BMA400_TAP_CONFIG1_QUIET_MASK GENMASK(3, 2) +#define BMA400_TAP_CONFIG1_QUIETDT_MASK GENMASK(5, 4) #define BMA400_TAP_TIM_LIST_LEN 4 +#define BMA400_CMD_REG 0x7e /* * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before * converting to micro values for +-2g range. @@ -138,8 +149,8 @@ * To select +-8g = 9577 << 2 = raw value to write is 2. * To select +-16g = 9577 << 3 = raw value to write is 3. */ -#define BMA400_SCALE_MIN 9577 -#define BMA400_SCALE_MAX 76617 +#define BMA400_ACC_SCALE_MIN 9577 +#define BMA400_ACC_SCALE_MAX 76617 extern const struct regmap_config bma400_regmap_config; diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index 85e23badf733..2324c4ef645c 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -127,15 +127,15 @@ static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) case BMA400_CHIP_ID_REG: case BMA400_ERR_REG: case BMA400_STATUS_REG: - case BMA400_X_AXIS_LSB_REG: - case BMA400_X_AXIS_MSB_REG: - case BMA400_Y_AXIS_LSB_REG: - case BMA400_Y_AXIS_MSB_REG: - case BMA400_Z_AXIS_LSB_REG: - case BMA400_Z_AXIS_MSB_REG: - case BMA400_SENSOR_TIME0: - case BMA400_SENSOR_TIME1: - case BMA400_SENSOR_TIME2: + case BMA400_ACC_X_LSB_REG: + case BMA400_ACC_X_MSB_REG: + case BMA400_ACC_Y_LSB_REG: + case BMA400_ACC_Y_MSB_REG: + case BMA400_ACC_Z_LSB_REG: + case BMA400_ACC_Z_MSB_REG: + case BMA400_SENSOR_TIME0_REG: + case BMA400_SENSOR_TIME1_REG: + case BMA400_SENSOR_TIME2_REG: case BMA400_EVENT_REG: case BMA400_INT_STAT0_REG: case BMA400_INT_STAT1_REG: @@ -159,15 +159,15 @@ static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg) switch (reg) { case BMA400_ERR_REG: case BMA400_STATUS_REG: - case BMA400_X_AXIS_LSB_REG: - case BMA400_X_AXIS_MSB_REG: - case BMA400_Y_AXIS_LSB_REG: - case BMA400_Y_AXIS_MSB_REG: - case BMA400_Z_AXIS_LSB_REG: - case BMA400_Z_AXIS_MSB_REG: - case BMA400_SENSOR_TIME0: - case BMA400_SENSOR_TIME1: - case BMA400_SENSOR_TIME2: + case BMA400_ACC_X_LSB_REG: + case BMA400_ACC_X_MSB_REG: + case BMA400_ACC_Y_LSB_REG: + case BMA400_ACC_Y_MSB_REG: + case BMA400_ACC_Z_LSB_REG: + case BMA400_ACC_Z_MSB_REG: + case BMA400_SENSOR_TIME0_REG: + case BMA400_SENSOR_TIME1_REG: + case BMA400_SENSOR_TIME2_REG: case BMA400_EVENT_REG: case BMA400_INT_STAT0_REG: case BMA400_INT_STAT1_REG: @@ -275,11 +275,11 @@ static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev, struct bma400_data *data = iio_priv(indio_dev); int ret, reg_val, raw, vals[2]; - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, ®_val); + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); if (ret) return ret; - raw = FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val); + raw = FIELD_GET(BMA400_TAP_CONFIG1_TICSTH_MASK, reg_val); vals[0] = 0; vals[1] = tap_max2min_time[raw]; @@ -302,9 +302,9 @@ static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev, if (raw < 0) return -EINVAL; - ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1, - BMA400_TAP_TICSTH_MSK, - FIELD_PREP(BMA400_TAP_TICSTH_MSK, raw)); + ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1_REG, + BMA400_TAP_CONFIG1_TICSTH_MASK, + FIELD_PREP(BMA400_TAP_CONFIG1_TICSTH_MASK, raw)); if (ret) return ret; @@ -449,13 +449,13 @@ static int bma400_get_accel_reg(struct bma400_data *data, switch (chan->channel2) { case IIO_MOD_X: - lsb_reg = BMA400_X_AXIS_LSB_REG; + lsb_reg = BMA400_ACC_X_LSB_REG; break; case IIO_MOD_Y: - lsb_reg = BMA400_Y_AXIS_LSB_REG; + lsb_reg = BMA400_ACC_Y_LSB_REG; break; case IIO_MOD_Z: - lsb_reg = BMA400_Z_AXIS_LSB_REG; + lsb_reg = BMA400_ACC_Z_LSB_REG; break; default: dev_err(data->dev, "invalid axis channel modifier\n"); @@ -475,8 +475,8 @@ static int bma400_get_accel_reg(struct bma400_data *data, static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, unsigned int *val2) { - *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw); - if (raw > BMA400_ACC_ODR_MIN_RAW) + *val = BMA400_ACC_CONFIG1_ODR_MAX_HZ >> (BMA400_ACC_CONFIG1_ODR_MAX_RAW - raw); + if (raw > BMA400_ACC_CONFIG1_ODR_MIN_RAW) *val2 = 0; else *val2 = 500000; @@ -494,7 +494,7 @@ static int bma400_get_accel_output_data_rate(struct bma400_data *data) * Runs at a fixed rate in low-power mode. See section 4.3 * in the datasheet. */ - bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW, + bma400_output_data_rate_from_raw(BMA400_ACC_CONFIG1_ODR_LP_RAW, &data->sample_freq.hz, &data->sample_freq.uhz); return 0; @@ -507,9 +507,9 @@ static int bma400_get_accel_output_data_rate(struct bma400_data *data) if (ret) goto error; - odr = val & BMA400_ACC_ODR_MASK; - if (odr < BMA400_ACC_ODR_MIN_RAW || - odr > BMA400_ACC_ODR_MAX_RAW) { + odr = val & BMA400_ACC_CONFIG1_ODR_MASK; + if (odr < BMA400_ACC_CONFIG1_ODR_MIN_RAW || + odr > BMA400_ACC_CONFIG1_ODR_MAX_RAW) { ret = -EINVAL; goto error; } @@ -539,19 +539,19 @@ static int bma400_set_accel_output_data_rate(struct bma400_data *data, unsigned int val; int ret; - if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) { - if (uhz || hz > BMA400_ACC_ODR_MAX_HZ) + if (hz >= BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) { + if (uhz || hz > BMA400_ACC_CONFIG1_ODR_MAX_HZ) return -EINVAL; /* Note this works because MIN_WHOLE_HZ is odd */ idx = __ffs(hz); - if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ) + if (hz >> idx != BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) return -EINVAL; - idx += BMA400_ACC_ODR_MIN_RAW + 1; - } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) { - idx = BMA400_ACC_ODR_MIN_RAW; + idx += BMA400_ACC_CONFIG1_ODR_MIN_RAW + 1; + } else if (hz == BMA400_ACC_CONFIG1_ODR_MIN_HZ && uhz == 500000) { + idx = BMA400_ACC_CONFIG1_ODR_MIN_RAW; } else { return -EINVAL; } @@ -561,7 +561,7 @@ static int bma400_set_accel_output_data_rate(struct bma400_data *data, return ret; /* preserve the range and normal mode osr */ - odr = (~BMA400_ACC_ODR_MASK & val) | idx; + odr = (~BMA400_ACC_CONFIG1_ODR_MASK & val) | idx; ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr); if (ret) @@ -592,7 +592,7 @@ static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) return ret; } - osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; + osr = (val & BMA400_ACC_CONFIG0_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; data->oversampling_ratio = osr; return 0; @@ -603,7 +603,7 @@ static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) return ret; } - osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; + osr = (val & BMA400_ACC_CONFIG1_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; data->oversampling_ratio = osr; return 0; @@ -637,7 +637,7 @@ static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, return ret; ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, - (acc_config & ~BMA400_LP_OSR_MASK) | + (acc_config & ~BMA400_ACC_CONFIG0_LP_OSR_MASK) | (val << BMA400_LP_OSR_SHIFT)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); @@ -653,7 +653,7 @@ static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, return ret; ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, - (acc_config & ~BMA400_NP_OSR_MASK) | + (acc_config & ~BMA400_ACC_CONFIG1_NP_OSR_MASK) | (val << BMA400_NP_OSR_SHIFT)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); @@ -679,7 +679,7 @@ static int bma400_accel_scale_to_raw(struct bma400_data *data, /* Note this works because BMA400_SCALE_MIN is odd */ raw = __ffs(val); - if (val >> raw != BMA400_SCALE_MIN) + if (val >> raw != BMA400_ACC_SCALE_MIN) return -EINVAL; return raw; @@ -695,11 +695,11 @@ static int bma400_get_accel_scale(struct bma400_data *data) if (ret) return ret; - raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT; + raw_scale = (val & BMA400_ACC_CONFIG1_ACC_RANGE_MASK) >> BMA400_ACC_RANGE_SHIFT; if (raw_scale > BMA400_TWO_BITS_MASK) return -EINVAL; - data->scale = BMA400_SCALE_MIN << raw_scale; + data->scale = BMA400_ACC_SCALE_MIN << raw_scale; return 0; } @@ -719,8 +719,8 @@ static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val) return raw; ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, - (acc_config & ~BMA400_ACC_SCALE_MASK) | - (raw << BMA400_SCALE_SHIFT)); + (acc_config & ~BMA400_ACC_CONFIG1_ACC_RANGE_MASK) | + (raw << BMA400_ACC_RANGE_SHIFT)); if (ret) return ret; @@ -786,8 +786,8 @@ static int bma400_enable_steps(struct bma400_data *data, int val) return 0; ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, - BMA400_STEP_INT_MSK, - FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0)); + BMA400_INT_CONFIG1_STEP_INT_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, val ? 1 : 0)); if (ret) return ret; data->steps_enabled = val; @@ -826,7 +826,7 @@ static void bma400_init_tables(void) for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) { raw = i / 2; bma400_scales[i] = 0; - bma400_scales[i + 1] = BMA400_SCALE_MIN << raw; + bma400_scales[i + 1] = BMA400_ACC_SCALE_MIN << raw; } } @@ -1063,7 +1063,7 @@ static int bma400_write_raw(struct iio_dev *indio_dev, return ret; case IIO_CHAN_INFO_SCALE: if (val != 0 || - val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX) + val2 < BMA400_ACC_SCALE_MIN || val2 > BMA400_ACC_SCALE_MAX) return -EINVAL; mutex_lock(&data->mutex); @@ -1114,16 +1114,16 @@ static int bma400_read_event_config(struct iio_dev *indio_dev, case IIO_ACCEL: switch (dir) { case IIO_EV_DIR_RISING: - return FIELD_GET(BMA400_INT_GEN1_MSK, + return FIELD_GET(BMA400_INT_CONFIG0_GEN1_MASK, data->generic_event_en); case IIO_EV_DIR_FALLING: - return FIELD_GET(BMA400_INT_GEN2_MSK, + return FIELD_GET(BMA400_INT_CONFIG0_GEN2_MASK, data->generic_event_en); case IIO_EV_DIR_SINGLETAP: - return FIELD_GET(BMA400_S_TAP_MSK, + return FIELD_GET(BMA400_INT_CONFIG1_S_TAP_MASK, data->tap_event_en_bitmask); case IIO_EV_DIR_DOUBLETAP: - return FIELD_GET(BMA400_D_TAP_MSK, + return FIELD_GET(BMA400_INT_CONFIG1_D_TAP_MASK, data->tap_event_en_bitmask); default: return -EINVAL; @@ -1146,8 +1146,8 @@ static int bma400_steps_event_enable(struct bma400_data *data, int state) return ret; ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, - BMA400_STEP_INT_MSK, - FIELD_PREP(BMA400_STEP_INT_MSK, + BMA400_INT_CONFIG1_STEP_INT_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, state)); if (ret) return ret; @@ -1164,18 +1164,18 @@ static int bma400_activity_event_en(struct bma400_data *data, switch (dir) { case IIO_EV_DIR_RISING: - reg = BMA400_GEN1INT_CONFIG0; - msk = BMA400_INT_GEN1_MSK; + reg = BMA400_GEN1INT_CONFIG0_REG; + msk = BMA400_INT_CONFIG0_GEN1_MASK; value = 2; - set_mask_bits(&field_value, BMA400_INT_GEN1_MSK, - FIELD_PREP(BMA400_INT_GEN1_MSK, state)); + set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); break; case IIO_EV_DIR_FALLING: - reg = BMA400_GEN2INT_CONFIG0; - msk = BMA400_INT_GEN2_MSK; + reg = BMA400_GEN2INT_CONFIG0_REG; + msk = BMA400_INT_CONFIG0_GEN2_MASK; value = 0; - set_mask_bits(&field_value, BMA400_INT_GEN2_MSK, - FIELD_PREP(BMA400_INT_GEN2_MSK, state)); + set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); break; default: return -EINVAL; @@ -1240,21 +1240,21 @@ static int bma400_tap_event_en(struct bma400_data *data, } ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, - BMA400_S_TAP_MSK, - FIELD_PREP(BMA400_S_TAP_MSK, state)); + BMA400_INT_CONFIG1_S_TAP_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); if (ret) return ret; switch (dir) { case IIO_EV_DIR_SINGLETAP: - mask = BMA400_S_TAP_MSK; - set_mask_bits(&field_value, BMA400_S_TAP_MSK, - FIELD_PREP(BMA400_S_TAP_MSK, state)); + mask = BMA400_INT_CONFIG1_S_TAP_MASK; + set_mask_bits(&field_value, BMA400_INT_CONFIG1_S_TAP_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); break; case IIO_EV_DIR_DOUBLETAP: - mask = BMA400_D_TAP_MSK; - set_mask_bits(&field_value, BMA400_D_TAP_MSK, - FIELD_PREP(BMA400_D_TAP_MSK, state)); + mask = BMA400_INT_CONFIG1_D_TAP_MASK; + set_mask_bits(&field_value, BMA400_INT_CONFIG1_D_TAP_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_D_TAP_MASK, state)); break; default: return -EINVAL; @@ -1340,9 +1340,9 @@ static int get_gen_config_reg(enum iio_event_direction dir) { switch (dir) { case IIO_EV_DIR_FALLING: - return BMA400_GEN2INT_CONFIG0; + return BMA400_GEN2INT_CONFIG0_REG; case IIO_EV_DIR_RISING: - return BMA400_GEN1INT_CONFIG0; + return BMA400_GEN1INT_CONFIG0_REG; default: return -EINVAL; } @@ -1393,7 +1393,7 @@ static int bma400_read_event_value(struct iio_dev *indio_dev, ret = regmap_read(data->regmap, reg, val); if (ret) return ret; - *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val); + *val = FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); return IIO_VAL_INT; default: return -EINVAL; @@ -1401,30 +1401,30 @@ static int bma400_read_event_value(struct iio_dev *indio_dev, case IIO_EV_TYPE_GESTURE: switch (info) { case IIO_EV_INFO_VALUE: - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG, + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG_REG, ®_val); if (ret) return ret; - *val = FIELD_GET(BMA400_TAP_SEN_MSK, reg_val); + *val = FIELD_GET(BMA400_TAP_CONFIG_SEN_MASK, reg_val); return IIO_VAL_INT; case IIO_EV_INFO_RESET_TIMEOUT: - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); if (ret) return ret; - raw = FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val); + raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIET_MASK, reg_val); *val = 0; *val2 = tap_reset_timeout[raw]; return IIO_VAL_INT_PLUS_MICRO; case IIO_EV_INFO_TAP2_MIN_DELAY: - ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, + ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); if (ret) return ret; - raw = FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val); + raw = FIELD_GET(BMA400_TAP_CONFIG1_QUIETDT_MASK, reg_val); *val = 0; *val2 = double_tap2_min_delay[raw]; return IIO_VAL_INT_PLUS_MICRO; @@ -1480,8 +1480,8 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, return -EINVAL; return regmap_update_bits(data->regmap, reg, - BMA400_GEN_HYST_MSK, - FIELD_PREP(BMA400_GEN_HYST_MSK, + BMA400_GENINT_CONFIG0_HYST_MASK, + FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, val)); default: return -EINVAL; @@ -1493,9 +1493,9 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, return -EINVAL; return regmap_update_bits(data->regmap, - BMA400_TAP_CONFIG, - BMA400_TAP_SEN_MSK, - FIELD_PREP(BMA400_TAP_SEN_MSK, + BMA400_TAP_CONFIG_REG, + BMA400_TAP_CONFIG_SEN_MASK, + FIELD_PREP(BMA400_TAP_CONFIG_SEN_MASK, val)); case IIO_EV_INFO_RESET_TIMEOUT: raw = usec_to_tapreg_raw(val2, tap_reset_timeout); @@ -1503,9 +1503,9 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, return -EINVAL; return regmap_update_bits(data->regmap, - BMA400_TAP_CONFIG1, - BMA400_TAP_QUIET_MSK, - FIELD_PREP(BMA400_TAP_QUIET_MSK, + BMA400_TAP_CONFIG1_REG, + BMA400_TAP_CONFIG1_QUIET_MASK, + FIELD_PREP(BMA400_TAP_CONFIG1_QUIET_MASK, raw)); case IIO_EV_INFO_TAP2_MIN_DELAY: raw = usec_to_tapreg_raw(val2, double_tap2_min_delay); @@ -1513,9 +1513,9 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, return -EINVAL; return regmap_update_bits(data->regmap, - BMA400_TAP_CONFIG1, - BMA400_TAP_QUIETDT_MSK, - FIELD_PREP(BMA400_TAP_QUIETDT_MSK, + BMA400_TAP_CONFIG1_REG, + BMA400_TAP_CONFIG1_QUIETDT_MASK, + FIELD_PREP(BMA400_TAP_CONFIG1_QUIETDT_MASK, raw)); default: return -EINVAL; @@ -1533,14 +1533,14 @@ static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig, int ret; ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, - BMA400_INT_DRDY_MSK, - FIELD_PREP(BMA400_INT_DRDY_MSK, state)); + BMA400_INT_CONFIG0_DRDY_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); if (ret) return ret; return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, - BMA400_INT_DRDY_MSK, - FIELD_PREP(BMA400_INT_DRDY_MSK, state)); + BMA400_INT_CONFIG0_DRDY_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); } static const unsigned long bma400_avail_scan_masks[] = { @@ -1578,7 +1578,7 @@ static irqreturn_t bma400_trigger_handler(int irq, void *p) mutex_lock(&data->mutex); /* bulk read six registers, with the base being the LSB register */ - ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG, + ret = regmap_bulk_read(data->regmap, BMA400_ACC_X_LSB_REG, &data->buffer.buff, sizeof(data->buffer.buff)); if (ret) goto unlock_err; @@ -1628,13 +1628,13 @@ static irqreturn_t bma400_interrupt(int irq, void *private) * Disable all advance interrupts if interrupt engine overrun occurs. * See section 4.7 "Interrupt engine overrun" in datasheet v1.2. */ - if (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) { + if (FIELD_GET(BMA400_INT_STAT_ENG_OVRRUN_MASK, le16_to_cpu(data->status))) { bma400_disable_adv_interrupt(data); dev_err(data->dev, "Interrupt engine overrun\n"); goto unlock_err; } - if (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_INT_STAT1_S_TAP_MASK, le16_to_cpu(data->status))) iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, @@ -1642,7 +1642,7 @@ static irqreturn_t bma400_interrupt(int irq, void *private) IIO_EV_DIR_SINGLETAP), timestamp); - if (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_INT_STAT1_D_TAP_MASK, le16_to_cpu(data->status))) iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, @@ -1650,10 +1650,10 @@ static irqreturn_t bma400_interrupt(int irq, void *private) IIO_EV_DIR_DOUBLETAP), timestamp); - if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_INT_STAT0_GEN1_MASK, le16_to_cpu(data->status))) ev_dir = IIO_EV_DIR_RISING; - if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_INT_STAT0_GEN2_MASK, le16_to_cpu(data->status))) ev_dir = IIO_EV_DIR_FALLING; if (ev_dir != IIO_EV_DIR_NONE) { @@ -1664,7 +1664,7 @@ static irqreturn_t bma400_interrupt(int irq, void *private) timestamp); } - if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) { + if (FIELD_GET(BMA400_INT_STAT1_STEP_INT_MASK, le16_to_cpu(data->status))) { iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, IIO_EV_TYPE_CHANGE, @@ -1686,7 +1686,7 @@ static irqreturn_t bma400_interrupt(int irq, void *private) } } - if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) { + if (FIELD_GET(BMA400_INT_STAT0_DRDY_MASK, le16_to_cpu(data->status))) { mutex_unlock(&data->mutex); iio_trigger_poll_nested(data->trig); return IRQ_HANDLED; From a2ef0af1923ba3fa0b46adfd8fb01d5920906980 Mon Sep 17 00:00:00 2001 From: Akshay Jindal Date: Sun, 12 Oct 2025 23:36:09 +0530 Subject: [PATCH 086/304] iio: accel: bma400: Use macros for generic event configuration values Add macros and enums for configuration values used in generic event handling for activity and inactivity detection. Replace hard-coded values in activity_event_en() with the new definitions to make the configuration explicit. No functional changes are intended. Signed-off-by: Akshay Jindal Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma400.h | 30 ++++++++++++++++++++++++++++++ drivers/iio/accel/bma400_core.c | 14 +++++++++++--- 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index fcafd1fba57a..12e7bf5fe647 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -113,8 +113,38 @@ #define BMA400_GEN1INT_CONFIG0_REG 0x3f #define BMA400_GEN2INT_CONFIG0_REG 0x4A #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) +#define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2) +#define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4) +#define BMA400_GENINT_CONFIG0_X_EN_MASK BIT(5) +#define BMA400_GENINT_CONFIG0_Y_EN_MASK BIT(6) +#define BMA400_GENINT_CONFIG0_Z_EN_MASK BIT(7) + +enum bma400_accel_data_src { + ACCEL_FILT1 = 0x0, + ACCEL_FILT2 = 0x1, +}; + +enum bma400_ref_updt_mode { + BMA400_REF_MANUAL_UPDT_MODE = 0x0, + BMA400_REF_ONETIME_UPDT_MODE = 0x1, + BMA400_REF_EVERYTIME_UPDT_MODE = 0x2, + BMA400_REF_EVERYTIME_LP_UPDT_MODE = 0x3, +}; #define BMA400_GEN_CONFIG1_OFF 0x01 +#define BMA400_GENINT_CONFIG1_AXES_COMB_MASK BIT(0) +#define BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK BIT(1) + +enum bma400_genintr_acceleval_axescomb { + BMA400_EVAL_X_OR_Y_OR_Z = 0x0, + BMA400_EVAL_X_AND_Y_AND_Z = 0x1, +}; + +enum bma400_detect_criterion { + BMA400_DETECT_INACTIVITY = 0x0, + BMA400_DETECT_ACTIVITY = 0x1, +}; + #define BMA400_GEN_CONFIG2_OFF 0x02 #define BMA400_GEN_CONFIG3_OFF 0x03 #define BMA400_GEN_CONFIG31_OFF 0x04 diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index 2324c4ef645c..46855073ce3a 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -1166,14 +1166,16 @@ static int bma400_activity_event_en(struct bma400_data *data, case IIO_EV_DIR_RISING: reg = BMA400_GEN1INT_CONFIG0_REG; msk = BMA400_INT_CONFIG0_GEN1_MASK; - value = 2; + value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVITY); set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); break; case IIO_EV_DIR_FALLING: reg = BMA400_GEN2INT_CONFIG0_REG; msk = BMA400_INT_CONFIG0_GEN2_MASK; - value = 0; + value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIVITY); set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); break; @@ -1182,7 +1184,13 @@ static int bma400_activity_event_en(struct bma400_data *data, } /* Enabling all axis for interrupt evaluation */ - ret = regmap_write(data->regmap, reg, 0xF8); + ret = regmap_write(data->regmap, reg, + BMA400_GENINT_CONFIG0_X_EN_MASK | + BMA400_GENINT_CONFIG0_Y_EN_MASK | + BMA400_GENINT_CONFIG0_Z_EN_MASK| + FIELD_PREP(BMA400_GENINT_CONFIG0_DATA_SRC_MASK, ACCEL_FILT2)| + FIELD_PREP(BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK, + BMA400_REF_EVERYTIME_UPDT_MODE)); if (ret) return ret; From e03d213848b045aa370af57da559b49b5ab3c966 Mon Sep 17 00:00:00 2001 From: Akshay Jindal Date: Sun, 12 Oct 2025 23:36:10 +0530 Subject: [PATCH 087/304] iio: accel: bma400: Use index-based register addressing and lookup Introduce formula-based macros to compute GEN INTR configuration register addresses from the interrupt number and register index. This reduces the need for 22 explicit register macros to three base definitions. Add a centralized lookup table keyed by IIO event direction and replace get_gen_config_reg() with a helper integrated with this table. Apply these changes across the affected callbacks to ensure consistent access to generic interrupt registers. No functional changes are intended. Signed-off-by: Akshay Jindal Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma400.h | 17 +++-- drivers/iio/accel/bma400_core.c | 131 +++++++++++++++++++------------- 2 files changed, 88 insertions(+), 60 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 12e7bf5fe647..e2832d33862d 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -98,6 +98,11 @@ #define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) #define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) +enum bma400_generic_intr { + BMA400_GEN1_INTR = 0x1, + BMA400_GEN2_INTR = 0x2, +}; + #define BMA400_INT_CONFIG1_REG 0x20 #define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) #define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) @@ -110,8 +115,12 @@ #define BMA400_TWO_BITS_MASK GENMASK(1, 0) /* Generic interrupts register */ -#define BMA400_GEN1INT_CONFIG0_REG 0x3f -#define BMA400_GEN2INT_CONFIG0_REG 0x4A +#define BMA400_GENINT_CONFIG_REG_BASE 0x3f +#define BMA400_NUM_GENINT_CONFIG_REGS 11 +#define BMA400_GENINT_CONFIG_REG(gen_intr, config_idx) \ + (BMA400_GENINT_CONFIG_REG_BASE + \ + (gen_intr - 1) * BMA400_NUM_GENINT_CONFIG_REGS + \ + (config_idx)) #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) #define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2) #define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4) @@ -145,10 +154,6 @@ enum bma400_detect_criterion { BMA400_DETECT_ACTIVITY = 0x1, }; -#define BMA400_GEN_CONFIG2_OFF 0x02 -#define BMA400_GEN_CONFIG3_OFF 0x03 -#define BMA400_GEN_CONFIG31_OFF 0x04 - /* TAP config registers */ #define BMA400_TAP_CONFIG_REG 0x57 #define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index 46855073ce3a..42cd55fa1609 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -121,6 +121,41 @@ struct bma400_data { __be16 duration; }; +struct bma400_genintr_info { + enum bma400_generic_intr genintr; + unsigned int intrmask; + enum iio_event_direction dir; + enum bma400_detect_criterion detect_mode; +}; + +/* Lookup struct for determining GEN1/GEN2 based on dir */ +static const struct bma400_genintr_info bma400_genintrs[] = { + [IIO_EV_DIR_RISING] = { + .genintr = BMA400_GEN1_INTR, + .intrmask = BMA400_INT_CONFIG0_GEN1_MASK, + .dir = IIO_EV_DIR_RISING, + .detect_mode = BMA400_DETECT_ACTIVITY, + }, + [IIO_EV_DIR_FALLING] = { + .genintr = BMA400_GEN2_INTR, + .intrmask = BMA400_INT_CONFIG0_GEN2_MASK, + .dir = IIO_EV_DIR_FALLING, + .detect_mode = BMA400_DETECT_INACTIVITY, + } +}; + +static inline const struct bma400_genintr_info * +get_bma400_genintr_info(enum iio_event_direction dir) +{ + switch (dir) { + case IIO_EV_DIR_RISING: + case IIO_EV_DIR_FALLING: + return &bma400_genintrs[dir]; + default: + return NULL; + }; +} + static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -1159,32 +1194,22 @@ static int bma400_activity_event_en(struct bma400_data *data, enum iio_event_direction dir, int state) { - int ret, reg, msk, value; - int field_value = 0; + int ret; + unsigned int intrmask, regval; + enum bma400_generic_intr genintr; + enum bma400_detect_criterion detect_criterion; + const struct bma400_genintr_info *bma400_genintr; - switch (dir) { - case IIO_EV_DIR_RISING: - reg = BMA400_GEN1INT_CONFIG0_REG; - msk = BMA400_INT_CONFIG0_GEN1_MASK; - value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVITY); - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, - FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); - break; - case IIO_EV_DIR_FALLING: - reg = BMA400_GEN2INT_CONFIG0_REG; - msk = BMA400_INT_CONFIG0_GEN2_MASK; - value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIVITY); - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, - FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); - break; - default: + bma400_genintr = get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; - } + + genintr = bma400_genintr->genintr; + detect_criterion = bma400_genintr->detect_mode; + intrmask = bma400_genintr->intrmask; /* Enabling all axis for interrupt evaluation */ - ret = regmap_write(data->regmap, reg, + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_X_EN_MASK | BMA400_GENINT_CONFIG0_Y_EN_MASK | BMA400_GENINT_CONFIG0_Z_EN_MASK| @@ -1195,31 +1220,32 @@ static int bma400_activity_event_en(struct bma400_data *data, return ret; /* OR combination of all axis for interrupt evaluation */ - ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); + regval = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, detect_criterion); + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), regval); if (ret) return ret; /* Initial value to avoid interrupts while enabling*/ - ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), 0x0A); if (ret) return ret; /* Initial duration value to avoid interrupts while enabling*/ - ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); + ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 4), 0x0F); if (ret) return ret; - ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, - field_value); + regval = state ? intrmask : 0; + ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, regval); if (ret) return ret; - ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, - field_value); + ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask, regval); if (ret) return ret; - set_mask_bits(&data->generic_event_en, msk, field_value); + set_mask_bits(&data->generic_event_en, intrmask, regval); return 0; } @@ -1344,18 +1370,6 @@ static int bma400_write_event_config(struct iio_dev *indio_dev, } } -static int get_gen_config_reg(enum iio_event_direction dir) -{ - switch (dir) { - case IIO_EV_DIR_FALLING: - return BMA400_GEN2INT_CONFIG0_REG; - case IIO_EV_DIR_RISING: - return BMA400_GEN1INT_CONFIG0_REG; - default: - return -EINVAL; - } -} - static int bma400_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, @@ -1364,22 +1378,25 @@ static int bma400_read_event_value(struct iio_dev *indio_dev, int *val, int *val2) { struct bma400_data *data = iio_priv(indio_dev); - int ret, reg, reg_val, raw; + int ret, reg_val, raw; + enum bma400_generic_intr genintr; + const struct bma400_genintr_info *bma400_genintr; if (chan->type != IIO_ACCEL) return -EINVAL; switch (type) { case IIO_EV_TYPE_MAG: - reg = get_gen_config_reg(dir); - if (reg < 0) + bma400_genintr = get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; + genintr = bma400_genintr->genintr; *val2 = 0; switch (info) { case IIO_EV_INFO_VALUE: ret = regmap_read(data->regmap, - reg + BMA400_GEN_CONFIG2_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 2), val); if (ret) return ret; @@ -1387,7 +1404,7 @@ static int bma400_read_event_value(struct iio_dev *indio_dev, case IIO_EV_INFO_PERIOD: mutex_lock(&data->mutex); ret = regmap_bulk_read(data->regmap, - reg + BMA400_GEN_CONFIG3_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 3), &data->duration, sizeof(data->duration)); if (ret) { @@ -1398,7 +1415,9 @@ static int bma400_read_event_value(struct iio_dev *indio_dev, mutex_unlock(&data->mutex); return IIO_VAL_INT; case IIO_EV_INFO_HYSTERESIS: - ret = regmap_read(data->regmap, reg, val); + ret = regmap_read(data->regmap, + BMA400_GENINT_CONFIG_REG(genintr, 0), + val); if (ret) return ret; *val = FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); @@ -1452,16 +1471,19 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, int val, int val2) { struct bma400_data *data = iio_priv(indio_dev); - int reg, ret, raw; + int ret, raw; + enum bma400_generic_intr genintr; + const struct bma400_genintr_info *bma400_genintr; if (chan->type != IIO_ACCEL) return -EINVAL; switch (type) { case IIO_EV_TYPE_MAG: - reg = get_gen_config_reg(dir); - if (reg < 0) + bma400_genintr = get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; + genintr = bma400_genintr->genintr; switch (info) { case IIO_EV_INFO_VALUE: @@ -1469,7 +1491,7 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, return -EINVAL; return regmap_write(data->regmap, - reg + BMA400_GEN_CONFIG2_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 2), val); case IIO_EV_INFO_PERIOD: if (val < 1 || val > 65535) @@ -1478,7 +1500,7 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, mutex_lock(&data->mutex); put_unaligned_be16(val, &data->duration); ret = regmap_bulk_write(data->regmap, - reg + BMA400_GEN_CONFIG3_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 3), &data->duration, sizeof(data->duration)); mutex_unlock(&data->mutex); @@ -1487,7 +1509,8 @@ static int bma400_write_event_value(struct iio_dev *indio_dev, if (val < 0 || val > 3) return -EINVAL; - return regmap_update_bits(data->regmap, reg, + return regmap_update_bits(data->regmap, + BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_HYST_MASK, FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, val)); From 1a7a6c5db6366c29f687796c75ef5bd00e4921a2 Mon Sep 17 00:00:00 2001 From: Akshay Jindal Date: Sun, 12 Oct 2025 23:36:11 +0530 Subject: [PATCH 088/304] iio: accel: bma400: Replace bit shifts with FIELD_PREP() and FIELD_GET() set_* functions involve left shift of param values into respective register fields before writing to register. Similarly get_* functions involve right shift to extract values from the respective bit fields. Replace these explicit shifting statements with standard kernel style macros FIELD_GET() and FIELD_PREP(). Signed-off-by: Akshay Jindal Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma400.h | 3 --- drivers/iio/accel/bma400_core.c | 12 ++++++------ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index e2832d33862d..b5f3cac51610 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -75,7 +75,6 @@ */ #define BMA400_ACC_CONFIG0_REG 0x19 #define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5) -#define BMA400_LP_OSR_SHIFT 5 #define BMA400_ACC_CONFIG1_REG 0x1a #define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0) @@ -86,9 +85,7 @@ #define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ 25 #define BMA400_ACC_CONFIG1_ODR_MIN_HZ 12 #define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4) -#define BMA400_NP_OSR_SHIFT 4 #define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6) -#define BMA400_ACC_RANGE_SHIFT 6 #define BMA400_ACC_CONFIG2_REG 0x1b diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index 42cd55fa1609..cec59d409531 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -627,7 +627,7 @@ static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) return ret; } - osr = (val & BMA400_ACC_CONFIG0_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; + osr = FIELD_GET(BMA400_ACC_CONFIG0_LP_OSR_MASK, val); data->oversampling_ratio = osr; return 0; @@ -638,7 +638,7 @@ static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) return ret; } - osr = (val & BMA400_ACC_CONFIG1_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; + osr = FIELD_GET(BMA400_ACC_CONFIG1_NP_OSR_MASK, val); data->oversampling_ratio = osr; return 0; @@ -673,7 +673,7 @@ static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, (acc_config & ~BMA400_ACC_CONFIG0_LP_OSR_MASK) | - (val << BMA400_LP_OSR_SHIFT)); + FIELD_PREP(BMA400_ACC_CONFIG0_LP_OSR_MASK, val)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); return ret; @@ -689,7 +689,7 @@ static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, (acc_config & ~BMA400_ACC_CONFIG1_NP_OSR_MASK) | - (val << BMA400_NP_OSR_SHIFT)); + FIELD_PREP(BMA400_ACC_CONFIG1_NP_OSR_MASK, val)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); return ret; @@ -730,7 +730,7 @@ static int bma400_get_accel_scale(struct bma400_data *data) if (ret) return ret; - raw_scale = (val & BMA400_ACC_CONFIG1_ACC_RANGE_MASK) >> BMA400_ACC_RANGE_SHIFT; + raw_scale = FIELD_GET(BMA400_ACC_CONFIG1_ACC_RANGE_MASK, val); if (raw_scale > BMA400_TWO_BITS_MASK) return -EINVAL; @@ -755,7 +755,7 @@ static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val) ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, (acc_config & ~BMA400_ACC_CONFIG1_ACC_RANGE_MASK) | - (raw << BMA400_ACC_RANGE_SHIFT)); + FIELD_PREP(BMA400_ACC_CONFIG1_ACC_RANGE_MASK, raw)); if (ret) return ret; From 31f3af6283a0810c1a51d56eaf3c5936df718f84 Mon Sep 17 00:00:00 2001 From: Akshay Jindal Date: Sun, 12 Oct 2025 23:36:12 +0530 Subject: [PATCH 089/304] iio: accel: bma400: Rename activity_event_en() to generic_event_en() The function activity_event_en() configures the generic interrupts GEN1 and GEN2, which are used for activity and inactivity detection as per the datasheet. The existing name is misleading, since the device also provides activity change and activity recognition interrupts. Activity change interrupt is not supported yet whereas Activity recognition interrupt is configured in a different function. Rename activity_event_en() to generic_event_en() to better reflect its actual purpose. No functional changes intended. Signed-off-by: Akshay Jindal Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma400_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index cec59d409531..840c4156ba60 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -1190,9 +1190,9 @@ static int bma400_steps_event_enable(struct bma400_data *data, int state) return 0; } -static int bma400_activity_event_en(struct bma400_data *data, - enum iio_event_direction dir, - int state) +static int bma400_generic_event_en(struct bma400_data *data, + enum iio_event_direction dir, + int state) { int ret; unsigned int intrmask, regval; @@ -1337,7 +1337,7 @@ static int bma400_write_event_config(struct iio_dev *indio_dev, switch (type) { case IIO_EV_TYPE_MAG: mutex_lock(&data->mutex); - ret = bma400_activity_event_en(data, dir, state); + ret = bma400_generic_event_en(data, dir, state); mutex_unlock(&data->mutex); return ret; case IIO_EV_TYPE_GESTURE: From 6ea3b542646f45a4b279228989348a8dc229f53c Mon Sep 17 00:00:00 2001 From: Akshay Jindal Date: Sun, 12 Oct 2025 23:36:13 +0530 Subject: [PATCH 090/304] iio: accel: bma400: Add detail to comments in GEN INTR configuration Append additional information to existing comments in the generic interrupt configuration code to provide more context. Signed-off-by: Akshay Jindal Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma400_core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index 840c4156ba60..05f72707f830 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -1208,7 +1208,10 @@ static int bma400_generic_event_en(struct bma400_data *data, detect_criterion = bma400_genintr->detect_mode; intrmask = bma400_genintr->intrmask; - /* Enabling all axis for interrupt evaluation */ + /* + * Enabling all axis for interrupt evaluation + * Acc_filt2 is recommended as data source in datasheet (Section 4.7) + */ ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_X_EN_MASK | BMA400_GENINT_CONFIG0_Y_EN_MASK | @@ -1226,7 +1229,10 @@ static int bma400_generic_event_en(struct bma400_data *data, if (ret) return ret; - /* Initial value to avoid interrupts while enabling*/ + /* + * Initial value to avoid interrupts while enabling + * Value is in units of 8mg/lsb, i.e. effective val is val * 8mg/lsb + */ ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), 0x0A); if (ret) return ret; From c9fb952360d0c78bbe98239bd6b702f05c2dbb31 Mon Sep 17 00:00:00 2001 From: Pei Xiao Date: Tue, 14 Oct 2025 17:12:50 +0800 Subject: [PATCH 091/304] iio: adc: ti_am335x_adc: Limit step_avg to valid range for gcc complains FIELD_PREP() checks that a value fits into the available bitfield, add a check for step_avg to fix gcc complains. which gcc complains about: drivers/iio/adc/ti_am335x_adc.c: In function 'tiadc_step_config': include/linux/compiler_types.h:572:38: error: call to '__compiletime_assert_491' declared with attribute error: FIELD_PREP: value too large for the field include/linux/mfd/ti_am335x_tscadc.h:58:29: note: in expansion of macro 'FIELD_PREP' #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val)) ^~~~~~~~~~ drivers/iio/adc/ti_am335x_adc.c:127:17: note: in expansion of macro 'STEPCONFIG_AVG' stepconfig = STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202510102117.Jqxrw1vF-lkp@intel.com/ Signed-off-by: Pei Xiao Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ti_am335x_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c index 99f274adc870..a1a28584de93 100644 --- a/drivers/iio/adc/ti_am335x_adc.c +++ b/drivers/iio/adc/ti_am335x_adc.c @@ -123,7 +123,7 @@ static void tiadc_step_config(struct iio_dev *indio_dev) chan = adc_dev->channel_line[i]; - if (adc_dev->step_avg[i]) + if (adc_dev->step_avg[i] && adc_dev->step_avg[i] <= STEPCONFIG_AVG_16) stepconfig = STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | STEPCONFIG_FIFO1; else From d8cfb1c6494d0dc07cc960dd6511dbda524698d0 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Tue, 14 Oct 2025 19:42:57 +0300 Subject: [PATCH 092/304] iio: accel: bma220: white space cleanup Clean up white space inconsistencies from the last patch series as requested by Jonathan. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_core.c | 2 +- drivers/iio/accel/bma220_spi.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 2531d6a54ff0..871342d21456 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -128,7 +128,7 @@ enum bma220_axis { }; static const int bma220_scale_table[][2] = { - {0, 623000}, {1, 248000}, {2, 491000}, {4, 983000}, + { 0, 623000 }, { 1, 248000 }, { 2, 491000 }, { 4, 983000 }, }; struct bma220_data { diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c index 7aced4017373..383ee8a135ee 100644 --- a/drivers/iio/accel/bma220_spi.c +++ b/drivers/iio/accel/bma220_spi.c @@ -26,12 +26,12 @@ static int bma220_spi_probe(struct spi_device *spi) } static const struct spi_device_id bma220_spi_id[] = { - {"bma220", 0}, + { "bma220", 0 }, { } }; static const struct acpi_device_id bma220_acpi_id[] = { - {"BMA0220", 0}, + { "BMA0220", 0 }, { } }; MODULE_DEVICE_TABLE(spi, bma220_spi_id); From 003930040784b30902870a945ed9503f9cdc2327 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Tue, 14 Oct 2025 19:42:58 +0300 Subject: [PATCH 093/304] iio: accel: bma220: remove useless include Remove errno.h include from bma220_i2c.c since error codes are generated within bma220_core.c instead. Signed-off-by: Petre Rodan Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220_i2c.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iio/accel/bma220_i2c.c b/drivers/iio/accel/bma220_i2c.c index 5dc7c38f53b3..2b85d4921768 100644 --- a/drivers/iio/accel/bma220_i2c.c +++ b/drivers/iio/accel/bma220_i2c.c @@ -8,7 +8,6 @@ * I2C address is either 0x0b or 0x0a depending on CSB (pin 10) */ -#include #include #include #include From c6d702f2b77194b62fb2098c63bb7f2a87da142d Mon Sep 17 00:00:00 2001 From: Francesco Lavra Date: Fri, 17 Oct 2025 18:42:54 +0200 Subject: [PATCH 094/304] iio: imu: st_lsm6dsx: Fix measurement unit for odr struct member The `odr` field in struct st_lsm6dsx_sensor contains a data rate value expressed in mHz, not in Hz. Fixes: f8710f0357bc3 ("iio: imu: st_lsm6dsx: express odr in mHZ") Signed-off-by: Francesco Lavra Acked-by: Lorenzo Bianconi Signed-off-by: Jonathan Cameron --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index c225b246c8a5..bd366c6e282a 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -365,7 +365,7 @@ enum st_lsm6dsx_fifo_mode { * @id: Sensor identifier. * @hw: Pointer to instance of struct st_lsm6dsx_hw. * @gain: Configured sensor sensitivity. - * @odr: Output data rate of the sensor [Hz]. + * @odr: Output data rate of the sensor [mHz]. * @samples_to_discard: Number of samples to discard for filters settling time. * @watermark: Sensor watermark level. * @decimator: Sensor decimation factor. From 6b648a36c200dfd3e776e657a4c8a8ce63fb52d3 Mon Sep 17 00:00:00 2001 From: Francesco Lavra Date: Fri, 17 Oct 2025 18:42:55 +0200 Subject: [PATCH 095/304] iio: imu: st_lsm6dsx: Decouple sensor ODR from FIFO batch data rate The rate at which accelerometer or gyroscope sensor samples are fed to the hardware FIFO (batch data rate, or BDR) does not have to coincide with the sensor sampling frequency (output data rate, or ODR); the only requirement is for the BDR to not be greater than the ODR. Having a BDR lower than the ODR is useful in cases where an application requires a high sampling rate for accurate detection of motion events (e.g. wakeup events), but wants to read sensor sample values from the hardware FIFO at a lower data rate (e.g. to minimize the amount of I2C or SPI traffic and the rate of periodic interrupts). To support the above use case, add a sampling_frequency sysfs attribute to the buffer directory of st_lsm6dsx IIO devices, which controls the BDR for a given sensor independently from the "main" sampling_frequency attribute (which controls the ODR); introduce a new `hwfifo_odr_mHz` field in struct st_lsm6dsx_sensor to keep track of the current BDR value, and use this field instead of the `odr` field in the code that deals with the FIFO data rate. In the sensor hub driver, make the hwfifo_odr_mHz value always mirror the odr value, since there is no separate configuration setting to control the BDR for data produced by the sensor hub functionality. For backwards compatibility, set the buffer frequency equal to the main frequency whenever the latter is updated via sysfs; if userspace wants a different buffer frequency, it has to write to the relevant sysfs attribute after any writes to the main frequency attribute. Signed-off-by: Francesco Lavra Acked-by: Lorenzo Bianconi Signed-off-by: Jonathan Cameron --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 2 + .../iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 71 ++++++++++++++++--- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 7 +- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c | 2 + 4 files changed, 72 insertions(+), 10 deletions(-) diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index bd366c6e282a..3cd520bdec46 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -366,6 +366,7 @@ enum st_lsm6dsx_fifo_mode { * @hw: Pointer to instance of struct st_lsm6dsx_hw. * @gain: Configured sensor sensitivity. * @odr: Output data rate of the sensor [mHz]. + * hwfifo_odr_mHz: Batch data rate for hardware FIFO [mHz] * @samples_to_discard: Number of samples to discard for filters settling time. * @watermark: Sensor watermark level. * @decimator: Sensor decimation factor. @@ -380,6 +381,7 @@ struct st_lsm6dsx_sensor { u32 gain; u32 odr; + u32 hwfifo_odr_mHz; u16 samples_to_discard; u16 watermark; diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c index 8a9d2593576a..55d877745575 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include @@ -105,7 +106,7 @@ static int st_lsm6dsx_get_decimator_val(struct st_lsm6dsx_sensor *sensor, u32 max_odr) { const int max_size = ARRAY_SIZE(st_lsm6dsx_decimator_table); - u32 decimator = max_odr / sensor->odr; + u32 decimator = max_odr / sensor->hwfifo_odr_mHz; int i; if (decimator > 1) @@ -136,14 +137,14 @@ static void st_lsm6dsx_get_max_min_odr(struct st_lsm6dsx_hw *hw, if (!(hw->enable_mask & BIT(sensor->id))) continue; - *max_odr = max_t(u32, *max_odr, sensor->odr); - *min_odr = min_t(u32, *min_odr, sensor->odr); + *max_odr = max(*max_odr, sensor->hwfifo_odr_mHz); + *min_odr = min(*min_odr, sensor->hwfifo_odr_mHz); } } static u8 st_lsm6dsx_get_sip(struct st_lsm6dsx_sensor *sensor, u32 min_odr) { - u8 sip = sensor->odr / min_odr; + u8 sip = sensor->hwfifo_odr_mHz / min_odr; return sip > 1 ? round_down(sip, 2) : sip; } @@ -231,7 +232,7 @@ static int st_lsm6dsx_set_fifo_odr(struct st_lsm6dsx_sensor *sensor, if (enable) { int err; - err = st_lsm6dsx_check_odr(sensor, sensor->odr, + err = st_lsm6dsx_check_odr(sensor, sensor->hwfifo_odr_mHz, &data); if (err < 0) return err; @@ -713,7 +714,7 @@ st_lsm6dsx_update_samples_to_discard(struct st_lsm6dsx_sensor *sensor) data = &hw->settings->samples_to_discard[sensor->id]; for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) { - if (data->val[i].milli_hz == sensor->odr) { + if (data->val[i].milli_hz == sensor->hwfifo_odr_mHz) { sensor->samples_to_discard = data->val[i].samples; return; } @@ -799,6 +800,59 @@ static const struct iio_buffer_setup_ops st_lsm6dsx_buffer_ops = { .postdisable = st_lsm6dsx_buffer_postdisable, }; +static ssize_t st_lsm6dsx_hwfifo_odr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_lsm6dsx_sensor *sensor = iio_priv(dev_to_iio_dev(dev)); + + return sysfs_emit(buf, "%d.%03d\n", sensor->hwfifo_odr_mHz / 1000, + sensor->hwfifo_odr_mHz % 1000); +} + +static ssize_t st_lsm6dsx_hwfifo_odr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *iio_dev = dev_to_iio_dev(dev); + struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); + int integer, milli; + int ret; + u32 hwfifo_odr; + u8 data; + + if (!iio_device_claim_direct(iio_dev)) + return -EBUSY; + + ret = iio_str_to_fixpoint(buf, 100, &integer, &milli); + if (ret) + goto out; + + hwfifo_odr = integer * 1000 + milli; + ret = st_lsm6dsx_check_odr(sensor, hwfifo_odr, &data); + if (ret < 0) + goto out; + + hwfifo_odr = ret; + + /* the batch data rate must not exceed the sensor output data rate */ + if (hwfifo_odr <= sensor->odr) + sensor->hwfifo_odr_mHz = hwfifo_odr; + else + ret = -EINVAL; + +out: + iio_device_release_direct(iio_dev); + + return ret < 0 ? ret : len; +} + +static IIO_DEV_ATTR_SAMP_FREQ(0664, st_lsm6dsx_hwfifo_odr_show, st_lsm6dsx_hwfifo_odr_store); + +static const struct iio_dev_attr *st_lsm6dsx_buffer_attrs[] = { + &iio_dev_attr_sampling_frequency, + NULL +}; + int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw) { int i, ret; @@ -807,8 +861,9 @@ int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw) if (!hw->iio_devs[i]) continue; - ret = devm_iio_kfifo_buffer_setup(hw->dev, hw->iio_devs[i], - &st_lsm6dsx_buffer_ops); + ret = devm_iio_kfifo_buffer_setup_ext(hw->dev, hw->iio_devs[i], + &st_lsm6dsx_buffer_ops, + st_lsm6dsx_buffer_attrs); if (ret) return ret; } diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c index d8cb4b0218d5..88939625ace4 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -1847,10 +1847,12 @@ static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, val = val * 1000 + val2 / 1000; val = st_lsm6dsx_check_odr(sensor, val, &data); - if (val < 0) + if (val < 0) { err = val; - else + } else { sensor->odr = val; + sensor->hwfifo_odr_mHz = val; + } break; } default: @@ -2384,6 +2386,7 @@ static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, sensor->id = id; sensor->hw = hw; sensor->odr = hw->settings->odr_table[id].odr_avl[0].milli_hz; + sensor->hwfifo_odr_mHz = sensor->odr; sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; sensor->watermark = 1; diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c index 3c5e65dc0f97..d6a1eeb151ca 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c @@ -640,6 +640,7 @@ __st_lsm6dsx_shub_write_raw(struct iio_dev *iio_dev, sensor->ext_info.slv_odr = val; sensor->odr = odr; + sensor->hwfifo_odr_mHz = odr; return 0; } case IIO_CHAN_INFO_SCALE: @@ -746,6 +747,7 @@ st_lsm6dsx_shub_alloc_iiodev(struct st_lsm6dsx_hw *hw, sensor->id = id; sensor->hw = hw; sensor->odr = hw->settings->odr_table[ref_id].odr_avl[0].milli_hz; + sensor->hwfifo_odr_mHz = sensor->odr; sensor->ext_info.slv_odr = info->odr_table.odr_avl[0].milli_hz; sensor->gain = info->fs_table.fs_avl[0].gain; sensor->ext_info.settings = info; From 192e5bbf0a8d7a629e6f9fa9e2fae54c3268bb7f Mon Sep 17 00:00:00 2001 From: Marilene Andrade Garcia Date: Wed, 15 Oct 2025 02:11:08 -0300 Subject: [PATCH 096/304] dt-bindings: iio: adc: add max14001 Add device-tree documentation for MAX14001/MAX14002 ADCs. The MAX14001/MAX14002 are isolated, single-channel analog-to-digital converters with programmable voltage comparators and inrush current control optimized for configurable binary input applications. They share the same features, but in the MAX14001 the inrush trigger threshold, current magnitude, and current duration are all programmable, whereas in the MAX14002 these parameters are fixed. Co-developed-by: Kim Seer Paller Signed-off-by: Kim Seer Paller Signed-off-by: Marilene Andrade Garcia Reviewed-by: Conor Dooley Reviewed-by: Marcelo Schmitt Signed-off-by: Jonathan Cameron --- .../bindings/iio/adc/adi,max14001.yaml | 89 +++++++++++++++++++ MAINTAINERS | 8 ++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,max14001.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,max14001.yaml b/Documentation/devicetree/bindings/iio/adc/adi,max14001.yaml new file mode 100644 index 000000000000..a2dc59c9dcd8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,max14001.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023-2025 Analog Devices Inc. +# Copyright 2023 Kim Seer Paller +# Copyright 2025 Marilene Andrade Garcia +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,max14001.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX14001-MAX14002 ADC + +maintainers: + - Kim Seer Paller + - Marilene Andrade Garcia + +description: | + Single channel 10 bit ADC with SPI interface. + Datasheet can be found here + https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: adi,max14002 + - items: + - const: adi,max14001 + - const: adi,max14002 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 5000000 + + vdd-supply: + description: + Isolated DC-DC power supply input voltage. + + vddl-supply: + description: + Logic power supply. + + refin-supply: + description: + ADC voltage reference supply. + + interrupts: + minItems: 1 + items: + - description: | + cout: comparator output signal that asserts high on the COUT pin + when ADC readings exceed the upper threshold and low when readings + fall below the lower threshold. + - description: | + fault: when fault reporting is enabled, the FAULT pin is asserted + low whenever one of the monitored fault conditions occurs. + + interrupt-names: + minItems: 1 + items: + - const: cout + - const: fault + +required: + - compatible + - reg + - vdd-supply + - vddl-supply + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,max14001", "adi,max14002"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-lsb-first; + vdd-supply = <&vdd>; + vddl-supply = <&vddl>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 8082081ea742..f584196d3260 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15174,6 +15174,14 @@ S: Orphan F: drivers/video/fbdev/matrox/matroxfb_* F: include/uapi/linux/matroxfb.h +MAX14001/MAX14002 IIO ADC DRIVER +M: Kim Seer Paller +M: Marilene Andrade Garcia +L: linux-iio@vger.kernel.org +S: Maintained +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,max14001.yaml + MAX15301 DRIVER M: Daniel Nilsson L: linux-hwmon@vger.kernel.org From 59795109fa67d2bee7c8c2847a487d4dddb428c1 Mon Sep 17 00:00:00 2001 From: Marilene Andrade Garcia Date: Wed, 15 Oct 2025 02:12:08 -0300 Subject: [PATCH 097/304] iio: adc: max14001: New driver The MAX14001/MAX14002 is configurable, isolated 10-bit ADCs for multi-range binary inputs. In addition to ADC readings, the MAX14001/MAX14002 offers more features, like a binary comparator, a filtered reading that can provide the average of the last 2, 4, or 8 ADC readings, and an inrush comparator that triggers the inrush current. There is also a fault feature that can diagnose seven possible fault conditions. And an option to select an external or internal ADC voltage reference. MAX14001/MAX14002 features implemented so far: - Raw ADC reading. - MV fault disable. - Selection of external or internal ADC voltage reference, depending on whether it is declared in the device tree. Co-developed-by: Kim Seer Paller Signed-off-by: Kim Seer Paller Signed-off-by: Marilene Andrade Garcia Tested-by: Marcelo Schmitt Reviewed-by: Marcelo Schmitt Signed-off-by: Jonathan Cameron --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/max14001.c | 391 +++++++++++++++++++++++++++++++++++++ 4 files changed, 403 insertions(+) create mode 100644 drivers/iio/adc/max14001.c diff --git a/MAINTAINERS b/MAINTAINERS index f584196d3260..940889b158eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15181,6 +15181,7 @@ L: linux-iio@vger.kernel.org S: Maintained W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,max14001.yaml +F: drivers/iio/adc/max14001.c MAX15301 DRIVER M: Daniel Nilsson diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index b0580fcefef5..31335af6b2f1 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1020,6 +1020,16 @@ config MAX1363 To compile this driver as a module, choose M here: the module will be called max1363. +config MAX14001 + tristate "Analog Devices MAX14001/MAX14002 ADC driver" + depends on SPI + help + Say yes here to build support for Analog Devices MAX14001/MAX14002 + Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs. + + To compile this driver as a module, choose M here: the module will be + called max14001. + config MAX34408 tristate "Maxim max34408/max344089 ADC driver" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index ed647a734c51..e5349b01e4d9 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MAX11205) += max11205.o obj-$(CONFIG_MAX11410) += max11410.o obj-$(CONFIG_MAX1241) += max1241.o obj-$(CONFIG_MAX1363) += max1363.o +obj-$(CONFIG_MAX14001) += max14001.o obj-$(CONFIG_MAX34408) += max34408.o obj-$(CONFIG_MAX77541_ADC) += max77541-adc.o obj-$(CONFIG_MAX9611) += max9611.o diff --git a/drivers/iio/adc/max14001.c b/drivers/iio/adc/max14001.c new file mode 100644 index 000000000000..90ad4cb5868d --- /dev/null +++ b/drivers/iio/adc/max14001.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Analog Devices MAX14001/MAX14002 ADC driver + * + * Copyright (C) 2023-2025 Analog Devices Inc. + * Copyright (C) 2023 Kim Seer Paller + * Copyright (c) 2025 Marilene Andrade Garcia + * + * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* MAX14001 Registers Address */ +#define MAX14001_REG_ADC 0x00 +#define MAX14001_REG_FADC 0x01 +#define MAX14001_REG_FLAGS 0x02 +#define MAX14001_REG_FLTEN 0x03 +#define MAX14001_REG_THL 0x04 +#define MAX14001_REG_THU 0x05 +#define MAX14001_REG_INRR 0x06 +#define MAX14001_REG_INRT 0x07 +#define MAX14001_REG_INRP 0x08 +#define MAX14001_REG_CFG 0x09 +#define MAX14001_REG_ENBL 0x0A +#define MAX14001_REG_ACT 0x0B +#define MAX14001_REG_WEN 0x0C + +#define MAX14001_REG_VERIFICATION(x) ((x) + 0x10) + +#define MAX14001_REG_CFG_BIT_EXRF BIT(5) + +#define MAX14001_REG_WEN_VALUE_WRITE 0x294 + +#define MAX14001_MASK_ADDR GENMASK(15, 11) +#define MAX14001_MASK_WR BIT(10) +#define MAX14001_MASK_DATA GENMASK(9, 0) + +struct max14001_state { + const struct max14001_chip_info *chip_info; + struct spi_device *spi; + struct regmap *regmap; + int vref_mV; + bool spi_hw_has_lsb_first; + + /* + * The following buffers will be bit-reversed during device + * communication, because the device transmits and receives data + * LSB-first. + * DMA (thus cache coherency maintenance) requires the transfer + * buffers to live in their own cache lines. + */ + union { + __be16 be; + __le16 le; + } spi_tx_buffer __aligned(IIO_DMA_MINALIGN); + + union { + __be16 be; + __le16 le; + } spi_rx_buffer; +}; + +struct max14001_chip_info { + const char *name; +}; + +static int max14001_read(void *context, unsigned int reg, unsigned int *val) +{ + struct max14001_state *st = context; + struct spi_transfer xfers[] = { + { + .tx_buf = &st->spi_tx_buffer, + .len = sizeof(st->spi_tx_buffer), + .cs_change = 1, + }, { + .rx_buf = &st->spi_rx_buffer, + .len = sizeof(st->spi_rx_buffer), + }, + }; + int ret; + unsigned int addr, data; + + /* + * Prepare SPI transmit buffer 16 bit-value and reverse bit order + * to align with the LSB-first input on SDI port in order to meet + * the device communication requirements. If the controller supports + * SPI_LSB_FIRST, this step will be handled by the SPI controller. + */ + addr = FIELD_PREP(MAX14001_MASK_ADDR, reg); + + if (st->spi_hw_has_lsb_first) + st->spi_tx_buffer.le = cpu_to_le16(addr); + else + st->spi_tx_buffer.be = cpu_to_be16(bitrev16(addr)); + + ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret) + return ret; + + /* + * Convert received 16-bit value to cpu-endian format and reverse + * bit order. If the controller supports SPI_LSB_FIRST, this step + * will be handled by the SPI controller. + */ + if (st->spi_hw_has_lsb_first) + data = le16_to_cpu(st->spi_rx_buffer.le); + else + data = bitrev16(be16_to_cpu(st->spi_rx_buffer.be)); + + *val = FIELD_GET(MAX14001_MASK_DATA, data); + + return 0; +} + +static int max14001_write(struct max14001_state *st, unsigned int reg, unsigned int val) +{ + unsigned int addr; + + /* + * Prepare SPI transmit buffer 16 bit-value and reverse bit order + * to align with the LSB-first input on SDI port in order to meet + * the device communication requirements. If the controller supports + * SPI_LSB_FIRST, this step will be handled by the SPI controller. + */ + addr = FIELD_PREP(MAX14001_MASK_ADDR, reg) | + FIELD_PREP(MAX14001_MASK_WR, 1) | + FIELD_PREP(MAX14001_MASK_DATA, val); + + if (st->spi_hw_has_lsb_first) + st->spi_tx_buffer.le = cpu_to_le16(addr); + else + st->spi_tx_buffer.be = cpu_to_be16(bitrev16(addr)); + + return spi_write(st->spi, &st->spi_tx_buffer, sizeof(st->spi_tx_buffer)); +} + +static int max14001_write_single_reg(void *context, unsigned int reg, unsigned int val) +{ + struct max14001_state *st = context; + int ret; + + /* Enable writing to the SPI register. */ + ret = max14001_write(st, MAX14001_REG_WEN, MAX14001_REG_WEN_VALUE_WRITE); + if (ret) + return ret; + + /* Writing data into SPI register. */ + ret = max14001_write(st, reg, val); + if (ret) + return ret; + + /* Disable writing to the SPI register. */ + return max14001_write(st, MAX14001_REG_WEN, 0); +} + +static int max14001_write_verification_reg(struct max14001_state *st, unsigned int reg) +{ + unsigned int val; + int ret; + + ret = regmap_read(st->regmap, reg, &val); + if (ret) + return ret; + + return max14001_write(st, MAX14001_REG_VERIFICATION(reg), val); +} + +static int max14001_disable_mv_fault(struct max14001_state *st) +{ + unsigned int reg; + int ret; + + /* Enable writing to the SPI registers. */ + ret = max14001_write(st, MAX14001_REG_WEN, MAX14001_REG_WEN_VALUE_WRITE); + if (ret) + return ret; + + /* + * Reads all registers and writes the values to their appropriate + * verification registers to clear the Memory Validation fault. + */ + for (reg = MAX14001_REG_FLTEN; reg <= MAX14001_REG_ENBL; reg++) { + ret = max14001_write_verification_reg(st, reg); + if (ret) + return ret; + } + + /* Disable writing to the SPI registers. */ + return max14001_write(st, MAX14001_REG_WEN, 0); +} + +static int max14001_debugfs_reg_access(struct iio_dev *indio_dev, + unsigned int reg, unsigned int writeval, + unsigned int *readval) +{ + struct max14001_state *st = iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int max14001_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct max14001_state *st = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = regmap_read(st->regmap, MAX14001_REG_ADC, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val = st->vref_mV; + *val2 = 10; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct regmap_range max14001_regmap_rd_range[] = { + regmap_reg_range(MAX14001_REG_ADC, MAX14001_REG_ENBL), + regmap_reg_range(MAX14001_REG_WEN, MAX14001_REG_WEN), + regmap_reg_range(MAX14001_REG_VERIFICATION(MAX14001_REG_FLTEN), + MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL)), +}; + +static const struct regmap_access_table max14001_regmap_rd_table = { + .yes_ranges = max14001_regmap_rd_range, + .n_yes_ranges = ARRAY_SIZE(max14001_regmap_rd_range), +}; + +static const struct regmap_range max14001_regmap_wr_range[] = { + regmap_reg_range(MAX14001_REG_FLTEN, MAX14001_REG_WEN), + regmap_reg_range(MAX14001_REG_VERIFICATION(MAX14001_REG_FLTEN), + MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL)), +}; + +static const struct regmap_access_table max14001_regmap_wr_table = { + .yes_ranges = max14001_regmap_wr_range, + .n_yes_ranges = ARRAY_SIZE(max14001_regmap_wr_range), +}; + +static const struct regmap_config max14001_regmap_config = { + .reg_read = max14001_read, + .reg_write = max14001_write_single_reg, + .max_register = MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL), + .rd_table = &max14001_regmap_rd_table, + .wr_table = &max14001_regmap_wr_table, +}; + +static const struct iio_info max14001_info = { + .read_raw = max14001_read_raw, + .debugfs_reg_access = max14001_debugfs_reg_access, +}; + +static const struct iio_chan_spec max14001_channel[] = { + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, +}; + +static int max14001_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct iio_dev *indio_dev; + struct max14001_state *st; + int ret; + bool use_ext_vrefin = false; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + st->spi = spi; + st->spi_hw_has_lsb_first = spi->mode & SPI_LSB_FIRST; + st->chip_info = spi_get_device_match_data(spi); + if (!st->chip_info) + return -EINVAL; + + indio_dev->name = st->chip_info->name; + indio_dev->info = &max14001_info; + indio_dev->channels = max14001_channel; + indio_dev->num_channels = ARRAY_SIZE(max14001_channel); + indio_dev->modes = INDIO_DIRECT_MODE; + + st->regmap = devm_regmap_init(dev, NULL, st, &max14001_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n"); + + ret = devm_regulator_get_enable(dev, "vdd"); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable Vdd supply\n"); + + ret = devm_regulator_get_enable(dev, "vddl"); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable Vddl supply\n"); + + ret = devm_regulator_get_enable_read_voltage(dev, "refin"); + if (ret < 0 && ret != -ENODEV) + return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n"); + + if (ret == -ENODEV) + ret = 1250000; + else + use_ext_vrefin = true; + st->vref_mV = ret / (MICRO / MILLI); + + if (use_ext_vrefin) { + /* + * Configure the MAX14001/MAX14002 to use an external voltage + * reference source by setting the bit 5 of the configuration register. + */ + ret = regmap_set_bits(st->regmap, MAX14001_REG_CFG, + MAX14001_REG_CFG_BIT_EXRF); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set External REFIN in Configuration Register\n"); + } + + ret = max14001_disable_mv_fault(st); + if (ret) + return dev_err_probe(dev, ret, "Failed to disable MV Fault\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static struct max14001_chip_info max14001_chip_info = { + .name = "max14001", +}; + +static struct max14001_chip_info max14002_chip_info = { + .name = "max14002", +}; + +static const struct spi_device_id max14001_id_table[] = { + { "max14001", (kernel_ulong_t)&max14001_chip_info }, + { "max14002", (kernel_ulong_t)&max14002_chip_info }, + { } +}; + +static const struct of_device_id max14001_of_match[] = { + { .compatible = "adi,max14001", .data = &max14001_chip_info }, + { .compatible = "adi,max14002", .data = &max14002_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, max14001_of_match); + +static struct spi_driver max14001_driver = { + .driver = { + .name = "max14001", + .of_match_table = max14001_of_match, + }, + .probe = max14001_probe, + .id_table = max14001_id_table, +}; +module_spi_driver(max14001_driver); + +MODULE_AUTHOR("Kim Seer Paller "); +MODULE_AUTHOR("Marilene Andrade Garcia "); +MODULE_DESCRIPTION("Analog Devices MAX14001/MAX14002 ADCs driver"); +MODULE_LICENSE("GPL"); From c5ebcc80fcf7d2c6ed917371f024d2da5bce9128 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 17 Oct 2025 00:07:27 -0700 Subject: [PATCH 098/304] iio: adc: qcom-vadc-common: fix vadc_scale_fn_type kernel-doc Fix multiple warnings in enum vadc_scale_fn_type by adding a leading '@' to the kernel-doc descriptions. Fixed 14 warnings in this one enum, such as: Warning: include/linux/iio/adc/qcom-vadc-common.h:123 Enum value 'SCALE_DEFAULT' not described in enum 'vadc_scale_fn_type' Warning: ../include/linux/iio/adc/qcom-vadc-common.h:123 Enum value 'SCALE_THERM_100K_PULLUP' not described in enum 'vadc_scale_fn_type' Warning: ../include/linux/iio/adc/qcom-vadc-common.h:123 Enum value 'SCALE_PMIC_THERM' not described in enum 'vadc_scale_fn_type' Also prevent the warning on SCALE_HW_CALIB_INVALID by marking it "private:" so that kernel-doc notation is not needed for it. This leaves only one warning here, which I don't know the appropriate description of: qcom-vadc-common.h:125: warning: Enum value 'SCALE_HW_CALIB_PMIC_THERM_PM7' not described in enum 'vadc_scale_fn_type' Signed-off-by: Randy Dunlap Signed-off-by: Jonathan Cameron --- include/linux/iio/adc/qcom-vadc-common.h | 27 ++++++++++++------------ 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/include/linux/iio/adc/qcom-vadc-common.h b/include/linux/iio/adc/qcom-vadc-common.h index aa21b032e861..3bf4c49726a7 100644 --- a/include/linux/iio/adc/qcom-vadc-common.h +++ b/include/linux/iio/adc/qcom-vadc-common.h @@ -83,27 +83,27 @@ struct vadc_linear_graph { /** * enum vadc_scale_fn_type - Scaling function to convert ADC code to * physical scaled units for the channel. - * SCALE_DEFAULT: Default scaling to convert raw adc code to voltage (uV). - * SCALE_THERM_100K_PULLUP: Returns temperature in millidegC. + * @SCALE_DEFAULT: Default scaling to convert raw adc code to voltage (uV). + * @SCALE_THERM_100K_PULLUP: Returns temperature in millidegC. * Uses a mapping table with 100K pullup. - * SCALE_PMIC_THERM: Returns result in milli degree's Centigrade. - * SCALE_XOTHERM: Returns XO thermistor voltage in millidegC. - * SCALE_PMI_CHG_TEMP: Conversion for PMI CHG temp - * SCALE_HW_CALIB_DEFAULT: Default scaling to convert raw adc code to + * @SCALE_PMIC_THERM: Returns result in milli degree's Centigrade. + * @SCALE_XOTHERM: Returns XO thermistor voltage in millidegC. + * @SCALE_PMI_CHG_TEMP: Conversion for PMI CHG temp + * @SCALE_HW_CALIB_DEFAULT: Default scaling to convert raw adc code to * voltage (uV) with hardware applied offset/slope values to adc code. - * SCALE_HW_CALIB_THERM_100K_PULLUP: Returns temperature in millidegC using + * @SCALE_HW_CALIB_THERM_100K_PULLUP: Returns temperature in millidegC using * lookup table. The hardware applies offset/slope to adc code. - * SCALE_HW_CALIB_XOTHERM: Returns XO thermistor voltage in millidegC using + * @SCALE_HW_CALIB_XOTHERM: Returns XO thermistor voltage in millidegC using * 100k pullup. The hardware applies offset/slope to adc code. - * SCALE_HW_CALIB_THERM_100K_PU_PM7: Returns temperature in millidegC using + * @SCALE_HW_CALIB_THERM_100K_PU_PM7: Returns temperature in millidegC using * lookup table for PMIC7. The hardware applies offset/slope to adc code. - * SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. + * @SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. * The hardware applies offset/slope to adc code. - * SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. + * @SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. * The hardware applies offset/slope to adc code. This is for PMIC7. - * SCALE_HW_CALIB_PM5_CHG_TEMP: Returns result in millidegrees for PMIC5 + * @SCALE_HW_CALIB_PM5_CHG_TEMP: Returns result in millidegrees for PMIC5 * charger temperature. - * SCALE_HW_CALIB_PM5_SMB_TEMP: Returns result in millidegrees for PMIC5 + * @SCALE_HW_CALIB_PM5_SMB_TEMP: Returns result in millidegrees for PMIC5 * SMB1390 temperature. */ enum vadc_scale_fn_type { @@ -120,6 +120,7 @@ enum vadc_scale_fn_type { SCALE_HW_CALIB_PMIC_THERM_PM7, SCALE_HW_CALIB_PM5_CHG_TEMP, SCALE_HW_CALIB_PM5_SMB_TEMP, + /* private: */ SCALE_HW_CALIB_INVALID, }; From 1c9986e782de45bf32fb4f886a40c1393d169568 Mon Sep 17 00:00:00 2001 From: Jianping Shen Date: Thu, 9 Oct 2025 17:31:48 +0200 Subject: [PATCH 099/304] dt-bindings: iio: imu: smi330: Add binding Add devicetree binding for Bosch imu smi330. The smi330 is a combined three axis angular rate and three axis acceleration sensor module. Signed-off-by: Jianping Shen Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- .../bindings/iio/imu/bosch,smi330.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/imu/bosch,smi330.yaml diff --git a/Documentation/devicetree/bindings/iio/imu/bosch,smi330.yaml b/Documentation/devicetree/bindings/iio/imu/bosch,smi330.yaml new file mode 100644 index 000000000000..0270ca456d2b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/imu/bosch,smi330.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/bosch,smi330.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch SMI330 6-Axis IMU + +maintainers: + - Stefan Gutmann + +description: + SMI330 is a 6-axis inertial measurement unit that supports acceleration and + gyroscopic measurements with hardware fifo buffering. Sensor also provides + events information such as motion, no-motion and tilt detection. + +properties: + compatible: + const: bosch,smi330 + + reg: + maxItems: 1 + + vdd-supply: + description: provide VDD power to the sensor. + + vddio-supply: + description: provide VDD IO power to the sensor. + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 + + drive-open-drain: + type: boolean + description: + set if the interrupt pin(s) should be configured as + open drain. If not set, defaults to push-pull. + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + // Example for I2C + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imu@68 { + compatible = "bosch,smi330"; + reg = <0x68>; + vddio-supply = <&vddio>; + vdd-supply = <&vdd>; + interrupt-parent = <&gpio>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + }; + }; + + // Example for SPI + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + imu@0 { + compatible = "bosch,smi330"; + reg = <0>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + }; + }; From fdd00d79dc0e8a3f90be65d5060c55bb115c0f43 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 15 Oct 2025 20:35:43 -0700 Subject: [PATCH 100/304] ipack: fix ipack.h kernel-doc warnings Fix various kernel-doc warnings in ipack.h: - Remove an empty kernel-doc comment. - Add 2 missing struct short descriptions. - Fix a typo in a description. - Add a missing struct field description. - Add some missing Return descriptions. - Clarify one function short description. Warning: ../include/linux/ipack.h:73 Cannot find identifier on line: */ Warning: ../include/linux/ipack.h:74 Cannot find identifier on line: struct ipack_region { Warning: ../include/linux/ipack.h:75 Cannot find identifier on line: phys_addr_t start; Warning: ../include/linux/ipack.h:76 Cannot find identifier on line: size_t size; Warning: ../include/linux/ipack.h:77 Cannot find identifier on line: }; Warning: ../include/linux/ipack.h:78 Cannot find identifier on line: Warning: ../include/linux/ipack.h:79 Cannot find identifier on line: /** Warning: ipack.h:80 missing initial short description on line: * struct ipack_device Warning: ipack.h:163 missing initial short description on line: * struct ipack_bus_device Warning: ipack.h:130 struct member 'id_table' not described in 'ipack_driver' Warning: ipack.h:189 No description found for return value of 'ipack_bus_register' Warning: ipack.h:194 No description found for return value of 'ipack_bus_unregister' *** Warning: ipack.h:202 No description found for return value of 'ipack_driver_register' Warning: ipack.h:221 No description found for return value of 'ipack_device_init' Warning: ipack.h:236 No description found for return value of 'ipack_device_add' Warning: ipack.h:271 No description found for return value of 'ipack_get_carrier' Signed-off-by: Randy Dunlap Acked-by: Vaibhav Gupta Link: https://patch.msgid.link/20251016033543.1142049-1-rdunlap@infradead.org Signed-off-by: Greg Kroah-Hartman --- include/linux/ipack.h | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/include/linux/ipack.h b/include/linux/ipack.h index 2c6936b8371f..455f6c2a1903 100644 --- a/include/linux/ipack.h +++ b/include/linux/ipack.h @@ -70,15 +70,13 @@ enum ipack_space { IPACK_SPACE_COUNT, }; -/** - */ struct ipack_region { phys_addr_t start; size_t size; }; /** - * struct ipack_device + * struct ipack_device - subsystem representation of an IPack device * * @slot: Slot where the device is plugged in the carrier board * @bus: ipack_bus_device where the device is plugged to. @@ -89,7 +87,7 @@ struct ipack_region { * * Warning: Direct access to mapped memory is possible but the endianness * is not the same with PCI carrier or VME carrier. The endianness is managed - * by the carrier board throught bus->ops. + * by the carrier board through bus->ops. */ struct ipack_device { unsigned int slot; @@ -124,6 +122,7 @@ struct ipack_driver_ops { * struct ipack_driver -- Specific data to each ipack device driver * * @driver: Device driver kernel representation + * @id_table: Device ID table for this driver * @ops: Callbacks provided by the IPack device driver */ struct ipack_driver { @@ -161,7 +160,7 @@ struct ipack_bus_ops { }; /** - * struct ipack_bus_device + * struct ipack_bus_device - IPack bus representation * * @dev: pointer to carrier device * @slots: number of slots available @@ -185,6 +184,8 @@ struct ipack_bus_device { * * The carrier board device should call this function to register itself as * available bus device in ipack. + * + * Return: %NULL on error or &struct ipack_bus_device on success */ struct ipack_bus_device *ipack_bus_register(struct device *parent, int slots, const struct ipack_bus_ops *ops, @@ -192,6 +193,8 @@ struct ipack_bus_device *ipack_bus_register(struct device *parent, int slots, /** * ipack_bus_unregister -- unregister an ipack bus + * + * Return: %0 */ int ipack_bus_unregister(struct ipack_bus_device *bus); @@ -200,6 +203,8 @@ int ipack_bus_unregister(struct ipack_bus_device *bus); * * Called by a ipack driver to register itself as a driver * that can manage ipack devices. + * + * Return: zero on success or error code on failure. */ int ipack_driver_register(struct ipack_driver *edrv, struct module *owner, const char *name); @@ -215,7 +220,7 @@ void ipack_driver_unregister(struct ipack_driver *edrv); * function. The rest of the fields will be allocated and populated * during initalization. * - * Return zero on success or error code on failure. + * Return: zero on success or error code on failure. * * NOTE: _Never_ directly free @dev after calling this function, even * if it returned an error! Always use ipack_put_device() to give up the @@ -230,7 +235,7 @@ int ipack_device_init(struct ipack_device *dev); * Add a new IPack device. The call is done by the carrier driver * after calling ipack_device_init(). * - * Return zero on success or error code on failure. + * Return: zero on success or error code on failure. * * NOTE: _Never_ directly free @dev after calling this function, even * if it returned an error! Always use ipack_put_device() to give up the @@ -266,9 +271,11 @@ void ipack_put_device(struct ipack_device *dev); .device = (dev) /** - * ipack_get_carrier - it increase the carrier ref. counter of + * ipack_get_carrier - try to increase the carrier ref. counter of * the carrier module * @dev: mezzanine device which wants to get the carrier + * + * Return: true on success. */ static inline int ipack_get_carrier(struct ipack_device *dev) { From 47f1a2acee55a116dfd1daff7ee37cc4ff5fa5ed Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 13 Oct 2025 20:00:38 -0700 Subject: [PATCH 101/304] MAINTAINERS: ipack: add ipack.h header file Add the header file so that get_maintainer.pl will report useful info instead of just linux-kernel@vger. Fixes: 14dc124f1b2f ("MAINTAINERS: Add maintainers for Industry Pack subsystem") Signed-off-by: Randy Dunlap Acked-by: Vaibhav Gupta Link: https://patch.msgid.link/20251014030038.759222-1-rdunlap@infradead.org Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..a94383b4d87e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12216,6 +12216,7 @@ L: industrypack-devel@lists.sourceforge.net S: Maintained W: http://industrypack.sourceforge.net F: drivers/ipack/ +F: include/linux/ipack.h INFINEON DPS310 Driver M: Eddie James From f50d2dcd1a2a0a8c959f9d6fd1dafa78954086f4 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Mon, 8 Sep 2025 20:13:54 +0200 Subject: [PATCH 102/304] char/adi: Use min_t(size_t,,) in adi_read() + adi_write() Replace min() and manual casting of MAX_BUF_SZ with min_t(size_t,,) in both adi_read() and adi_write(). This matches the initial buffer size calculation: ver_buf_sz = min_t(size_t, count, MAX_BUF_SZ); and makes the code more consistent. No functional changes intended. Signed-off-by: Thorsten Blum Link: https://patch.msgid.link/20250908181354.436680-2-thorsten.blum@linux.dev Signed-off-by: Greg Kroah-Hartman --- drivers/char/adi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/char/adi.c b/drivers/char/adi.c index 4312b0cc391c..0849d933a2d5 100644 --- a/drivers/char/adi.c +++ b/drivers/char/adi.c @@ -80,8 +80,8 @@ static ssize_t adi_read(struct file *file, char __user *buf, bytes_read += ver_buf_sz; ver_buf_idx = 0; - ver_buf_sz = min(count - bytes_read, - (size_t)MAX_BUF_SZ); + ver_buf_sz = min_t(size_t, count - bytes_read, + MAX_BUF_SZ); } } @@ -157,7 +157,7 @@ static ssize_t adi_write(struct file *file, const char __user *buf, } bytes_written += ver_buf_sz; - ver_buf_sz = min(count - bytes_written, (size_t)MAX_BUF_SZ); + ver_buf_sz = min_t(size_t, count - bytes_written, MAX_BUF_SZ); } while (bytes_written < count); (*offp) += bytes_written; From cdc93023954b8c2c8f228f501d82342cfad53354 Mon Sep 17 00:00:00 2001 From: Akiyoshi Kurita Date: Thu, 11 Sep 2025 21:59:39 +0900 Subject: [PATCH 103/304] vmw_vmci: fix typo in comment Correct a spelling mistake in vmci_context.h ("receive" was spelled incorrectly). No functional change. Signed-off-by: Akiyoshi Kurita Link: https://patch.msgid.link/20250911125939.587139-1-weibu@redadmin.org Signed-off-by: Greg Kroah-Hartman --- drivers/misc/vmw_vmci/vmci_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/vmw_vmci/vmci_context.h b/drivers/misc/vmw_vmci/vmci_context.h index 980fdece0f7d..083effa08102 100644 --- a/drivers/misc/vmw_vmci/vmci_context.h +++ b/drivers/misc/vmw_vmci/vmci_context.h @@ -98,7 +98,7 @@ struct vmci_ctx_chkpt_buf_info { }; /* - * VMCINotificationReceiveInfo: Used to recieve pending notifications + * VMCINotificationReceiveInfo: Used to receive pending notifications * for doorbells and queue pairs. */ struct vmci_ctx_notify_recv_info { From 69cddd82ef78bbd5a92d11f725ab22a84b561a10 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 14 Sep 2025 15:44:13 +0200 Subject: [PATCH 104/304] intel_th: make intel_th_bus_type constant Now that the driver core can properly handle constant struct bus_type, move the intel_th_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Alexander Shishkin Reviewed-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman Link: https://patch.msgid.link/2025091412-machine-despair-248e@gregkh Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/intel_th/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/intel_th/core.c b/drivers/hwtracing/intel_th/core.c index 47d9e6c3bac0..ba7c8b184cbc 100644 --- a/drivers/hwtracing/intel_th/core.c +++ b/drivers/hwtracing/intel_th/core.c @@ -166,7 +166,7 @@ static void intel_th_remove(struct device *dev) pm_runtime_enable(dev); } -static struct bus_type intel_th_bus = { +static const struct bus_type intel_th_bus = { .name = "intel_th", .match = intel_th_match, .probe = intel_th_probe, From 9fd2eb9e18a0a0b5a127937586388ed0181d9dac Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 14 Sep 2025 15:42:40 +0200 Subject: [PATCH 105/304] cdx: make cdx_bus_type constant Now that the driver core can properly handle constant struct bus_type, move the cdx_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Nipun Gupta Cc: Nikhil Agarwal Acked-by: Nipun Gupta Signed-off-by: Greg Kroah-Hartman Link: https://patch.msgid.link/2025091439-sustained-acorn-4af4@gregkh Signed-off-by: Greg Kroah-Hartman --- drivers/cdx/cdx.c | 4 ++-- include/linux/cdx/cdx_bus.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cdx/cdx.c b/drivers/cdx/cdx.c index 3d50f8cd9c0b..b39af2f1937f 100644 --- a/drivers/cdx/cdx.c +++ b/drivers/cdx/cdx.c @@ -170,7 +170,7 @@ static int cdx_unregister_device(struct device *dev, return 0; } -static void cdx_unregister_devices(struct bus_type *bus) +static void cdx_unregister_devices(const struct bus_type *bus) { /* Reset all the devices attached to cdx bus */ bus_for_each_dev(bus, NULL, NULL, cdx_unregister_device); @@ -651,7 +651,7 @@ static struct attribute *cdx_bus_attrs[] = { }; ATTRIBUTE_GROUPS(cdx_bus); -struct bus_type cdx_bus_type = { +const struct bus_type cdx_bus_type = { .name = "cdx", .match = cdx_bus_match, .probe = cdx_probe, diff --git a/include/linux/cdx/cdx_bus.h b/include/linux/cdx/cdx_bus.h index 79bb80e56790..b1ba97f6c9ad 100644 --- a/include/linux/cdx/cdx_bus.h +++ b/include/linux/cdx/cdx_bus.h @@ -234,7 +234,7 @@ int __must_check __cdx_driver_register(struct cdx_driver *cdx_driver, */ void cdx_driver_unregister(struct cdx_driver *cdx_driver); -extern struct bus_type cdx_bus_type; +extern const struct bus_type cdx_bus_type; /** * cdx_dev_reset - Reset CDX device From 48d45ae4ddaadaf67408cc588596a96b282ce2b4 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Wed, 17 Sep 2025 15:13:47 +0200 Subject: [PATCH 106/304] comedi: Replace kcalloc + copy_from_user with memdup_array_user Replace kcalloc() followed by copy_from_user() with memdup_array_user() to improve and simplify comedi_unlocked_ioctl(). No functional changes intended. Signed-off-by: Thorsten Blum Reviewed-by: Ian Abbott Link: https://patch.msgid.link/20250917131349.117642-2-thorsten.blum@linux.dev Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/comedi_fops.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c index 7e2f2b1a1c36..dea698e509b1 100644 --- a/drivers/comedi/comedi_fops.c +++ b/drivers/comedi/comedi_fops.c @@ -2284,15 +2284,10 @@ static long comedi_unlocked_ioctl(struct file *file, unsigned int cmd, rc = check_insnlist_len(dev, insnlist.n_insns); if (rc) break; - insns = kcalloc(insnlist.n_insns, sizeof(*insns), GFP_KERNEL); - if (!insns) { - rc = -ENOMEM; - break; - } - if (copy_from_user(insns, insnlist.insns, - sizeof(*insns) * insnlist.n_insns)) { - rc = -EFAULT; - kfree(insns); + insns = memdup_array_user(insnlist.insns, insnlist.n_insns, + sizeof(*insns)); + if (IS_ERR(insns)) { + rc = PTR_ERR(insns); break; } rc = do_insnlist_ioctl(dev, insns, insnlist.n_insns, file); From 6db608171a9047f076bea9273061fcc9ad3d4d85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Thu, 18 Sep 2025 13:44:28 +0000 Subject: [PATCH 107/304] arm: make sa1111_bus_type const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the sa1111_bus_type to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250918134429.270814-1-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- arch/arm/common/sa1111.c | 2 +- arch/arm/include/asm/hardware/sa1111.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 3389a70e4d49..04ff75dcc20e 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -1371,7 +1371,7 @@ static void sa1111_bus_remove(struct device *dev) drv->remove(sadev); } -struct bus_type sa1111_bus_type = { +const struct bus_type sa1111_bus_type = { .name = "sa1111-rab", .match = sa1111_match, .probe = sa1111_bus_probe, diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h index a815f39b4243..90b6a832108d 100644 --- a/arch/arm/include/asm/hardware/sa1111.h +++ b/arch/arm/include/asm/hardware/sa1111.h @@ -368,7 +368,7 @@ -extern struct bus_type sa1111_bus_type; +extern const struct bus_type sa1111_bus_type; #define SA1111_DEVID_SBI (1 << 0) #define SA1111_DEVID_SK (1 << 1) From b93606c51b5463766c4cf250072df219f20f49bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Thu, 18 Sep 2025 14:16:33 +0000 Subject: [PATCH 108/304] powerpc: cell: make spu_subsys const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the spu_subsys to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250918141633.339803-1-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/platforms/cell/spu_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index 2c07387201d0..733b512992c0 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -464,7 +464,7 @@ void spu_init_channels(struct spu *spu) } EXPORT_SYMBOL_GPL(spu_init_channels); -static struct bus_type spu_subsys = { +static const struct bus_type spu_subsys = { .name = "spu", .dev_name = "spu", }; From 61e606305672342858a647af3629d9dfcc4e4265 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Fri, 19 Sep 2025 06:53:27 +0000 Subject: [PATCH 109/304] drivers: eisa: make eisa_bus_type const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the eisa_bus_type to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250919065327.672924-1-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/eisa/eisa-bus.c | 2 +- include/linux/eisa.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/eisa/eisa-bus.c b/drivers/eisa/eisa-bus.c index edceea083b98..bd76d599109c 100644 --- a/drivers/eisa/eisa-bus.c +++ b/drivers/eisa/eisa-bus.c @@ -135,7 +135,7 @@ static int eisa_bus_uevent(const struct device *dev, struct kobj_uevent_env *env return 0; } -struct bus_type eisa_bus_type = { +const struct bus_type eisa_bus_type = { .name = "eisa", .match = eisa_bus_match, .uevent = eisa_bus_uevent, diff --git a/include/linux/eisa.h b/include/linux/eisa.h index 21a2ecc1e538..cf55630b595b 100644 --- a/include/linux/eisa.h +++ b/include/linux/eisa.h @@ -68,7 +68,7 @@ struct eisa_driver { /* These external functions are only available when EISA support is enabled. */ #ifdef CONFIG_EISA -extern struct bus_type eisa_bus_type; +extern const struct bus_type eisa_bus_type; int eisa_driver_register (struct eisa_driver *edrv); void eisa_driver_unregister (struct eisa_driver *edrv); From 8ce6b508f24b4ef3a78c2c0d92e67b9e324c4f7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Fri, 19 Sep 2025 07:32:01 +0000 Subject: [PATCH 110/304] drivers: rapidio: make rio_bus_type const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the rio_bus_type to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250919073201.751348-1-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/rapidio/rio-driver.c | 2 +- include/linux/rio.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rapidio/rio-driver.c b/drivers/rapidio/rio-driver.c index 238250e69005..bcfe0b45b377 100644 --- a/drivers/rapidio/rio-driver.c +++ b/drivers/rapidio/rio-driver.c @@ -227,7 +227,7 @@ struct class rio_mport_class = { }; EXPORT_SYMBOL_GPL(rio_mport_class); -struct bus_type rio_bus_type = { +const struct bus_type rio_bus_type = { .name = "rapidio", .match = rio_match_bus, .dev_groups = rio_dev_groups, diff --git a/include/linux/rio.h b/include/linux/rio.h index 3c29f40f3c94..2c29f21ba9e5 100644 --- a/include/linux/rio.h +++ b/include/linux/rio.h @@ -78,7 +78,7 @@ #define RIO_CTAG_RESRVD 0xfffe0000 /* Reserved */ #define RIO_CTAG_UDEVID 0x0001ffff /* Unique device identifier */ -extern struct bus_type rio_bus_type; +extern const struct bus_type rio_bus_type; extern struct class rio_mport_class; struct rio_mport; From 8ae7090dc7862c1c351bce14cdbf9125d3a4416e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Thu, 18 Sep 2025 11:48:40 +0000 Subject: [PATCH 111/304] arch: powerpc: ps3: Make ps3_system_bus_type const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the ps3_system_bus_type to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Geert Uytterhoeven Reviewed-by: Greg Kroah-Hartman Acked-by: Geoff Levand Link: https://patch.msgid.link/20250918114840.53581-1-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/platforms/ps3/system-bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index afbaabf182d0..c5b880c411ef 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c @@ -465,7 +465,7 @@ static struct attribute *ps3_system_bus_dev_attrs[] = { }; ATTRIBUTE_GROUPS(ps3_system_bus_dev); -static struct bus_type ps3_system_bus_type = { +static const struct bus_type ps3_system_bus_type = { .name = "ps3_system_bus", .match = ps3_system_bus_match, .uevent = ps3_system_bus_uevent, From 73350c385235b0f567e81fe3e04509b5d0b50ef4 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Oct 2025 10:21:57 -0500 Subject: [PATCH 112/304] fsi: occ: Update response size to 8kb Newer OCCs return more data. Signed-off-by: Eddie James Reviewed-by: Ninad Palsule Link: https://patch.msgid.link/20251008152157.1387182-1-eajames@linux.ibm.com Signed-off-by: Greg Kroah-Hartman --- drivers/fsi/fsi-occ.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c index d3e6bf37878a..e41ef12fa095 100644 --- a/drivers/fsi/fsi-occ.c +++ b/drivers/fsi/fsi-occ.c @@ -22,9 +22,9 @@ #include #include -#define OCC_SRAM_BYTES 4096 -#define OCC_CMD_DATA_BYTES 4090 -#define OCC_RESP_DATA_BYTES 4089 +#define OCC_SRAM_BYTES 8192 +#define OCC_CMD_DATA_BYTES 8186 +#define OCC_RESP_DATA_BYTES 8185 #define OCC_P9_SRAM_CMD_ADDR 0xFFFBE000 #define OCC_P9_SRAM_RSP_ADDR 0xFFFBF000 @@ -86,7 +86,7 @@ static int occ_open(struct inode *inode, struct file *file) if (!client) return -ENOMEM; - client->buffer = (u8 *)__get_free_page(GFP_KERNEL); + client->buffer = kvmalloc(OCC_SRAM_BYTES, GFP_KERNEL); if (!client->buffer) { kfree(client); return -ENOMEM; @@ -97,10 +97,6 @@ static int occ_open(struct inode *inode, struct file *file) file->private_data = client; get_device(occ->dev); - /* We allocate a 1-page buffer, make sure it all fits */ - BUILD_BUG_ON((OCC_CMD_DATA_BYTES + 3) > PAGE_SIZE); - BUILD_BUG_ON((OCC_RESP_DATA_BYTES + 7) > PAGE_SIZE); - return 0; } @@ -176,7 +172,7 @@ static ssize_t occ_write(struct file *file, const char __user *buf, } /* Submit command; 4 bytes before the data and 2 bytes after */ - rlen = PAGE_SIZE; + rlen = OCC_SRAM_BYTES; rc = fsi_occ_submit(client->occ->dev, cmd, data_length + 6, cmd, &rlen); if (rc) @@ -200,7 +196,7 @@ static int occ_release(struct inode *inode, struct file *file) struct occ_client *client = file->private_data; put_device(client->occ->dev); - free_page((unsigned long)client->buffer); + kvfree(client->buffer); kfree(client); return 0; From b91c13534a63e8b54fd47ae2de53941e8620ce75 Mon Sep 17 00:00:00 2001 From: Madhur Kumar Date: Mon, 13 Oct 2025 18:58:33 +0530 Subject: [PATCH 113/304] misc: cb710: Replace deprecated PCI functions pcim_iomap_table() and pcim_iomap_regions() have been deprecated. Replace them with pcim_iomap_region(). Signed-off-by: Madhur Kumar Link: https://patch.msgid.link/20251013132833.1783880-1-madhurkumar004@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/cb710/core.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/misc/cb710/core.c b/drivers/misc/cb710/core.c index 55b7ee0e8f93..a1e6ba62c298 100644 --- a/drivers/misc/cb710/core.c +++ b/drivers/misc/cb710/core.c @@ -223,13 +223,11 @@ static int cb710_probe(struct pci_dev *pdev, if (err) return err; - err = pcim_iomap_regions(pdev, 0x0001, KBUILD_MODNAME); - if (err) - return err; - spin_lock_init(&chip->irq_lock); chip->pdev = pdev; - chip->iobase = pcim_iomap_table(pdev)[0]; + chip->iobase = pcim_iomap_region(pdev, 0, KBUILD_MODNAME); + if (!chip->iobase) + return -ENOMEM; pci_set_drvdata(pdev, chip); From b94eb28cb3ed624f7c335b8f4438b5ba36ea4885 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Thu, 16 Oct 2025 13:42:33 +0200 Subject: [PATCH 114/304] misc: lis3lv02d: Use min to simplify lis3lv02d_misc_read Use min() to simplify lis3lv02d_misc_read(). Signed-off-by: Thorsten Blum Link: https://patch.msgid.link/20251016114234.72221-1-thorsten.blum@linux.dev Signed-off-by: Greg Kroah-Hartman --- drivers/misc/lis3lv02d/lis3lv02d.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/misc/lis3lv02d/lis3lv02d.c b/drivers/misc/lis3lv02d/lis3lv02d.c index 6957091ab6de..1a634ac1a241 100644 --- a/drivers/misc/lis3lv02d/lis3lv02d.c +++ b/drivers/misc/lis3lv02d/lis3lv02d.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -629,10 +630,7 @@ static ssize_t lis3lv02d_misc_read(struct file *file, char __user *buf, schedule(); } - if (data < 255) - byte_data = data; - else - byte_data = 255; + byte_data = min(data, 255); /* make sure we are not going into copy_to_user() with * TASK_INTERRUPTIBLE state */ From f20c1dbe82f52ff24a366e1e72c4f19031915808 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ahelenia=20Ziemia=C5=84ska?= Date: Fri, 17 Oct 2025 00:05:10 +0200 Subject: [PATCH 115/304] apm-emulation: remove unused __apm_get_power_status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The API for apm_get_power_status is "call it if it isn't NULL", except it's also initialised with a no-op __apm_get_power_status. This was added alongside apm_get_power_status in 2007. The apm_get_power_status symbol is used in these files: arch/arm/mach-pxa/sharpsl_pm.c:extern void (*apm_get_power_status)(struct apm_power_info *); arch/arm/mach-pxa/sharpsl_pm.c: apm_get_power_status = sharpsl_apm_get_power_status; arch/sh/boards/mach-hp6xx/hp6xx_apm.c: apm_get_power_status = hp6x0_apm_get_power_status; drivers/char/apm-emulation.c:void (*apm_get_power_status)(struct apm_power_info *) = __apm_get_power_status; drivers/char/apm-emulation.c:EXPORT_SYMBOL(apm_get_power_status); drivers/char/apm-emulation.c: if (apm_get_power_status) drivers/char/apm-emulation.c: apm_get_power_status(&info); drivers/macintosh/apm_emu.c: apm_get_power_status = pmu_apm_get_power_status; drivers/macintosh/apm_emu.c: if (apm_get_power_status == pmu_apm_get_power_status) drivers/macintosh/apm_emu.c: apm_get_power_status = NULL; drivers/power/supply/apm_power.c: apm_get_power_status = apm_battery_apm_get_power_status; drivers/power/supply/apm_power.c: apm_get_power_status = NULL; include/linux/apm-emulation.h:extern void (*apm_get_power_status)(struct apm_power_info *); All of them are compatible with the API (post-remove UAFs notwithstanding) and don't even read it except to compare with their own values; on a cursory glance this doesn't seem to have ever not been the case. Fixes: 7726942fb15e ("[APM] Add shared version of APM emulation") Signed-off-by: Ahelenia Ziemiańska Link: https://patch.msgid.link/ba3nzxffdpuz2eo5kbpm5iez2rcdves3qpd4kvnmshxwjburwo@tarta.nabijaczleweli.xyz Signed-off-by: Greg Kroah-Hartman --- drivers/char/apm-emulation.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/char/apm-emulation.c b/drivers/char/apm-emulation.c index 53ce352f7197..4aa5d1c76f83 100644 --- a/drivers/char/apm-emulation.c +++ b/drivers/char/apm-emulation.c @@ -142,18 +142,10 @@ static struct apm_queue kapmd_queue; static DEFINE_MUTEX(state_lock); -/* - * Compatibility cruft until the IPAQ people move over to the new - * interface. - */ -static void __apm_get_power_status(struct apm_power_info *info) -{ -} - /* * This allows machines to provide their own "apm get power status" function. */ -void (*apm_get_power_status)(struct apm_power_info *) = __apm_get_power_status; +void (*apm_get_power_status)(struct apm_power_info *); EXPORT_SYMBOL(apm_get_power_status); From 4c987d67b31f93ac88f4be6dfec6a169997fc2c8 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Mon, 20 Oct 2025 16:58:47 +0200 Subject: [PATCH 116/304] eeprom: at25: fram: Fix chip range in comment The first chip supported by the commented code is CY15B102QN, fix the copy-paste error. Signed-off-by: Alexander Sverdlin Link: https://patch.msgid.link/20251020145858.1598599-1-alexander.sverdlin@siemens.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/eeprom/at25.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c index e2868f7bdb03..883dfd0ed658 100644 --- a/drivers/misc/eeprom/at25.c +++ b/drivers/misc/eeprom/at25.c @@ -408,7 +408,7 @@ static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip) chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024; break; case 0x2a ... 0x30: - /* CY15B116QN ... CY15B116QN */ + /* CY15B102QN ... CY15B116QN */ chip->byte_len = BIT(((id[7] >> 1) & 0xf) + 13); break; default: From 6848990d4d78ccc790294df1c8741a8c4005db9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Thu, 18 Sep 2025 14:08:15 +0000 Subject: [PATCH 117/304] powerpc: pseries: make suspend_subsys const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the suspend_subsys to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250918140816.335916-2-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/platforms/pseries/suspend.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/pseries/suspend.c b/arch/powerpc/platforms/pseries/suspend.c index 382003dfdb9a..c51db63d3e88 100644 --- a/arch/powerpc/platforms/pseries/suspend.c +++ b/arch/powerpc/platforms/pseries/suspend.c @@ -126,7 +126,7 @@ static ssize_t show_hibernate(struct device *dev, static DEVICE_ATTR(hibernate, 0644, show_hibernate, store_hibernate); -static struct bus_type suspend_subsys = { +static const struct bus_type suspend_subsys = { .name = "power", .dev_name = "power", }; From 8c00944301fdbb2cc7ee805843934ce0f882ee29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20Barna=C5=9B?= Date: Thu, 18 Sep 2025 14:08:16 +0000 Subject: [PATCH 118/304] powerpc: pseries: make cmm_subsys const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because driver core can properly handle constant struct bus_type, move the cmm_subsys to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Signed-off-by: Adrian Barnaś Reviewed-by: Greg Kroah-Hartman Link: https://patch.msgid.link/20250918140816.335916-3-abarnas@google.com Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/platforms/pseries/cmm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c index 0823fa2da151..502133979e22 100644 --- a/arch/powerpc/platforms/pseries/cmm.c +++ b/arch/powerpc/platforms/pseries/cmm.c @@ -375,7 +375,7 @@ static struct device_attribute *cmm_attrs[] = { static DEVICE_ULONG_ATTR(simulate_loan_target_kb, 0644, simulate_loan_target_kb); -static struct bus_type cmm_subsys = { +static const struct bus_type cmm_subsys = { .name = "cmm", .dev_name = "cmm", }; From b9a7c9599120185ae65424cb93ab8af7b9024cf9 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Mon, 15 Sep 2025 10:36:44 +0000 Subject: [PATCH 119/304] misc: amd-sbi: Add helper function to prepare I3C support New AMD processors support APML connection over I3C. Move the code, common for both I2C and I3C to new helper function, "sbrmi_common_probe()" While at it, renaming the static structure regmap_config "sbrmi_i2c_regmap_config" to "sbrmi_regmap_config" to avoid confusion. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-1-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/amd-sbi/rmi-i2c.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c index f891f5af4bc6..d41457a52376 100644 --- a/drivers/misc/amd-sbi/rmi-i2c.c +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -50,26 +50,18 @@ static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data) return ret; } -static int sbrmi_i2c_probe(struct i2c_client *client) +static int sbrmi_common_probe(struct device *dev, struct regmap *regmap, uint8_t address) { - struct device *dev = &client->dev; struct sbrmi_data *data; - struct regmap_config sbrmi_i2c_regmap_config = { - .reg_bits = 8, - .val_bits = 8, - }; int ret; data = devm_kzalloc(dev, sizeof(struct sbrmi_data), GFP_KERNEL); if (!data) return -ENOMEM; + data->regmap = regmap; mutex_init(&data->lock); - data->regmap = devm_regmap_init_i2c(client, &sbrmi_i2c_regmap_config); - if (IS_ERR(data->regmap)) - return PTR_ERR(data->regmap); - /* Enable alert for SB-RMI sequence */ ret = sbrmi_enable_alert(data); if (ret < 0) @@ -80,7 +72,8 @@ static int sbrmi_i2c_probe(struct i2c_client *client) if (ret < 0) return ret; - data->dev_static_addr = client->addr; + data->dev_static_addr = address; + dev_set_drvdata(dev, data); ret = create_hwmon_sensor_device(dev, data); @@ -89,6 +82,23 @@ static int sbrmi_i2c_probe(struct i2c_client *client) return create_misc_rmi_device(data, dev); } +static struct regmap_config sbrmi_regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int sbrmi_i2c_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct regmap *regmap; + + regmap = devm_regmap_init_i2c(client, &sbrmi_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return sbrmi_common_probe(dev, regmap, client->addr); +} + static void sbrmi_i2c_remove(struct i2c_client *client) { struct sbrmi_data *data = dev_get_drvdata(&client->dev); From 5c7dddd7360b9f24d535c34dcd4101fe41b35aa1 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Mon, 15 Sep 2025 10:36:45 +0000 Subject: [PATCH 120/304] misc: amd-sbi: Add support for SB-RMI over I3C AMD EPYC platforms with zen5 and later support APML(SB-RMI) connection to the BMC over I3C bus for faster data transfer up to 12.5 Mhz. I2C and I3C is supported in same file using module_i3c_i2c_driver() with probe based on dts entry. AMD APML I3C devices support static address for backward compatibility to I2C. I3C static address can be used to assign I3C device dynamic address. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-2-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/amd-sbi/Kconfig | 4 ++- drivers/misc/amd-sbi/rmi-i2c.c | 45 +++++++++++++++++++++++++++++++++- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/misc/amd-sbi/Kconfig b/drivers/misc/amd-sbi/Kconfig index 4aae0733d0fc..acf0450ba220 100644 --- a/drivers/misc/amd-sbi/Kconfig +++ b/drivers/misc/amd-sbi/Kconfig @@ -3,8 +3,10 @@ config AMD_SBRMI_I2C tristate "AMD side band RMI support" depends on I2C select REGMAP_I2C + depends on I3C || !I3C + select REGMAP_I3C if I3C help - Side band RMI over I2C support for AMD out of band management. + Side band RMI over I2C/I3C support for AMD out of band management. This driver can also be built as a module. If so, the module will be called sbrmi-i2c. diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c index d41457a52376..087c57bb0f37 100644 --- a/drivers/misc/amd-sbi/rmi-i2c.c +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -135,7 +137,48 @@ static struct i2c_driver sbrmi_driver = { .id_table = sbrmi_id, }; -module_i2c_driver(sbrmi_driver); +static int sbrmi_i3c_probe(struct i3c_device *i3cdev) +{ + struct device *dev = i3cdev_to_dev(i3cdev); + struct regmap *regmap; + + regmap = devm_regmap_init_i3c(i3cdev, &sbrmi_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * AMD APML I3C devices support static address. + * If static address is defined, dynamic address is same as static address. + * In case static address is not defined, I3C master controller defined + * dynamic address is used. + */ + return sbrmi_common_probe(dev, regmap, i3cdev->desc->info.dyn_addr); +} + +static void sbrmi_i3c_remove(struct i3c_device *i3cdev) +{ + struct sbrmi_data *data = dev_get_drvdata(&i3cdev->dev); + + misc_deregister(&data->sbrmi_misc_dev); +} + +static const struct i3c_device_id sbrmi_i3c_id[] = { + /* PID for AMD SBRMI device */ + I3C_DEVICE_EXTRA_INFO(0x112, 0x0, 0x2, NULL), + {} +}; +MODULE_DEVICE_TABLE(i3c, sbrmi_i3c_id); + +static struct i3c_driver sbrmi_i3c_driver = { + .driver = { + .name = "sbrmi-i3c", + }, + .probe = sbrmi_i3c_probe, + .remove = sbrmi_i3c_remove, + .id_table = sbrmi_i3c_id, +}; + +module_i3c_i2c_driver(sbrmi_i3c_driver, &sbrmi_driver); MODULE_AUTHOR("Akshay Gupta "); MODULE_AUTHOR("Naveen Krishna Chatradhi "); From 45392fd4394cb8d4b39ba0f144651aba05b7b2a7 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Mon, 15 Sep 2025 10:36:46 +0000 Subject: [PATCH 121/304] misc: amd-sbi: Add support for Turin platform - RMI registers addresses in AMD new platforms are 2 bytes, on previous processors the address size is 1 byte. - Implement logic to identify register address size at runtime. - The identification is done in first transaction using the Revision register. - The revision register can be read using 1 byte in both, older and newer platforms. - However, sending 1 byte on later platform can cause unrecoverable error. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-3-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/amd-sbi/rmi-i2c.c | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c index 087c57bb0f37..f0cc99000b69 100644 --- a/drivers/misc/amd-sbi/rmi-i2c.c +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -18,6 +18,8 @@ #include #include "rmi-core.h" +#define REV_TWO_BYTE_ADDR 0x21 + static int sbrmi_enable_alert(struct sbrmi_data *data) { int ctrl, ret; @@ -89,15 +91,40 @@ static struct regmap_config sbrmi_regmap_config = { .val_bits = 8, }; +static struct regmap_config sbrmi_regmap_config_ext = { + .reg_bits = 16, + .val_bits = 8, + .reg_format_endian = REGMAP_ENDIAN_LITTLE, +}; + static int sbrmi_i2c_probe(struct i2c_client *client) { struct device *dev = &client->dev; struct regmap *regmap; + int rev, ret; regmap = devm_regmap_init_i2c(client, &sbrmi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + ret = regmap_read(regmap, SBRMI_REV, &rev); + if (ret) + return ret; + + /* + * For Turin and newer platforms, revision is 0x21 or later. This is + * to identify the two byte register address size. However, one + * byte transaction can be successful. + * Verify if revision is 0x21 or later, if yes, switch to 2 byte + * address size. + * Continuously using 1 byte address for revision 0x21 or later can lead + * to bus corruption. + */ + if (rev >= REV_TWO_BYTE_ADDR) { + regmap = devm_regmap_init_i2c(client, &sbrmi_regmap_config_ext); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + } return sbrmi_common_probe(dev, regmap, client->addr); } @@ -141,11 +168,31 @@ static int sbrmi_i3c_probe(struct i3c_device *i3cdev) { struct device *dev = i3cdev_to_dev(i3cdev); struct regmap *regmap; + int rev, ret; regmap = devm_regmap_init_i3c(i3cdev, &sbrmi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + ret = regmap_read(regmap, SBRMI_REV, &rev); + if (ret) + return ret; + + /* + * For Turin and newer platforms, revision is 0x21 or later. This is + * to identify the two byte register address size. However, one + * byte transaction can be successful. + * Verify if revision is 0x21 or later, if yes, switch to 2 byte + * address size. + * Continuously using 1 byte address for revision 0x21 or later can lead + * to bus corruption. + */ + if (rev >= REV_TWO_BYTE_ADDR) { + regmap = devm_regmap_init_i3c(i3cdev, &sbrmi_regmap_config_ext); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + } + /* * AMD APML I3C devices support static address. * If static address is defined, dynamic address is same as static address. From dd68c06380f67beda28b0cb7d77a75b91a6174e4 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Mon, 15 Sep 2025 10:36:47 +0000 Subject: [PATCH 122/304] misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21 - CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the CPUID and MCAMSR protocol to return error, "-EOPNOTSUPP", for revision 0x21. - Next set of patches will add support for CPUID and MCAMSR for Turin and later platforms. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-4-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/amd-sbi/rmi-core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 3dec2fc00124..bf534ba757db 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -122,8 +122,8 @@ static int rmi_cpuid_read(struct sbrmi_data *data, if (ret < 0) goto exit_unlock; } - /* CPUID protocol for REV 0x10 is not supported*/ - if (data->rev == 0x10) { + /* CPUID protocol for REV 0x20 is only supported*/ + if (data->rev != 0x20) { ret = -EOPNOTSUPP; goto exit_unlock; } @@ -203,8 +203,8 @@ static int rmi_mca_msr_read(struct sbrmi_data *data, if (ret < 0) goto exit_unlock; } - /* MCA MSR protocol for REV 0x10 is not supported*/ - if (data->rev == 0x10) { + /* MCA MSR protocol for REV 0x20 is supported*/ + if (data->rev != 0x20) { ret = -EOPNOTSUPP; goto exit_unlock; } From 87816eb4701f9f1aa2866e0585b270a716769e6e Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Mon, 15 Sep 2025 10:36:48 +0000 Subject: [PATCH 123/304] misc: amd-sbi: Extend support for CPUID protocol for rev 0x21 - CPUID protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-5-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/amd-sbi/rmi-core.c | 110 +++++++++++++++++++++++++------- 1 file changed, 86 insertions(+), 24 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index bf534ba757db..ef93dce7e038 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -28,8 +28,10 @@ /* CPUID */ #define CPUID_RD_DATA_LEN 0x8 #define CPUID_WR_DATA_LEN 0x8 +#define CPUID_WR_DATA_LEN_EXT 0x9 #define CPUID_RD_REG_LEN 0xa #define CPUID_WR_REG_LEN 0x9 +#define CPUID_WR_REG_LEN_EXT 0xa /* MSR */ #define MSR_RD_REG_LEN 0xa #define MSR_WR_REG_LEN 0x8 @@ -59,6 +61,20 @@ struct cpu_msr_indata { u8 ext; /* extended function */ }; +/* input for bulk write to CPUID protocol for REV 0x21 */ +struct cpu_msr_indata_ext { + u8 wr_len; /* const value */ + u8 rd_len; /* const value */ + u8 proto_cmd; /* const value */ + u8 thread_lo; /* thread number low */ + u8 thread_hi; /* thread number high */ + union { + u8 reg_offset[4]; /* input value */ + u32 value; + } __packed; + u8 ext; /* extended function */ +}; + /* output for bulk read from CPUID protocol */ struct cpu_msr_outdata { u8 num_bytes; /* number of bytes return */ @@ -81,6 +97,19 @@ static inline void prepare_cpuid_input_message(struct cpu_msr_indata *input, input->ext = ext_func; } +static inline void prepare_cpuid_input_message_ext(struct cpu_msr_indata_ext *input, + u16 thread_id, u32 func, + u8 ext_func) +{ + input->rd_len = CPUID_RD_DATA_LEN; + input->wr_len = CPUID_WR_DATA_LEN_EXT; + input->proto_cmd = RD_CPUID_CMD; + input->thread_lo = (thread_id & 0xFF) << 1; + input->thread_hi = thread_id >> 8; + input->value = func; + input->ext = ext_func; +} + static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input, u8 thread_id, u32 data_in) { @@ -105,13 +134,48 @@ static int sbrmi_get_rev(struct sbrmi_data *data) return 0; } +static int rmi_cpuid_input(struct sbrmi_data *data, struct apml_cpuid_msg *msg, + u16 thread) +{ + struct cpu_msr_indata input = {0}; + int val = 0, ret; + + /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ + if (thread > 127) { + thread -= 128; + val = 1; + } + + ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); + if (ret < 0) + return ret; + + prepare_cpuid_input_message(&input, thread, + msg->cpu_in_out & CPUID_MCA_FUNC_MASK, + msg->cpu_in_out >> CPUID_EXT_FUNC_INDEX); + + return regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, CPUID_WR_REG_LEN); +} + +static int rmi_cpuid_input_ext(struct sbrmi_data *data, struct apml_cpuid_msg *msg, + u16 thread) +{ + struct cpu_msr_indata_ext input = {0}; + + prepare_cpuid_input_message_ext(&input, thread, + msg->cpu_in_out & CPUID_MCA_FUNC_MASK, + msg->cpu_in_out >> CPUID_EXT_FUNC_INDEX); + + return regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, CPUID_WR_REG_LEN_EXT); +} + /* Read CPUID function protocol */ static int rmi_cpuid_read(struct sbrmi_data *data, struct apml_cpuid_msg *msg) { - struct cpu_msr_indata input = {0}; struct cpu_msr_outdata output = {0}; - int val = 0; int ret, hw_status; u16 thread; @@ -122,32 +186,30 @@ static int rmi_cpuid_read(struct sbrmi_data *data, if (ret < 0) goto exit_unlock; } - /* CPUID protocol for REV 0x20 is only supported*/ - if (data->rev != 0x20) { + + /* Extract thread from the input msg structure */ + thread = msg->cpu_in_out >> CPUID_MCA_THRD_INDEX; + + switch (data->rev) { + case 0x10: + /* CPUID protocol for REV 0x10 is not supported*/ + ret = -EOPNOTSUPP; + goto exit_unlock; + case 0x20: + ret = rmi_cpuid_input(data, msg, thread); + if (ret) + goto exit_unlock; + break; + case 0x21: + ret = rmi_cpuid_input_ext(data, msg, thread); + if (ret) + goto exit_unlock; + break; + default: ret = -EOPNOTSUPP; goto exit_unlock; } - thread = msg->cpu_in_out >> CPUID_MCA_THRD_INDEX; - - /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ - if (thread > 127) { - thread -= 128; - val = 1; - } - ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); - if (ret < 0) - goto exit_unlock; - - prepare_cpuid_input_message(&input, thread, - msg->cpu_in_out & CPUID_MCA_FUNC_MASK, - msg->cpu_in_out >> CPUID_EXT_FUNC_INDEX); - - ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD, - &input, CPUID_WR_REG_LEN); - if (ret < 0) - goto exit_unlock; - /* * For RMI Rev 0x20, new h/w status bit is introduced. which is used * by firmware to indicate completion of commands (0x71, 0x72, 0x73). From 18e4a02963b7582207b8a7b25d053f40ac206e4d Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Mon, 15 Sep 2025 10:36:49 +0000 Subject: [PATCH 124/304] misc: amd-sbi: Extend support for MCAMSR protocol for rev 0x21 - MCAMSR protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-6-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/amd-sbi/rmi-core.c | 92 ++++++++++++++++++++++++--------- 1 file changed, 69 insertions(+), 23 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index ef93dce7e038..c3a58912d6db 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -35,8 +35,10 @@ /* MSR */ #define MSR_RD_REG_LEN 0xa #define MSR_WR_REG_LEN 0x8 +#define MSR_WR_REG_LEN_EXT 0x9 #define MSR_RD_DATA_LEN 0x8 #define MSR_WR_DATA_LEN 0x7 +#define MSR_WR_DATA_LEN_EXT 0x8 /* CPUID MSR Command Ids */ #define CPUID_MCA_CMD 0x73 @@ -120,6 +122,17 @@ static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input, input->value = data_in; } +static inline void prepare_mca_msr_input_message_ext(struct cpu_msr_indata_ext *input, + u16 thread_id, u32 data_in) +{ + input->rd_len = MSR_RD_DATA_LEN; + input->wr_len = MSR_WR_DATA_LEN_EXT; + input->proto_cmd = RD_MCA_CMD; + input->thread_lo = (thread_id & 0xFF) << 1; + input->thread_hi = thread_id >> 8; + input->value = data_in; +} + static int sbrmi_get_rev(struct sbrmi_data *data) { unsigned int rev; @@ -248,13 +261,47 @@ exit_unlock: return ret; } +static int rmi_mcamsr_input(struct sbrmi_data *data, struct apml_mcamsr_msg *msg, + u16 thread) +{ + struct cpu_msr_indata input = {0}; + int val = 0, ret; + + /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ + if (thread > 127) { + thread -= 128; + val = 1; + } + + ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); + if (ret < 0) + return ret; + + prepare_mca_msr_input_message(&input, thread, + msg->mcamsr_in_out & CPUID_MCA_FUNC_MASK); + + return regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, MSR_WR_REG_LEN); +} + +static int rmi_mcamsr_input_ext(struct sbrmi_data *data, struct apml_mcamsr_msg *msg, + u16 thread) +{ + struct cpu_msr_indata_ext input = {0}; + + prepare_mca_msr_input_message_ext(&input, thread, + msg->mcamsr_in_out & CPUID_MCA_FUNC_MASK); + + return regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, MSR_WR_REG_LEN_EXT); +} + /* MCA MSR protocol */ static int rmi_mca_msr_read(struct sbrmi_data *data, struct apml_mcamsr_msg *msg) { struct cpu_msr_outdata output = {0}; - struct cpu_msr_indata input = {0}; - int ret, val = 0; + int ret; int hw_status; u16 thread; @@ -265,31 +312,30 @@ static int rmi_mca_msr_read(struct sbrmi_data *data, if (ret < 0) goto exit_unlock; } - /* MCA MSR protocol for REV 0x20 is supported*/ - if (data->rev != 0x20) { + + /* Extract thread from the input msg structure */ + thread = msg->mcamsr_in_out >> CPUID_MCA_THRD_INDEX; + + switch (data->rev) { + case 0x10: + /* MCAMSR protocol for REV 0x10 is not supported*/ + ret = -EOPNOTSUPP; + goto exit_unlock; + case 0x20: + ret = rmi_mcamsr_input(data, msg, thread); + if (ret) + goto exit_unlock; + break; + case 0x21: + ret = rmi_mcamsr_input_ext(data, msg, thread); + if (ret) + goto exit_unlock; + break; + default: ret = -EOPNOTSUPP; goto exit_unlock; } - thread = msg->mcamsr_in_out >> CPUID_MCA_THRD_INDEX; - - /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ - if (thread > 127) { - thread -= 128; - val = 1; - } - ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); - if (ret < 0) - goto exit_unlock; - - prepare_mca_msr_input_message(&input, thread, - msg->mcamsr_in_out & CPUID_MCA_FUNC_MASK); - - ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD, - &input, MSR_WR_REG_LEN); - if (ret < 0) - goto exit_unlock; - /* * For RMI Rev 0x20, new h/w status bit is introduced. which is used * by firmware to indicate completion of commands (0x71, 0x72, 0x73). From d48fb15e6ad142e0577428a8c5028136e10c7b3d Mon Sep 17 00:00:00 2001 From: Li Qiang Date: Wed, 15 Oct 2025 14:40:20 +0800 Subject: [PATCH 125/304] uio: uio_fsl_elbc_gpcm:: Add null pointer check to uio_fsl_elbc_gpcm_probe devm_kasprintf() returns a pointer to dynamically allocated memory which can be NULL upon failure. Fixes: d57801c45f53e ("uio: uio_fsl_elbc_gpcm: use device-managed allocators") Signed-off-by: Li Qiang Link: https://patch.msgid.link/20251015064020.56589-1-liqiang01@kylinos.cn Signed-off-by: Greg Kroah-Hartman --- drivers/uio/uio_fsl_elbc_gpcm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/uio/uio_fsl_elbc_gpcm.c b/drivers/uio/uio_fsl_elbc_gpcm.c index 81454c3e2484..338dd2aaabc8 100644 --- a/drivers/uio/uio_fsl_elbc_gpcm.c +++ b/drivers/uio/uio_fsl_elbc_gpcm.c @@ -384,6 +384,11 @@ static int uio_fsl_elbc_gpcm_probe(struct platform_device *pdev) /* set all UIO data */ info->mem[0].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOFn", node); + if (!info->mem[0].name) { + ret = -ENODEV; + goto out_err3; + } + info->mem[0].addr = res.start; info->mem[0].size = resource_size(&res); info->mem[0].memtype = UIO_MEM_PHYS; @@ -423,6 +428,8 @@ static int uio_fsl_elbc_gpcm_probe(struct platform_device *pdev) out_err2: if (priv->shutdown) priv->shutdown(info, true); + +out_err3: iounmap(info->mem[0].internal_addr); return ret; } From 245f14f5fe283c782b16143280f283bee29dbb5f Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Tue, 30 Sep 2025 12:30:55 +0800 Subject: [PATCH 126/304] interconnect: Optimize kbps_to_icc() macro The current expansion of kbps_to_icc() introduces unnecessary logic when compiled from a general expression. Rewriting it allows compilers to emit shorter and more efficient code across architectures. For example, with gcc -O2: arm64: old: tst x0, 7 add w1, w0, 7 cset w2, ne cmp w0, 0 csel w0, w1, w0, lt add w0, w2, w0, asr 3 new: add w1, w0, 14 adds w0, w0, 7 csel w0, w1, w0, mi asr w0, w0, 3 x86-64: old: xor eax, eax test dil, 7 lea edx, [rdi+7] setne al test edi, edi cmovns edx, edi sar edx, 3 add eax, edx new: lea eax, [rdi+14] add edi, 7 cmovns eax, edi sar eax, 3 In both cases the old form relies on extra test and compare instructions (tst, test, cmp) combined with conditional moves or sets, while the new form uses fewer instructions by folding the addition and flag update together (adds on arm64, add on x86). This reduces the instruction sequence, prevents multiple evaluations of x when it is an expression or a function call, and keeps the macro simpler. Signed-off-by: Kuan-Wei Chiu Link: https://lore.kernel.org/r/20250930043055.2200322-1-visitorckw@gmail.com Signed-off-by: Georgi Djakov --- include/linux/interconnect.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index e4b8808823ad..4b12821528a6 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -16,7 +16,7 @@ #define MBps_to_icc(x) ((x) * 1000) #define GBps_to_icc(x) ((x) * 1000 * 1000) #define bps_to_icc(x) (1) -#define kbps_to_icc(x) ((x) / 8 + ((x) % 8 ? 1 : 0)) +#define kbps_to_icc(x) (((x) + 7) / 8) #define Mbps_to_icc(x) ((x) * 1000 / 8) #define Gbps_to_icc(x) ((x) * 1000 * 1000 / 8) From 8cf9b43f6b4d90e19a9341edefdd46842d4adb55 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Oct 2025 11:53:00 +0300 Subject: [PATCH 127/304] interconnect: qcom: msm8996: add missing link to SLAVE_USB_HS >From the initial submission the interconnect driver missed the link from SNOC_PNOC to the USB 2 configuration space. Add missing link in order to let the platform configure and utilize this path. Fixes: 7add937f5222 ("interconnect: qcom: Add MSM8996 interconnect provider driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251002-fix-msm8996-icc-v1-1-a36a05d1f869@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/msm8996.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index b73566c9b21f..84cfafb22aa1 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -552,6 +552,7 @@ static struct qcom_icc_node mas_venus_vmem = { static const u16 mas_snoc_pnoc_links[] = { MSM8996_SLAVE_BLSP_1, MSM8996_SLAVE_BLSP_2, + MSM8996_SLAVE_USB_HS, MSM8996_SLAVE_SDCC_1, MSM8996_SLAVE_SDCC_2, MSM8996_SLAVE_SDCC_4, From 242f7558e7bf54cb63c06506f7b0630dd67d45a4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Oct 2025 11:53:01 +0300 Subject: [PATCH 128/304] arm64: dts: qcom: msm8996: add interconnect paths to USB2 controller Add the missing interconnects to the USB2 host. The Fixes tag points to the commit which broke probing of the USB host on that platform. Fixes: 130733a10079 ("interconnect: qcom: msm8996: Promote to core_initcall") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Acked-by: Bjorn Andersson Link: https://lore.kernel.org/r/20251002-fix-msm8996-icc-v1-2-a36a05d1f869@oss.qualcomm.com Signed-off-by: Georgi Djakov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c75b522f6eba..33608b1d7d06 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3496,6 +3496,9 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <60000000>; + interconnects = <&pnoc MASTER_USB_HS &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &pnoc SLAVE_USB_HS>; + interconnect-names = "usb-ddr", "apps-usb"; power-domains = <&gcc USB30_GDSC>; qcom,select-utmi-as-pipe-clk; status = "disabled"; From 8a55fbe4c94db5f86e2dce9caa72eeb2233e0a02 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 1 Oct 2025 13:03:42 +0530 Subject: [PATCH 129/304] dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p Add 'reg' and 'clocks' properties to enable QoS configuration. These properties enable access to QoS registers and necessary clocks for configuration. QoS configuration is essential for ensuring that latency sensitive components such as CPUs and multimedia engines receive prioritized access to memory and interconnect resources. This helps to manage bandwidth and latency across subsystems, improving system responsiveness and performance in concurrent workloads. Both 'reg' and 'clocks' properties are optional. If either is missing, QoS configuration will be skipped. This behavior is controlled by the 'qos_requires_clocks' flag in the driver, which ensures that QoS configuration is bypassed when required clocks are not defined. Signed-off-by: Odelu Kukatla Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251001073344.6599-2-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../interconnect/qcom,sa8775p-rpmh.yaml | 52 ++++++++++++++++++- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml index db19fd5c5708..71428d2cce18 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml @@ -33,18 +33,66 @@ properties: - qcom,sa8775p-pcie-anoc - qcom,sa8775p-system-noc + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 5 + required: - compatible allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre UFS CARD AXI clock + - description: RPMH CC IPA clock unevaluatedProperties: false examples: - | - aggre1_noc: interconnect-aggre1-noc { - compatible = "qcom,sa8775p-aggre1-noc"; + #include + clk_virt: interconnect-clk-virt { + compatible = "qcom,sa8775p-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; + + aggre1_noc: interconnect@16c0000 { + compatible = "qcom,sa8775p-aggre1-noc"; + reg = <0x016c0000 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; From 3c046c3e043c6cbbde55af200adbe98850686273 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 1 Oct 2025 13:03:43 +0530 Subject: [PATCH 130/304] interconnect: qcom: sa8775p: enable QoS configuration Enable QoS configuration for master ports with predefinedi priority and urgency forwarding. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251001073344.6599-3-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sa8775p.c | 439 ++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index 04b4abbf4487..5bf27dbe818d 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -213,6 +213,13 @@ static struct qcom_icc_node qxm_qup3 = { .name = "qxm_qup3", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -221,6 +228,13 @@ static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -229,6 +243,13 @@ static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -237,6 +258,13 @@ static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -245,6 +273,13 @@ static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -253,6 +288,13 @@ static struct qcom_icc_node xm_usb2_2 = { .name = "xm_usb2_2", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -261,6 +303,13 @@ static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -269,6 +318,13 @@ static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -277,6 +333,13 @@ static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -285,6 +348,13 @@ static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -293,6 +363,13 @@ static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -301,6 +378,13 @@ static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -309,6 +393,13 @@ static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -317,6 +408,13 @@ static struct qcom_icc_node qxm_crypto_0 = { .name = "qxm_crypto_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -325,6 +423,13 @@ static struct qcom_icc_node qxm_crypto_1 = { .name = "qxm_crypto_1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1a000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -333,6 +438,13 @@ static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -341,6 +453,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -349,6 +468,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x19000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -357,6 +483,13 @@ static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1b000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -461,6 +594,13 @@ static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb4000 }, + .prio_fwd_disable = 1, + .prio = 1, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -469,6 +609,13 @@ static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb5000 }, + .prio_fwd_disable = 1, + .prio = 3, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -477,6 +624,13 @@ static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb6000 }, + .prio_fwd_disable = 1, + .prio = 6, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -494,6 +648,13 @@ static struct qcom_icc_node qnm_cmpnoc0 = { .name = "qnm_cmpnoc0", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf3000, 0xf4000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -502,6 +663,13 @@ static struct qcom_icc_node qnm_cmpnoc1 = { .name = "qnm_cmpnoc1", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf5000, 0xf6000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -527,6 +695,13 @@ static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xed000, 0xee000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -535,6 +710,13 @@ static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xef000, 0xf0000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, }; @@ -543,6 +725,13 @@ static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .channels = 2, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf1000, 0xf2000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 3, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -552,6 +741,13 @@ static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb8000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 2, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -560,6 +756,13 @@ static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb9000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, }; @@ -568,6 +771,13 @@ static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xba000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 3, .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -620,6 +830,13 @@ static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -628,6 +845,13 @@ static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -636,6 +860,13 @@ static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a080 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -644,6 +875,13 @@ static struct qcom_icc_node qnm_mdp0_0 = { .name = "qnm_mdp0_0", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa080 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -652,6 +890,13 @@ static struct qcom_icc_node qnm_mdp0_1 = { .name = "qnm_mdp0_1", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa180 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -660,6 +905,13 @@ static struct qcom_icc_node qnm_mdp1_0 = { .name = "qnm_mdp1_0", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa100 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -668,6 +920,13 @@ static struct qcom_icc_node qnm_mdp1_1 = { .name = "qnm_mdp1_1", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa200 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -692,6 +951,13 @@ static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a100 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -700,6 +966,13 @@ static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a180 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -708,6 +981,13 @@ static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a200 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -716,6 +996,13 @@ static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a280 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -756,6 +1043,13 @@ static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, }; @@ -764,6 +1058,13 @@ static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, }; @@ -772,6 +1073,13 @@ static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, }; @@ -796,6 +1104,13 @@ static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, }; @@ -812,6 +1127,13 @@ static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, }; @@ -820,6 +1142,13 @@ static struct qcom_icc_node xm_gic = { .name = "xm_gic", .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, }; @@ -1836,12 +2165,22 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, }; +static const struct regmap_config sa8775p_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x18080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_aggre1_noc = { + .config = &sa8775p_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), .alloc_dyn_id = true, + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1864,12 +2203,22 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, }; +static const struct regmap_config sa8775p_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1b080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_aggre2_noc = { + .config = &sa8775p_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), .alloc_dyn_id = true, + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1995,7 +2344,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config sa8775p_config_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x13080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_config_noc = { + .config = &sa8775p_config_noc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -2012,7 +2370,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; +static const struct regmap_config sa8775p_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_dc_noc = { + .config = &sa8775p_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -2049,7 +2416,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, }; +static const struct regmap_config sa8775p_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf6080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_gem_noc = { + .config = &sa8775p_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -2068,7 +2444,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, }; +static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { + .config = &sa8775p_gpdsp_anoc_regmap_config, .nodes = gpdsp_anoc_nodes, .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), .bcms = gpdsp_anoc_bcms, @@ -2092,7 +2477,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; +static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17200, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { + .config = &sa8775p_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -2143,7 +2537,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, }; +static const struct regmap_config sa8775p_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_mmss_noc = { + .config = &sa8775p_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -2164,7 +2567,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; +static const struct regmap_config sa8775p_nspa_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x16080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_nspa_noc = { + .config = &sa8775p_nspa_noc_regmap_config, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -2177,6 +2589,14 @@ static struct qcom_icc_bcm * const nspb_noc_bcms[] = { &bcm_nsb1, }; +static const struct regmap_config sa8775p_nspb_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x16080, + .fast_io = true, +}; + static struct qcom_icc_node * const nspb_noc_nodes[] = { [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, [MASTER_CDSP_PROC_B] = &qxm_nspb, @@ -2186,6 +2606,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = { }; static const struct qcom_icc_desc sa8775p_nspb_noc = { + .config = &sa8775p_nspb_noc_regmap_config, .nodes = nspb_noc_nodes, .num_nodes = ARRAY_SIZE(nspb_noc_nodes), .bcms = nspb_noc_bcms, @@ -2203,7 +2624,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, }; +static const struct regmap_config sa8775p_pcie_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_pcie_anoc = { + .config = &sa8775p_pcie_anoc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -2232,7 +2662,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; +static const struct regmap_config sa8775p_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_system_noc = { + .config = &sa8775p_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, From 295f58fdccd05b2d6da1f4a4f81952ccb565c4dc Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 26 Sep 2025 12:12:09 +0530 Subject: [PATCH 131/304] interconnect: qcom: sdx75: Drop QPIC interconnect and BCM nodes As like other SDX SoCs, SDX75 SoC's QPIC BCM resource was modeled as a RPMh clock in clk-rpmh driver. However, for SDX75, this resource was also described as an interconnect and BCM node mistakenly. It is incorrect to describe the same resource in two different providers, as it will lead to votes from clients overriding each other. Hence, drop the QPIC interconnect and BCM nodes and let the clients use clk-rpmh driver to vote for this resource. Without this change, the NAND driver fails to probe on SDX75, as the interconnect sync state disables the QPIC nodes as there were no clients voting for this ICC resource. However, the NAND driver had already voted for this BCM resource through the clk-rpmh driver. Since both votes come from Linux, RPMh was unable to distinguish between these two and ends up disabling the QPIC resource during sync state. Cc: stable@vger.kernel.org Fixes: 3642b4e5cbfe ("interconnect: qcom: Add SDX75 interconnect provider driver") Signed-off-by: Raviteja Laggyshetty [mani: dropped the reference to bcm_qp0, reworded description] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Tested-by: Lakshmi Sowjanya D # on SDX75 Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-1-20d6820e455c@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdx75.c | 26 -------------------------- drivers/interconnect/qcom/sdx75.h | 2 -- 2 files changed, 28 deletions(-) diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c index 7ef1f17f3292..2def75f67eb8 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -16,15 +16,6 @@ #include "icc-rpmh.h" #include "sdx75.h" -static struct qcom_icc_node qpic_core_master = { - .name = "qpic_core_master", - .id = SDX75_MASTER_QPIC_CORE, - .channels = 1, - .buswidth = 4, - .num_links = 1, - .links = { SDX75_SLAVE_QPIC_CORE }, -}; - static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", .id = SDX75_MASTER_QUP_CORE_0, @@ -375,14 +366,6 @@ static struct qcom_icc_node xm_usb3 = { .links = { SDX75_SLAVE_A1NOC_CFG }, }; -static struct qcom_icc_node qpic_core_slave = { - .name = "qpic_core_slave", - .id = SDX75_SLAVE_QPIC_CORE, - .channels = 1, - .buswidth = 4, - .num_links = 0, -}; - static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", .id = SDX75_SLAVE_QUP_CORE_0, @@ -831,12 +814,6 @@ static struct qcom_icc_bcm bcm_mc0 = { .nodes = { &ebi }, }; -static struct qcom_icc_bcm bcm_qp0 = { - .name = "QP0", - .num_nodes = 1, - .nodes = { &qpic_core_slave }, -}; - static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .keepalive = true, @@ -898,14 +875,11 @@ static struct qcom_icc_bcm bcm_sn4 = { }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { - &bcm_qp0, &bcm_qup0, }; static struct qcom_icc_node * const clk_virt_nodes[] = { - [MASTER_QPIC_CORE] = &qpic_core_master, [MASTER_QUP_CORE_0] = &qup0_core_master, - [SLAVE_QPIC_CORE] = &qpic_core_slave, [SLAVE_QUP_CORE_0] = &qup0_core_slave, }; diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h index 24e887159920..34f51add59dc 100644 --- a/drivers/interconnect/qcom/sdx75.h +++ b/drivers/interconnect/qcom/sdx75.h @@ -33,7 +33,6 @@ #define SDX75_MASTER_QDSS_ETR 24 #define SDX75_MASTER_QDSS_ETR_1 25 #define SDX75_MASTER_QPIC 26 -#define SDX75_MASTER_QPIC_CORE 27 #define SDX75_MASTER_QUP_0 28 #define SDX75_MASTER_QUP_CORE_0 29 #define SDX75_MASTER_SDCC_1 30 @@ -76,7 +75,6 @@ #define SDX75_SLAVE_QDSS_CFG 67 #define SDX75_SLAVE_QDSS_STM 68 #define SDX75_SLAVE_QPIC 69 -#define SDX75_SLAVE_QPIC_CORE 70 #define SDX75_SLAVE_QUP_0 71 #define SDX75_SLAVE_QUP_CORE_0 72 #define SDX75_SLAVE_SDCC_1 73 From 11e15a6f3287711e637e208df7089c710cef82b5 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 26 Sep 2025 12:12:10 +0530 Subject: [PATCH 132/304] dt-bindings: interconnect: qcom: Drop QPIC_CORE IDs As like other SDX targets, SDX75 QPIC BCM resource is also modeled as a RPMh clock in clk-rpmh driver. However, for SDX75, this resource was also described as an interconnect node mistakenly. Hence, drop the QPIC interconnect IDs and let the clients use clk-rpmh driver to vote for this resource. Even though this change is an ABI break, it is necessary to avoid describing the same resource provider in two different drivers, as it may lead to votes from clients overriding each other. Fixes: 956329ec7c5e ("dt-bindings: interconnect: Add compatibles for SDX75") Signed-off-by: Raviteja Laggyshetty [mani: kept the QUP defines value unchanged] Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-2-20d6820e455c@oss.qualcomm.com Signed-off-by: Georgi Djakov --- include/dt-bindings/interconnect/qcom,sdx75.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/dt-bindings/interconnect/qcom,sdx75.h b/include/dt-bindings/interconnect/qcom,sdx75.h index e903f5f3dd8f..0e19ee8f1687 100644 --- a/include/dt-bindings/interconnect/qcom,sdx75.h +++ b/include/dt-bindings/interconnect/qcom,sdx75.h @@ -6,9 +6,7 @@ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H -#define MASTER_QPIC_CORE 0 #define MASTER_QUP_CORE_0 1 -#define SLAVE_QPIC_CORE 2 #define SLAVE_QUP_CORE_0 3 #define MASTER_LLCC 0 From 6bfe104fd0f94d0248af22c256ce725ee087157b Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Fri, 10 Oct 2025 23:14:47 +0800 Subject: [PATCH 133/304] interconnect: debugfs: Fix incorrect error handling for NULL path The icc_commit_set() function, used by the debugfs interface, checks the validity of the global cur_path pointer using IS_ERR_OR_NULL(). However, in the specific case where cur_path is NULL, while IS_ERR_OR_NULL(NULL) correctly evaluates to true, the subsequent call to PTR_ERR(NULL) returns 0. This causes the function to return a success code (0) instead of an error, misleading the user into believing their bandwidth request was successfully committed when, in fact, no operation was performed. Fix this by adding an explicit check to return -EINVAL if cur_path is NULL. This prevents silent failures and ensures that an invalid operational sequence is immediately and clearly reported as an error. Fixes: 770c69f037c1 ("interconnect: Add debugfs test client") Signed-off-by: Kuan-Wei Chiu Link: https://lore.kernel.org/r/20251010151447.2289779-1-visitorckw@gmail.com Signed-off-by: Georgi Djakov --- drivers/interconnect/debugfs-client.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/debugfs-client.c b/drivers/interconnect/debugfs-client.c index bc3fd8a7b9eb..778deeb4a7e8 100644 --- a/drivers/interconnect/debugfs-client.c +++ b/drivers/interconnect/debugfs-client.c @@ -117,7 +117,12 @@ static int icc_commit_set(void *data, u64 val) mutex_lock(&debugfs_lock); - if (IS_ERR_OR_NULL(cur_path)) { + if (!cur_path) { + ret = -EINVAL; + goto out; + } + + if (IS_ERR(cur_path)) { ret = PTR_ERR(cur_path); goto out; } From 7463f5ad36d8073a0e740433faf97f030d226398 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 31 Oct 2025 03:38:47 +0000 Subject: [PATCH 134/304] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Kaanapali SoC Document the RPMh Network-On-Chip Interconnect of the Kaanapali platform. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251031-knp-interconnect-v4-1-568bba2cb3e5@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../interconnect/qcom,kaanapali-rpmh.yaml | 124 +++++++++++++++ .../interconnect/qcom,kaanapali-rpmh.h | 149 ++++++++++++++++++ 2 files changed, 273 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml new file mode 100644 index 000000000000..2c3b2fd81a74 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,kaanapali-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Kaanapali + +maintainers: + - Raviteja Laggyshetty + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h + +properties: + compatible: + enum: + - qcom,kaanapali-aggre-noc + - qcom,kaanapali-clk-virt + - qcom,kaanapali-cnoc-main + - qcom,kaanapali-cnoc-cfg + - qcom,kaanapali-gem-noc + - qcom,kaanapali-lpass-ag-noc + - qcom,kaanapali-lpass-lpiaon-noc + - qcom,kaanapali-lpass-lpicx-noc + - qcom,kaanapali-mc-virt + - qcom,kaanapali-mmss-noc + - qcom,kaanapali-nsp-noc + - qcom,kaanapali-pcie-anoc + - qcom,kaanapali-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-clk-virt + - qcom,kaanapali-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-aggre-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-aggre-noc + - qcom,kaanapali-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-0 { + compatible = "qcom,kaanapali-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@16e0000 { + compatible = "qcom,kaanapali-aggre-noc"; + reg = <0x016e0000 0x42400>; + #interconnect-cells = <2>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h b/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h new file mode 100644 index 000000000000..dde3f9abd677 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H + +#define MASTER_QSPI_0 0 +#define MASTER_CRYPTO 1 +#define MASTER_QUP_1 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB3 5 +#define MASTER_QUP_2 6 +#define MASTER_QUP_3 7 +#define MASTER_QUP_4 8 +#define MASTER_IPA 9 +#define MASTER_SOCCP_PROC 10 +#define MASTER_SP 11 +#define MASTER_QDSS_ETR 12 +#define MASTER_QDSS_ETR_1 13 +#define MASTER_SDCC_2 14 +#define SLAVE_A1NOC_SNOC 15 +#define SLAVE_A2NOC_SNOC 16 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define MASTER_QUP_CORE_4 4 +#define SLAVE_QUP_CORE_0 5 +#define SLAVE_QUP_CORE_1 6 +#define SLAVE_QUP_CORE_2 7 +#define SLAVE_QUP_CORE_3 8 +#define SLAVE_QUP_CORE_4 9 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_CRYPTO_0_CFG 5 +#define SLAVE_DISPLAY_CFG 6 +#define SLAVE_EVA_CFG 7 +#define SLAVE_GFX3D_CFG 8 +#define SLAVE_I2C 9 +#define SLAVE_I3C_IBI0_CFG 10 +#define SLAVE_I3C_IBI1_CFG 11 +#define SLAVE_IMEM_CFG 12 +#define SLAVE_IPC_ROUTER_CFG 13 +#define SLAVE_CNOC_MSS 14 +#define SLAVE_PCIE_CFG 15 +#define SLAVE_PRNG 16 +#define SLAVE_QDSS_CFG 17 +#define SLAVE_QSPI_0 18 +#define SLAVE_QUP_1 19 +#define SLAVE_QUP_2 20 +#define SLAVE_QUP_3 21 +#define SLAVE_QUP_4 22 +#define SLAVE_SDCC_2 23 +#define SLAVE_SDCC_4 24 +#define SLAVE_SPSS_CFG 25 +#define SLAVE_TCSR 26 +#define SLAVE_TLMM 27 +#define SLAVE_UFS_MEM_CFG 28 +#define SLAVE_USB3 29 +#define SLAVE_VENUS_CFG 30 +#define SLAVE_VSENSE_CTRL_CFG 31 +#define SLAVE_CNOC_MNOC_CFG 32 +#define SLAVE_PCIE_ANOC_CFG 33 +#define SLAVE_QDSS_STM 34 +#define SLAVE_TCU 35 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_FENCE 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_APPSS 7 +#define SLAVE_CNOC_CFG 8 +#define SLAVE_DDRSS_CFG 9 +#define SLAVE_BOOT_IMEM 10 +#define SLAVE_IMEM 11 +#define SLAVE_PCIE_0 12 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_QPACE 10 +#define MASTER_SNOC_SF_MEM_NOC 11 +#define MASTER_WLAN_Q6 12 +#define MASTER_GIC 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_MEM_NOC_PCIE_SNOC 16 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP 4 +#define MASTER_MDSS_DCP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO_CV_PROC 7 +#define MASTER_VIDEO_EVA 8 +#define MASTER_VIDEO_MVP 9 +#define MASTER_VIDEO_V_PROC 10 +#define MASTER_CNOC_MNOC_CFG 11 +#define SLAVE_MNOC_HF_MEM_NOC 12 +#define SLAVE_MNOC_SF_MEM_NOC 13 +#define SLAVE_SERVICE_MNOC 14 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define SLAVE_ANOC_PCIE_GEM_NOC 2 +#define SLAVE_SERVICE_PCIE_ANOC 3 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_APSS_NOC 2 +#define MASTER_CNOC_SNOC 3 +#define SLAVE_SNOC_GEM_NOC_SF 4 + +#endif From c7f8ff611a14be1cc7591b6aa0d66d5f71f5c4ac Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 31 Oct 2025 03:38:48 +0000 Subject: [PATCH 135/304] interconnect: qcom: add Kaanapali interconnect provider driver Add driver for the Qualcomm interconnect buses found in Kaanapali based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Signed-off-by: Raviteja Laggyshetty Link: https://lore.kernel.org/r/20251031-knp-interconnect-v4-2-568bba2cb3e5@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/kaanapali.c | 1868 +++++++++++++++++++++++++ 3 files changed, 1879 insertions(+) create mode 100644 drivers/interconnect/qcom/kaanapali.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 5b4bb9f1382b..bb1cb8a640c1 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -17,6 +17,15 @@ config INTERCONNECT_QCOM_GLYMUR This is a driver for the Qualcomm Network-on-Chip on glymur-based platforms. +config INTERCONNECT_QCOM_KAANAPALI + tristate "Qualcomm KAANAPALI interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on kaanapali-based + platforms. + config INTERCONNECT_QCOM_MSM8909 tristate "Qualcomm MSM8909 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index cf8cba73ee3e..6eedff043b41 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o interconnect_qcom-y := icc-common.o icc-bcm-voter-objs := bcm-voter.o qnoc-glymur-objs := glymur.o +qnoc-kaanapali-objs := kaanapali.o qnoc-milos-objs := milos.o qnoc-msm8909-objs := msm8909.o qnoc-msm8916-objs := msm8916.o @@ -48,6 +49,7 @@ icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o +obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o diff --git a/drivers/interconnect/qcom/kaanapali.c b/drivers/interconnect/qcom/kaanapali.c new file mode 100644 index 000000000000..c6b4902e057f --- /dev/null +++ b/drivers/interconnect/qcom/kaanapali.c @@ -0,0 +1,1868 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup3_core_slave = { + .name = "qup3_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup4_core_slave = { + .name = "qup4_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_eva_cfg = { + .name = "qhs_eva_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_i2c = { + .name = "qhs_i2c", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi0_cfg = { + .name = "qhs_i3c_ibi0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi1_cfg = { + .name = "qhs_i3c_ibi1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg = { + .name = "qhs_pcie_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup3 = { + .name = "qhs_qup3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup4 = { + .name = "qhs_qup4", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router_fence = { + .name = "qhs_ipc_router_fence", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_soccp = { + .name = "qhs_soccp", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apss = { + .name = "qns_apss", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qss_ddrss_cfg = { + .name = "qss_ddrss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc = { + .name = "srvc_pcie_aggre_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave }, +}; + +static struct qcom_icc_node qup3_core_master = { + .name = "qup3_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qup3_core_slave }, +}; + +static struct qcom_icc_node qup4_core_master = { + .name = "qup4_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qup4_core_slave }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 4, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &ebi }, +}; + +static struct qcom_icc_node qsm_mnoc_cfg = { + .name = "qsm_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg = { + .name = "qsm_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_node qss_mnoc_cfg = { + .name = "qss_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qsm_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg = { + .name = "qss_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_anoc_cfg }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 4, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qsm_cfg = { + .name = "qsm_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 35, + .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup1, &qhs_qup2, + &qhs_qup3, &qhs_qup4, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_qpace = { + .name = "qnm_qpace", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14e000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x145000 }, + .prio = 4, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, +}; + +static struct qcom_icc_node qss_cfg = { + .name = "qss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qsm_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 10, + .link_nodes = (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router_fence, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13d000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13f000 }, + .prio = 6, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 4, + .buswidth = 32, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x31000, 0xb1000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc = { + .name = "qnm_lpass_gemnoc", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x141000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x33000, 0xb3000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x35000, 0xb5000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc = { + .name = "qnm_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x37000, 0xb7000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x143000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 2, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x147000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_wlan_q6 = { + .name = "qnm_wlan_q6", + .channels = 1, + .buswidth = 8, + .num_links = 3, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { + .name = "qns_lpass_ag_noc_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_gemnoc }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node qns_pcie_gemnoc = { + .name = "qns_pcie_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc = { + .name = "qnm_lpiaon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2a000, 0x2b000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { + .name = "qnm_camnoc_nrt_icp_sf", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2c000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { + .name = "qnm_camnoc_rt_cdm_sf", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x38000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2d000, 0x2e000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2f000, 0x30000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdss_dcp = { + .name = "qnm_mdss_dcp", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x39000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_vapss_hcp = { + .name = "qnm_vapss_hcp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu = { + .name = "qnm_video_cv_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x34000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_eva = { + .name = "qnm_video_eva", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x35000, 0x36000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp = { + .name = "qnm_video_mvp", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x32000, 0x33000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x37000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_nsp = { + .name = "qnm_nsp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 3, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_apss_noc = { + .name = "qnm_apss_noc", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1e000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_cnoc_data = { + .name = "qnm_cnoc_data", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1f000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc = { + .name = "qns_lpass_aggnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x36000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_qup1 = { + .name = "qxm_qup1", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xf000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x10000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup3 = { + .name = "qhm_qup3", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3c000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup4 = { + .name = "qhm_qup4", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3d000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x37000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp = { + .name = "qxm_soccp", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3b000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_sp = { + .name = "qxm_sp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x38000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x39000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3a000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc = { + .name = "qnm_lpass_lpinoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc = { + .name = "qns_lpi_aon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { + .name = "qnm_lpinoc_dsp_qns4m", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = (struct qcom_icc_node *[]) { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = BIT(3), + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .enable_mask = BIT(0), + .keepalive = true, + .num_nodes = 43, + .nodes = { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_cfg, &qss_pcie_anoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg, + &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_aoss, &qhs_ipa, + &qhs_ipc_router_fence, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 6, + .nodes = { &qhs_display_cfg, &qhs_i2c, + &qhs_qup1, &qhs_qup2, + &qhs_qup3, &qhs_qup4 }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .enable_mask = BIT(0), + .num_nodes = 2, + .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 = { + .name = "LP0", + .num_nodes = 2, + .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .enable_mask = BIT(0), + .num_nodes = 9, + .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, + &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, + &qnm_vapss_hcp, &qnm_video_cv_cpu, + &qnm_video_mvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qpc0 = { + .name = "QPC0", + .num_nodes = 1, + .nodes = { &qnm_qpace }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup3 = { + .name = "QUP3", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup4 = { + .name = "QUP4", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup4_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .enable_mask = BIT(0), + .num_nodes = 14, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_sf, + &qnm_wlan_q6, &xm_gic, + &qns_gem_noc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_bcm * const aggre_noc_bcms[] = { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre_noc_nodes[] = { + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_QUP_1] = &qxm_qup1, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3] = &xm_usb3, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_QUP_3] = &qhm_qup3, + [MASTER_QUP_4] = &qhm_qup4, + [MASTER_IPA] = &qxm_ipa, + [MASTER_SOCCP_PROC] = &qxm_soccp, + [MASTER_SP] = &qxm_sp, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_SDCC_2] = &xm_sdc2, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct regmap_config kaanapali_aggre_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x42400, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_aggre_noc = { + .config = &kaanapali_aggre_noc_regmap_config, + .nodes = aggre_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre_noc_nodes), + .bcms = aggre_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre_noc_bcms), + .qos_requires_clocks = true, + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, + &bcm_qup3, + &bcm_qup4, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [MASTER_QUP_CORE_3] = &qup3_core_master, + [MASTER_QUP_CORE_4] = &qup4_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, + [SLAVE_QUP_CORE_3] = &qup3_core_slave, + [SLAVE_QUP_CORE_4] = &qup4_core_slave, +}; + +static const struct qcom_icc_desc kaanapali_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] = { + [MASTER_CNOC_CFG] = &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_EVA_CFG] = &qhs_eva_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_I2C] = &qhs_i2c, + [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, + [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_QUP_3] = &qhs_qup3, + [SLAVE_QUP_4] = &qhs_qup4, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SPSS_CFG] = &qhs_spss_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct regmap_config kaanapali_cnoc_cfg_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x6200, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_cnoc_cfg = { + .config = &kaanapali_cnoc_cfg_regmap_config, + .nodes = cnoc_cfg_nodes, + .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), + .bcms = cnoc_cfg_bcms, + .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence, + [SLAVE_SOCCP] = &qhs_soccp, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_APPSS] = &qns_apss, + [SLAVE_CNOC_CFG] = &qss_cfg, + [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PCIE_0] = &xs_pcie, +}; + +static const struct regmap_config kaanapali_cnoc_main_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1a080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_cnoc_main = { + .config = &kaanapali_cnoc_main_regmap_config, + .nodes = cnoc_main_nodes, + .num_nodes = ARRAY_SIZE(cnoc_main_nodes), + .bcms = cnoc_main_bcms, + .num_bcms = ARRAY_SIZE(cnoc_main_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_qpc0, + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_QPACE] = &qnm_qpace, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_WLAN_Q6] = &qnm_wlan_q6, + [MASTER_GIC] = &xm_gic, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct regmap_config kaanapali_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x153080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_gem_noc = { + .config = &kaanapali_gem_noc_regmap_config, + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config kaanapali_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_lpass_ag_noc = { + .config = &kaanapali_lpass_ag_noc_regmap_config, + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { + [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, +}; + +static const struct regmap_config kaanapali_lpass_lpiaon_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x19080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_lpass_lpiaon_noc = { + .config = &kaanapali_lpass_lpiaon_noc_regmap_config, + .nodes = lpass_lpiaon_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms = lpass_lpiaon_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { + [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, +}; + +static const struct regmap_config kaanapali_lpass_lpicx_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x44080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_lpass_lpicx_noc = { + .config = &kaanapali_lpass_lpicx_noc_regmap_config, + .nodes = lpass_lpicx_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc kaanapali_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, + [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP] = &qnm_mdp, + [MASTER_MDSS_DCP] = &qnm_mdss_dcp, + [MASTER_CDSP_HCP] = &qnm_vapss_hcp, + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, + [MASTER_VIDEO_EVA] = &qnm_video_eva, + [MASTER_VIDEO_MVP] = &qnm_video_mvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct regmap_config kaanapali_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5b800, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_mmss_noc = { + .config = &kaanapali_mmss_noc_regmap_config, + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] = { + [MASTER_CDSP_PROC] = &qnm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, +}; + +static const struct regmap_config kaanapali_nsp_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x21280, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_nsp_noc = { + .config = &kaanapali_nsp_noc_regmap_config, + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] = &xm_pcie, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, +}; + +static const struct regmap_config kaanapali_pcie_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x11400, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_pcie_anoc = { + .config = &kaanapali_pcie_anoc_regmap_config, + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), + .qos_requires_clocks = true, + .alloc_dyn_id = true, +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_APSS_NOC] = &qnm_apss_noc, + [MASTER_CNOC_SNOC] = &qnm_cnoc_data, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, +}; + +static const struct regmap_config kaanapali_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_system_noc = { + .config = &kaanapali_system_noc_regmap_config, + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), + .alloc_dyn_id = true, +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,kaanapali-aggre-noc", .data = &kaanapali_aggre_noc }, + { .compatible = "qcom,kaanapali-clk-virt", .data = &kaanapali_clk_virt }, + { .compatible = "qcom,kaanapali-cnoc-cfg", .data = &kaanapali_cnoc_cfg }, + { .compatible = "qcom,kaanapali-cnoc-main", .data = &kaanapali_cnoc_main }, + { .compatible = "qcom,kaanapali-gem-noc", .data = &kaanapali_gem_noc }, + { .compatible = "qcom,kaanapali-lpass-ag-noc", .data = &kaanapali_lpass_ag_noc }, + { .compatible = "qcom,kaanapali-lpass-lpiaon-noc", .data = &kaanapali_lpass_lpiaon_noc }, + { .compatible = "qcom,kaanapali-lpass-lpicx-noc", .data = &kaanapali_lpass_lpicx_noc }, + { .compatible = "qcom,kaanapali-mc-virt", .data = &kaanapali_mc_virt }, + { .compatible = "qcom,kaanapali-mmss-noc", .data = &kaanapali_mmss_noc }, + { .compatible = "qcom,kaanapali-nsp-noc", .data = &kaanapali_nsp_noc }, + { .compatible = "qcom,kaanapali-pcie-anoc", .data = &kaanapali_pcie_anoc }, + { .compatible = "qcom,kaanapali-system-noc", .data = &kaanapali_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-kaanapali", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Kaanapali NoC driver"); +MODULE_LICENSE("GPL"); From fb6f1aaeb44b48debabfbb25f90565042d46ea6d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:17 +0200 Subject: [PATCH 136/304] interconnect: qcom: icc-rpmh: convert link_nodes to dynamic array Declaring link_nodes as a double-pointer results in a syntax sugar in the interconnect driver to typecast the array. Change the type of link_nodes field to the array to remove the need for the extra typecast. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-1-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/glymur.c | 204 +++++++++++++-------------- drivers/interconnect/qcom/icc-rpmh.h | 2 +- drivers/interconnect/qcom/milos.c | 130 ++++++++--------- drivers/interconnect/qcom/sa8775p.c | 186 ++++++++++++------------ 4 files changed, 261 insertions(+), 261 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom/glymur.c index cf20b5752dbb..104ac6c1bd36 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -457,7 +457,7 @@ static struct qcom_icc_node qup0_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { @@ -465,7 +465,7 @@ static struct qcom_icc_node qup1_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { @@ -473,7 +473,7 @@ static struct qcom_icc_node qup2_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node llcc_mc = { @@ -481,7 +481,7 @@ static struct qcom_icc_node llcc_mc = { .channels = 12, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &ebi }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qsm_mnoc_cfg = { @@ -489,7 +489,7 @@ static struct qcom_icc_node qsm_mnoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qsm_pcie_east_anoc_cfg = { @@ -497,7 +497,7 @@ static struct qcom_icc_node qsm_pcie_east_anoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_east_aggre_noc }, + .link_nodes = { &srvc_pcie_east_aggre_noc }, }; static struct qcom_icc_node qnm_hscnoc_pcie_east = { @@ -505,7 +505,7 @@ static struct qcom_icc_node qnm_hscnoc_pcie_east = { .channels = 1, .buswidth = 32, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1, + .link_nodes = { &xs_pcie_0, &xs_pcie_1, &xs_pcie_5 }, }; @@ -514,7 +514,7 @@ static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg = { .channels = 1, .buswidth = 4, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_east_ms_mpu_cfg, + .link_nodes = { &qhs_hscnoc_pcie_east_ms_mpu_cfg, &srvc_pcie_east }, }; @@ -523,7 +523,7 @@ static struct qcom_icc_node qsm_pcie_west_anoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_west_aggre_noc }, + .link_nodes = { &srvc_pcie_west_aggre_noc }, }; static struct qcom_icc_node qnm_hscnoc_pcie_west = { @@ -531,7 +531,7 @@ static struct qcom_icc_node qnm_hscnoc_pcie_west = { .channels = 1, .buswidth = 32, .num_links = 5, - .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_2, &xs_pcie_3a, + .link_nodes = { &xs_pcie_2, &xs_pcie_3a, &xs_pcie_3b, &xs_pcie_4, &xs_pcie_6 }, }; @@ -541,7 +541,7 @@ static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg = { .channels = 1, .buswidth = 4, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_west_ms_mpu_cfg, + .link_nodes = { &qhs_hscnoc_pcie_west_ms_mpu_cfg, &srvc_pcie_west }, }; @@ -550,7 +550,7 @@ static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_east_slave_cfg }, + .link_nodes = { &qsm_cnoc_pcie_east_slave_cfg }, }; static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = { @@ -558,7 +558,7 @@ static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_west_slave_cfg }, + .link_nodes = { &qsm_cnoc_pcie_west_slave_cfg }, }; static struct qcom_icc_node qss_mnoc_cfg = { @@ -566,7 +566,7 @@ static struct qcom_icc_node qss_mnoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_mnoc_cfg }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_pcie_east_anoc_cfg = { @@ -574,7 +574,7 @@ static struct qcom_icc_node qss_pcie_east_anoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_east_anoc_cfg }, + .link_nodes = { &qsm_pcie_east_anoc_cfg }, }; static struct qcom_icc_node qss_pcie_west_anoc_cfg = { @@ -582,7 +582,7 @@ static struct qcom_icc_node qss_pcie_west_anoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_west_anoc_cfg }, + .link_nodes = { &qsm_pcie_west_anoc_cfg }, }; static struct qcom_icc_node qns_llcc = { @@ -590,7 +590,7 @@ static struct qcom_icc_node qns_llcc = { .channels = 12, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie_east = { @@ -598,7 +598,7 @@ static struct qcom_icc_node qns_pcie_east = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_east }, + .link_nodes = { &qnm_hscnoc_pcie_east }, }; static struct qcom_icc_node qns_pcie_west = { @@ -606,7 +606,7 @@ static struct qcom_icc_node qns_pcie_west = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_west }, + .link_nodes = { &qnm_hscnoc_pcie_west }, }; static struct qcom_icc_node qsm_cfg = { @@ -614,7 +614,7 @@ static struct qcom_icc_node qsm_cfg = { .channels = 1, .buswidth = 4, .num_links = 51, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, &qhs_av1_enc_cfg, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_crypto0_cfg, @@ -654,7 +654,7 @@ static struct qcom_icc_node xm_gic = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qss_cfg = { @@ -662,7 +662,7 @@ static struct qcom_icc_node qss_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_cfg }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qnm_hscnoc_cnoc = { @@ -670,7 +670,7 @@ static struct qcom_icc_node qnm_hscnoc_cnoc = { .channels = 1, .buswidth = 16, .num_links = 8, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_ipc_router, + .link_nodes = { &qhs_aoss, &qhs_ipc_router, &qhs_soccp, &qhs_tme_cfg, &qns_apss, &qss_cfg, &qxs_boot_imem, &qxs_imem }, @@ -681,7 +681,7 @@ static struct qcom_icc_node qns_hscnoc_cnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_cnoc }, + .link_nodes = { &qnm_hscnoc_cnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { @@ -696,7 +696,7 @@ static struct qcom_icc_node alm_gpu_tcu = { .prio_fwd_disable = 1, }, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_pcie_qtc = { @@ -711,7 +711,7 @@ static struct qcom_icc_node alm_pcie_qtc = { .prio_fwd_disable = 1, }, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { @@ -726,7 +726,7 @@ static struct qcom_icc_node alm_sys_tcu = { .prio_fwd_disable = 1, }, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { @@ -734,7 +734,7 @@ static struct qcom_icc_node chm_apps = { .channels = 6, .buswidth = 32, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -750,7 +750,7 @@ static struct qcom_icc_node qnm_aggre_noc_east = { .prio_fwd_disable = 1, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -766,7 +766,7 @@ static struct qcom_icc_node qnm_gpu = { .prio_fwd_disable = 1, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -782,7 +782,7 @@ static struct qcom_icc_node qnm_lpass = { .prio_fwd_disable = 0, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -798,7 +798,7 @@ static struct qcom_icc_node qnm_mnoc_hf = { .prio_fwd_disable = 0, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -814,7 +814,7 @@ static struct qcom_icc_node qnm_mnoc_sf = { .prio_fwd_disable = 0, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -830,7 +830,7 @@ static struct qcom_icc_node qnm_nsp_noc = { .prio_fwd_disable = 1, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -846,7 +846,7 @@ static struct qcom_icc_node qnm_pcie_east = { .prio_fwd_disable = 1, }, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie_west = { @@ -861,7 +861,7 @@ static struct qcom_icc_node qnm_pcie_west = { .prio_fwd_disable = 1, }, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { @@ -876,7 +876,7 @@ static struct qcom_icc_node qnm_snoc_sf = { .prio_fwd_disable = 1, }, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -885,7 +885,7 @@ static struct qcom_icc_node qxm_wlan_q6 = { .channels = 1, .buswidth = 8, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; @@ -894,7 +894,7 @@ static struct qcom_icc_node qns_a4noc_hscnoc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre_noc_east }, + .link_nodes = { &qnm_aggre_noc_east }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { @@ -902,7 +902,7 @@ static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass }, + .link_nodes = { &qnm_lpass }, }; static struct qcom_icc_node qns_mem_noc_hf = { @@ -910,7 +910,7 @@ static struct qcom_icc_node qns_mem_noc_hf = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { @@ -918,7 +918,7 @@ static struct qcom_icc_node qns_mem_noc_sf = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_nsp_hscnoc = { @@ -926,7 +926,7 @@ static struct qcom_icc_node qns_nsp_hscnoc = { .channels = 4, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_nsp_noc }, + .link_nodes = { &qnm_nsp_noc }, }; static struct qcom_icc_node qns_pcie_east_mem_noc = { @@ -934,7 +934,7 @@ static struct qcom_icc_node qns_pcie_east_mem_noc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie_east }, + .link_nodes = { &qnm_pcie_east }, }; static struct qcom_icc_node qns_pcie_west_mem_noc = { @@ -942,7 +942,7 @@ static struct qcom_icc_node qns_pcie_west_mem_noc = { .channels = 1, .buswidth = 64, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie_west }, + .link_nodes = { &qnm_pcie_west }, }; static struct qcom_icc_node qns_gemnoc_sf = { @@ -950,7 +950,7 @@ static struct qcom_icc_node qns_gemnoc_sf = { .channels = 1, .buswidth = 64, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node xm_usb3_0 = { @@ -965,7 +965,7 @@ static struct qcom_icc_node xm_usb3_0 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes = { &qns_a4noc_hscnoc }, }; static struct qcom_icc_node xm_usb3_1 = { @@ -980,7 +980,7 @@ static struct qcom_icc_node xm_usb3_1 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes = { &qns_a4noc_hscnoc }, }; static struct qcom_icc_node xm_usb4_0 = { @@ -995,7 +995,7 @@ static struct qcom_icc_node xm_usb4_0 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes = { &qns_a4noc_hscnoc }, }; static struct qcom_icc_node xm_usb4_1 = { @@ -1010,7 +1010,7 @@ static struct qcom_icc_node xm_usb4_1 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes = { &qns_a4noc_hscnoc }, }; static struct qcom_icc_node qnm_lpiaon_noc = { @@ -1018,7 +1018,7 @@ static struct qcom_icc_node qnm_lpiaon_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_av1_enc = { @@ -1033,7 +1033,7 @@ static struct qcom_icc_node qnm_av1_enc = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_hf = { @@ -1048,7 +1048,7 @@ static struct qcom_icc_node qnm_camnoc_hf = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { @@ -1063,7 +1063,7 @@ static struct qcom_icc_node qnm_camnoc_icp = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { @@ -1078,7 +1078,7 @@ static struct qcom_icc_node qnm_camnoc_sf = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_eva = { @@ -1093,7 +1093,7 @@ static struct qcom_icc_node qnm_eva = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { @@ -1108,7 +1108,7 @@ static struct qcom_icc_node qnm_mdp = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_vapss_hcp = { @@ -1116,7 +1116,7 @@ static struct qcom_icc_node qnm_vapss_hcp = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video = { @@ -1131,7 +1131,7 @@ static struct qcom_icc_node qnm_video = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { @@ -1146,7 +1146,7 @@ static struct qcom_icc_node qnm_video_cv_cpu = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { @@ -1161,7 +1161,7 @@ static struct qcom_icc_node qnm_video_v_cpu = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_nsp = { @@ -1169,7 +1169,7 @@ static struct qcom_icc_node qnm_nsp = { .channels = 4, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_nsp_hscnoc }, + .link_nodes = { &qns_nsp_hscnoc }, }; static struct qcom_icc_node xm_pcie_0 = { @@ -1184,7 +1184,7 @@ static struct qcom_icc_node xm_pcie_0 = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, + .link_nodes = { &qns_pcie_east_mem_noc }, }; static struct qcom_icc_node xm_pcie_1 = { @@ -1199,7 +1199,7 @@ static struct qcom_icc_node xm_pcie_1 = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, + .link_nodes = { &qns_pcie_east_mem_noc }, }; static struct qcom_icc_node xm_pcie_5 = { @@ -1214,7 +1214,7 @@ static struct qcom_icc_node xm_pcie_5 = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, + .link_nodes = { &qns_pcie_east_mem_noc }, }; static struct qcom_icc_node xm_pcie_2 = { @@ -1229,7 +1229,7 @@ static struct qcom_icc_node xm_pcie_2 = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes = { &qns_pcie_west_mem_noc }, }; static struct qcom_icc_node xm_pcie_3a = { @@ -1244,7 +1244,7 @@ static struct qcom_icc_node xm_pcie_3a = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes = { &qns_pcie_west_mem_noc }, }; static struct qcom_icc_node xm_pcie_3b = { @@ -1259,7 +1259,7 @@ static struct qcom_icc_node xm_pcie_3b = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes = { &qns_pcie_west_mem_noc }, }; static struct qcom_icc_node xm_pcie_4 = { @@ -1274,7 +1274,7 @@ static struct qcom_icc_node xm_pcie_4 = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes = { &qns_pcie_west_mem_noc }, }; static struct qcom_icc_node xm_pcie_6 = { @@ -1289,7 +1289,7 @@ static struct qcom_icc_node xm_pcie_6 = { .prio_fwd_disable = 0, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes = { &qns_pcie_west_mem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { @@ -1297,7 +1297,7 @@ static struct qcom_icc_node qnm_aggre1_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { @@ -1305,7 +1305,7 @@ static struct qcom_icc_node qnm_aggre2_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre3_noc = { @@ -1313,7 +1313,7 @@ static struct qcom_icc_node qnm_aggre3_noc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_nsi_noc = { @@ -1328,7 +1328,7 @@ static struct qcom_icc_node qnm_nsi_noc = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_oobmss = { @@ -1343,7 +1343,7 @@ static struct qcom_icc_node qnm_oobmss = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qns_a1noc_snoc = { @@ -1351,7 +1351,7 @@ static struct qcom_icc_node qns_a1noc_snoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { @@ -1359,7 +1359,7 @@ static struct qcom_icc_node qns_a2noc_snoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_a3noc_snoc = { @@ -1367,7 +1367,7 @@ static struct qcom_icc_node qns_a3noc_snoc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre3_noc }, + .link_nodes = { &qnm_aggre3_noc }, }; static struct qcom_icc_node qns_lpass_aggnoc = { @@ -1375,7 +1375,7 @@ static struct qcom_icc_node qns_lpass_aggnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpiaon_noc }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_system_noc = { @@ -1383,7 +1383,7 @@ static struct qcom_icc_node qns_system_noc = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_nsi_noc }, + .link_nodes = { &qnm_nsi_noc }, }; static struct qcom_icc_node qns_oobmss_snoc = { @@ -1391,7 +1391,7 @@ static struct qcom_icc_node qns_oobmss_snoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_oobmss }, + .link_nodes = { &qnm_oobmss }, }; static struct qcom_icc_node qxm_crypto = { @@ -1406,7 +1406,7 @@ static struct qcom_icc_node qxm_crypto = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_soccp = { @@ -1421,7 +1421,7 @@ static struct qcom_icc_node qxm_soccp = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { @@ -1436,7 +1436,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { @@ -1451,7 +1451,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { @@ -1466,7 +1466,7 @@ static struct qcom_icc_node xm_ufs_mem = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_2 = { @@ -1481,7 +1481,7 @@ static struct qcom_icc_node xm_usb3_2 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb4_2 = { @@ -1496,7 +1496,7 @@ static struct qcom_icc_node xm_usb4_2 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qspi = { @@ -1511,7 +1511,7 @@ static struct qcom_icc_node qhm_qspi = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { @@ -1526,7 +1526,7 @@ static struct qcom_icc_node qhm_qup0 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { @@ -1541,7 +1541,7 @@ static struct qcom_icc_node qhm_qup1 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { @@ -1556,7 +1556,7 @@ static struct qcom_icc_node qhm_qup2 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node qxm_sp = { @@ -1564,7 +1564,7 @@ static struct qcom_icc_node qxm_sp = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { @@ -1579,7 +1579,7 @@ static struct qcom_icc_node xm_sdc2 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { @@ -1594,7 +1594,7 @@ static struct qcom_icc_node xm_sdc4 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node xm_usb2_0 = { @@ -1609,7 +1609,7 @@ static struct qcom_icc_node xm_usb2_0 = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node xm_usb3_mp = { @@ -1624,7 +1624,7 @@ static struct qcom_icc_node xm_usb3_mp = { .prio_fwd_disable = 1, }, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes = { &qns_a3noc_snoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { @@ -1632,7 +1632,7 @@ static struct qcom_icc_node qnm_lpass_lpinoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_aggnoc }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node xm_cpucp = { @@ -1640,7 +1640,7 @@ static struct qcom_icc_node xm_cpucp = { .channels = 1, .buswidth = 8, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_system_noc, &srvc_nsinoc }, + .link_nodes = { &qns_system_noc, &srvc_nsinoc }, }; static struct qcom_icc_node xm_mem_sp = { @@ -1648,7 +1648,7 @@ static struct qcom_icc_node xm_mem_sp = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_oobmss_snoc }, + .link_nodes = { &qns_oobmss_snoc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { @@ -1656,7 +1656,7 @@ static struct qcom_icc_node qns_lpi_aon_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_lpinoc }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { @@ -1664,7 +1664,7 @@ static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_lpi_aon_noc }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_bcm bcm_acv = { diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 307f48412563..b72939cceba3 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -98,7 +98,6 @@ struct qcom_icc_node { const char *name; u16 links[MAX_LINKS]; u16 id; - struct qcom_icc_node **link_nodes; struct icc_node *node; u16 num_links; u16 channels; @@ -108,6 +107,7 @@ struct qcom_icc_node { struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE]; size_t num_bcms; const struct qcom_icc_qosbox *qosbox; + struct qcom_icc_node *link_nodes[]; }; /** diff --git a/drivers/interconnect/qcom/milos.c b/drivers/interconnect/qcom/milos.c index 167d479f7764..814ec0517f6b 100644 --- a/drivers/interconnect/qcom/milos.c +++ b/drivers/interconnect/qcom/milos.c @@ -151,7 +151,7 @@ static struct qcom_icc_node qhm_qup1 = { .buswidth = 4, .qosbox = &qhm_qup1_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox xm_ufs_mem_qos = { @@ -168,7 +168,7 @@ static struct qcom_icc_node xm_ufs_mem = { .buswidth = 8, .qosbox = &xm_ufs_mem_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox xm_usb3_0_qos = { @@ -185,7 +185,7 @@ static struct qcom_icc_node xm_usb3_0 = { .buswidth = 8, .qosbox = &xm_usb3_0_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox qhm_qdss_bam_qos = { @@ -202,7 +202,7 @@ static struct qcom_icc_node qhm_qdss_bam = { .buswidth = 4, .qosbox = &qhm_qdss_bam_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qhm_qspi_qos = { @@ -219,7 +219,7 @@ static struct qcom_icc_node qhm_qspi = { .buswidth = 4, .qosbox = &qhm_qspi_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qhm_qup0_qos = { @@ -236,7 +236,7 @@ static struct qcom_icc_node qhm_qup0 = { .buswidth = 4, .qosbox = &qhm_qup0_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qxm_crypto_qos = { @@ -253,7 +253,7 @@ static struct qcom_icc_node qxm_crypto = { .buswidth = 8, .qosbox = &qxm_crypto_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qxm_ipa_qos = { @@ -270,7 +270,7 @@ static struct qcom_icc_node qxm_ipa = { .buswidth = 8, .qosbox = &qxm_ipa_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { @@ -287,7 +287,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = { .buswidth = 8, .qosbox = &xm_qdss_etr_0_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { @@ -304,7 +304,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = { .buswidth = 8, .qosbox = &xm_qdss_etr_1_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_sdc1_qos = { @@ -321,7 +321,7 @@ static struct qcom_icc_node xm_sdc1 = { .buswidth = 8, .qosbox = &xm_sdc1_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_sdc2_qos = { @@ -338,7 +338,7 @@ static struct qcom_icc_node xm_sdc2 = { .buswidth = 8, .qosbox = &xm_sdc2_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { @@ -346,7 +346,7 @@ static struct qcom_icc_node qup0_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { @@ -354,7 +354,7 @@ static struct qcom_icc_node qup1_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qsm_cfg = { @@ -362,7 +362,7 @@ static struct qcom_icc_node qsm_cfg = { .channels = 1, .buswidth = 4, .num_links = 35, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mxa, &qhs_crypto0_cfg, &qhs_cx_rdpm, @@ -387,7 +387,7 @@ static struct qcom_icc_node qnm_gemnoc_cnoc = { .channels = 1, .buswidth = 16, .num_links = 14, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_display_cfg, + .link_nodes = { &qhs_aoss, &qhs_display_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_prng, &qhs_tme_cfg, @@ -401,7 +401,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = { .channels = 1, .buswidth = 8, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_qosbox alm_gpu_tcu_qos = { @@ -418,7 +418,7 @@ static struct qcom_icc_node alm_gpu_tcu = { .buswidth = 8, .qosbox = &alm_gpu_tcu_qos, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox alm_sys_tcu_qos = { @@ -435,7 +435,7 @@ static struct qcom_icc_node alm_sys_tcu = { .buswidth = 8, .qosbox = &alm_sys_tcu_qos, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { @@ -443,7 +443,7 @@ static struct qcom_icc_node chm_apps = { .channels = 3, .buswidth = 32, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -461,7 +461,7 @@ static struct qcom_icc_node qnm_gpu = { .buswidth = 32, .qosbox = &qnm_gpu_qos, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { @@ -478,7 +478,7 @@ static struct qcom_icc_node qnm_lpass_gemnoc = { .buswidth = 16, .qosbox = &qnm_lpass_gemnoc_qos, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -487,7 +487,7 @@ static struct qcom_icc_node qnm_mdsp = { .channels = 1, .buswidth = 16, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -505,7 +505,7 @@ static struct qcom_icc_node qnm_mnoc_hf = { .buswidth = 32, .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { @@ -522,7 +522,7 @@ static struct qcom_icc_node qnm_mnoc_sf = { .buswidth = 32, .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { @@ -539,7 +539,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = { .buswidth = 32, .qosbox = &qnm_nsp_gemnoc_qos, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -557,7 +557,7 @@ static struct qcom_icc_node qnm_pcie = { .buswidth = 8, .qosbox = &qnm_pcie_qos, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_snoc_gc_qos = { @@ -574,7 +574,7 @@ static struct qcom_icc_node qnm_snoc_gc = { .buswidth = 8, .qosbox = &qnm_snoc_gc_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_qosbox qnm_snoc_sf_qos = { @@ -591,7 +591,7 @@ static struct qcom_icc_node qnm_snoc_sf = { .buswidth = 16, .qosbox = &qnm_snoc_sf_qos, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -600,7 +600,7 @@ static struct qcom_icc_node qxm_wlan_q6 = { .channels = 1, .buswidth = 8, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -609,7 +609,7 @@ static struct qcom_icc_node qxm_lpass_dsp = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node llcc_mc = { @@ -617,7 +617,7 @@ static struct qcom_icc_node llcc_mc = { .channels = 2, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &ebi }, + .link_nodes = { &ebi }, }; static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { @@ -634,7 +634,7 @@ static struct qcom_icc_node qnm_camnoc_hf = { .buswidth = 32, .qosbox = &qnm_camnoc_hf_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { @@ -651,7 +651,7 @@ static struct qcom_icc_node qnm_camnoc_icp = { .buswidth = 8, .qosbox = &qnm_camnoc_icp_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { @@ -668,7 +668,7 @@ static struct qcom_icc_node qnm_camnoc_sf = { .buswidth = 32, .qosbox = &qnm_camnoc_sf_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_mdp_qos = { @@ -685,7 +685,7 @@ static struct qcom_icc_node qnm_mdp = { .buswidth = 32, .qosbox = &qnm_mdp_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_qosbox qnm_video_qos = { @@ -702,7 +702,7 @@ static struct qcom_icc_node qnm_video = { .buswidth = 32, .qosbox = &qnm_video_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_hf_mnoc_cfg = { @@ -710,7 +710,7 @@ static struct qcom_icc_node qsm_hf_mnoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_hf }, + .link_nodes = { &srvc_mnoc_hf }, }; static struct qcom_icc_node qsm_sf_mnoc_cfg = { @@ -718,7 +718,7 @@ static struct qcom_icc_node qsm_sf_mnoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_sf }, + .link_nodes = { &srvc_mnoc_sf }, }; static struct qcom_icc_node qxm_nsp = { @@ -726,7 +726,7 @@ static struct qcom_icc_node qxm_nsp = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_nsp_gemnoc }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qsm_pcie_anoc_cfg = { @@ -734,7 +734,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_aggre_noc }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_qosbox xm_pcie3_0_qos = { @@ -751,7 +751,7 @@ static struct qcom_icc_node xm_pcie3_0 = { .buswidth = 8, .qosbox = &xm_pcie3_0_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_qosbox xm_pcie3_1_qos = { @@ -768,7 +768,7 @@ static struct qcom_icc_node xm_pcie3_1 = { .buswidth = 8, .qosbox = &xm_pcie3_1_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { @@ -776,7 +776,7 @@ static struct qcom_icc_node qnm_aggre1_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { @@ -784,7 +784,7 @@ static struct qcom_icc_node qnm_aggre2_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_qosbox qnm_apss_noc_qos = { @@ -801,7 +801,7 @@ static struct qcom_icc_node qnm_apss_noc = { .buswidth = 4, .qosbox = &qnm_apss_noc_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_qosbox qnm_cnoc_data_qos = { @@ -818,7 +818,7 @@ static struct qcom_icc_node qnm_cnoc_data = { .buswidth = 8, .qosbox = &qnm_cnoc_data_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_qosbox qxm_pimem_qos = { @@ -835,7 +835,7 @@ static struct qcom_icc_node qxm_pimem = { .buswidth = 8, .qosbox = &qxm_pimem_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_qosbox xm_gic_qos = { @@ -852,7 +852,7 @@ static struct qcom_icc_node xm_gic = { .buswidth = 8, .qosbox = &xm_gic_qos, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { @@ -860,7 +860,7 @@ static struct qcom_icc_node qns_a1noc_snoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { @@ -868,7 +868,7 @@ static struct qcom_icc_node qns_a2noc_snoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { @@ -1079,7 +1079,7 @@ static struct qcom_icc_node qss_mnoc_hf_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_hf_mnoc_cfg }, + .link_nodes = { &qsm_hf_mnoc_cfg }, }; static struct qcom_icc_node qss_mnoc_sf_cfg = { @@ -1087,7 +1087,7 @@ static struct qcom_icc_node qss_mnoc_sf_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_sf_mnoc_cfg }, + .link_nodes = { &qsm_sf_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { @@ -1102,7 +1102,7 @@ static struct qcom_icc_node qss_pcie_anoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_anoc_cfg }, + .link_nodes = { &qsm_pcie_anoc_cfg }, }; static struct qcom_icc_node qss_wlan_q6_throttle_cfg = { @@ -1201,7 +1201,7 @@ static struct qcom_icc_node qss_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qsm_cfg }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qss_ddrss_cfg = { @@ -1251,7 +1251,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { @@ -1259,7 +1259,7 @@ static struct qcom_icc_node qns_llcc = { .channels = 2, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { @@ -1267,7 +1267,7 @@ static struct qcom_icc_node qns_pcie = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { @@ -1275,7 +1275,7 @@ static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_gemnoc }, + .link_nodes = { &qnm_lpass_gemnoc }, }; static struct qcom_icc_node ebi = { @@ -1290,7 +1290,7 @@ static struct qcom_icc_node qns_mem_noc_hf = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { @@ -1298,7 +1298,7 @@ static struct qcom_icc_node qns_mem_noc_sf = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc_hf = { @@ -1320,7 +1320,7 @@ static struct qcom_icc_node qns_nsp_gemnoc = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_nsp_gemnoc }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { @@ -1328,7 +1328,7 @@ static struct qcom_icc_node qns_pcie_mem_noc = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { @@ -1343,7 +1343,7 @@ static struct qcom_icc_node qns_gemnoc_gc = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_gc }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { @@ -1351,7 +1351,7 @@ static struct qcom_icc_node qns_gemnoc_sf = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_bcm bcm_acv = { diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index 04b4abbf4487..d144e8cb5d1e 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -214,7 +214,7 @@ static struct qcom_icc_node qxm_qup3 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_0 = { @@ -222,7 +222,7 @@ static struct qcom_icc_node xm_emac_0 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_1 = { @@ -230,7 +230,7 @@ static struct qcom_icc_node xm_emac_1 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc1 = { @@ -238,7 +238,7 @@ static struct qcom_icc_node xm_sdc1 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { @@ -246,7 +246,7 @@ static struct qcom_icc_node xm_ufs_mem = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb2_2 = { @@ -254,7 +254,7 @@ static struct qcom_icc_node xm_usb2_2 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { @@ -262,7 +262,7 @@ static struct qcom_icc_node xm_usb3_0 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { @@ -270,7 +270,7 @@ static struct qcom_icc_node xm_usb3_1 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { @@ -278,7 +278,7 @@ static struct qcom_icc_node qhm_qdss_bam = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { @@ -286,7 +286,7 @@ static struct qcom_icc_node qhm_qup0 = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { @@ -294,7 +294,7 @@ static struct qcom_icc_node qhm_qup1 = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { @@ -302,7 +302,7 @@ static struct qcom_icc_node qhm_qup2 = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc_datapath = { @@ -310,7 +310,7 @@ static struct qcom_icc_node qnm_cnoc_datapath = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto_0 = { @@ -318,7 +318,7 @@ static struct qcom_icc_node qxm_crypto_0 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto_1 = { @@ -326,7 +326,7 @@ static struct qcom_icc_node qxm_crypto_1 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { @@ -334,7 +334,7 @@ static struct qcom_icc_node qxm_ipa = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { @@ -342,7 +342,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { @@ -350,7 +350,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { @@ -358,7 +358,7 @@ static struct qcom_icc_node xm_ufs_card = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { @@ -366,7 +366,7 @@ static struct qcom_icc_node qup0_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { @@ -374,7 +374,7 @@ static struct qcom_icc_node qup1_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { @@ -382,7 +382,7 @@ static struct qcom_icc_node qup2_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qup3_core_master = { @@ -390,7 +390,7 @@ static struct qcom_icc_node qup3_core_master = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qup3_core_slave }, + .link_nodes = { &qup3_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { @@ -398,7 +398,7 @@ static struct qcom_icc_node qnm_gemnoc_cnoc = { .channels = 1, .buswidth = 16, .num_links = 82, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, &qhs_anoc_throttle_cfg, &qhs_aoss, &qhs_apss, &qhs_boot_rom, @@ -446,7 +446,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = { .channels = 1, .buswidth = 16, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { @@ -454,7 +454,7 @@ static struct qcom_icc_node qnm_cnoc_dc_noc = { .channels = 1, .buswidth = 4, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_llcc, &qns_gemnoc }, + .link_nodes = { &qhs_llcc, &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { @@ -462,7 +462,7 @@ static struct qcom_icc_node alm_gpu_tcu = { .channels = 1, .buswidth = 8, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { @@ -470,7 +470,7 @@ static struct qcom_icc_node alm_pcie_tcu = { .channels = 1, .buswidth = 8, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { @@ -478,7 +478,7 @@ static struct qcom_icc_node alm_sys_tcu = { .channels = 1, .buswidth = 8, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { @@ -486,7 +486,7 @@ static struct qcom_icc_node chm_apps = { .channels = 4, .buswidth = 32, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -495,7 +495,7 @@ static struct qcom_icc_node qnm_cmpnoc0 = { .channels = 2, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_cmpnoc1 = { @@ -503,7 +503,7 @@ static struct qcom_icc_node qnm_cmpnoc1 = { .channels = 2, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { @@ -511,7 +511,7 @@ static struct qcom_icc_node qnm_gemnoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_even_gemnoc, &srvc_odd_gemnoc, + .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc, &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, }; @@ -520,7 +520,7 @@ static struct qcom_icc_node qnm_gpdsp_sail = { .channels = 1, .buswidth = 16, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gpu = { @@ -528,7 +528,7 @@ static struct qcom_icc_node qnm_gpu = { .channels = 2, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { @@ -536,7 +536,7 @@ static struct qcom_icc_node qnm_mnoc_hf = { .channels = 2, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, + .link_nodes = { &qns_llcc, &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_sf = { @@ -544,7 +544,7 @@ static struct qcom_icc_node qnm_mnoc_sf = { .channels = 2, .buswidth = 32, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -553,7 +553,7 @@ static struct qcom_icc_node qnm_pcie = { .channels = 1, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { @@ -561,7 +561,7 @@ static struct qcom_icc_node qnm_snoc_gc = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { @@ -569,7 +569,7 @@ static struct qcom_icc_node qnm_snoc_sf = { .channels = 1, .buswidth = 16, .num_links = 3, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; @@ -578,7 +578,7 @@ static struct qcom_icc_node qxm_dsp0 = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc }, + .link_nodes = { &qns_gp_dsp_sail_noc }, }; static struct qcom_icc_node qxm_dsp1 = { @@ -586,7 +586,7 @@ static struct qcom_icc_node qxm_dsp1 = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc }, + .link_nodes = { &qns_gp_dsp_sail_noc }, }; static struct qcom_icc_node qhm_config_noc = { @@ -594,7 +594,7 @@ static struct qcom_icc_node qhm_config_noc = { .channels = 1, .buswidth = 4, .num_links = 6, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_core, &qhs_lpass_lpi, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, &qhs_lpass_mpu, &qhs_lpass_top, &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; @@ -604,7 +604,7 @@ static struct qcom_icc_node qxm_lpass_dsp = { .channels = 1, .buswidth = 8, .num_links = 4, - .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_top, &qns_sysnoc, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; @@ -613,7 +613,7 @@ static struct qcom_icc_node llcc_mc = { .channels = 8, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &ebi }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { @@ -621,7 +621,7 @@ static struct qcom_icc_node qnm_camnoc_hf = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { @@ -629,7 +629,7 @@ static struct qcom_icc_node qnm_camnoc_icp = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { @@ -637,7 +637,7 @@ static struct qcom_icc_node qnm_camnoc_sf = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp0_0 = { @@ -645,7 +645,7 @@ static struct qcom_icc_node qnm_mdp0_0 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_1 = { @@ -653,7 +653,7 @@ static struct qcom_icc_node qnm_mdp0_1 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_0 = { @@ -661,7 +661,7 @@ static struct qcom_icc_node qnm_mdp1_0 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_1 = { @@ -669,7 +669,7 @@ static struct qcom_icc_node qnm_mdp1_1 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_hf_cfg = { @@ -677,7 +677,7 @@ static struct qcom_icc_node qnm_mnoc_hf_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_hf }, + .link_nodes = { &srvc_mnoc_hf }, }; static struct qcom_icc_node qnm_mnoc_sf_cfg = { @@ -685,7 +685,7 @@ static struct qcom_icc_node qnm_mnoc_sf_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_sf }, + .link_nodes = { &srvc_mnoc_sf }, }; static struct qcom_icc_node qnm_video0 = { @@ -693,7 +693,7 @@ static struct qcom_icc_node qnm_video0 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { @@ -701,7 +701,7 @@ static struct qcom_icc_node qnm_video1 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { @@ -709,7 +709,7 @@ static struct qcom_icc_node qnm_video_cvp = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { @@ -717,7 +717,7 @@ static struct qcom_icc_node qnm_video_v_cpu = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { @@ -725,7 +725,7 @@ static struct qcom_icc_node qhm_nsp_noc_config = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &service_nsp_noc }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { @@ -733,7 +733,7 @@ static struct qcom_icc_node qxm_nsp = { .channels = 2, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_hcp, &qns_nsp_gemnoc }, + .link_nodes = { &qns_hcp, &qns_nsp_gemnoc }, }; static struct qcom_icc_node qhm_nspb_noc_config = { @@ -741,7 +741,7 @@ static struct qcom_icc_node qhm_nspb_noc_config = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &service_nspb_noc }, + .link_nodes = { &service_nspb_noc }, }; static struct qcom_icc_node qxm_nspb = { @@ -749,7 +749,7 @@ static struct qcom_icc_node qxm_nspb = { .channels = 2, .buswidth = 32, .num_links = 2, - .link_nodes = (struct qcom_icc_node *[]) { &qns_nspb_hcp, &qns_nspb_gemnoc }, + .link_nodes = { &qns_nspb_hcp, &qns_nspb_gemnoc }, }; static struct qcom_icc_node xm_pcie3_0 = { @@ -757,7 +757,7 @@ static struct qcom_icc_node xm_pcie3_0 = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { @@ -765,7 +765,7 @@ static struct qcom_icc_node xm_pcie3_1 = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { @@ -773,7 +773,7 @@ static struct qcom_icc_node qhm_gic = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { @@ -781,7 +781,7 @@ static struct qcom_icc_node qnm_aggre1_noc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { @@ -789,7 +789,7 @@ static struct qcom_icc_node qnm_aggre2_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { @@ -797,7 +797,7 @@ static struct qcom_icc_node qnm_lpass_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { @@ -805,7 +805,7 @@ static struct qcom_icc_node qnm_snoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &srvc_snoc }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { @@ -813,7 +813,7 @@ static struct qcom_icc_node qxm_pimem = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { @@ -821,7 +821,7 @@ static struct qcom_icc_node xm_gic = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { @@ -829,7 +829,7 @@ static struct qcom_icc_node qns_a1noc_snoc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { @@ -837,7 +837,7 @@ static struct qcom_icc_node qns_a2noc_snoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { @@ -941,7 +941,7 @@ static struct qcom_icc_node qhs_compute0_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qhm_nsp_noc_config }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_compute1_cfg = { @@ -949,7 +949,7 @@ static struct qcom_icc_node qhs_compute1_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qhm_nspb_noc_config }, + .link_nodes = { &qhm_nspb_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { @@ -1089,7 +1089,7 @@ static struct qcom_icc_node qhs_lpass_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qhm_config_noc }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_lpass_throttle_cfg = { @@ -1301,7 +1301,7 @@ static struct qcom_icc_node qns_ddrss_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_cnoc_dc_noc }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qns_gpdsp_noc_cfg = { @@ -1315,7 +1315,7 @@ static struct qcom_icc_node qns_mnoc_hf_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf_cfg }, + .link_nodes = { &qnm_mnoc_hf_cfg }, }; static struct qcom_icc_node qns_mnoc_sf_cfg = { @@ -1323,7 +1323,7 @@ static struct qcom_icc_node qns_mnoc_sf_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf_cfg }, + .link_nodes = { &qnm_mnoc_sf_cfg }, }; static struct qcom_icc_node qns_pcie_anoc_cfg = { @@ -1337,7 +1337,7 @@ static struct qcom_icc_node qns_snoc_cfg = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_cfg }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qxs_boot_imem = { @@ -1393,7 +1393,7 @@ static struct qcom_icc_node qns_gemnoc = { .channels = 1, .buswidth = 4, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cfg }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_cnoc = { @@ -1401,7 +1401,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { @@ -1409,7 +1409,7 @@ static struct qcom_icc_node qns_llcc = { .channels = 6, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { @@ -1417,7 +1417,7 @@ static struct qcom_icc_node qns_pcie = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { @@ -1449,7 +1449,7 @@ static struct qcom_icc_node qns_gp_dsp_sail_noc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_gpdsp_sail }, + .link_nodes = { &qnm_gpdsp_sail }, }; static struct qcom_icc_node qhs_lpass_core = { @@ -1481,7 +1481,7 @@ static struct qcom_icc_node qns_sysnoc = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_noc }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { @@ -1507,7 +1507,7 @@ static struct qcom_icc_node qns_mem_noc_hf = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { @@ -1515,7 +1515,7 @@ static struct qcom_icc_node qns_mem_noc_sf = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc_hf = { @@ -1541,7 +1541,7 @@ static struct qcom_icc_node qns_nsp_gemnoc = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc0 }, + .link_nodes = { &qnm_cmpnoc0 }, }; static struct qcom_icc_node service_nsp_noc = { @@ -1555,7 +1555,7 @@ static struct qcom_icc_node qns_nspb_gemnoc = { .channels = 2, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc1 }, + .link_nodes = { &qnm_cmpnoc1 }, }; static struct qcom_icc_node qns_nspb_hcp = { @@ -1575,7 +1575,7 @@ static struct qcom_icc_node qns_pcie_mem_noc = { .channels = 1, .buswidth = 32, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qns_gemnoc_gc = { @@ -1583,7 +1583,7 @@ static struct qcom_icc_node qns_gemnoc_gc = { .channels = 1, .buswidth = 8, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_gc }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { @@ -1591,7 +1591,7 @@ static struct qcom_icc_node qns_gemnoc_sf = { .channels = 1, .buswidth = 16, .num_links = 1, - .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { From 93938e0c8c97339fd9d99d6bb6382b95071921a1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:18 +0200 Subject: [PATCH 137/304] interconnect: qcom: sc7280: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-2-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc7280.c | 629 +++++++++++++---------------- drivers/interconnect/qcom/sc7280.h | 154 ------- 2 files changed, 287 insertions(+), 496 deletions(-) delete mode 100644 drivers/interconnect/qcom/sc7280.h diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 905403a3a930..3dc8b81f917d 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -15,11 +15,152 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7280.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_cnoc3_cnoc2; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qnm_cnoc2_cnoc3; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cpu; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_cnoc2_cnoc3; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc3_cnoc2; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qhs_modem_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SC7280_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -29,12 +170,11 @@ static struct qcom_icc_node qhm_qspi = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SC7280_MASTER_QUP_0, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -44,12 +184,11 @@ static struct qcom_icc_node qhm_qup0 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SC7280_MASTER_QUP_1, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -59,21 +198,19 @@ static struct qcom_icc_node qhm_qup1 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SC7280_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SC7280_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -83,12 +220,11 @@ static struct qcom_icc_node xm_sdc1 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SC7280_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -98,12 +234,11 @@ static struct qcom_icc_node xm_sdc2 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SC7280_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -113,12 +248,11 @@ static struct qcom_icc_node xm_sdc4 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SC7280_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -128,21 +262,19 @@ static struct qcom_icc_node xm_ufs_mem = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb2 = { .name = "xm_usb2", - .id = SC7280_MASTER_USB2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SC7280_MASTER_USB3_0, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -152,12 +284,11 @@ static struct qcom_icc_node xm_usb3_0 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SC7280_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -167,21 +298,19 @@ static struct qcom_icc_node qhm_qdss_bam = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SC7280_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", - .id = SC7280_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -191,12 +320,11 @@ static struct qcom_icc_node qnm_cnoc_datapath = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SC7280_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -206,12 +334,11 @@ static struct qcom_icc_node qxm_crypto = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SC7280_MASTER_IPA, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -221,30 +348,27 @@ static struct qcom_icc_node qxm_ipa = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SC7280_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SC7280_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SC7280_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -254,135 +378,126 @@ static struct qcom_icc_node xm_qdss_etr = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SC7280_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SC7280_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qnm_cnoc3_cnoc2 = { .name = "qnm_cnoc3_cnoc2", - .id = SC7280_MASTER_CNOC3_CNOC2, .channels = 1, .buswidth = 8, .num_links = 44, - .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, - SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, - SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, - SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, - SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, - SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, - SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, - SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, - SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, - SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, - SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, - SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, - SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, - SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, - SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, - SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, - SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, - SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, - SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, - SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, - SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, - SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mss_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_sdc4, + &qhs_security, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SC7280_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 45, - .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, - SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, - SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, - SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, - SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, - SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, - SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, - SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, - SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, - SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, - SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, - SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, - SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, - SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, - SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, - SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, - SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, - SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, - SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, - SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, - SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, - SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG, - SC7280_SLAVE_SNOC_CFG }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mss_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_sdc4, + &qhs_security, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_cnoc2_cnoc3, &qns_mnoc_cfg, + &qns_snoc_cfg }, }; static struct qcom_icc_node qnm_cnoc2_cnoc3 = { .name = "qnm_cnoc2_cnoc3", - .id = SC7280_MASTER_CNOC2_CNOC3, .channels = 1, .buswidth = 8, .num_links = 9, - .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, - SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG, - SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, - SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, - SC7280_SLAVE_TCU }, + .link_nodes = { &qhs_aoss, &qhs_apss, + &qns_cnoc_a2noc, &qns_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SC7280_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, - SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG, - SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, - SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, - SC7280_SLAVE_TCU }, + .link_nodes = { &qhs_aoss, &qhs_apss, + &qns_cnoc3_cnoc2, &qns_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SC7280_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, + .link_nodes = { &qhs_llcc, &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SC7280_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -392,12 +507,11 @@ static struct qcom_icc_node alm_gpu_tcu = { .urg_fwd = 0, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SC7280_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -407,22 +521,20 @@ static struct qcom_icc_node alm_sys_tcu = { .urg_fwd = 0, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SC7280_MASTER_APPSS_PROC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, - SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SC7280_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -432,23 +544,21 @@ static struct qcom_icc_node qnm_cmpnoc = { .urg_fwd = 1, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SC7280_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 5, - .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG, - SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2, - SC7280_SLAVE_SERVICE_GEM_NOC }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg, + &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SC7280_MASTER_GFX3D, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -458,12 +568,11 @@ static struct qcom_icc_node qnm_gpu = { .urg_fwd = 0, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SC7280_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -473,12 +582,11 @@ static struct qcom_icc_node qnm_mnoc_hf = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SC7280_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -488,21 +596,19 @@ static struct qcom_icc_node qnm_mnoc_sf = { .urg_fwd = 1, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SC7280_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -512,12 +618,11 @@ static struct qcom_icc_node qnm_snoc_gc = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SC7280_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &(const struct qcom_icc_qosbox) { @@ -527,42 +632,38 @@ static struct qcom_icc_node qnm_snoc_sf = { .urg_fwd = 1, }, .num_links = 3, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, - SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SC7280_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG, - SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG, - SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SC7280_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SC7280_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SC7280_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -572,12 +673,11 @@ static struct qcom_icc_node qnm_video0 = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cpu = { .name = "qnm_video_cpu", - .id = SC7280_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -587,12 +687,11 @@ static struct qcom_icc_node qnm_video_cpu = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", - .id = SC7280_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -602,12 +701,11 @@ static struct qcom_icc_node qxm_camnoc_hf = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", - .id = SC7280_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -617,12 +715,11 @@ static struct qcom_icc_node qxm_camnoc_icp = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SC7280_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -632,12 +729,11 @@ static struct qcom_icc_node qxm_camnoc_sf = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SC7280_MASTER_MDP0, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -647,57 +743,51 @@ static struct qcom_icc_node qxm_mdp0 = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SC7280_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SC7280_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7280_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SC7280_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SC7280_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SC7280_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SC7280_MASTER_PIMEM, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -707,12 +797,11 @@ static struct qcom_icc_node qxm_pimem = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SC7280_MASTER_GIC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -722,741 +811,585 @@ static struct qcom_icc_node xm_gic = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SC7280_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SC7280_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SC7280_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SC7280_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SC7280_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SC7280_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SC7280_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SC7280_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SC7280_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SC7280_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SC7280_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SC7280_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SC7280_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SC7280_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SC7280_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SC7280_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SC7280_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SC7280_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SC7280_SLAVE_HWKM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SC7280_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SC7280_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SC7280_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SC7280_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SC7280_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SC7280_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SC7280_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SC7280_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SC7280_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SC7280_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pka_wrapper_cfg = { .name = "qhs_pka_wrapper_cfg", - .id = SC7280_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pmu_wrapper_cfg = { .name = "qhs_pmu_wrapper_cfg", - .id = SC7280_SLAVE_PMU_WRAPPER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SC7280_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SC7280_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SC7280_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SC7280_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SC7280_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SC7280_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SC7280_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SC7280_SLAVE_SECURITY, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SC7280_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SC7280_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SC7280_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb2 = { .name = "qhs_usb2", - .id = SC7280_SLAVE_USB2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SC7280_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SC7280_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SC7280_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SC7280_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_A1NOC_CFG }, + .link_nodes = { &qnm_a1noc_cfg }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SC7280_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_A2NOC_CFG }, + .link_nodes = { &qnm_a2noc_cfg }, }; static struct qcom_icc_node qns_cnoc2_cnoc3 = { .name = "qns_cnoc2_cnoc3", - .id = SC7280_SLAVE_CNOC2_CNOC3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_CNOC2_CNOC3 }, + .link_nodes = { &qnm_cnoc2_cnoc3 }, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SC7280_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SC7280_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SC7280_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SC7280_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qns_cnoc3_cnoc2 = { .name = "qns_cnoc3_cnoc2", - .id = SC7280_SLAVE_CNOC3_CNOC2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_CNOC3_CNOC2 }, + .link_nodes = { &qnm_cnoc3_cnoc2 }, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SC7280_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc_datapath }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SC7280_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SC7280_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SC7280_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SC7280_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SC7280_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SC7280_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SC7280_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SC7280_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SC7280_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SC7280_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { .name = "qhs_modem_ms_mpu_cfg", - .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SC7280_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SC7280_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SC7280_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SC7280_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SC7280_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SC7280_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SC7280_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SC7280_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SC7280_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SC7280_SLAVE_EBI1, .channels = 2, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SC7280_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7280_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SC7280_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7280_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SC7280_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SC7280_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7280_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SC7280_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SC7280_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SC7280_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SC7280_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -1687,6 +1620,7 @@ static const struct regmap_config sc7280_aggre1_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_aggre1_noc = { + .alloc_dyn_id = true, .config = &sc7280_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), @@ -1719,6 +1653,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc7280_aggre2_noc = { + .alloc_dyn_id = true, .config = &sc7280_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), @@ -1740,6 +1675,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sc7280_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1810,6 +1746,7 @@ static const struct regmap_config sc7280_cnoc2_regmap_config = { }; static const struct qcom_icc_desc sc7280_cnoc2 = { + .alloc_dyn_id = true, .config = &sc7280_cnoc2_regmap_config, .nodes = cnoc2_nodes, .num_nodes = ARRAY_SIZE(cnoc2_nodes), @@ -1851,6 +1788,7 @@ static const struct regmap_config sc7280_cnoc3_regmap_config = { }; static const struct qcom_icc_desc sc7280_cnoc3 = { + .alloc_dyn_id = true, .config = &sc7280_cnoc3_regmap_config, .nodes = cnoc3_nodes, .num_nodes = ARRAY_SIZE(cnoc3_nodes), @@ -1876,6 +1814,7 @@ static const struct regmap_config sc7280_dc_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_dc_noc = { + .alloc_dyn_id = true, .config = &sc7280_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), @@ -1921,6 +1860,7 @@ static const struct regmap_config sc7280_gem_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_gem_noc = { + .alloc_dyn_id = true, .config = &sc7280_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), @@ -1950,6 +1890,7 @@ static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_lpass_ag_noc = { + .alloc_dyn_id = true, .config = &sc7280_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1976,6 +1917,7 @@ static const struct regmap_config sc7280_mc_virt_regmap_config = { }; static const struct qcom_icc_desc sc7280_mc_virt = { + .alloc_dyn_id = true, .config = &sc7280_mc_virt_regmap_config, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), @@ -2012,6 +1954,7 @@ static const struct regmap_config sc7280_mmss_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_mmss_noc = { + .alloc_dyn_id = true, .config = &sc7280_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), @@ -2040,6 +1983,7 @@ static const struct regmap_config sc7280_nsp_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_nsp_noc = { + .alloc_dyn_id = true, .config = &sc7280_nsp_noc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), @@ -2074,6 +2018,7 @@ static const struct regmap_config sc7280_system_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_system_noc = { + .alloc_dyn_id = true, .config = &sc7280_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h deleted file mode 100644 index 175e400305c5..000000000000 --- a/drivers/interconnect/qcom/sc7280.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7280 interconnect IDs - * - * Copyright (c) 2021, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H - -#define SC7280_MASTER_GPU_TCU 0 -#define SC7280_MASTER_SYS_TCU 1 -#define SC7280_MASTER_APPSS_PROC 2 -#define SC7280_MASTER_LLCC 3 -#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4 -#define SC7280_MASTER_CDSP_NOC_CFG 5 -#define SC7280_MASTER_QDSS_BAM 6 -#define SC7280_MASTER_QSPI_0 7 -#define SC7280_MASTER_QUP_0 8 -#define SC7280_MASTER_QUP_1 9 -#define SC7280_MASTER_A1NOC_CFG 10 -#define SC7280_MASTER_A2NOC_CFG 11 -#define SC7280_MASTER_A1NOC_SNOC 12 -#define SC7280_MASTER_A2NOC_SNOC 13 -#define SC7280_MASTER_COMPUTE_NOC 14 -#define SC7280_MASTER_CNOC2_CNOC3 15 -#define SC7280_MASTER_CNOC3_CNOC2 16 -#define SC7280_MASTER_CNOC_A2NOC 17 -#define SC7280_MASTER_CNOC_DC_NOC 18 -#define SC7280_MASTER_GEM_NOC_CFG 19 -#define SC7280_MASTER_GEM_NOC_CNOC 20 -#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SC7280_MASTER_GFX3D 22 -#define SC7280_MASTER_CNOC_MNOC_CFG 23 -#define SC7280_MASTER_MNOC_HF_MEM_NOC 24 -#define SC7280_MASTER_MNOC_SF_MEM_NOC 25 -#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26 -#define SC7280_MASTER_SNOC_CFG 27 -#define SC7280_MASTER_SNOC_GC_MEM_NOC 28 -#define SC7280_MASTER_SNOC_SF_MEM_NOC 29 -#define SC7280_MASTER_VIDEO_P0 30 -#define SC7280_MASTER_VIDEO_PROC 31 -#define SC7280_MASTER_QUP_CORE_0 32 -#define SC7280_MASTER_QUP_CORE_1 33 -#define SC7280_MASTER_CAMNOC_HF 34 -#define SC7280_MASTER_CAMNOC_ICP 35 -#define SC7280_MASTER_CAMNOC_SF 36 -#define SC7280_MASTER_CRYPTO 37 -#define SC7280_MASTER_IPA 38 -#define SC7280_MASTER_MDP0 39 -#define SC7280_MASTER_CDSP_PROC 40 -#define SC7280_MASTER_PIMEM 41 -#define SC7280_MASTER_GIC 42 -#define SC7280_MASTER_PCIE_0 43 -#define SC7280_MASTER_PCIE_1 44 -#define SC7280_MASTER_QDSS_DAP 45 -#define SC7280_MASTER_QDSS_ETR 46 -#define SC7280_MASTER_SDCC_1 47 -#define SC7280_MASTER_SDCC_2 48 -#define SC7280_MASTER_SDCC_4 49 -#define SC7280_MASTER_UFS_MEM 50 -#define SC7280_MASTER_USB2 51 -#define SC7280_MASTER_USB3_0 52 -#define SC7280_SLAVE_EBI1 53 -#define SC7280_SLAVE_AHB2PHY_SOUTH 54 -#define SC7280_SLAVE_AHB2PHY_NORTH 55 -#define SC7280_SLAVE_AOSS 56 -#define SC7280_SLAVE_APPSS 57 -#define SC7280_SLAVE_CAMERA_CFG 58 -#define SC7280_SLAVE_CLK_CTL 59 -#define SC7280_SLAVE_CDSP_CFG 60 -#define SC7280_SLAVE_RBCPR_CX_CFG 61 -#define SC7280_SLAVE_RBCPR_MX_CFG 62 -#define SC7280_SLAVE_CRYPTO_0_CFG 63 -#define SC7280_SLAVE_CX_RDPM 64 -#define SC7280_SLAVE_DCC_CFG 65 -#define SC7280_SLAVE_DISPLAY_CFG 66 -#define SC7280_SLAVE_GFX3D_CFG 67 -#define SC7280_SLAVE_HWKM 68 -#define SC7280_SLAVE_IMEM_CFG 69 -#define SC7280_SLAVE_IPA_CFG 70 -#define SC7280_SLAVE_IPC_ROUTER_CFG 71 -#define SC7280_SLAVE_LLCC_CFG 72 -#define SC7280_SLAVE_LPASS 73 -#define SC7280_SLAVE_LPASS_CORE_CFG 74 -#define SC7280_SLAVE_LPASS_LPI_CFG 75 -#define SC7280_SLAVE_LPASS_MPU_CFG 76 -#define SC7280_SLAVE_LPASS_TOP_CFG 77 -#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78 -#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79 -#define SC7280_SLAVE_CNOC_MSS 80 -#define SC7280_SLAVE_MX_RDPM 81 -#define SC7280_SLAVE_PCIE_0_CFG 82 -#define SC7280_SLAVE_PCIE_1_CFG 83 -#define SC7280_SLAVE_PDM 84 -#define SC7280_SLAVE_PIMEM_CFG 85 -#define SC7280_SLAVE_PKA_WRAPPER_CFG 86 -#define SC7280_SLAVE_PMU_WRAPPER_CFG 87 -#define SC7280_SLAVE_QDSS_CFG 88 -#define SC7280_SLAVE_QSPI_0 89 -#define SC7280_SLAVE_QUP_0 90 -#define SC7280_SLAVE_QUP_1 91 -#define SC7280_SLAVE_SDCC_1 92 -#define SC7280_SLAVE_SDCC_2 93 -#define SC7280_SLAVE_SDCC_4 94 -#define SC7280_SLAVE_SECURITY 95 -#define SC7280_SLAVE_TCSR 96 -#define SC7280_SLAVE_TLMM 97 -#define SC7280_SLAVE_UFS_MEM_CFG 98 -#define SC7280_SLAVE_USB2 99 -#define SC7280_SLAVE_USB3_0 100 -#define SC7280_SLAVE_VENUS_CFG 101 -#define SC7280_SLAVE_VSENSE_CTRL_CFG 102 -#define SC7280_SLAVE_A1NOC_CFG 103 -#define SC7280_SLAVE_A1NOC_SNOC 104 -#define SC7280_SLAVE_A2NOC_CFG 105 -#define SC7280_SLAVE_A2NOC_SNOC 106 -#define SC7280_SLAVE_CNOC2_CNOC3 107 -#define SC7280_SLAVE_CNOC3_CNOC2 108 -#define SC7280_SLAVE_CNOC_A2NOC 109 -#define SC7280_SLAVE_DDRSS_CFG 110 -#define SC7280_SLAVE_GEM_NOC_CNOC 111 -#define SC7280_SLAVE_GEM_NOC_CFG 112 -#define SC7280_SLAVE_SNOC_GEM_NOC_GC 113 -#define SC7280_SLAVE_SNOC_GEM_NOC_SF 114 -#define SC7280_SLAVE_LLCC 115 -#define SC7280_SLAVE_MNOC_HF_MEM_NOC 116 -#define SC7280_SLAVE_MNOC_SF_MEM_NOC 117 -#define SC7280_SLAVE_CNOC_MNOC_CFG 118 -#define SC7280_SLAVE_CDSP_MEM_NOC 119 -#define SC7280_SLAVE_MEM_NOC_PCIE_SNOC 120 -#define SC7280_SLAVE_ANOC_PCIE_GEM_NOC 121 -#define SC7280_SLAVE_SNOC_CFG 122 -#define SC7280_SLAVE_QUP_CORE_0 123 -#define SC7280_SLAVE_QUP_CORE_1 124 -#define SC7280_SLAVE_BOOT_IMEM 125 -#define SC7280_SLAVE_IMEM 126 -#define SC7280_SLAVE_PIMEM 127 -#define SC7280_SLAVE_SERVICE_NSP_NOC 128 -#define SC7280_SLAVE_SERVICE_A1NOC 129 -#define SC7280_SLAVE_SERVICE_A2NOC 130 -#define SC7280_SLAVE_SERVICE_GEM_NOC_1 131 -#define SC7280_SLAVE_SERVICE_MNOC 132 -#define SC7280_SLAVE_SERVICES_LPASS_AML_NOC 133 -#define SC7280_SLAVE_SERVICE_LPASS_AG_NOC 134 -#define SC7280_SLAVE_SERVICE_GEM_NOC_2 135 -#define SC7280_SLAVE_SERVICE_SNOC 136 -#define SC7280_SLAVE_SERVICE_GEM_NOC 137 -#define SC7280_SLAVE_PCIE_0 138 -#define SC7280_SLAVE_PCIE_1 139 -#define SC7280_SLAVE_QDSS_STM 140 -#define SC7280_SLAVE_TCU 141 - -#endif From ddf2ef52f6230ebbf21cb86b44f0a43ce7e05295 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:19 +0200 Subject: [PATCH 138/304] interconnect: qcom: sc8180x: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-3-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc8180x.c | 659 ++++++++++++++-------------- drivers/interconnect/qcom/sc8180x.h | 179 -------- 2 files changed, 335 insertions(+), 503 deletions(-) delete mode 100644 drivers/interconnect/qcom/sc8180x.h diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 4dd1d2f2e821..b80a255ba8c3 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -14,1331 +14,1331 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8180x.h" + +static struct qcom_icc_node mas_qhm_a1noc_cfg; +static struct qcom_icc_node mas_xm_ufs_card; +static struct qcom_icc_node mas_xm_ufs_g4; +static struct qcom_icc_node mas_xm_ufs_mem; +static struct qcom_icc_node mas_xm_usb3_0; +static struct qcom_icc_node mas_xm_usb3_1; +static struct qcom_icc_node mas_xm_usb3_2; +static struct qcom_icc_node mas_qhm_a2noc_cfg; +static struct qcom_icc_node mas_qhm_qdss_bam; +static struct qcom_icc_node mas_qhm_qspi; +static struct qcom_icc_node mas_qhm_qspi1; +static struct qcom_icc_node mas_qhm_qup0; +static struct qcom_icc_node mas_qhm_qup1; +static struct qcom_icc_node mas_qhm_qup2; +static struct qcom_icc_node mas_qhm_sensorss_ahb; +static struct qcom_icc_node mas_qxm_crypto; +static struct qcom_icc_node mas_qxm_ipa; +static struct qcom_icc_node mas_xm_emac; +static struct qcom_icc_node mas_xm_pcie3_0; +static struct qcom_icc_node mas_xm_pcie3_1; +static struct qcom_icc_node mas_xm_pcie3_2; +static struct qcom_icc_node mas_xm_pcie3_3; +static struct qcom_icc_node mas_xm_qdss_etr; +static struct qcom_icc_node mas_xm_sdc2; +static struct qcom_icc_node mas_xm_sdc4; +static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp; +static struct qcom_icc_node mas_qnm_npu; +static struct qcom_icc_node mas_qnm_snoc; +static struct qcom_icc_node mas_qhm_cnoc_dc_noc; +static struct qcom_icc_node mas_acm_apps; +static struct qcom_icc_node mas_acm_gpu_tcu; +static struct qcom_icc_node mas_acm_sys_tcu; +static struct qcom_icc_node mas_qhm_gemnoc_cfg; +static struct qcom_icc_node mas_qnm_cmpnoc; +static struct qcom_icc_node mas_qnm_gpu; +static struct qcom_icc_node mas_qnm_mnoc_hf; +static struct qcom_icc_node mas_qnm_mnoc_sf; +static struct qcom_icc_node mas_qnm_pcie; +static struct qcom_icc_node mas_qnm_snoc_gc; +static struct qcom_icc_node mas_qnm_snoc_sf; +static struct qcom_icc_node mas_qxm_ecc; +static struct qcom_icc_node mas_llcc_mc; +static struct qcom_icc_node mas_qhm_mnoc_cfg; +static struct qcom_icc_node mas_qxm_camnoc_hf0; +static struct qcom_icc_node mas_qxm_camnoc_hf1; +static struct qcom_icc_node mas_qxm_camnoc_sf; +static struct qcom_icc_node mas_qxm_mdp0; +static struct qcom_icc_node mas_qxm_mdp1; +static struct qcom_icc_node mas_qxm_rot; +static struct qcom_icc_node mas_qxm_venus0; +static struct qcom_icc_node mas_qxm_venus1; +static struct qcom_icc_node mas_qxm_venus_arm9; +static struct qcom_icc_node mas_qhm_snoc_cfg; +static struct qcom_icc_node mas_qnm_aggre1_noc; +static struct qcom_icc_node mas_qnm_aggre2_noc; +static struct qcom_icc_node mas_qnm_gemnoc; +static struct qcom_icc_node mas_qxm_pimem; +static struct qcom_icc_node mas_xm_gic; +static struct qcom_icc_node mas_qup_core_0; +static struct qcom_icc_node mas_qup_core_1; +static struct qcom_icc_node mas_qup_core_2; +static struct qcom_icc_node slv_qns_a1noc_snoc; +static struct qcom_icc_node slv_srvc_aggre1_noc; +static struct qcom_icc_node slv_qns_a2noc_snoc; +static struct qcom_icc_node slv_qns_pcie_mem_noc; +static struct qcom_icc_node slv_srvc_aggre2_noc; +static struct qcom_icc_node slv_qns_camnoc_uncomp; +static struct qcom_icc_node slv_qns_cdsp_mem_noc; +static struct qcom_icc_node slv_qhs_a1_noc_cfg; +static struct qcom_icc_node slv_qhs_a2_noc_cfg; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west; +static struct qcom_icc_node slv_qhs_ahb2phy_south; +static struct qcom_icc_node slv_qhs_aop; +static struct qcom_icc_node slv_qhs_aoss; +static struct qcom_icc_node slv_qhs_camera_cfg; +static struct qcom_icc_node slv_qhs_clk_ctl; +static struct qcom_icc_node slv_qhs_compute_dsp; +static struct qcom_icc_node slv_qhs_cpr_cx; +static struct qcom_icc_node slv_qhs_cpr_mmcx; +static struct qcom_icc_node slv_qhs_cpr_mx; +static struct qcom_icc_node slv_qhs_crypto0_cfg; +static struct qcom_icc_node slv_qhs_ddrss_cfg; +static struct qcom_icc_node slv_qhs_display_cfg; +static struct qcom_icc_node slv_qhs_emac_cfg; +static struct qcom_icc_node slv_qhs_glm; +static struct qcom_icc_node slv_qhs_gpuss_cfg; +static struct qcom_icc_node slv_qhs_imem_cfg; +static struct qcom_icc_node slv_qhs_ipa; +static struct qcom_icc_node slv_qhs_mnoc_cfg; +static struct qcom_icc_node slv_qhs_npu_cfg; +static struct qcom_icc_node slv_qhs_pcie0_cfg; +static struct qcom_icc_node slv_qhs_pcie1_cfg; +static struct qcom_icc_node slv_qhs_pcie2_cfg; +static struct qcom_icc_node slv_qhs_pcie3_cfg; +static struct qcom_icc_node slv_qhs_pdm; +static struct qcom_icc_node slv_qhs_pimem_cfg; +static struct qcom_icc_node slv_qhs_prng; +static struct qcom_icc_node slv_qhs_qdss_cfg; +static struct qcom_icc_node slv_qhs_qspi_0; +static struct qcom_icc_node slv_qhs_qspi_1; +static struct qcom_icc_node slv_qhs_qupv3_east0; +static struct qcom_icc_node slv_qhs_qupv3_east1; +static struct qcom_icc_node slv_qhs_qupv3_west; +static struct qcom_icc_node slv_qhs_sdc2; +static struct qcom_icc_node slv_qhs_sdc4; +static struct qcom_icc_node slv_qhs_security; +static struct qcom_icc_node slv_qhs_snoc_cfg; +static struct qcom_icc_node slv_qhs_spss_cfg; +static struct qcom_icc_node slv_qhs_tcsr; +static struct qcom_icc_node slv_qhs_tlmm_east; +static struct qcom_icc_node slv_qhs_tlmm_south; +static struct qcom_icc_node slv_qhs_tlmm_west; +static struct qcom_icc_node slv_qhs_tsif; +static struct qcom_icc_node slv_qhs_ufs_card_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem0_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem1_cfg; +static struct qcom_icc_node slv_qhs_usb3_0; +static struct qcom_icc_node slv_qhs_usb3_1; +static struct qcom_icc_node slv_qhs_usb3_2; +static struct qcom_icc_node slv_qhs_venus_cfg; +static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg; +static struct qcom_icc_node slv_srvc_cnoc; +static struct qcom_icc_node slv_qhs_gemnoc; +static struct qcom_icc_node slv_qhs_llcc; +static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node slv_qns_ecc; +static struct qcom_icc_node slv_qns_gem_noc_snoc; +static struct qcom_icc_node slv_qns_llcc; +static struct qcom_icc_node slv_srvc_gemnoc; +static struct qcom_icc_node slv_srvc_gemnoc1; +static struct qcom_icc_node slv_ebi; +static struct qcom_icc_node slv_qns2_mem_noc; +static struct qcom_icc_node slv_qns_mem_noc_hf; +static struct qcom_icc_node slv_srvc_mnoc; +static struct qcom_icc_node slv_qhs_apss; +static struct qcom_icc_node slv_qns_cnoc; +static struct qcom_icc_node slv_qns_gemnoc_gc; +static struct qcom_icc_node slv_qns_gemnoc_sf; +static struct qcom_icc_node slv_qxs_imem; +static struct qcom_icc_node slv_qxs_pimem; +static struct qcom_icc_node slv_srvc_snoc; +static struct qcom_icc_node slv_xs_pcie_0; +static struct qcom_icc_node slv_xs_pcie_1; +static struct qcom_icc_node slv_xs_pcie_2; +static struct qcom_icc_node slv_xs_pcie_3; +static struct qcom_icc_node slv_xs_qdss_stm; +static struct qcom_icc_node slv_xs_sys_tcu_cfg; +static struct qcom_icc_node slv_qup_core_0; +static struct qcom_icc_node slv_qup_core_1; +static struct qcom_icc_node slv_qup_core_2; static struct qcom_icc_node mas_qhm_a1noc_cfg = { .name = "mas_qhm_a1noc_cfg", - .id = SC8180X_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_A1NOC } + .link_nodes = { &slv_srvc_aggre1_noc }, }; static struct qcom_icc_node mas_xm_ufs_card = { .name = "mas_xm_ufs_card", - .id = SC8180X_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_ufs_g4 = { .name = "mas_xm_ufs_g4", - .id = SC8180X_MASTER_UFS_GEN4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_ufs_mem = { .name = "mas_xm_ufs_mem", - .id = SC8180X_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_usb3_0 = { .name = "mas_xm_usb3_0", - .id = SC8180X_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_usb3_1 = { .name = "mas_xm_usb3_1", - .id = SC8180X_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_usb3_2 = { .name = "mas_xm_usb3_2", - .id = SC8180X_MASTER_USB3_2, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_qhm_a2noc_cfg = { .name = "mas_qhm_a2noc_cfg", - .id = SC8180X_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_A2NOC } + .link_nodes = { &slv_srvc_aggre2_noc }, }; static struct qcom_icc_node mas_qhm_qdss_bam = { .name = "mas_qhm_qdss_bam", - .id = SC8180X_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qspi = { .name = "mas_qhm_qspi", - .id = SC8180X_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qspi1 = { .name = "mas_qhm_qspi1", - .id = SC8180X_MASTER_QSPI_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qup0 = { .name = "mas_qhm_qup0", - .id = SC8180X_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qup1 = { .name = "mas_qhm_qup1", - .id = SC8180X_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qup2 = { .name = "mas_qhm_qup2", - .id = SC8180X_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_sensorss_ahb = { .name = "mas_qhm_sensorss_ahb", - .id = SC8180X_MASTER_SENSORS_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qxm_crypto = { .name = "mas_qxm_crypto", - .id = SC8180X_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qxm_ipa = { .name = "mas_qxm_ipa", - .id = SC8180X_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_emac = { .name = "mas_xm_emac", - .id = SC8180X_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_pcie3_0 = { .name = "mas_xm_pcie3_0", - .id = SC8180X_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_pcie3_1 = { .name = "mas_xm_pcie3_1", - .id = SC8180X_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_pcie3_2 = { .name = "mas_xm_pcie3_2", - .id = SC8180X_MASTER_PCIE_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_pcie3_3 = { .name = "mas_xm_pcie3_3", - .id = SC8180X_MASTER_PCIE_3, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_qdss_etr = { .name = "mas_xm_qdss_etr", - .id = SC8180X_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_sdc2 = { .name = "mas_xm_sdc2", - .id = SC8180X_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_sdc4 = { .name = "mas_xm_sdc4", - .id = SC8180X_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { .name = "mas_qxm_camnoc_hf0_uncomp", - .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes = { &slv_qns_camnoc_uncomp }, }; static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { .name = "mas_qxm_camnoc_hf1_uncomp", - .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes = { &slv_qns_camnoc_uncomp }, }; static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { .name = "mas_qxm_camnoc_sf_uncomp", - .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes = { &slv_qns_camnoc_uncomp }, }; static struct qcom_icc_node mas_qnm_npu = { .name = "mas_qnm_npu", - .id = SC8180X_MASTER_NPU, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CDSP_MEM_NOC } + .link_nodes = { &slv_qns_cdsp_mem_noc }, }; static struct qcom_icc_node mas_qnm_snoc = { .name = "mas_qnm_snoc", - .id = SC8180X_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 56, - .links = { SC8180X_SLAVE_TLMM_SOUTH, - SC8180X_SLAVE_CDSP_CFG, - SC8180X_SLAVE_SPSS_CFG, - SC8180X_SLAVE_CAMERA_CFG, - SC8180X_SLAVE_SDCC_4, - SC8180X_SLAVE_AHB2PHY_CENTER, - SC8180X_SLAVE_SDCC_2, - SC8180X_SLAVE_PCIE_2_CFG, - SC8180X_SLAVE_CNOC_MNOC_CFG, - SC8180X_SLAVE_EMAC_CFG, - SC8180X_SLAVE_QSPI_0, - SC8180X_SLAVE_QSPI_1, - SC8180X_SLAVE_TLMM_EAST, - SC8180X_SLAVE_SNOC_CFG, - SC8180X_SLAVE_AHB2PHY_EAST, - SC8180X_SLAVE_GLM, - SC8180X_SLAVE_PDM, - SC8180X_SLAVE_PCIE_1_CFG, - SC8180X_SLAVE_A2NOC_CFG, - SC8180X_SLAVE_QDSS_CFG, - SC8180X_SLAVE_DISPLAY_CFG, - SC8180X_SLAVE_TCSR, - SC8180X_SLAVE_UFS_MEM_0_CFG, - SC8180X_SLAVE_CNOC_DDRSS, - SC8180X_SLAVE_PCIE_0_CFG, - SC8180X_SLAVE_QUP_1, - SC8180X_SLAVE_QUP_2, - SC8180X_SLAVE_NPU_CFG, - SC8180X_SLAVE_CRYPTO_0_CFG, - SC8180X_SLAVE_GRAPHICS_3D_CFG, - SC8180X_SLAVE_VENUS_CFG, - SC8180X_SLAVE_TSIF, - SC8180X_SLAVE_IPA_CFG, - SC8180X_SLAVE_CLK_CTL, - SC8180X_SLAVE_SECURITY, - SC8180X_SLAVE_AOP, - SC8180X_SLAVE_AHB2PHY_WEST, - SC8180X_SLAVE_AHB2PHY_SOUTH, - SC8180X_SLAVE_SERVICE_CNOC, - SC8180X_SLAVE_UFS_CARD_CFG, - SC8180X_SLAVE_USB3_1, - SC8180X_SLAVE_USB3_2, - SC8180X_SLAVE_PCIE_3_CFG, - SC8180X_SLAVE_RBCPR_CX_CFG, - SC8180X_SLAVE_TLMM_WEST, - SC8180X_SLAVE_A1NOC_CFG, - SC8180X_SLAVE_AOSS, - SC8180X_SLAVE_PRNG, - SC8180X_SLAVE_VSENSE_CTRL_CFG, - SC8180X_SLAVE_QUP_0, - SC8180X_SLAVE_USB3, - SC8180X_SLAVE_RBCPR_MMCX_CFG, - SC8180X_SLAVE_PIMEM_CFG, - SC8180X_SLAVE_UFS_MEM_1_CFG, - SC8180X_SLAVE_RBCPR_MX_CFG, - SC8180X_SLAVE_IMEM_CFG } + .link_nodes = { &slv_qhs_tlmm_south, + &slv_qhs_compute_dsp, + &slv_qhs_spss_cfg, + &slv_qhs_camera_cfg, + &slv_qhs_sdc4, + &slv_qhs_ahb2phy_refgen_center, + &slv_qhs_sdc2, + &slv_qhs_pcie2_cfg, + &slv_qhs_mnoc_cfg, + &slv_qhs_emac_cfg, + &slv_qhs_qspi_0, + &slv_qhs_qspi_1, + &slv_qhs_tlmm_east, + &slv_qhs_snoc_cfg, + &slv_qhs_ahb2phy_refgen_east, + &slv_qhs_glm, + &slv_qhs_pdm, + &slv_qhs_pcie1_cfg, + &slv_qhs_a2_noc_cfg, + &slv_qhs_qdss_cfg, + &slv_qhs_display_cfg, + &slv_qhs_tcsr, + &slv_qhs_ufs_mem0_cfg, + &slv_qhs_ddrss_cfg, + &slv_qhs_pcie0_cfg, + &slv_qhs_qupv3_east0, + &slv_qhs_qupv3_east1, + &slv_qhs_npu_cfg, + &slv_qhs_crypto0_cfg, + &slv_qhs_gpuss_cfg, + &slv_qhs_venus_cfg, + &slv_qhs_tsif, + &slv_qhs_ipa, + &slv_qhs_clk_ctl, + &slv_qhs_security, + &slv_qhs_aop, + &slv_qhs_ahb2phy_refgen_west, + &slv_qhs_ahb2phy_south, + &slv_srvc_cnoc, + &slv_qhs_ufs_card_cfg, + &slv_qhs_usb3_1, + &slv_qhs_usb3_2, + &slv_qhs_pcie3_cfg, + &slv_qhs_cpr_cx, + &slv_qhs_tlmm_west, + &slv_qhs_a1_noc_cfg, + &slv_qhs_aoss, + &slv_qhs_prng, + &slv_qhs_vsense_ctrl_cfg, + &slv_qhs_qupv3_west, + &slv_qhs_usb3_0, + &slv_qhs_cpr_mmcx, + &slv_qhs_pimem_cfg, + &slv_qhs_ufs_mem1_cfg, + &slv_qhs_cpr_mx, + &slv_qhs_imem_cfg }, }; static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { .name = "mas_qhm_cnoc_dc_noc", - .id = SC8180X_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC_CFG, - SC8180X_SLAVE_GEM_NOC_CFG } + .link_nodes = { &slv_qhs_llcc, + &slv_qhs_gemnoc }, }; static struct qcom_icc_node mas_acm_apps = { .name = "mas_acm_apps", - .id = SC8180X_MASTER_AMPSS_M0, .channels = 4, .buswidth = 64, .num_links = 3, - .links = { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_acm_gpu_tcu = { .name = "mas_acm_gpu_tcu", - .id = SC8180X_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_acm_sys_tcu = { .name = "mas_acm_sys_tcu", - .id = SC8180X_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qhm_gemnoc_cfg = { .name = "mas_qhm_gemnoc_cfg", - .id = SC8180X_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1, - SC8180X_SLAVE_SERVICE_GEM_NOC, - SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } + .link_nodes = { &slv_srvc_gemnoc1, + &slv_srvc_gemnoc, + &slv_qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node mas_qnm_cmpnoc = { .name = "mas_qnm_cmpnoc", - .id = SC8180X_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_gpu = { .name = "mas_qnm_gpu", - .id = SC8180X_MASTER_GRAPHICS_3D, .channels = 4, .buswidth = 32, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_mnoc_hf = { .name = "mas_qnm_mnoc_hf", - .id = SC8180X_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_qnm_mnoc_sf = { .name = "mas_qnm_mnoc_sf", - .id = SC8180X_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_pcie = { .name = "mas_qnm_pcie", - .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_snoc_gc = { .name = "mas_qnm_snoc_gc", - .id = SC8180X_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_qnm_snoc_sf = { .name = "mas_qnm_snoc_sf", - .id = SC8180X_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_qxm_ecc = { .name = "mas_qxm_ecc", - .id = SC8180X_MASTER_ECC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_llcc_mc = { .name = "mas_llcc_mc", - .id = SC8180X_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_EBI_CH0 } + .link_nodes = { &slv_ebi }, }; static struct qcom_icc_node mas_qhm_mnoc_cfg = { .name = "mas_qhm_mnoc_cfg", - .id = SC8180X_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_MNOC } + .link_nodes = { &slv_srvc_mnoc }, }; static struct qcom_icc_node mas_qxm_camnoc_hf0 = { .name = "mas_qxm_camnoc_hf0", - .id = SC8180X_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_camnoc_hf1 = { .name = "mas_qxm_camnoc_hf1", - .id = SC8180X_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_camnoc_sf = { .name = "mas_qxm_camnoc_sf", - .id = SC8180X_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_mdp0 = { .name = "mas_qxm_mdp0", - .id = SC8180X_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_mdp1 = { .name = "mas_qxm_mdp1", - .id = SC8180X_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_rot = { .name = "mas_qxm_rot", - .id = SC8180X_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_venus0 = { .name = "mas_qxm_venus0", - .id = SC8180X_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_venus1 = { .name = "mas_qxm_venus1", - .id = SC8180X_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_venus_arm9 = { .name = "mas_qxm_venus_arm9", - .id = SC8180X_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qhm_snoc_cfg = { .name = "mas_qhm_snoc_cfg", - .id = SC8180X_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_SNOC } + .link_nodes = { &slv_srvc_snoc }, }; static struct qcom_icc_node mas_qnm_aggre1_noc = { .name = "mas_qnm_aggre1_noc", - .id = SC8180X_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 32, .num_links = 6, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_QDSS_STM } + .link_nodes = { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_qdss_stm }, }; static struct qcom_icc_node mas_qnm_aggre2_noc = { .name = "mas_qnm_aggre2_noc", - .id = SC8180X_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 11, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_PCIE_3, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SLAVE_PCIE_2, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_PCIE_0, - SC8180X_SLAVE_PCIE_1, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes = { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_xs_pcie_3, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_xs_pcie_2, + &slv_qns_cnoc, + &slv_xs_pcie_0, + &slv_xs_pcie_1, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm }, }; static struct qcom_icc_node mas_qnm_gemnoc = { .name = "mas_qnm_gemnoc", - .id = SC8180X_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes = { &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm }, }; static struct qcom_icc_node mas_qxm_pimem = { .name = "mas_qxm_pimem", - .id = SC8180X_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes = { &slv_qns_gemnoc_gc, + &slv_qxs_imem }, }; static struct qcom_icc_node mas_xm_gic = { .name = "mas_xm_gic", - .id = SC8180X_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes = { &slv_qns_gemnoc_gc, + &slv_qxs_imem }, }; static struct qcom_icc_node mas_qup_core_0 = { .name = "mas_qup_core_0", - .id = SC8180X_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_QUP_CORE_0 } + .link_nodes = { &slv_qup_core_0 }, }; static struct qcom_icc_node mas_qup_core_1 = { .name = "mas_qup_core_1", - .id = SC8180X_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_QUP_CORE_1 } + .link_nodes = { &slv_qup_core_1 }, }; static struct qcom_icc_node mas_qup_core_2 = { .name = "mas_qup_core_2", - .id = SC8180X_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_QUP_CORE_2 } + .link_nodes = { &slv_qup_core_2 }, }; static struct qcom_icc_node slv_qns_a1noc_snoc = { .name = "slv_qns_a1noc_snoc", - .id = SC8180X_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_MAS } + .link_nodes = { &mas_qnm_aggre1_noc }, }; static struct qcom_icc_node slv_srvc_aggre1_noc = { .name = "slv_srvc_aggre1_noc", - .id = SC8180X_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qns_a2noc_snoc = { .name = "slv_qns_a2noc_snoc", - .id = SC8180X_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_MAS } + .link_nodes = { &mas_qnm_aggre2_noc }, }; static struct qcom_icc_node slv_qns_pcie_mem_noc = { .name = "slv_qns_pcie_mem_noc", - .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } + .link_nodes = { &mas_qnm_pcie }, }; static struct qcom_icc_node slv_srvc_aggre2_noc = { .name = "slv_srvc_aggre2_noc", - .id = SC8180X_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qns_camnoc_uncomp = { .name = "slv_qns_camnoc_uncomp", - .id = SC8180X_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32 }; static struct qcom_icc_node slv_qns_cdsp_mem_noc = { .name = "slv_qns_cdsp_mem_noc", - .id = SC8180X_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_COMPUTE_NOC } + .link_nodes = { &mas_qnm_cmpnoc }, }; static struct qcom_icc_node slv_qhs_a1_noc_cfg = { .name = "slv_qhs_a1_noc_cfg", - .id = SC8180X_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_A1NOC_CFG } + .link_nodes = { &mas_qhm_a1noc_cfg }, }; static struct qcom_icc_node slv_qhs_a2_noc_cfg = { .name = "slv_qhs_a2_noc_cfg", - .id = SC8180X_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_A2NOC_CFG } + .link_nodes = { &mas_qhm_a2noc_cfg }, }; static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { .name = "slv_qhs_ahb2phy_refgen_center", - .id = SC8180X_SLAVE_AHB2PHY_CENTER, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { .name = "slv_qhs_ahb2phy_refgen_east", - .id = SC8180X_SLAVE_AHB2PHY_EAST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { .name = "slv_qhs_ahb2phy_refgen_west", - .id = SC8180X_SLAVE_AHB2PHY_WEST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ahb2phy_south = { .name = "slv_qhs_ahb2phy_south", - .id = SC8180X_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_aop = { .name = "slv_qhs_aop", - .id = SC8180X_SLAVE_AOP, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_aoss = { .name = "slv_qhs_aoss", - .id = SC8180X_SLAVE_AOSS, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_camera_cfg = { .name = "slv_qhs_camera_cfg", - .id = SC8180X_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_clk_ctl = { .name = "slv_qhs_clk_ctl", - .id = SC8180X_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_compute_dsp = { .name = "slv_qhs_compute_dsp", - .id = SC8180X_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_cpr_cx = { .name = "slv_qhs_cpr_cx", - .id = SC8180X_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_cpr_mmcx = { .name = "slv_qhs_cpr_mmcx", - .id = SC8180X_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_cpr_mx = { .name = "slv_qhs_cpr_mx", - .id = SC8180X_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_crypto0_cfg = { .name = "slv_qhs_crypto0_cfg", - .id = SC8180X_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ddrss_cfg = { .name = "slv_qhs_ddrss_cfg", - .id = SC8180X_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_CNOC_DC_NOC } + .link_nodes = { &mas_qhm_cnoc_dc_noc }, }; static struct qcom_icc_node slv_qhs_display_cfg = { .name = "slv_qhs_display_cfg", - .id = SC8180X_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_emac_cfg = { .name = "slv_qhs_emac_cfg", - .id = SC8180X_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_glm = { .name = "slv_qhs_glm", - .id = SC8180X_SLAVE_GLM, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_gpuss_cfg = { .name = "slv_qhs_gpuss_cfg", - .id = SC8180X_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qhs_imem_cfg = { .name = "slv_qhs_imem_cfg", - .id = SC8180X_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ipa = { .name = "slv_qhs_ipa", - .id = SC8180X_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_mnoc_cfg = { .name = "slv_qhs_mnoc_cfg", - .id = SC8180X_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_CNOC_MNOC_CFG } + .link_nodes = { &mas_qhm_mnoc_cfg }, }; static struct qcom_icc_node slv_qhs_npu_cfg = { .name = "slv_qhs_npu_cfg", - .id = SC8180X_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie0_cfg = { .name = "slv_qhs_pcie0_cfg", - .id = SC8180X_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie1_cfg = { .name = "slv_qhs_pcie1_cfg", - .id = SC8180X_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie2_cfg = { .name = "slv_qhs_pcie2_cfg", - .id = SC8180X_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie3_cfg = { .name = "slv_qhs_pcie3_cfg", - .id = SC8180X_SLAVE_PCIE_3_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pdm = { .name = "slv_qhs_pdm", - .id = SC8180X_SLAVE_PDM, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pimem_cfg = { .name = "slv_qhs_pimem_cfg", - .id = SC8180X_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_prng = { .name = "slv_qhs_prng", - .id = SC8180X_SLAVE_PRNG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qdss_cfg = { .name = "slv_qhs_qdss_cfg", - .id = SC8180X_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qspi_0 = { .name = "slv_qhs_qspi_0", - .id = SC8180X_SLAVE_QSPI_0, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qspi_1 = { .name = "slv_qhs_qspi_1", - .id = SC8180X_SLAVE_QSPI_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qupv3_east0 = { .name = "slv_qhs_qupv3_east0", - .id = SC8180X_SLAVE_QUP_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qupv3_east1 = { .name = "slv_qhs_qupv3_east1", - .id = SC8180X_SLAVE_QUP_2, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qupv3_west = { .name = "slv_qhs_qupv3_west", - .id = SC8180X_SLAVE_QUP_0, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_sdc2 = { .name = "slv_qhs_sdc2", - .id = SC8180X_SLAVE_SDCC_2, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_sdc4 = { .name = "slv_qhs_sdc4", - .id = SC8180X_SLAVE_SDCC_4, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_security = { .name = "slv_qhs_security", - .id = SC8180X_SLAVE_SECURITY, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_snoc_cfg = { .name = "slv_qhs_snoc_cfg", - .id = SC8180X_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_SNOC_CFG } + .link_nodes = { &mas_qhm_snoc_cfg }, }; static struct qcom_icc_node slv_qhs_spss_cfg = { .name = "slv_qhs_spss_cfg", - .id = SC8180X_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tcsr = { .name = "slv_qhs_tcsr", - .id = SC8180X_SLAVE_TCSR, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tlmm_east = { .name = "slv_qhs_tlmm_east", - .id = SC8180X_SLAVE_TLMM_EAST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tlmm_south = { .name = "slv_qhs_tlmm_south", - .id = SC8180X_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tlmm_west = { .name = "slv_qhs_tlmm_west", - .id = SC8180X_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tsif = { .name = "slv_qhs_tsif", - .id = SC8180X_SLAVE_TSIF, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ufs_card_cfg = { .name = "slv_qhs_ufs_card_cfg", - .id = SC8180X_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { .name = "slv_qhs_ufs_mem0_cfg", - .id = SC8180X_SLAVE_UFS_MEM_0_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { .name = "slv_qhs_ufs_mem1_cfg", - .id = SC8180X_SLAVE_UFS_MEM_1_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_usb3_0 = { .name = "slv_qhs_usb3_0", - .id = SC8180X_SLAVE_USB3, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_usb3_1 = { .name = "slv_qhs_usb3_1", - .id = SC8180X_SLAVE_USB3_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_usb3_2 = { .name = "slv_qhs_usb3_2", - .id = SC8180X_SLAVE_USB3_2, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_venus_cfg = { .name = "slv_qhs_venus_cfg", - .id = SC8180X_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { .name = "slv_qhs_vsense_ctrl_cfg", - .id = SC8180X_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_srvc_cnoc = { .name = "slv_srvc_cnoc", - .id = SC8180X_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_gemnoc = { .name = "slv_qhs_gemnoc", - .id = SC8180X_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_GEM_NOC_CFG } + .link_nodes = { &mas_qhm_gemnoc_cfg }, }; static struct qcom_icc_node slv_qhs_llcc = { .name = "slv_qhs_llcc", - .id = SC8180X_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { .name = "slv_qhs_mdsp_ms_mpu_cfg", - .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qns_ecc = { .name = "slv_qns_ecc", - .id = SC8180X_SLAVE_ECC, .channels = 1, .buswidth = 32 }; static struct qcom_icc_node slv_qns_gem_noc_snoc = { .name = "slv_qns_gem_noc_snoc", - .id = SC8180X_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_MASTER_GEM_NOC_SNOC } + .link_nodes = { &mas_qnm_gemnoc }, }; static struct qcom_icc_node slv_qns_llcc = { .name = "slv_qns_llcc", - .id = SC8180X_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { SC8180X_MASTER_LLCC } + .link_nodes = { &mas_llcc_mc }, }; static struct qcom_icc_node slv_srvc_gemnoc = { .name = "slv_srvc_gemnoc", - .id = SC8180X_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_srvc_gemnoc1 = { .name = "slv_srvc_gemnoc1", - .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_ebi = { .name = "slv_ebi", - .id = SC8180X_SLAVE_EBI_CH0, .channels = 8, .buswidth = 4 }; static struct qcom_icc_node slv_qns2_mem_noc = { .name = "slv_qns2_mem_noc", - .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC } + .link_nodes = { &mas_qnm_mnoc_sf }, }; static struct qcom_icc_node slv_qns_mem_noc_hf = { .name = "slv_qns_mem_noc_hf", - .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC } + .link_nodes = { &mas_qnm_mnoc_hf }, }; static struct qcom_icc_node slv_srvc_mnoc = { .name = "slv_srvc_mnoc", - .id = SC8180X_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_apss = { .name = "slv_qhs_apss", - .id = SC8180X_SLAVE_APPSS, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qns_cnoc = { .name = "slv_qns_cnoc", - .id = SC8180X_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SNOC_CNOC_MAS } + .link_nodes = { &mas_qnm_snoc }, }; static struct qcom_icc_node slv_qns_gemnoc_gc = { .name = "slv_qns_gemnoc_gc", - .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC } + .link_nodes = { &mas_qnm_snoc_gc }, }; static struct qcom_icc_node slv_qns_gemnoc_sf = { .name = "slv_qns_gemnoc_sf", - .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC } + .link_nodes = { &mas_qnm_snoc_sf }, }; static struct qcom_icc_node slv_qxs_imem = { .name = "slv_qxs_imem", - .id = SC8180X_SLAVE_OCIMEM, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qxs_pimem = { .name = "slv_qxs_pimem", - .id = SC8180X_SLAVE_PIMEM, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_srvc_snoc = { .name = "slv_srvc_snoc", - .id = SC8180X_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_xs_pcie_0 = { .name = "slv_xs_pcie_0", - .id = SC8180X_SLAVE_PCIE_0, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_pcie_1 = { .name = "slv_xs_pcie_1", - .id = SC8180X_SLAVE_PCIE_1, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_pcie_2 = { .name = "slv_xs_pcie_2", - .id = SC8180X_SLAVE_PCIE_2, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_pcie_3 = { .name = "slv_xs_pcie_3", - .id = SC8180X_SLAVE_PCIE_3, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_qdss_stm = { .name = "slv_xs_qdss_stm", - .id = SC8180X_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_xs_sys_tcu_cfg = { .name = "slv_xs_sys_tcu_cfg", - .id = SC8180X_SLAVE_TCU, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qup_core_0 = { .name = "slv_qup_core_0", - .id = SC8180X_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qup_core_1 = { .name = "slv_qup_core_1", - .id = SC8180X_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qup_core_2 = { .name = "slv_qup_core_2", - .id = SC8180X_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4 }; @@ -1790,6 +1790,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sc8180x_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1797,6 +1798,7 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = { }; static const struct qcom_icc_desc sc8180x_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1804,6 +1806,7 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = { }; static const struct qcom_icc_desc sc8180x_camnoc_virt = { + .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1811,6 +1814,7 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt = { }; static const struct qcom_icc_desc sc8180x_compute_noc = { + .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1818,6 +1822,7 @@ static const struct qcom_icc_desc sc8180x_compute_noc = { }; static const struct qcom_icc_desc sc8180x_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1825,11 +1830,13 @@ static const struct qcom_icc_desc sc8180x_config_noc = { }; static const struct qcom_icc_desc sc8180x_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; static const struct qcom_icc_desc sc8180x_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1837,6 +1844,7 @@ static const struct qcom_icc_desc sc8180x_gem_noc = { }; static const struct qcom_icc_desc sc8180x_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1844,6 +1852,7 @@ static const struct qcom_icc_desc sc8180x_mc_virt = { }; static const struct qcom_icc_desc sc8180x_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1851,6 +1860,7 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = { }; static const struct qcom_icc_desc sc8180x_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1871,6 +1881,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = { }; static const struct qcom_icc_desc sc8180x_qup_virt = { + .alloc_dyn_id = true, .nodes = qup_virt_nodes, .num_nodes = ARRAY_SIZE(qup_virt_nodes), .bcms = qup_virt_bcms, diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qcom/sc8180x.h deleted file mode 100644 index f8d90598335a..000000000000 --- a/drivers/interconnect/qcom/sc8180x.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC8180X interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H - -#define SC8180X_MASTER_A1NOC_CFG 1 -#define SC8180X_MASTER_UFS_CARD 2 -#define SC8180X_MASTER_UFS_GEN4 3 -#define SC8180X_MASTER_UFS_MEM 4 -#define SC8180X_MASTER_USB3 5 -#define SC8180X_MASTER_USB3_1 6 -#define SC8180X_MASTER_USB3_2 7 -#define SC8180X_MASTER_A2NOC_CFG 8 -#define SC8180X_MASTER_QDSS_BAM 9 -#define SC8180X_MASTER_QSPI_0 10 -#define SC8180X_MASTER_QSPI_1 11 -#define SC8180X_MASTER_QUP_0 12 -#define SC8180X_MASTER_QUP_1 13 -#define SC8180X_MASTER_QUP_2 14 -#define SC8180X_MASTER_SENSORS_AHB 15 -#define SC8180X_MASTER_CRYPTO_CORE_0 16 -#define SC8180X_MASTER_IPA 17 -#define SC8180X_MASTER_EMAC 18 -#define SC8180X_MASTER_PCIE 19 -#define SC8180X_MASTER_PCIE_1 20 -#define SC8180X_MASTER_PCIE_2 21 -#define SC8180X_MASTER_PCIE_3 22 -#define SC8180X_MASTER_QDSS_ETR 23 -#define SC8180X_MASTER_SDCC_2 24 -#define SC8180X_MASTER_SDCC_4 25 -#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26 -#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27 -#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28 -#define SC8180X_MASTER_NPU 29 -#define SC8180X_SNOC_CNOC_MAS 30 -#define SC8180X_MASTER_CNOC_DC_NOC 31 -#define SC8180X_MASTER_AMPSS_M0 32 -#define SC8180X_MASTER_GPU_TCU 33 -#define SC8180X_MASTER_SYS_TCU 34 -#define SC8180X_MASTER_GEM_NOC_CFG 35 -#define SC8180X_MASTER_COMPUTE_NOC 36 -#define SC8180X_MASTER_GRAPHICS_3D 37 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39 -#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40 -#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41 -#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42 -#define SC8180X_MASTER_ECC 43 -/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_MASTER_LLCC 45 -#define SC8180X_MASTER_CNOC_MNOC_CFG 46 -#define SC8180X_MASTER_CAMNOC_HF0 47 -#define SC8180X_MASTER_CAMNOC_HF1 48 -#define SC8180X_MASTER_CAMNOC_SF 49 -#define SC8180X_MASTER_MDP_PORT0 50 -#define SC8180X_MASTER_MDP_PORT1 51 -#define SC8180X_MASTER_ROTATOR 52 -#define SC8180X_MASTER_VIDEO_P0 53 -#define SC8180X_MASTER_VIDEO_P1 54 -#define SC8180X_MASTER_VIDEO_PROC 55 -#define SC8180X_MASTER_SNOC_CFG 56 -#define SC8180X_A1NOC_SNOC_MAS 57 -#define SC8180X_A2NOC_SNOC_MAS 58 -#define SC8180X_MASTER_GEM_NOC_SNOC 59 -#define SC8180X_MASTER_PIMEM 60 -#define SC8180X_MASTER_GIC 61 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63 -#define SC8180X_MASTER_LLCC_DISPLAY 64 -#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65 -#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66 -#define SC8180X_MASTER_ROTATOR_DISPLAY 67 -#define SC8180X_A1NOC_SNOC_SLV 68 -#define SC8180X_SLAVE_SERVICE_A1NOC 69 -#define SC8180X_A2NOC_SNOC_SLV 70 -#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71 -#define SC8180X_SLAVE_SERVICE_A2NOC 72 -#define SC8180X_SLAVE_CAMNOC_UNCOMP 73 -#define SC8180X_SLAVE_CDSP_MEM_NOC 74 -#define SC8180X_SLAVE_A1NOC_CFG 75 -#define SC8180X_SLAVE_A2NOC_CFG 76 -#define SC8180X_SLAVE_AHB2PHY_CENTER 77 -#define SC8180X_SLAVE_AHB2PHY_EAST 78 -#define SC8180X_SLAVE_AHB2PHY_WEST 79 -#define SC8180X_SLAVE_AHB2PHY_SOUTH 80 -#define SC8180X_SLAVE_AOP 81 -#define SC8180X_SLAVE_AOSS 82 -#define SC8180X_SLAVE_CAMERA_CFG 83 -#define SC8180X_SLAVE_CLK_CTL 84 -#define SC8180X_SLAVE_CDSP_CFG 85 -#define SC8180X_SLAVE_RBCPR_CX_CFG 86 -#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87 -#define SC8180X_SLAVE_RBCPR_MX_CFG 88 -#define SC8180X_SLAVE_CRYPTO_0_CFG 89 -#define SC8180X_SLAVE_CNOC_DDRSS 90 -#define SC8180X_SLAVE_DISPLAY_CFG 91 -#define SC8180X_SLAVE_EMAC_CFG 92 -#define SC8180X_SLAVE_GLM 93 -#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94 -#define SC8180X_SLAVE_IMEM_CFG 95 -#define SC8180X_SLAVE_IPA_CFG 96 -#define SC8180X_SLAVE_CNOC_MNOC_CFG 97 -#define SC8180X_SLAVE_NPU_CFG 98 -#define SC8180X_SLAVE_PCIE_0_CFG 99 -#define SC8180X_SLAVE_PCIE_1_CFG 100 -#define SC8180X_SLAVE_PCIE_2_CFG 101 -#define SC8180X_SLAVE_PCIE_3_CFG 102 -#define SC8180X_SLAVE_PDM 103 -#define SC8180X_SLAVE_PIMEM_CFG 104 -#define SC8180X_SLAVE_PRNG 105 -#define SC8180X_SLAVE_QDSS_CFG 106 -#define SC8180X_SLAVE_QSPI_0 107 -#define SC8180X_SLAVE_QSPI_1 108 -#define SC8180X_SLAVE_QUP_1 109 -#define SC8180X_SLAVE_QUP_2 110 -#define SC8180X_SLAVE_QUP_0 111 -#define SC8180X_SLAVE_SDCC_2 112 -#define SC8180X_SLAVE_SDCC_4 113 -#define SC8180X_SLAVE_SECURITY 114 -#define SC8180X_SLAVE_SNOC_CFG 115 -#define SC8180X_SLAVE_SPSS_CFG 116 -#define SC8180X_SLAVE_TCSR 117 -#define SC8180X_SLAVE_TLMM_EAST 118 -#define SC8180X_SLAVE_TLMM_SOUTH 119 -#define SC8180X_SLAVE_TLMM_WEST 120 -#define SC8180X_SLAVE_TSIF 121 -#define SC8180X_SLAVE_UFS_CARD_CFG 122 -#define SC8180X_SLAVE_UFS_MEM_0_CFG 123 -#define SC8180X_SLAVE_UFS_MEM_1_CFG 124 -#define SC8180X_SLAVE_USB3 125 -#define SC8180X_SLAVE_USB3_1 126 -#define SC8180X_SLAVE_USB3_2 127 -#define SC8180X_SLAVE_VENUS_CFG 128 -#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129 -#define SC8180X_SLAVE_SERVICE_CNOC 130 -#define SC8180X_SLAVE_GEM_NOC_CFG 131 -#define SC8180X_SLAVE_LLCC_CFG 132 -#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133 -#define SC8180X_SLAVE_ECC 134 -#define SC8180X_SLAVE_GEM_NOC_SNOC 135 -#define SC8180X_SLAVE_LLCC 136 -#define SC8180X_SLAVE_SERVICE_GEM_NOC 137 -#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138 -/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_SLAVE_EBI_CH0 140 -#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141 -#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142 -#define SC8180X_SLAVE_SERVICE_MNOC 143 -#define SC8180X_SLAVE_APPSS 144 -#define SC8180X_SNOC_CNOC_SLV 145 -#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146 -#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147 -#define SC8180X_SLAVE_OCIMEM 148 -#define SC8180X_SLAVE_PIMEM 149 -#define SC8180X_SLAVE_SERVICE_SNOC 150 -#define SC8180X_SLAVE_PCIE_0 151 -#define SC8180X_SLAVE_PCIE_1 152 -#define SC8180X_SLAVE_PCIE_2 153 -#define SC8180X_SLAVE_PCIE_3 154 -#define SC8180X_SLAVE_QDSS_STM 155 -#define SC8180X_SLAVE_TCU 156 -#define SC8180X_SLAVE_LLCC_DISPLAY 157 -#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158 -#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159 -#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160 - -#define SC8180X_MASTER_QUP_CORE_0 163 -#define SC8180X_MASTER_QUP_CORE_1 164 -#define SC8180X_MASTER_QUP_CORE_2 165 -#define SC8180X_SLAVE_QUP_CORE_0 166 -#define SC8180X_SLAVE_QUP_CORE_1 167 -#define SC8180X_SLAVE_QUP_CORE_2 168 - -#endif From 0ab0f87df82f9e4f8c208323399dffaba8cc3eb0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:20 +0200 Subject: [PATCH 139/304] interconnect: qcom: sc8280xp: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-4-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc8280xp.c | 837 +++++++++++++-------------- drivers/interconnect/qcom/sc8280xp.h | 209 ------- 2 files changed, 416 insertions(+), 630 deletions(-) delete mode 100644 drivers/interconnect/qcom/sc8280xp.h diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index c646cdf8a19b..c46846191e63 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -14,1699 +14,1682 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8280xp.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node xm_usb3_mp; +static struct qcom_icc_node xm_usb4_host0; +static struct qcom_icc_node xm_usb4_host1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_sensorss_q6; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2a; +static struct qcom_icc_node xm_pcie3_2b; +static struct qcom_icc_node xm_pcie3_3a; +static struct qcom_icc_node xm_pcie3_3b; +static struct qcom_icc_node xm_pcie3_4; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_cmpnoc1; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mdp1_0; +static struct qcom_icc_node qnm_mdp1_1; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_rot_0; +static struct qcom_icc_node qnm_rot_1; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qhm_nspb_noc_config; +static struct qcom_icc_node qxm_nspb; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_aggre_usb_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_aggre_usb_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_gem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_compute1_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display1_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_emac1_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2a_cfg; +static struct qcom_icc_node qhs_pcie2b_cfg; +static struct qcom_icc_node qhs_pcie3a_cfg; +static struct qcom_icc_node qhs_pcie3b_cfg; +static struct qcom_icc_node qhs_pcie4_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_smmuv3_cfg; +static struct qcom_icc_node qhs_smss_cfg; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_usb3_mp; +static struct qcom_icc_node qhs_usb4_host_0; +static struct qcom_icc_node qhs_usb4_host_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_r_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_anoc_pcie_bridge_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qns_snoc_sf_bridge_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2a; +static struct qcom_icc_node xs_pcie_2b; +static struct qcom_icc_node xs_pcie_3a; +static struct qcom_icc_node xs_pcie_3b; +static struct qcom_icc_node xs_pcie_4; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_smss; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qxs_nsp_xfr; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_nspb_gemnoc; +static struct qcom_icc_node qxs_nspb_xfr; +static struct qcom_icc_node service_nspb_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SC8280XP_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SC8280XP_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SC8280XP_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SC8280XP_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SC8280XP_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", - .id = SC8280XP_MASTER_EMAC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SC8280XP_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SC8280XP_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SC8280XP_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SC8280XP_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb3_mp = { .name = "xm_usb3_mp", - .id = SC8280XP_MASTER_USB3_MP, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb4_host0 = { .name = "xm_usb4_host0", - .id = SC8280XP_MASTER_USB4_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb4_host1 = { .name = "xm_usb4_host1", - .id = SC8280XP_MASTER_USB4_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SC8280XP_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SC8280XP_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SC8280XP_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SC8280XP_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sensorss_q6 = { .name = "qxm_sensorss_q6", - .id = SC8280XP_MASTER_SENSORS_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SC8280XP_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", - .id = SC8280XP_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SC8280XP_MASTER_PCIE_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SC8280XP_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_2a = { .name = "xm_pcie3_2a", - .id = SC8280XP_MASTER_PCIE_2A, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_2b = { .name = "xm_pcie3_2b", - .id = SC8280XP_MASTER_PCIE_2B, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_3a = { .name = "xm_pcie3_3a", - .id = SC8280XP_MASTER_PCIE_3A, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_3b = { .name = "xm_pcie3_3b", - .id = SC8280XP_MASTER_PCIE_3B, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_4 = { .name = "xm_pcie3_4", - .id = SC8280XP_MASTER_PCIE_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SC8280XP_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SC8280XP_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SC8280XP_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SC8280XP_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SC8280XP_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SC8280XP_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SC8280XP_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 76, - .links = { SC8280XP_SLAVE_AHB2PHY_0, - SC8280XP_SLAVE_AHB2PHY_1, - SC8280XP_SLAVE_AHB2PHY_2, - SC8280XP_SLAVE_AOSS, - SC8280XP_SLAVE_APPSS, - SC8280XP_SLAVE_CAMERA_CFG, - SC8280XP_SLAVE_CLK_CTL, - SC8280XP_SLAVE_CDSP_CFG, - SC8280XP_SLAVE_CDSP1_CFG, - SC8280XP_SLAVE_RBCPR_CX_CFG, - SC8280XP_SLAVE_RBCPR_MMCX_CFG, - SC8280XP_SLAVE_RBCPR_MX_CFG, - SC8280XP_SLAVE_CPR_NSPCX, - SC8280XP_SLAVE_CRYPTO_0_CFG, - SC8280XP_SLAVE_CX_RDPM, - SC8280XP_SLAVE_DCC_CFG, - SC8280XP_SLAVE_DISPLAY_CFG, - SC8280XP_SLAVE_DISPLAY1_CFG, - SC8280XP_SLAVE_EMAC_CFG, - SC8280XP_SLAVE_EMAC1_CFG, - SC8280XP_SLAVE_GFX3D_CFG, - SC8280XP_SLAVE_HWKM, - SC8280XP_SLAVE_IMEM_CFG, - SC8280XP_SLAVE_IPA_CFG, - SC8280XP_SLAVE_IPC_ROUTER_CFG, - SC8280XP_SLAVE_LPASS, - SC8280XP_SLAVE_MX_RDPM, - SC8280XP_SLAVE_MXC_RDPM, - SC8280XP_SLAVE_PCIE_0_CFG, - SC8280XP_SLAVE_PCIE_1_CFG, - SC8280XP_SLAVE_PCIE_2A_CFG, - SC8280XP_SLAVE_PCIE_2B_CFG, - SC8280XP_SLAVE_PCIE_3A_CFG, - SC8280XP_SLAVE_PCIE_3B_CFG, - SC8280XP_SLAVE_PCIE_4_CFG, - SC8280XP_SLAVE_PCIE_RSC_CFG, - SC8280XP_SLAVE_PDM, - SC8280XP_SLAVE_PIMEM_CFG, - SC8280XP_SLAVE_PKA_WRAPPER_CFG, - SC8280XP_SLAVE_PMU_WRAPPER_CFG, - SC8280XP_SLAVE_QDSS_CFG, - SC8280XP_SLAVE_QSPI_0, - SC8280XP_SLAVE_QUP_0, - SC8280XP_SLAVE_QUP_1, - SC8280XP_SLAVE_QUP_2, - SC8280XP_SLAVE_SDCC_2, - SC8280XP_SLAVE_SDCC_4, - SC8280XP_SLAVE_SECURITY, - SC8280XP_SLAVE_SMMUV3_CFG, - SC8280XP_SLAVE_SMSS_CFG, - SC8280XP_SLAVE_SPSS_CFG, - SC8280XP_SLAVE_TCSR, - SC8280XP_SLAVE_TLMM, - SC8280XP_SLAVE_UFS_CARD_CFG, - SC8280XP_SLAVE_UFS_MEM_CFG, - SC8280XP_SLAVE_USB3_0, - SC8280XP_SLAVE_USB3_1, - SC8280XP_SLAVE_USB3_MP, - SC8280XP_SLAVE_USB4_0, - SC8280XP_SLAVE_USB4_1, - SC8280XP_SLAVE_VENUS_CFG, - SC8280XP_SLAVE_VSENSE_CTRL_CFG, - SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, - SC8280XP_SLAVE_A1NOC_CFG, - SC8280XP_SLAVE_A2NOC_CFG, - SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, - SC8280XP_SLAVE_DDRSS_CFG, - SC8280XP_SLAVE_CNOC_MNOC_CFG, - SC8280XP_SLAVE_SNOC_CFG, - SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, - SC8280XP_SLAVE_IMEM, - SC8280XP_SLAVE_PIMEM, - SC8280XP_SLAVE_SERVICE_CNOC, - SC8280XP_SLAVE_QDSS_STM, - SC8280XP_SLAVE_SMSS, - SC8280XP_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_ahb2phy2, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute0_cfg, + &qhs_compute1_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_cpr_nspcx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display0_cfg, + &qhs_display1_cfg, + &qhs_emac0_cfg, + &qhs_emac1_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mx_rdpm, + &qhs_mxc_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie2a_cfg, + &qhs_pcie2b_cfg, + &qhs_pcie3a_cfg, + &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, + &qhs_pcie_rsc_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_smmuv3_cfg, + &qhs_smss_cfg, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_usb3_mp, + &qhs_usb4_host_0, + &qhs_usb4_host_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_vsense_ctrl_r_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_anoc_pcie_bridge_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qns_snoc_sf_bridge_cfg, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_smss, + &xs_sys_tcu_cfg, + NULL }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SC8280XP_SLAVE_PCIE_0, - SC8280XP_SLAVE_PCIE_1, - SC8280XP_SLAVE_PCIE_2A, - SC8280XP_SLAVE_PCIE_2B, - SC8280XP_SLAVE_PCIE_3A, - SC8280XP_SLAVE_PCIE_3B, - SC8280XP_SLAVE_PCIE_4 - }, + .link_nodes = { &xs_pcie_0, + &xs_pcie_1, + &xs_pcie_2a, + &xs_pcie_2b, + &xs_pcie_3a, + &xs_pcie_3b, + &xs_pcie_4 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SC8280XP_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC8280XP_SLAVE_LLCC_CFG, - SC8280XP_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SC8280XP_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", - .id = SC8280XP_MASTER_PCIE_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SC8280XP_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SC8280XP_MASTER_APPSS_PROC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc0 = { .name = "qnm_cmpnoc0", - .id = SC8280XP_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_cmpnoc1 = { .name = "qnm_cmpnoc1", - .id = SC8280XP_MASTER_COMPUTE_NOC_1, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SC8280XP_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1, - SC8280XP_SLAVE_SERVICE_GEM_NOC_2, - SC8280XP_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &srvc_even_gemnoc, + &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SC8280XP_MASTER_GFX3D, .channels = 4, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes = { &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SC8280XP_SLAVE_LPASS_CORE_CFG, - SC8280XP_SLAVE_LPASS_LPI_CFG, - SC8280XP_SLAVE_LPASS_MPU_CFG, - SC8280XP_SLAVE_LPASS_TOP_CFG, - SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, - SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_core, + &qhs_lpass_lpi, + &qhs_lpass_mpu, + &qhs_lpass_top, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = SC8280XP_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SC8280XP_SLAVE_LPASS_TOP_CFG, - SC8280XP_SLAVE_LPASS_SNOC, - SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, - SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_top, + &qns_sysnoc, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SC8280XP_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SC8280XP_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_0 = { .name = "qnm_mdp0_0", - .id = SC8280XP_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_1 = { .name = "qnm_mdp0_1", - .id = SC8280XP_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_0 = { .name = "qnm_mdp1_0", - .id = SC8280XP_MASTER_MDP_CORE1_0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_1 = { .name = "qnm_mdp1_1", - .id = SC8280XP_MASTER_MDP_CORE1_1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SC8280XP_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_rot_0 = { .name = "qnm_rot_0", - .id = SC8280XP_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_rot_1 = { .name = "qnm_rot_1", - .id = SC8280XP_MASTER_ROTATOR_1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SC8280XP_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SC8280XP_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SC8280XP_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", - .id = SC8280XP_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SC8280XP_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SC8280XP_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SC8280XP_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_CDSP_MEM_NOC, - SC8280XP_SLAVE_NSP_XFR - }, + .link_nodes = { &qns_nsp_gemnoc, + &qxs_nsp_xfr }, }; static struct qcom_icc_node qhm_nspb_noc_config = { .name = "qhm_nspb_noc_config", - .id = SC8280XP_MASTER_CDSPB_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC }, + .link_nodes = { &service_nspb_noc }, }; static struct qcom_icc_node qxm_nspb = { .name = "qxm_nspb", - .id = SC8280XP_MASTER_CDSP_PROC_B, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC, - SC8280XP_SLAVE_NSPB_XFR - }, + .link_nodes = { &qns_nspb_gemnoc, + &qxs_nspb_xfr }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SC8280XP_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SC8280XP_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre_usb_noc = { .name = "qnm_aggre_usb_noc", - .id = SC8280XP_MASTER_USB_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = SC8280XP_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SC8280XP_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SC8280XP_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SC8280XP_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SC8280XP_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_aggre_usb_snoc = { .name = "qns_aggre_usb_snoc", - .id = SC8280XP_SLAVE_USB_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_USB_NOC_SNOC }, + .link_nodes = { &qnm_aggre_usb_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SC8280XP_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SC8280XP_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_gem_noc = { .name = "qns_pcie_gem_noc", - .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SC8280XP_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SC8280XP_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SC8280XP_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SC8280XP_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SC8280XP_SLAVE_AHB2PHY_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SC8280XP_SLAVE_AHB2PHY_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SC8280XP_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SC8280XP_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SC8280XP_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SC8280XP_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SC8280XP_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute0_cfg = { .name = "qhs_compute0_cfg", - .id = SC8280XP_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_compute1_cfg = { .name = "qhs_compute1_cfg", - .id = SC8280XP_SLAVE_CDSP1_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CDSPB_NOC_CFG }, + .link_nodes = { &qhm_nspb_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SC8280XP_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SC8280XP_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SC8280XP_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SC8280XP_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SC8280XP_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SC8280XP_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display0_cfg = { .name = "qhs_display0_cfg", - .id = SC8280XP_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display1_cfg = { .name = "qhs_display1_cfg", - .id = SC8280XP_SLAVE_DISPLAY1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac0_cfg = { .name = "qhs_emac0_cfg", - .id = SC8280XP_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac1_cfg = { .name = "qhs_emac1_cfg", - .id = SC8280XP_SLAVE_EMAC1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SC8280XP_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SC8280XP_SLAVE_HWKM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SC8280XP_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SC8280XP_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SC8280XP_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SC8280XP_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SC8280XP_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mxc_rdpm = { .name = "qhs_mxc_rdpm", - .id = SC8280XP_SLAVE_MXC_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SC8280XP_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SC8280XP_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie2a_cfg = { .name = "qhs_pcie2a_cfg", - .id = SC8280XP_SLAVE_PCIE_2A_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie2b_cfg = { .name = "qhs_pcie2b_cfg", - .id = SC8280XP_SLAVE_PCIE_2B_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie3a_cfg = { .name = "qhs_pcie3a_cfg", - .id = SC8280XP_SLAVE_PCIE_3A_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie3b_cfg = { .name = "qhs_pcie3b_cfg", - .id = SC8280XP_SLAVE_PCIE_3B_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie4_cfg = { .name = "qhs_pcie4_cfg", - .id = SC8280XP_SLAVE_PCIE_4_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_rsc_cfg = { .name = "qhs_pcie_rsc_cfg", - .id = SC8280XP_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SC8280XP_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SC8280XP_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pka_wrapper_cfg = { .name = "qhs_pka_wrapper_cfg", - .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pmu_wrapper_cfg = { .name = "qhs_pmu_wrapper_cfg", - .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SC8280XP_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SC8280XP_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SC8280XP_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SC8280XP_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SC8280XP_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SC8280XP_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SC8280XP_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SC8280XP_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_smmuv3_cfg = { .name = "qhs_smmuv3_cfg", - .id = SC8280XP_SLAVE_SMMUV3_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_smss_cfg = { .name = "qhs_smss_cfg", - .id = SC8280XP_SLAVE_SMSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SC8280XP_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SC8280XP_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SC8280XP_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SC8280XP_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SC8280XP_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SC8280XP_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SC8280XP_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_mp = { .name = "qhs_usb3_mp", - .id = SC8280XP_SLAVE_USB3_MP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb4_host_0 = { .name = "qhs_usb4_host_0", - .id = SC8280XP_SLAVE_USB4_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb4_host_1 = { .name = "qhs_usb4_host_1", - .id = SC8280XP_SLAVE_USB4_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SC8280XP_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { .name = "qhs_vsense_ctrl_r_cfg", - .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SC8280XP_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_A1NOC_CFG }, + .link_nodes = { &qnm_a1noc_cfg }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SC8280XP_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_A2NOC_CFG }, + .link_nodes = { &qnm_a2noc_cfg }, }; static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { .name = "qns_anoc_pcie_bridge_cfg", - .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SC8280XP_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SC8280XP_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SC8280XP_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { .name = "qns_snoc_sf_bridge_cfg", - .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SC8280XP_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SC8280XP_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SC8280XP_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SC8280XP_SLAVE_PCIE_0, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SC8280XP_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_2a = { .name = "xs_pcie_2a", - .id = SC8280XP_SLAVE_PCIE_2A, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_2b = { .name = "xs_pcie_2b", - .id = SC8280XP_SLAVE_PCIE_2B, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_3a = { .name = "xs_pcie_3a", - .id = SC8280XP_SLAVE_PCIE_3A, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_3b = { .name = "xs_pcie_3b", - .id = SC8280XP_SLAVE_PCIE_3B, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_4 = { .name = "xs_pcie_4", - .id = SC8280XP_SLAVE_PCIE_4, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SC8280XP_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_smss = { .name = "xs_smss", - .id = SC8280XP_SLAVE_SMSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SC8280XP_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SC8280XP_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SC8280XP_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SC8280XP_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SC8280XP_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SC8280XP_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SC8280XP_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SC8280XP_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SC8280XP_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SC8280XP_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = SC8280XP_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SC8280XP_SLAVE_EBI1, .channels = 8, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SC8280XP_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SC8280XP_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc0 }, }; static struct qcom_icc_node qxs_nsp_xfr = { .name = "qxs_nsp_xfr", - .id = SC8280XP_SLAVE_NSP_XFR, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SC8280XP_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nspb_gemnoc = { .name = "qns_nspb_gemnoc", - .id = SC8280XP_SLAVE_CDSPB_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_COMPUTE_NOC_1 }, + .link_nodes = { &qnm_cmpnoc1 }, }; static struct qcom_icc_node qxs_nspb_xfr = { .name = "qxs_nspb_xfr", - .id = SC8280XP_SLAVE_NSPB_XFR, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node service_nspb_noc = { .name = "service_nspb_noc", - .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SC8280XP_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; @@ -2015,6 +1998,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -2051,6 +2035,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -2073,6 +2058,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -2177,6 +2163,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -2193,6 +2180,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -2227,6 +2215,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -2250,6 +2239,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -2267,6 +2257,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -2298,6 +2289,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -2318,6 +2310,7 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_nspa_noc = { + .alloc_dyn_id = true, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -2338,6 +2331,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_nspb_noc = { + .alloc_dyn_id = true, .nodes = nspb_noc_nodes, .num_nodes = ARRAY_SIZE(nspb_noc_nodes), .bcms = nspb_noc_bcms, @@ -2367,6 +2361,7 @@ static struct qcom_icc_node * const system_noc_main_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_system_noc_main = { + .alloc_dyn_id = true, .nodes = system_noc_main_nodes, .num_nodes = ARRAY_SIZE(system_noc_main_nodes), .bcms = system_noc_main_bcms, diff --git a/drivers/interconnect/qcom/sc8280xp.h b/drivers/interconnect/qcom/sc8280xp.h deleted file mode 100644 index c5c410fd5ec3..000000000000 --- a/drivers/interconnect/qcom/sc8280xp.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2021, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H - -#define SC8280XP_MASTER_GPU_TCU 0 -#define SC8280XP_MASTER_PCIE_TCU 1 -#define SC8280XP_MASTER_SYS_TCU 2 -#define SC8280XP_MASTER_APPSS_PROC 3 -/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8280XP_MASTER_LLCC 5 -#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6 -#define SC8280XP_MASTER_CDSP_NOC_CFG 7 -#define SC8280XP_MASTER_CDSPB_NOC_CFG 8 -#define SC8280XP_MASTER_QDSS_BAM 9 -#define SC8280XP_MASTER_QSPI_0 10 -#define SC8280XP_MASTER_QUP_0 11 -#define SC8280XP_MASTER_QUP_1 12 -#define SC8280XP_MASTER_QUP_2 13 -#define SC8280XP_MASTER_A1NOC_CFG 14 -#define SC8280XP_MASTER_A2NOC_CFG 15 -#define SC8280XP_MASTER_A1NOC_SNOC 16 -#define SC8280XP_MASTER_A2NOC_SNOC 17 -#define SC8280XP_MASTER_USB_NOC_SNOC 18 -#define SC8280XP_MASTER_CAMNOC_HF 19 -#define SC8280XP_MASTER_COMPUTE_NOC 20 -#define SC8280XP_MASTER_COMPUTE_NOC_1 21 -#define SC8280XP_MASTER_CNOC_DC_NOC 22 -#define SC8280XP_MASTER_GEM_NOC_CFG 23 -#define SC8280XP_MASTER_GEM_NOC_CNOC 24 -#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25 -#define SC8280XP_MASTER_GFX3D 26 -#define SC8280XP_MASTER_LPASS_ANOC 27 -#define SC8280XP_MASTER_MDP0 28 -#define SC8280XP_MASTER_MDP1 29 -#define SC8280XP_MASTER_MDP_CORE1_0 30 -#define SC8280XP_MASTER_MDP_CORE1_1 31 -#define SC8280XP_MASTER_CNOC_MNOC_CFG 32 -#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33 -#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34 -#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35 -#define SC8280XP_MASTER_ROTATOR 36 -#define SC8280XP_MASTER_ROTATOR_1 37 -#define SC8280XP_MASTER_SNOC_CFG 38 -#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39 -#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40 -#define SC8280XP_MASTER_VIDEO_P0 41 -#define SC8280XP_MASTER_VIDEO_P1 42 -#define SC8280XP_MASTER_VIDEO_PROC 43 -#define SC8280XP_MASTER_QUP_CORE_0 44 -#define SC8280XP_MASTER_QUP_CORE_1 45 -#define SC8280XP_MASTER_QUP_CORE_2 46 -#define SC8280XP_MASTER_CAMNOC_ICP 47 -#define SC8280XP_MASTER_CAMNOC_SF 48 -#define SC8280XP_MASTER_CRYPTO 49 -#define SC8280XP_MASTER_IPA 50 -#define SC8280XP_MASTER_LPASS_PROC 51 -#define SC8280XP_MASTER_CDSP_PROC 52 -#define SC8280XP_MASTER_CDSP_PROC_B 53 -#define SC8280XP_MASTER_PIMEM 54 -#define SC8280XP_MASTER_SENSORS_PROC 55 -#define SC8280XP_MASTER_SP 56 -#define SC8280XP_MASTER_EMAC 57 -#define SC8280XP_MASTER_EMAC_1 58 -#define SC8280XP_MASTER_GIC 59 -#define SC8280XP_MASTER_PCIE_0 60 -#define SC8280XP_MASTER_PCIE_1 61 -#define SC8280XP_MASTER_PCIE_2A 62 -#define SC8280XP_MASTER_PCIE_2B 63 -#define SC8280XP_MASTER_PCIE_3A 64 -#define SC8280XP_MASTER_PCIE_3B 65 -#define SC8280XP_MASTER_PCIE_4 66 -#define SC8280XP_MASTER_QDSS_ETR 67 -#define SC8280XP_MASTER_SDCC_2 68 -#define SC8280XP_MASTER_SDCC_4 69 -#define SC8280XP_MASTER_UFS_CARD 70 -#define SC8280XP_MASTER_UFS_MEM 71 -#define SC8280XP_MASTER_USB3_0 72 -#define SC8280XP_MASTER_USB3_1 73 -#define SC8280XP_MASTER_USB3_MP 74 -#define SC8280XP_MASTER_USB4_0 75 -#define SC8280XP_MASTER_USB4_1 76 -#define SC8280XP_SLAVE_EBI1 512 -/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8280XP_SLAVE_AHB2PHY_0 514 -#define SC8280XP_SLAVE_AHB2PHY_1 515 -#define SC8280XP_SLAVE_AHB2PHY_2 516 -#define SC8280XP_SLAVE_AOSS 517 -#define SC8280XP_SLAVE_APPSS 518 -#define SC8280XP_SLAVE_CAMERA_CFG 519 -#define SC8280XP_SLAVE_CLK_CTL 520 -#define SC8280XP_SLAVE_CDSP_CFG 521 -#define SC8280XP_SLAVE_CDSP1_CFG 522 -#define SC8280XP_SLAVE_RBCPR_CX_CFG 523 -#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524 -#define SC8280XP_SLAVE_RBCPR_MX_CFG 525 -#define SC8280XP_SLAVE_CPR_NSPCX 526 -#define SC8280XP_SLAVE_CRYPTO_0_CFG 527 -#define SC8280XP_SLAVE_CX_RDPM 528 -#define SC8280XP_SLAVE_DCC_CFG 529 -#define SC8280XP_SLAVE_DISPLAY_CFG 530 -#define SC8280XP_SLAVE_DISPLAY1_CFG 531 -#define SC8280XP_SLAVE_EMAC_CFG 532 -#define SC8280XP_SLAVE_EMAC1_CFG 533 -#define SC8280XP_SLAVE_GFX3D_CFG 534 -#define SC8280XP_SLAVE_HWKM 535 -#define SC8280XP_SLAVE_IMEM_CFG 536 -#define SC8280XP_SLAVE_IPA_CFG 537 -#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538 -#define SC8280XP_SLAVE_LLCC_CFG 539 -#define SC8280XP_SLAVE_LPASS 540 -#define SC8280XP_SLAVE_LPASS_CORE_CFG 541 -#define SC8280XP_SLAVE_LPASS_LPI_CFG 542 -#define SC8280XP_SLAVE_LPASS_MPU_CFG 543 -#define SC8280XP_SLAVE_LPASS_TOP_CFG 544 -#define SC8280XP_SLAVE_MX_RDPM 545 -#define SC8280XP_SLAVE_MXC_RDPM 546 -#define SC8280XP_SLAVE_PCIE_0_CFG 547 -#define SC8280XP_SLAVE_PCIE_1_CFG 548 -#define SC8280XP_SLAVE_PCIE_2A_CFG 549 -#define SC8280XP_SLAVE_PCIE_2B_CFG 550 -#define SC8280XP_SLAVE_PCIE_3A_CFG 551 -#define SC8280XP_SLAVE_PCIE_3B_CFG 552 -#define SC8280XP_SLAVE_PCIE_4_CFG 553 -#define SC8280XP_SLAVE_PCIE_RSC_CFG 554 -#define SC8280XP_SLAVE_PDM 555 -#define SC8280XP_SLAVE_PIMEM_CFG 556 -#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557 -#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558 -#define SC8280XP_SLAVE_QDSS_CFG 559 -#define SC8280XP_SLAVE_QSPI_0 560 -#define SC8280XP_SLAVE_QUP_0 561 -#define SC8280XP_SLAVE_QUP_1 562 -#define SC8280XP_SLAVE_QUP_2 563 -#define SC8280XP_SLAVE_SDCC_2 564 -#define SC8280XP_SLAVE_SDCC_4 565 -#define SC8280XP_SLAVE_SECURITY 566 -#define SC8280XP_SLAVE_SMMUV3_CFG 567 -#define SC8280XP_SLAVE_SMSS_CFG 568 -#define SC8280XP_SLAVE_SPSS_CFG 569 -#define SC8280XP_SLAVE_TCSR 570 -#define SC8280XP_SLAVE_TLMM 571 -#define SC8280XP_SLAVE_UFS_CARD_CFG 572 -#define SC8280XP_SLAVE_UFS_MEM_CFG 573 -#define SC8280XP_SLAVE_USB3_0 574 -#define SC8280XP_SLAVE_USB3_1 575 -#define SC8280XP_SLAVE_USB3_MP 576 -#define SC8280XP_SLAVE_USB4_0 577 -#define SC8280XP_SLAVE_USB4_1 578 -#define SC8280XP_SLAVE_VENUS_CFG 579 -#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580 -#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581 -#define SC8280XP_SLAVE_A1NOC_CFG 582 -#define SC8280XP_SLAVE_A1NOC_SNOC 583 -#define SC8280XP_SLAVE_A2NOC_CFG 584 -#define SC8280XP_SLAVE_A2NOC_SNOC 585 -#define SC8280XP_SLAVE_USB_NOC_SNOC 586 -#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587 -#define SC8280XP_SLAVE_DDRSS_CFG 588 -#define SC8280XP_SLAVE_GEM_NOC_CNOC 589 -#define SC8280XP_SLAVE_GEM_NOC_CFG 590 -#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591 -#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592 -#define SC8280XP_SLAVE_LLCC 593 -#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594 -#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595 -#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596 -#define SC8280XP_SLAVE_CDSP_MEM_NOC 597 -#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598 -#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599 -#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600 -#define SC8280XP_SLAVE_SNOC_CFG 601 -#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602 -#define SC8280XP_SLAVE_LPASS_SNOC 603 -#define SC8280XP_SLAVE_QUP_CORE_0 604 -#define SC8280XP_SLAVE_QUP_CORE_1 605 -#define SC8280XP_SLAVE_QUP_CORE_2 606 -#define SC8280XP_SLAVE_IMEM 607 -#define SC8280XP_SLAVE_NSP_XFR 608 -#define SC8280XP_SLAVE_NSPB_XFR 609 -#define SC8280XP_SLAVE_PIMEM 610 -#define SC8280XP_SLAVE_SERVICE_NSP_NOC 611 -#define SC8280XP_SLAVE_SERVICE_NSPB_NOC 612 -#define SC8280XP_SLAVE_SERVICE_A1NOC 613 -#define SC8280XP_SLAVE_SERVICE_A2NOC 614 -#define SC8280XP_SLAVE_SERVICE_CNOC 615 -#define SC8280XP_SLAVE_SERVICE_GEM_NOC_1 616 -#define SC8280XP_SLAVE_SERVICE_MNOC 617 -#define SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC 618 -#define SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 619 -#define SC8280XP_SLAVE_SERVICE_GEM_NOC_2 620 -#define SC8280XP_SLAVE_SERVICE_SNOC 621 -#define SC8280XP_SLAVE_SERVICE_GEM_NOC 622 -#define SC8280XP_SLAVE_PCIE_0 623 -#define SC8280XP_SLAVE_PCIE_1 624 -#define SC8280XP_SLAVE_PCIE_2A 625 -#define SC8280XP_SLAVE_PCIE_2B 626 -#define SC8280XP_SLAVE_PCIE_3A 627 -#define SC8280XP_SLAVE_PCIE_3B 628 -#define SC8280XP_SLAVE_PCIE_4 629 -#define SC8280XP_SLAVE_QDSS_STM 630 -#define SC8280XP_SLAVE_SMSS 631 -#define SC8280XP_SLAVE_TCU 632 - -#endif - From 4de68f33d10b8e22c304a540649a7efaa8293254 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:21 +0200 Subject: [PATCH 140/304] interconnect: qcom: sdm845: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-5-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdm845.c | 774 ++++++++++++++--------------- drivers/interconnect/qcom/sdm845.h | 140 ------ 2 files changed, 381 insertions(+), 533 deletions(-) delete mode 100644 drivers/interconnect/qcom/sdm845.h diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 855802be93fe..83d7a611cdf7 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -14,1251 +14,1231 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm845.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qhm_tic; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_pcie_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie_gen3_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pcie; +static struct qcom_icc_node qxs_pcie_gen3; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SDM845_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SDM845_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SDM845_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SDM845_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SDM845_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SDM845_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SDM845_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_pcie_0 = { .name = "xm_pcie_0", - .id = SDM845_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, + .link_nodes = { &qns_pcie_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SDM845_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDM845_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SDM845_MASTER_BLSP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SDM845_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDM845_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SDM845_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SDM845_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes = { &qns_pcie_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDM845_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SDM845_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SDM845_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SDM845_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SDM845_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qhm_tic = { .name = "qhm_tic", - .id = SDM845_MASTER_TIC, .channels = 1, .buswidth = 4, .num_links = 43, - .links = { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SDM845_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 42, - .links = { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SDM845_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 43, - .links = { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; static struct qcom_icc_node qhm_cnoc = { .name = "qhm_cnoc", - .id = SDM845_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM845_SLAVE_LLCC_CFG, - SDM845_SLAVE_MEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qhs_memnoc }, }; static struct qcom_icc_node acm_l3 = { .name = "acm_l3", - .id = SDM845_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDM845_SLAVE_GNOC_SNOC, - SDM845_SLAVE_GNOC_MEM_NOC, - SDM845_SLAVE_SERVICE_GNOC - }, + .link_nodes = { &qns_gladiator_sodv, + &qns_gnoc_memnoc, + &srvc_gnoc }, }; static struct qcom_icc_node pm_gnoc_cfg = { .name = "pm_gnoc_cfg", - .id = SDM845_MASTER_GNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_GNOC }, + .link_nodes = { &srvc_gnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDM845_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDM845_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_memnoc_cfg = { .name = "qhm_memnoc_cfg", - .id = SDM845_MASTER_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, - SDM845_SLAVE_SERVICE_MEM_NOC - }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, + &srvc_memnoc }, }; static struct qcom_icc_node qnm_apps = { .name = "qnm_apps", - .id = SDM845_MASTER_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SDM845_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SDM845_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDM845_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SDM845_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SDM845_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SDM845_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SDM845_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SDM845_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SDM845_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SDM845_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SDM845_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SDM845_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SDM845_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SDM845_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SDM845_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDM845_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SDM845_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SDM845_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gladiator_sodv = { .name = "qnm_gladiator_sodv", - .id = SDM845_MASTER_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 8, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDM845_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_pcie_anoc = { .name = "qnm_pcie_anoc", - .id = SDM845_MASTER_ANOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 5, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SDM845_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes = { &qns_memnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SDM845_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes = { &qns_memnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SDM845_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SDM845_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, - .num_links = 1, - .links = { 0 }, }; static struct qcom_icc_node qns_pcie_a1noc_snoc = { .name = "qns_pcie_a1noc_snoc", - .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie_anoc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SDM845_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_snoc = { .name = "qns_pcie_snoc", - .id = SDM845_SLAVE_ANOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie_anoc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SDM845_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SDM845_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SDM845_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SDM845_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SDM845_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDM845_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SDM845_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDM845_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp_cfg = { .name = "qhs_compute_dsp_cfg", - .id = SDM845_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SDM845_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDM845_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SDM845_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc }, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDM845_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SDM845_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SDM845_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SDM845_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDM845_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDM845_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SDM845_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SDM845_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_gen3_cfg = { .name = "qhs_pcie_gen3_cfg", - .id = SDM845_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDM845_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_phy_refgen_south = { .name = "qhs_phy_refgen_south", - .id = SDM845_SLAVE_SOUTH_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SDM845_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDM845_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDM845_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SDM845_SLAVE_BLSP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_south = { .name = "qhs_qupv3_south", - .id = SDM845_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SDM845_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SDM845_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDM845_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SDM845_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SDM845_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDM845_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SDM845_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SDM845_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SDM845_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SDM845_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SDM845_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SDM845_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SDM845_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SDM845_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SDM845_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SDM845_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SDM845_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SDM845_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SDM845_SLAVE_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_MEM_NOC_CFG }, + .link_nodes = { &qhm_memnoc_cfg }, }; static struct qcom_icc_node qns_gladiator_sodv = { .name = "qns_gladiator_sodv", - .id = SDM845_SLAVE_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_GNOC_SNOC }, + .link_nodes = { &qnm_gladiator_sodv }, }; static struct qcom_icc_node qns_gnoc_memnoc = { .name = "qns_gnoc_memnoc", - .id = SDM845_SLAVE_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM845_MASTER_GNOC_MEM_NOC }, + .link_nodes = { &qnm_apps }, }; static struct qcom_icc_node srvc_gnoc = { .name = "srvc_gnoc", - .id = SDM845_SLAVE_SERVICE_GNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDM845_SLAVE_EBI1, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_apps_io = { .name = "qns_apps_io", - .id = SDM845_SLAVE_MEM_NOC_GNOC, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDM845_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDM845_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node srvc_memnoc = { .name = "srvc_memnoc", - .id = SDM845_SLAVE_SERVICE_MEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SDM845_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SDM845_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM845_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SDM845_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDM845_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SDM845_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_memnoc_gc = { .name = "qns_memnoc_gc", - .id = SDM845_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_memnoc_sf = { .name = "qns_memnoc_sf", - .id = SDM845_SLAVE_SNOC_MEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDM845_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pcie = { .name = "qxs_pcie", - .id = SDM845_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pcie_gen3 = { .name = "qxs_pcie_gen3", - .id = SDM845_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SDM845_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDM845_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDM845_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDM845_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1534,6 +1514,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1563,6 +1544,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1624,6 +1606,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1640,6 +1623,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1658,6 +1642,7 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_gladiator_noc = { + .alloc_dyn_id = true, .nodes = gladiator_noc_nodes, .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), .bcms = gladiator_noc_bcms, @@ -1693,6 +1678,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_mem_noc = { + .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -1727,6 +1713,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1773,6 +1760,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h deleted file mode 100644 index bc7e425ce985..000000000000 --- a/drivers/interconnect/qcom/sdm845.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ -#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ - -#define SDM845_MASTER_A1NOC_CFG 1 -#define SDM845_MASTER_BLSP_1 2 -#define SDM845_MASTER_TSIF 3 -#define SDM845_MASTER_SDCC_2 4 -#define SDM845_MASTER_SDCC_4 5 -#define SDM845_MASTER_UFS_CARD 6 -#define SDM845_MASTER_UFS_MEM 7 -#define SDM845_MASTER_PCIE_0 8 -#define SDM845_MASTER_A2NOC_CFG 9 -#define SDM845_MASTER_QDSS_BAM 10 -#define SDM845_MASTER_BLSP_2 11 -#define SDM845_MASTER_CNOC_A2NOC 12 -#define SDM845_MASTER_CRYPTO 13 -#define SDM845_MASTER_IPA 14 -#define SDM845_MASTER_PCIE_1 15 -#define SDM845_MASTER_QDSS_ETR 16 -#define SDM845_MASTER_USB3_0 17 -#define SDM845_MASTER_USB3_1 18 -#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19 -#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20 -#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21 -#define SDM845_MASTER_SPDM 22 -#define SDM845_MASTER_TIC 23 -#define SDM845_MASTER_SNOC_CNOC 24 -#define SDM845_MASTER_QDSS_DAP 25 -#define SDM845_MASTER_CNOC_DC_NOC 26 -#define SDM845_MASTER_APPSS_PROC 27 -#define SDM845_MASTER_GNOC_CFG 28 -#define SDM845_MASTER_LLCC 29 -#define SDM845_MASTER_TCU_0 30 -#define SDM845_MASTER_MEM_NOC_CFG 31 -#define SDM845_MASTER_GNOC_MEM_NOC 32 -#define SDM845_MASTER_MNOC_HF_MEM_NOC 33 -#define SDM845_MASTER_MNOC_SF_MEM_NOC 34 -#define SDM845_MASTER_SNOC_GC_MEM_NOC 35 -#define SDM845_MASTER_SNOC_SF_MEM_NOC 36 -#define SDM845_MASTER_GFX3D 37 -#define SDM845_MASTER_CNOC_MNOC_CFG 38 -#define SDM845_MASTER_CAMNOC_HF0 39 -#define SDM845_MASTER_CAMNOC_HF1 40 -#define SDM845_MASTER_CAMNOC_SF 41 -#define SDM845_MASTER_MDP0 42 -#define SDM845_MASTER_MDP1 43 -#define SDM845_MASTER_ROTATOR 44 -#define SDM845_MASTER_VIDEO_P0 45 -#define SDM845_MASTER_VIDEO_P1 46 -#define SDM845_MASTER_VIDEO_PROC 47 -#define SDM845_MASTER_SNOC_CFG 48 -#define SDM845_MASTER_A1NOC_SNOC 49 -#define SDM845_MASTER_A2NOC_SNOC 50 -#define SDM845_MASTER_GNOC_SNOC 51 -#define SDM845_MASTER_MEM_NOC_SNOC 52 -#define SDM845_MASTER_ANOC_PCIE_SNOC 53 -#define SDM845_MASTER_PIMEM 54 -#define SDM845_MASTER_GIC 55 -#define SDM845_SLAVE_A1NOC_SNOC 56 -#define SDM845_SLAVE_SERVICE_A1NOC 57 -#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58 -#define SDM845_SLAVE_A2NOC_SNOC 59 -#define SDM845_SLAVE_ANOC_PCIE_SNOC 60 -#define SDM845_SLAVE_SERVICE_A2NOC 61 -#define SDM845_SLAVE_CAMNOC_UNCOMP 62 -#define SDM845_SLAVE_A1NOC_CFG 63 -#define SDM845_SLAVE_A2NOC_CFG 64 -#define SDM845_SLAVE_AOP 65 -#define SDM845_SLAVE_AOSS 66 -#define SDM845_SLAVE_CAMERA_CFG 67 -#define SDM845_SLAVE_CLK_CTL 68 -#define SDM845_SLAVE_CDSP_CFG 69 -#define SDM845_SLAVE_RBCPR_CX_CFG 70 -#define SDM845_SLAVE_CRYPTO_0_CFG 71 -#define SDM845_SLAVE_DCC_CFG 72 -#define SDM845_SLAVE_CNOC_DDRSS 73 -#define SDM845_SLAVE_DISPLAY_CFG 74 -#define SDM845_SLAVE_GLM 75 -#define SDM845_SLAVE_GFX3D_CFG 76 -#define SDM845_SLAVE_IMEM_CFG 77 -#define SDM845_SLAVE_IPA_CFG 78 -#define SDM845_SLAVE_CNOC_MNOC_CFG 79 -#define SDM845_SLAVE_PCIE_0_CFG 80 -#define SDM845_SLAVE_PCIE_1_CFG 81 -#define SDM845_SLAVE_PDM 82 -#define SDM845_SLAVE_SOUTH_PHY_CFG 83 -#define SDM845_SLAVE_PIMEM_CFG 84 -#define SDM845_SLAVE_PRNG 85 -#define SDM845_SLAVE_QDSS_CFG 86 -#define SDM845_SLAVE_BLSP_2 87 -#define SDM845_SLAVE_BLSP_1 88 -#define SDM845_SLAVE_SDCC_2 89 -#define SDM845_SLAVE_SDCC_4 90 -#define SDM845_SLAVE_SNOC_CFG 91 -#define SDM845_SLAVE_SPDM_WRAPPER 92 -#define SDM845_SLAVE_SPSS_CFG 93 -#define SDM845_SLAVE_TCSR 94 -#define SDM845_SLAVE_TLMM_NORTH 95 -#define SDM845_SLAVE_TLMM_SOUTH 96 -#define SDM845_SLAVE_TSIF 97 -#define SDM845_SLAVE_UFS_CARD_CFG 98 -#define SDM845_SLAVE_UFS_MEM_CFG 99 -#define SDM845_SLAVE_USB3_0 100 -#define SDM845_SLAVE_USB3_1 101 -#define SDM845_SLAVE_VENUS_CFG 102 -#define SDM845_SLAVE_VSENSE_CTRL_CFG 103 -#define SDM845_SLAVE_CNOC_A2NOC 104 -#define SDM845_SLAVE_SERVICE_CNOC 105 -#define SDM845_SLAVE_LLCC_CFG 106 -#define SDM845_SLAVE_MEM_NOC_CFG 107 -#define SDM845_SLAVE_GNOC_SNOC 108 -#define SDM845_SLAVE_GNOC_MEM_NOC 109 -#define SDM845_SLAVE_SERVICE_GNOC 110 -#define SDM845_SLAVE_EBI1 111 -#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112 -#define SDM845_SLAVE_MEM_NOC_GNOC 113 -#define SDM845_SLAVE_LLCC 114 -#define SDM845_SLAVE_MEM_NOC_SNOC 115 -#define SDM845_SLAVE_SERVICE_MEM_NOC 116 -#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117 -#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118 -#define SDM845_SLAVE_SERVICE_MNOC 119 -#define SDM845_SLAVE_APPSS 120 -#define SDM845_SLAVE_SNOC_CNOC 121 -#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122 -#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123 -#define SDM845_SLAVE_IMEM 124 -#define SDM845_SLAVE_PCIE_0 125 -#define SDM845_SLAVE_PCIE_1 126 -#define SDM845_SLAVE_PIMEM 127 -#define SDM845_SLAVE_SERVICE_SNOC 128 -#define SDM845_SLAVE_QDSS_STM 129 -#define SDM845_SLAVE_TCU 130 - -#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */ From 543f5fcba26356589254887c4ea7ed8a8ea2d38e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:22 +0200 Subject: [PATCH 141/304] interconnect: qcom: sm8250: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-6-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8250.c | 736 ++++++++++++++--------------- drivers/interconnect/qcom/sm8250.h | 168 ------- 2 files changed, 361 insertions(+), 543 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm8250.h diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index cc1b14c13529..2ed112eab155 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -14,1383 +14,1369 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8250.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_pcie3_modem; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node amm_npu_sys_cdp_w; +static struct qcom_icc_node qhm_cfg; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_pcie_modem_mem_noc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_modem_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm0; +static struct qcom_icc_node qhs_tlmm1; +static struct qcom_icc_node qhs_tlmm2; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cal_dp1; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_modem; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SM8250_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8250_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8250_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8250_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SM8250_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_pcie3_modem = { .name = "xm_pcie3_modem", - .id = SM8250_MASTER_PCIE_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, + .link_nodes = { &qns_pcie_modem_mem_noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8250_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8250_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8250_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SM8250_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM8250_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8250_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8250_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SM8250_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8250_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8250_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8250_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8250_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM8250_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8250_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SM8250_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM8250_MASTER_NPU, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_cdsp_mem_noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM8250_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 49, - .links = { SM8250_SLAVE_CDSP_CFG, - SM8250_SLAVE_CAMERA_CFG, - SM8250_SLAVE_TLMM_SOUTH, - SM8250_SLAVE_TLMM_NORTH, - SM8250_SLAVE_SDCC_4, - SM8250_SLAVE_TLMM_WEST, - SM8250_SLAVE_SDCC_2, - SM8250_SLAVE_CNOC_MNOC_CFG, - SM8250_SLAVE_UFS_MEM_CFG, - SM8250_SLAVE_SNOC_CFG, - SM8250_SLAVE_PDM, - SM8250_SLAVE_CX_RDPM, - SM8250_SLAVE_PCIE_1_CFG, - SM8250_SLAVE_A2NOC_CFG, - SM8250_SLAVE_QDSS_CFG, - SM8250_SLAVE_DISPLAY_CFG, - SM8250_SLAVE_PCIE_2_CFG, - SM8250_SLAVE_TCSR, - SM8250_SLAVE_DCC_CFG, - SM8250_SLAVE_CNOC_DDRSS, - SM8250_SLAVE_IPC_ROUTER_CFG, - SM8250_SLAVE_PCIE_0_CFG, - SM8250_SLAVE_RBCPR_MMCX_CFG, - SM8250_SLAVE_NPU_CFG, - SM8250_SLAVE_AHB2PHY_SOUTH, - SM8250_SLAVE_AHB2PHY_NORTH, - SM8250_SLAVE_GRAPHICS_3D_CFG, - SM8250_SLAVE_VENUS_CFG, - SM8250_SLAVE_TSIF, - SM8250_SLAVE_IPA_CFG, - SM8250_SLAVE_IMEM_CFG, - SM8250_SLAVE_USB3, - SM8250_SLAVE_SERVICE_CNOC, - SM8250_SLAVE_UFS_CARD_CFG, - SM8250_SLAVE_USB3_1, - SM8250_SLAVE_LPASS, - SM8250_SLAVE_RBCPR_CX_CFG, - SM8250_SLAVE_A1NOC_CFG, - SM8250_SLAVE_AOSS, - SM8250_SLAVE_PRNG, - SM8250_SLAVE_VSENSE_CTRL_CFG, - SM8250_SLAVE_QSPI_0, - SM8250_SLAVE_CRYPTO_0_CFG, - SM8250_SLAVE_PIMEM_CFG, - SM8250_SLAVE_RBCPR_MX_CFG, - SM8250_SLAVE_QUP_0, - SM8250_SLAVE_QUP_1, - SM8250_SLAVE_QUP_2, - SM8250_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_compute_dsp, + &qhs_camera_cfg, + &qhs_tlmm1, + &qhs_tlmm0, + &qhs_sdc4, + &qhs_tlmm2, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_snoc_cfg, + &qhs_pdm, + &qhs_cx_rdpm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_pcie_modem_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_ipc_router, + &qhs_pcie0_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_imem_cfg, + &qhs_usb3_0, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_usb3_1, + &qhs_lpass_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_clk_ctl }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM8250_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 50, - .links = { SM8250_SLAVE_CDSP_CFG, - SM8250_SLAVE_CAMERA_CFG, - SM8250_SLAVE_TLMM_SOUTH, - SM8250_SLAVE_TLMM_NORTH, - SM8250_SLAVE_SDCC_4, - SM8250_SLAVE_TLMM_WEST, - SM8250_SLAVE_SDCC_2, - SM8250_SLAVE_CNOC_MNOC_CFG, - SM8250_SLAVE_UFS_MEM_CFG, - SM8250_SLAVE_SNOC_CFG, - SM8250_SLAVE_PDM, - SM8250_SLAVE_CX_RDPM, - SM8250_SLAVE_PCIE_1_CFG, - SM8250_SLAVE_A2NOC_CFG, - SM8250_SLAVE_QDSS_CFG, - SM8250_SLAVE_DISPLAY_CFG, - SM8250_SLAVE_PCIE_2_CFG, - SM8250_SLAVE_TCSR, - SM8250_SLAVE_DCC_CFG, - SM8250_SLAVE_CNOC_DDRSS, - SM8250_SLAVE_IPC_ROUTER_CFG, - SM8250_SLAVE_CNOC_A2NOC, - SM8250_SLAVE_PCIE_0_CFG, - SM8250_SLAVE_RBCPR_MMCX_CFG, - SM8250_SLAVE_NPU_CFG, - SM8250_SLAVE_AHB2PHY_SOUTH, - SM8250_SLAVE_AHB2PHY_NORTH, - SM8250_SLAVE_GRAPHICS_3D_CFG, - SM8250_SLAVE_VENUS_CFG, - SM8250_SLAVE_TSIF, - SM8250_SLAVE_IPA_CFG, - SM8250_SLAVE_IMEM_CFG, - SM8250_SLAVE_USB3, - SM8250_SLAVE_SERVICE_CNOC, - SM8250_SLAVE_UFS_CARD_CFG, - SM8250_SLAVE_USB3_1, - SM8250_SLAVE_LPASS, - SM8250_SLAVE_RBCPR_CX_CFG, - SM8250_SLAVE_A1NOC_CFG, - SM8250_SLAVE_AOSS, - SM8250_SLAVE_PRNG, - SM8250_SLAVE_VSENSE_CTRL_CFG, - SM8250_SLAVE_QSPI_0, - SM8250_SLAVE_CRYPTO_0_CFG, - SM8250_SLAVE_PIMEM_CFG, - SM8250_SLAVE_RBCPR_MX_CFG, - SM8250_SLAVE_QUP_0, - SM8250_SLAVE_QUP_1, - SM8250_SLAVE_QUP_2, - SM8250_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_compute_dsp, + &qhs_camera_cfg, + &qhs_tlmm1, + &qhs_tlmm0, + &qhs_sdc4, + &qhs_tlmm2, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_snoc_cfg, + &qhs_pdm, + &qhs_cx_rdpm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_pcie_modem_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_ipc_router, + &qns_cnoc_a2noc, + &qhs_pcie0_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_imem_cfg, + &qhs_usb3_0, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_usb3_1, + &qhs_lpass_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_clk_ctl }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM8250_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8250_SLAVE_GEM_NOC_CFG, - SM8250_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_memnoc, + &qhs_llcc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8250_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8250_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8250_MASTER_AMPSS_M0, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC, - SM8250_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM8250_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SM8250_SLAVE_SERVICE_GEM_NOC_2, - SM8250_SLAVE_SERVICE_GEM_NOC_1, - SM8250_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &srvc_odd_gemnoc, + &srvc_even_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM8250_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8250_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8250_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8250_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8250_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8250_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8250_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC, - SM8250_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8250_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM8250_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8250_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8250_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8250_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SM8250_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SM8250_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8250_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM8250_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM8250_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM8250_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node amm_npu_sys = { .name = "amm_npu_sys", - .id = SM8250_MASTER_NPU_SYS, .channels = 4, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node amm_npu_sys_cdp_w = { .name = "amm_npu_sys_cdp_w", - .id = SM8250_MASTER_NPU_CDP, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node qhm_cfg = { .name = "qhm_cfg", - .id = SM8250_MASTER_NPU_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 9, - .links = { SM8250_SLAVE_SERVICE_NPU_NOC, - SM8250_SLAVE_ISENSE_CFG, - SM8250_SLAVE_NPU_LLM_CFG, - SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, - SM8250_SLAVE_NPU_CP, - SM8250_SLAVE_NPU_TCM, - SM8250_SLAVE_NPU_CAL_DP0, - SM8250_SLAVE_NPU_CAL_DP1, - SM8250_SLAVE_NPU_DPM - }, + .link_nodes = { &srvc_noc, + &qhs_isense, + &qhs_llm, + &qhs_dma_bwmon, + &qhs_cp, + &qhs_tcm, + &qhs_cal_dp0, + &qhs_cal_dp1, + &qhs_dpm }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM8250_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8250_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8250_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM8250_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM8250_SLAVE_PIMEM, - SM8250_SLAVE_OCIMEM, - SM8250_SLAVE_APPSS, - SM8250_SNOC_CNOC_SLV, - SM8250_SLAVE_TCU, - SM8250_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8250_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SM8250_SLAVE_PCIE_2, - SM8250_SLAVE_PCIE_0, - SM8250_SLAVE_PCIE_1 - }, + .link_nodes = { &xs_pcie_modem, + &xs_pcie_0, + &xs_pcie_1 }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8250_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8250_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8250_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_pcie_modem_mem_noc = { .name = "qns_pcie_modem_mem_noc", - .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8250_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8250_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8250_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cdsp_mem_noc = { .name = "qns_cdsp_mem_noc", - .id = SM8250_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM8250_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM8250_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8250_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8250_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8250_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8250_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8250_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp = { .name = "qhs_compute_dsp", - .id = SM8250_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8250_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8250_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM8250_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8250_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8250_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SM8250_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM8250_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8250_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8250_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8250_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8250_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8250_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SM8250_SLAVE_LPASS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM8250_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SM8250_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_NPU_NOC_CFG }, + .link_nodes = { &qhm_cfg }, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8250_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8250_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_modem_cfg = { .name = "qhs_pcie_modem_cfg", - .id = SM8250_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8250_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8250_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8250_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8250_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8250_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM8250_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8250_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8250_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8250_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8250_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM8250_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8250_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm0 = { .name = "qhs_tlmm0", - .id = SM8250_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm1 = { .name = "qhs_tlmm1", - .id = SM8250_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm2 = { .name = "qhs_tlmm2", - .id = SM8250_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SM8250_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SM8250_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8250_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8250_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SM8250_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8250_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8250_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SM8250_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8250_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM8250_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SM8250_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM8250_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8250_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SM8250_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SM8250_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SM8250_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8250_SLAVE_EBI_CH0, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8250_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8250_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8250_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp0 = { .name = "qhs_cal_dp0", - .id = SM8250_SLAVE_NPU_CAL_DP0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp1 = { .name = "qhs_cal_dp1", - .id = SM8250_SLAVE_NPU_CAL_DP1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cp = { .name = "qhs_cp", - .id = SM8250_SLAVE_NPU_CP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dma_bwmon = { .name = "qhs_dma_bwmon", - .id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dpm = { .name = "qhs_dpm", - .id = SM8250_SLAVE_NPU_DPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_isense = { .name = "qhs_isense", - .id = SM8250_SLAVE_ISENSE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llm = { .name = "qhs_llm", - .id = SM8250_SLAVE_NPU_LLM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcm = { .name = "qhs_tcm", - .id = SM8250_SLAVE_NPU_TCM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_npu_sys = { .name = "qns_npu_sys", - .id = SM8250_SLAVE_NPU_COMPUTE_NOC, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node srvc_noc = { .name = "srvc_noc", - .id = SM8250_SLAVE_SERVICE_NPU_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8250_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM8250_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8250_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8250_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8250_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8250_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8250_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8250_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8250_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_modem = { .name = "xs_pcie_modem", - .id = SM8250_SLAVE_PCIE_2, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8250_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8250_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8250_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8250_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8250_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8250_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8250_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8250_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, }; diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h deleted file mode 100644 index 032665093c5b..000000000000 --- a/drivers/interconnect/qcom/sm8250.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H - -#define SM8250_A1NOC_SNOC_MAS 0 -#define SM8250_A1NOC_SNOC_SLV 1 -#define SM8250_A2NOC_SNOC_MAS 2 -#define SM8250_A2NOC_SNOC_SLV 3 -#define SM8250_MASTER_A1NOC_CFG 4 -#define SM8250_MASTER_A2NOC_CFG 5 -#define SM8250_MASTER_AMPSS_M0 6 -#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7 -#define SM8250_MASTER_CAMNOC_HF 8 -#define SM8250_MASTER_CAMNOC_ICP 9 -#define SM8250_MASTER_CAMNOC_SF 10 -#define SM8250_MASTER_CNOC_A2NOC 11 -#define SM8250_MASTER_CNOC_DC_NOC 12 -#define SM8250_MASTER_CNOC_MNOC_CFG 13 -#define SM8250_MASTER_COMPUTE_NOC 14 -#define SM8250_MASTER_CRYPTO_CORE_0 15 -#define SM8250_MASTER_GEM_NOC_CFG 16 -#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17 -#define SM8250_MASTER_GEM_NOC_SNOC 18 -#define SM8250_MASTER_GIC 19 -#define SM8250_MASTER_GPU_TCU 20 -#define SM8250_MASTER_GRAPHICS_3D 21 -#define SM8250_MASTER_IPA 22 -/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SM8250_MASTER_LLCC 24 -#define SM8250_MASTER_MDP_PORT0 25 -#define SM8250_MASTER_MDP_PORT1 26 -#define SM8250_MASTER_MNOC_HF_MEM_NOC 27 -#define SM8250_MASTER_MNOC_SF_MEM_NOC 28 -#define SM8250_MASTER_NPU 29 -#define SM8250_MASTER_NPU_CDP 30 -#define SM8250_MASTER_NPU_NOC_CFG 31 -#define SM8250_MASTER_NPU_SYS 32 -#define SM8250_MASTER_PCIE 33 -#define SM8250_MASTER_PCIE_1 34 -#define SM8250_MASTER_PCIE_2 35 -#define SM8250_MASTER_PIMEM 36 -#define SM8250_MASTER_QDSS_BAM 37 -#define SM8250_MASTER_QDSS_DAP 38 -#define SM8250_MASTER_QDSS_ETR 39 -#define SM8250_MASTER_QSPI_0 40 -#define SM8250_MASTER_QUP_0 41 -#define SM8250_MASTER_QUP_1 42 -#define SM8250_MASTER_QUP_2 43 -#define SM8250_MASTER_ROTATOR 44 -#define SM8250_MASTER_SDCC_2 45 -#define SM8250_MASTER_SDCC_4 46 -#define SM8250_MASTER_SNOC_CFG 47 -#define SM8250_MASTER_SNOC_GC_MEM_NOC 48 -#define SM8250_MASTER_SNOC_SF_MEM_NOC 49 -#define SM8250_MASTER_SYS_TCU 50 -#define SM8250_MASTER_TSIF 51 -#define SM8250_MASTER_UFS_CARD 52 -#define SM8250_MASTER_UFS_MEM 53 -#define SM8250_MASTER_USB3 54 -#define SM8250_MASTER_USB3_1 55 -#define SM8250_MASTER_VIDEO_P0 56 -#define SM8250_MASTER_VIDEO_P1 57 -#define SM8250_MASTER_VIDEO_PROC 58 -#define SM8250_SLAVE_A1NOC_CFG 59 -#define SM8250_SLAVE_A2NOC_CFG 60 -#define SM8250_SLAVE_AHB2PHY_NORTH 61 -#define SM8250_SLAVE_AHB2PHY_SOUTH 62 -#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64 -#define SM8250_SLAVE_AOSS 65 -#define SM8250_SLAVE_APPSS 66 -#define SM8250_SLAVE_CAMERA_CFG 67 -#define SM8250_SLAVE_CDSP_CFG 68 -#define SM8250_SLAVE_CDSP_MEM_NOC 69 -#define SM8250_SLAVE_CLK_CTL 70 -#define SM8250_SLAVE_CNOC_A2NOC 71 -#define SM8250_SLAVE_CNOC_DDRSS 72 -#define SM8250_SLAVE_CNOC_MNOC_CFG 73 -#define SM8250_SLAVE_CRYPTO_0_CFG 74 -#define SM8250_SLAVE_CX_RDPM 75 -#define SM8250_SLAVE_DCC_CFG 76 -#define SM8250_SLAVE_DISPLAY_CFG 77 -#define SM8250_SLAVE_EBI_CH0 78 -#define SM8250_SLAVE_GEM_NOC_CFG 79 -#define SM8250_SLAVE_GEM_NOC_SNOC 80 -#define SM8250_SLAVE_GRAPHICS_3D_CFG 81 -#define SM8250_SLAVE_IMEM_CFG 82 -#define SM8250_SLAVE_IPA_CFG 83 -/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8250_SLAVE_IPC_ROUTER_CFG 85 -#define SM8250_SLAVE_ISENSE_CFG 86 -#define SM8250_SLAVE_LLCC 87 -#define SM8250_SLAVE_LLCC_CFG 88 -#define SM8250_SLAVE_LPASS 89 -#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90 -#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91 -#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92 -#define SM8250_SLAVE_NPU_CAL_DP0 93 -#define SM8250_SLAVE_NPU_CAL_DP1 94 -#define SM8250_SLAVE_NPU_CFG 95 -#define SM8250_SLAVE_NPU_COMPUTE_NOC 96 -#define SM8250_SLAVE_NPU_CP 97 -#define SM8250_SLAVE_NPU_DPM 98 -#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99 -#define SM8250_SLAVE_NPU_LLM_CFG 100 -#define SM8250_SLAVE_NPU_TCM 101 -#define SM8250_SLAVE_OCIMEM 102 -#define SM8250_SLAVE_PCIE_0 103 -#define SM8250_SLAVE_PCIE_0_CFG 104 -#define SM8250_SLAVE_PCIE_1 105 -#define SM8250_SLAVE_PCIE_1_CFG 106 -#define SM8250_SLAVE_PCIE_2 107 -#define SM8250_SLAVE_PCIE_2_CFG 108 -#define SM8250_SLAVE_PDM 109 -#define SM8250_SLAVE_PIMEM 110 -#define SM8250_SLAVE_PIMEM_CFG 111 -#define SM8250_SLAVE_PRNG 112 -#define SM8250_SLAVE_QDSS_CFG 113 -#define SM8250_SLAVE_QDSS_STM 114 -#define SM8250_SLAVE_QSPI_0 115 -#define SM8250_SLAVE_QUP_0 116 -#define SM8250_SLAVE_QUP_1 117 -#define SM8250_SLAVE_QUP_2 118 -#define SM8250_SLAVE_RBCPR_CX_CFG 119 -#define SM8250_SLAVE_RBCPR_MMCX_CFG 120 -#define SM8250_SLAVE_RBCPR_MX_CFG 121 -#define SM8250_SLAVE_SDCC_2 122 -#define SM8250_SLAVE_SDCC_4 123 -#define SM8250_SLAVE_SERVICE_A1NOC 124 -#define SM8250_SLAVE_SERVICE_A2NOC 125 -#define SM8250_SLAVE_SERVICE_CNOC 126 -#define SM8250_SLAVE_SERVICE_GEM_NOC 127 -#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128 -#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129 -#define SM8250_SLAVE_SERVICE_MNOC 130 -#define SM8250_SLAVE_SERVICE_NPU_NOC 131 -#define SM8250_SLAVE_SERVICE_SNOC 132 -#define SM8250_SLAVE_SNOC_CFG 133 -#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134 -#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135 -#define SM8250_SLAVE_TCSR 136 -#define SM8250_SLAVE_TCU 137 -#define SM8250_SLAVE_TLMM_NORTH 138 -#define SM8250_SLAVE_TLMM_SOUTH 139 -#define SM8250_SLAVE_TLMM_WEST 140 -#define SM8250_SLAVE_TSIF 141 -#define SM8250_SLAVE_UFS_CARD_CFG 142 -#define SM8250_SLAVE_UFS_MEM_CFG 143 -#define SM8250_SLAVE_USB3 144 -#define SM8250_SLAVE_USB3_1 145 -#define SM8250_SLAVE_VENUS_CFG 146 -#define SM8250_SLAVE_VSENSE_CTRL_CFG 147 -#define SM8250_SNOC_CNOC_MAS 148 -#define SM8250_SNOC_CNOC_SLV 149 -#define SM8250_MASTER_QUP_CORE_0 150 -#define SM8250_MASTER_QUP_CORE_1 151 -#define SM8250_MASTER_QUP_CORE_2 152 -#define SM8250_SLAVE_QUP_CORE_0 153 -#define SM8250_SLAVE_QUP_CORE_1 154 -#define SM8250_SLAVE_QUP_CORE_2 155 - -#endif From 793cfcd1d6ad43595ad1eb3c08a023b767525783 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:23 +0200 Subject: [PATCH 142/304] interconnect: qcom: x1e80100: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-7-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/x1e80100.c | 629 +++++++++++++-------------- drivers/interconnect/qcom/x1e80100.h | 192 -------- 2 files changed, 292 insertions(+), 529 deletions(-) delete mode 100644 drivers/interconnect/qcom/x1e80100.h diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c index 2c46fdb4a054..d5df26f02675 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -15,1342 +15,1278 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "x1e80100.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_noc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_av1_enc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_eva; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_pcie_north_gem_noc; +static struct qcom_icc_node qnm_pcie_south_gem_noc; +static struct qcom_icc_node xm_pcie_3; +static struct qcom_icc_node xm_pcie_4; +static struct qcom_icc_node xm_pcie_5; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node xm_pcie_1; +static struct qcom_icc_node xm_pcie_2; +static struct qcom_icc_node xm_pcie_6a; +static struct qcom_icc_node xm_pcie_6b; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gic; +static struct qcom_icc_node qnm_usb_anoc; +static struct qcom_icc_node qnm_aggre_usb_north_snoc; +static struct qcom_icc_node qnm_aggre_usb_south_snoc; +static struct qcom_icc_node xm_usb2_0; +static struct qcom_icc_node xm_usb3_mp; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node xm_usb3_2; +static struct qcom_icc_node xm_usb4_0; +static struct qcom_icc_node xm_usb4_1; +static struct qcom_icc_node xm_usb4_2; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_av1_enc_cfg; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie3_cfg; +static struct qcom_icc_node qhs_pcie4_cfg; +static struct qcom_icc_node qhs_pcie5_cfg; +static struct qcom_icc_node qhs_pcie6a_cfg; +static struct qcom_icc_node qhs_pcie6b_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_smmuv3_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0_cfg; +static struct qcom_icc_node qhs_usb3_0_cfg; +static struct qcom_icc_node qhs_usb3_1_cfg; +static struct qcom_icc_node qhs_usb3_2_cfg; +static struct qcom_icc_node qhs_usb3_mp_cfg; +static struct qcom_icc_node qhs_usb4_0_cfg; +static struct qcom_icc_node qhs_usb4_1_cfg; +static struct qcom_icc_node qhs_usb4_2_cfg; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qss_lpass_qtb_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_pcie_3; +static struct qcom_icc_node xs_pcie_4; +static struct qcom_icc_node xs_pcie_5; +static struct qcom_icc_node xs_pcie_6a; +static struct qcom_icc_node xs_pcie_6b; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_pcie_north_gem_noc; +static struct qcom_icc_node qns_pcie_south_gem_noc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_aggre_usb_snoc; +static struct qcom_icc_node qns_aggre_usb_north_snoc; +static struct qcom_icc_node qns_aggre_usb_south_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = X1E80100_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = X1E80100_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = X1E80100_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = X1E80100_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = X1E80100_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = X1E80100_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = X1E80100_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = X1E80100_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = X1E80100_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = X1E80100_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = X1E80100_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = X1E80100_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = X1E80100_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = X1E80100_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = X1E80100_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 47, - .links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH, - X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG, - X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL, - X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG, - X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG, - X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG, - X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG, - X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG, - X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG, - X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG, - X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG, - X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0, - X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1, - X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2, - X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG, - X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM, - X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2, - X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1, - X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP, - X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1, - X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG, - X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG, - X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM, - X1E80100_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_av1_enc_cfg, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3_cfg, &qhs_pcie4_cfg, + &qhs_pcie5_cfg, &qhs_pcie6a_cfg, + &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = X1E80100_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG, - X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG, - X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM }, + .link_nodes = { &qhs_aoss, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, .num_links = 8, - .links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1, - X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3, - X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5, - X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2, &xs_pcie_3, + &xs_pcie_4, &xs_pcie_5, + &xs_pcie_6a, &xs_pcie_6b }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = X1E80100_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", - .id = X1E80100_MASTER_PCIE_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = X1E80100_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = X1E80100_MASTER_APPSS_PROC, .channels = 6, .buswidth = 32, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = X1E80100_MASTER_GFX3D, .channels = 4, .buswidth = 32, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_lpass = { .name = "qnm_lpass", - .id = X1E80100_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = X1E80100_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = X1E80100_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_noc = { .name = "qnm_nsp_noc", - .id = X1E80100_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = X1E80100_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 64, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = X1E80100_MASTER_GIC2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = X1E80100_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = X1E80100_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qxm_lpinoc_dsp_axim = { .name = "qxm_lpinoc_dsp_axim", - .id = X1E80100_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = X1E80100_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_av1_enc = { .name = "qnm_av1_enc", - .id = X1E80100_MASTER_AV1_ENC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = X1E80100_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = X1E80100_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = X1E80100_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_eva = { .name = "qnm_eva", - .id = X1E80100_MASTER_EVA, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = X1E80100_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = X1E80100_MASTER_VIDEO, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = X1E80100_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = X1E80100_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = X1E80100_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = X1E80100_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_pcie_north_gem_noc = { .name = "qnm_pcie_north_gem_noc", - .id = X1E80100_MASTER_PCIE_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qnm_pcie_south_gem_noc = { .name = "qnm_pcie_south_gem_noc", - .id = X1E80100_MASTER_PCIE_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie_3 = { .name = "xm_pcie_3", - .id = X1E80100_MASTER_PCIE_3, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes = { &qns_pcie_north_gem_noc }, }; static struct qcom_icc_node xm_pcie_4 = { .name = "xm_pcie_4", - .id = X1E80100_MASTER_PCIE_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes = { &qns_pcie_north_gem_noc }, }; static struct qcom_icc_node xm_pcie_5 = { .name = "xm_pcie_5", - .id = X1E80100_MASTER_PCIE_5, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes = { &qns_pcie_north_gem_noc }, }; static struct qcom_icc_node xm_pcie_0 = { .name = "xm_pcie_0", - .id = X1E80100_MASTER_PCIE_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_1 = { .name = "xm_pcie_1", - .id = X1E80100_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_2 = { .name = "xm_pcie_2", - .id = X1E80100_MASTER_PCIE_2, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_6a = { .name = "xm_pcie_6a", - .id = X1E80100_MASTER_PCIE_6A, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_6b = { .name = "xm_pcie_6b", - .id = X1E80100_MASTER_PCIE_6B, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = X1E80100_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = X1E80100_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_gic = { .name = "qnm_gic", - .id = X1E80100_MASTER_GIC1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_usb_anoc = { .name = "qnm_usb_anoc", - .id = X1E80100_MASTER_USB_NOC_SNOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre_usb_north_snoc = { .name = "qnm_aggre_usb_north_snoc", - .id = X1E80100_MASTER_AGGRE_USB_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node qnm_aggre_usb_south_snoc = { .name = "qnm_aggre_usb_south_snoc", - .id = X1E80100_MASTER_AGGRE_USB_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb2_0 = { .name = "xm_usb2_0", - .id = X1E80100_MASTER_USB2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, + .link_nodes = { &qns_aggre_usb_north_snoc }, }; static struct qcom_icc_node xm_usb3_mp = { .name = "xm_usb3_mp", - .id = X1E80100_MASTER_USB3_MP, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, + .link_nodes = { &qns_aggre_usb_north_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = X1E80100_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = X1E80100_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb3_2 = { .name = "xm_usb3_2", - .id = X1E80100_MASTER_USB3_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb4_0 = { .name = "xm_usb4_0", - .id = X1E80100_MASTER_USB4_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb4_1 = { .name = "xm_usb4_1", - .id = X1E80100_MASTER_USB4_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb4_2 = { .name = "xm_usb4_2", - .id = X1E80100_MASTER_USB4_2, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = X1E80100_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = X1E80100_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = X1E80100_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = X1E80100_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = X1E80100_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = X1E80100_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = X1E80100_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = X1E80100_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_av1_enc_cfg = { .name = "qhs_av1_enc_cfg", - .id = X1E80100_SLAVE_AV1_ENC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = X1E80100_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = X1E80100_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = X1E80100_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = X1E80100_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = X1E80100_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = X1E80100_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = X1E80100_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = X1E80100_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = X1E80100_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie2_cfg = { .name = "qhs_pcie2_cfg", - .id = X1E80100_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie3_cfg = { .name = "qhs_pcie3_cfg", - .id = X1E80100_SLAVE_PCIE_3_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie4_cfg = { .name = "qhs_pcie4_cfg", - .id = X1E80100_SLAVE_PCIE_4_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie5_cfg = { .name = "qhs_pcie5_cfg", - .id = X1E80100_SLAVE_PCIE_5_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie6a_cfg = { .name = "qhs_pcie6a_cfg", - .id = X1E80100_SLAVE_PCIE_6A_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie6b_cfg = { .name = "qhs_pcie6b_cfg", - .id = X1E80100_SLAVE_PCIE_6B_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rsc_cfg = { .name = "qhs_pcie_rsc_cfg", - .id = X1E80100_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = X1E80100_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = X1E80100_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = X1E80100_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = X1E80100_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = X1E80100_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = X1E80100_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = X1E80100_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = X1E80100_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = X1E80100_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_smmuv3_cfg = { .name = "qhs_smmuv3_cfg", - .id = X1E80100_SLAVE_SMMUV3_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = X1E80100_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = X1E80100_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = X1E80100_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb2_0_cfg = { .name = "qhs_usb2_0_cfg", - .id = X1E80100_SLAVE_USB2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0_cfg = { .name = "qhs_usb3_0_cfg", - .id = X1E80100_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_1_cfg = { .name = "qhs_usb3_1_cfg", - .id = X1E80100_SLAVE_USB3_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_2_cfg = { .name = "qhs_usb3_2_cfg", - .id = X1E80100_SLAVE_USB3_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_mp_cfg = { .name = "qhs_usb3_mp_cfg", - .id = X1E80100_SLAVE_USB3_MP, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb4_0_cfg = { .name = "qhs_usb4_0_cfg", - .id = X1E80100_SLAVE_USB4_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb4_1_cfg = { .name = "qhs_usb4_1_cfg", - .id = X1E80100_SLAVE_USB4_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb4_2_cfg = { .name = "qhs_usb4_2_cfg", - .id = X1E80100_SLAVE_USB4_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = X1E80100_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_lpass_qtb_cfg = { .name = "qss_lpass_qtb_cfg", - .id = X1E80100_SLAVE_LPASS_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = X1E80100_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { .name = "qss_nsp_qtb_cfg", - .id = X1E80100_SLAVE_NSP_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = X1E80100_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = X1E80100_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = X1E80100_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = X1E80100_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_apss = { .name = "qns_apss", - .id = X1E80100_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = X1E80100_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = X1E80100_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = X1E80100_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = X1E80100_SLAVE_PCIE_0, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = X1E80100_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_2 = { .name = "xs_pcie_2", - .id = X1E80100_SLAVE_PCIE_2, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_3 = { .name = "xs_pcie_3", - .id = X1E80100_SLAVE_PCIE_3, .channels = 1, .buswidth = 64, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_4 = { .name = "xs_pcie_4", - .id = X1E80100_SLAVE_PCIE_4, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_5 = { .name = "xs_pcie_5", - .id = X1E80100_SLAVE_PCIE_5, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_6a = { .name = "xs_pcie_6a", - .id = X1E80100_SLAVE_PCIE_6A, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_6b = { .name = "xs_pcie_6b", - .id = X1E80100_SLAVE_PCIE_6B, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = X1E80100_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = X1E80100_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = X1E80100_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = X1E80100_SLAVE_EBI1, .channels = 8, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = X1E80100_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = X1E80100_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = X1E80100_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qns_pcie_north_gem_noc = { .name = "qns_pcie_north_gem_noc", - .id = X1E80100_SLAVE_PCIE_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_PCIE_NORTH }, + .link_nodes = { &qnm_pcie_north_gem_noc }, }; static struct qcom_icc_node qns_pcie_south_gem_noc = { .name = "qns_pcie_south_gem_noc", - .id = X1E80100_SLAVE_PCIE_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_PCIE_SOUTH }, + .link_nodes = { &qnm_pcie_south_gem_noc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = X1E80100_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_aggre_usb_snoc = { .name = "qns_aggre_usb_snoc", - .id = X1E80100_SLAVE_USB_NOC_SNOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_USB_NOC_SNOC }, + .link_nodes = { &qnm_usb_anoc }, }; static struct qcom_icc_node qns_aggre_usb_north_snoc = { .name = "qns_aggre_usb_north_snoc", - .id = X1E80100_SLAVE_AGGRE_USB_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_AGGRE_USB_NORTH }, + .link_nodes = { &qnm_aggre_usb_north_snoc }, }; static struct qcom_icc_node qns_aggre_usb_south_snoc = { .name = "qns_aggre_usb_south_snoc", - .id = X1E80100_SLAVE_AGGRE_USB_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_AGGRE_USB_SOUTH }, + .link_nodes = { &qnm_aggre_usb_south_snoc }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1531,6 +1467,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1553,6 +1490,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1575,6 +1513,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc x1e80100_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1638,6 +1577,7 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = { }; static const struct qcom_icc_desc x1e80100_cnoc_cfg = { + .alloc_dyn_id = true, .nodes = cnoc_cfg_nodes, .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), .bcms = cnoc_cfg_bcms, @@ -1668,6 +1608,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc x1e80100_cnoc_main = { + .alloc_dyn_id = true, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1698,6 +1639,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1713,6 +1655,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1729,6 +1672,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = { + .alloc_dyn_id = true, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1744,6 +1688,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = { + .alloc_dyn_id = true, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms = lpass_lpicx_noc_bcms, @@ -1761,6 +1706,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc x1e80100_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1789,6 +1735,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1805,6 +1752,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_nsp_noc = { + .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1822,6 +1770,7 @@ static struct qcom_icc_node * const pcie_center_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_pcie_center_anoc = { + .alloc_dyn_id = true, .nodes = pcie_center_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes), .bcms = pcie_center_anoc_bcms, @@ -1839,6 +1788,7 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_pcie_north_anoc = { + .alloc_dyn_id = true, .nodes = pcie_north_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes), .bcms = pcie_north_anoc_bcms, @@ -1858,6 +1808,7 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_pcie_south_anoc = { + .alloc_dyn_id = true, .nodes = pcie_south_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes), .bcms = pcie_south_anoc_bcms, @@ -1880,6 +1831,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1896,6 +1848,7 @@ static struct qcom_icc_node * const usb_center_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_usb_center_anoc = { + .alloc_dyn_id = true, .nodes = usb_center_anoc_nodes, .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes), .bcms = usb_center_anoc_bcms, @@ -1912,6 +1865,7 @@ static struct qcom_icc_node * const usb_north_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_usb_north_anoc = { + .alloc_dyn_id = true, .nodes = usb_north_anoc_nodes, .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes), .bcms = usb_north_anoc_bcms, @@ -1932,6 +1886,7 @@ static struct qcom_icc_node * const usb_south_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_usb_south_anoc = { + .alloc_dyn_id = true, .nodes = usb_south_anoc_nodes, .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes), .bcms = usb_south_anoc_bcms, diff --git a/drivers/interconnect/qcom/x1e80100.h b/drivers/interconnect/qcom/x1e80100.h deleted file mode 100644 index 2e14264f4c2b..000000000000 --- a/drivers/interconnect/qcom/x1e80100.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * X1E80100 interconnect IDs - * - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H -#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H - -#define X1E80100_MASTER_A1NOC_SNOC 0 -#define X1E80100_MASTER_A2NOC_SNOC 1 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3 -#define X1E80100_MASTER_APPSS_PROC 4 -#define X1E80100_MASTER_CAMNOC_HF 5 -#define X1E80100_MASTER_CAMNOC_ICP 6 -#define X1E80100_MASTER_CAMNOC_SF 7 -#define X1E80100_MASTER_CDSP_PROC 8 -#define X1E80100_MASTER_CNOC_CFG 9 -#define X1E80100_MASTER_CNOC_MNOC_CFG 10 -#define X1E80100_MASTER_COMPUTE_NOC 11 -#define X1E80100_MASTER_CRYPTO 12 -#define X1E80100_MASTER_GEM_NOC_CNOC 13 -#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14 -#define X1E80100_MASTER_GFX3D 15 -#define X1E80100_MASTER_GPU_TCU 16 -#define X1E80100_MASTER_IPA 17 -#define X1E80100_MASTER_LLCC 18 -#define X1E80100_MASTER_LLCC_DISP 19 -#define X1E80100_MASTER_LPASS_GEM_NOC 20 -#define X1E80100_MASTER_LPASS_LPINOC 21 -#define X1E80100_MASTER_LPASS_PROC 22 -#define X1E80100_MASTER_LPIAON_NOC 23 -#define X1E80100_MASTER_MDP 24 -#define X1E80100_MASTER_MDP_DISP 25 -#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26 -#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27 -#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28 -#define X1E80100_MASTER_PCIE_0 29 -#define X1E80100_MASTER_PCIE_1 30 -#define X1E80100_MASTER_QDSS_ETR 31 -#define X1E80100_MASTER_QDSS_ETR_1 32 -#define X1E80100_MASTER_QSPI_0 33 -#define X1E80100_MASTER_QUP_0 34 -#define X1E80100_MASTER_QUP_1 35 -#define X1E80100_MASTER_QUP_2 36 -#define X1E80100_MASTER_QUP_CORE_0 37 -#define X1E80100_MASTER_QUP_CORE_1 38 -#define X1E80100_MASTER_SDCC_2 39 -#define X1E80100_MASTER_SDCC_4 40 -#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41 -#define X1E80100_MASTER_SP 42 -#define X1E80100_MASTER_SYS_TCU 43 -#define X1E80100_MASTER_UFS_MEM 44 -#define X1E80100_MASTER_USB3_0 45 -#define X1E80100_MASTER_VIDEO 46 -#define X1E80100_MASTER_VIDEO_CV_PROC 47 -#define X1E80100_MASTER_VIDEO_V_PROC 48 -#define X1E80100_SLAVE_A1NOC_SNOC 49 -#define X1E80100_SLAVE_A2NOC_SNOC 50 -#define X1E80100_SLAVE_AHB2PHY_NORTH 51 -#define X1E80100_SLAVE_AHB2PHY_SOUTH 52 -#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53 -#define X1E80100_SLAVE_AOSS 54 -#define X1E80100_SLAVE_APPSS 55 -#define X1E80100_SLAVE_BOOT_IMEM 56 -#define X1E80100_SLAVE_CAMERA_CFG 57 -#define X1E80100_SLAVE_CDSP_MEM_NOC 58 -#define X1E80100_SLAVE_CLK_CTL 59 -#define X1E80100_SLAVE_CNOC_CFG 60 -#define X1E80100_SLAVE_CNOC_MNOC_CFG 61 -#define X1E80100_SLAVE_CRYPTO_0_CFG 62 -#define X1E80100_SLAVE_DISPLAY_CFG 63 -#define X1E80100_SLAVE_EBI1 64 -#define X1E80100_SLAVE_EBI1_DISP 65 -#define X1E80100_SLAVE_GEM_NOC_CNOC 66 -#define X1E80100_SLAVE_GFX3D_CFG 67 -#define X1E80100_SLAVE_IMEM 68 -#define X1E80100_SLAVE_IMEM_CFG 69 -#define X1E80100_SLAVE_IPC_ROUTER_CFG 70 -#define X1E80100_SLAVE_LLCC 71 -#define X1E80100_SLAVE_LLCC_DISP 72 -#define X1E80100_SLAVE_LPASS_GEM_NOC 73 -#define X1E80100_SLAVE_LPASS_QTB_CFG 74 -#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75 -#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76 -#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77 -#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78 -#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79 -#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80 -#define X1E80100_SLAVE_NSP_QTB_CFG 81 -#define X1E80100_SLAVE_PCIE_0 82 -#define X1E80100_SLAVE_PCIE_0_CFG 83 -#define X1E80100_SLAVE_PCIE_1 84 -#define X1E80100_SLAVE_PCIE_1_CFG 85 -#define X1E80100_SLAVE_PDM 86 -#define X1E80100_SLAVE_PRNG 87 -#define X1E80100_SLAVE_QDSS_CFG 88 -#define X1E80100_SLAVE_QDSS_STM 89 -#define X1E80100_SLAVE_QSPI_0 90 -#define X1E80100_SLAVE_QUP_1 91 -#define X1E80100_SLAVE_QUP_2 92 -#define X1E80100_SLAVE_QUP_CORE_0 93 -#define X1E80100_SLAVE_QUP_CORE_1 94 -#define X1E80100_SLAVE_QUP_CORE_2 95 -#define X1E80100_SLAVE_SDCC_2 96 -#define X1E80100_SLAVE_SDCC_4 97 -#define X1E80100_SLAVE_SERVICE_MNOC 98 -#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99 -#define X1E80100_SLAVE_TCSR 100 -#define X1E80100_SLAVE_TCU 101 -#define X1E80100_SLAVE_TLMM 102 -#define X1E80100_SLAVE_TME_CFG 103 -#define X1E80100_SLAVE_UFS_MEM_CFG 104 -#define X1E80100_SLAVE_USB3_0 105 -#define X1E80100_SLAVE_VENUS_CFG 106 -#define X1E80100_MASTER_DDR_PERF_MODE 107 -#define X1E80100_MASTER_QUP_CORE_2 108 -#define X1E80100_MASTER_PCIE_TCU 109 -#define X1E80100_MASTER_GIC2 110 -#define X1E80100_MASTER_AV1_ENC 111 -#define X1E80100_MASTER_EVA 112 -#define X1E80100_MASTER_PCIE_NORTH 113 -#define X1E80100_MASTER_PCIE_SOUTH 114 -#define X1E80100_MASTER_PCIE_3 115 -#define X1E80100_MASTER_PCIE_4 116 -#define X1E80100_MASTER_PCIE_5 117 -#define X1E80100_MASTER_PCIE_2 118 -#define X1E80100_MASTER_PCIE_6A 119 -#define X1E80100_MASTER_PCIE_6B 120 -#define X1E80100_MASTER_GIC1 121 -#define X1E80100_MASTER_USB_NOC_SNOC 122 -#define X1E80100_MASTER_AGGRE_USB_NORTH 123 -#define X1E80100_MASTER_AGGRE_USB_SOUTH 124 -#define X1E80100_MASTER_USB2 125 -#define X1E80100_MASTER_USB3_MP 126 -#define X1E80100_MASTER_USB3_1 127 -#define X1E80100_MASTER_USB3_2 128 -#define X1E80100_MASTER_USB4_0 129 -#define X1E80100_MASTER_USB4_1 130 -#define X1E80100_MASTER_USB4_2 131 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132 -#define X1E80100_MASTER_LLCC_PCIE 133 -#define X1E80100_MASTER_PCIE_NORTH_PCIE 134 -#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135 -#define X1E80100_MASTER_PCIE_3_PCIE 136 -#define X1E80100_MASTER_PCIE_4_PCIE 137 -#define X1E80100_MASTER_PCIE_5_PCIE 138 -#define X1E80100_MASTER_PCIE_0_PCIE 139 -#define X1E80100_MASTER_PCIE_1_PCIE 140 -#define X1E80100_MASTER_PCIE_2_PCIE 141 -#define X1E80100_MASTER_PCIE_6A_PCIE 142 -#define X1E80100_MASTER_PCIE_6B_PCIE 143 -#define X1E80100_SLAVE_AHB2PHY_2 144 -#define X1E80100_SLAVE_AV1_ENC_CFG 145 -#define X1E80100_SLAVE_PCIE_2_CFG 146 -#define X1E80100_SLAVE_PCIE_3_CFG 147 -#define X1E80100_SLAVE_PCIE_4_CFG 148 -#define X1E80100_SLAVE_PCIE_5_CFG 149 -#define X1E80100_SLAVE_PCIE_6A_CFG 150 -#define X1E80100_SLAVE_PCIE_6B_CFG 151 -#define X1E80100_SLAVE_PCIE_RSC_CFG 152 -#define X1E80100_SLAVE_QUP_0 153 -#define X1E80100_SLAVE_SMMUV3_CFG 154 -#define X1E80100_SLAVE_USB2 155 -#define X1E80100_SLAVE_USB3_1 156 -#define X1E80100_SLAVE_USB3_2 157 -#define X1E80100_SLAVE_USB3_MP 158 -#define X1E80100_SLAVE_USB4_0 159 -#define X1E80100_SLAVE_USB4_1 160 -#define X1E80100_SLAVE_USB4_2 161 -#define X1E80100_SLAVE_PCIE_2 162 -#define X1E80100_SLAVE_PCIE_3 163 -#define X1E80100_SLAVE_PCIE_4 164 -#define X1E80100_SLAVE_PCIE_5 165 -#define X1E80100_SLAVE_PCIE_6A 166 -#define X1E80100_SLAVE_PCIE_6B 167 -#define X1E80100_SLAVE_DDR_PERF_MODE 168 -#define X1E80100_SLAVE_PCIE_NORTH 169 -#define X1E80100_SLAVE_PCIE_SOUTH 170 -#define X1E80100_SLAVE_USB_NOC_SNOC 171 -#define X1E80100_SLAVE_AGGRE_USB_NORTH 172 -#define X1E80100_SLAVE_AGGRE_USB_SOUTH 173 -#define X1E80100_SLAVE_LLCC_PCIE 174 -#define X1E80100_SLAVE_EBI1_PCIE 175 -#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE 176 -#define X1E80100_SLAVE_PCIE_NORTH_PCIE 177 -#define X1E80100_SLAVE_PCIE_SOUTH_PCIE 178 - -#endif From b01058dfaedd45e41527c62273a357fde22db226 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:24 +0200 Subject: [PATCH 143/304] interconnect: qcom: qcs615: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-8-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/qcs615.c | 519 +++++++++++++---------------- drivers/interconnect/qcom/qcs615.h | 128 ------- 2 files changed, 239 insertions(+), 408 deletions(-) delete mode 100644 drivers/interconnect/qcom/qcs615.h diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c index 0549cfcbac64..fb0f623c0e64 100644 --- a/drivers/interconnect/qcom/qcs615.c +++ b/drivers/interconnect/qcom/qcs615.c @@ -13,1041 +13,992 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "qcs615.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_avb; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_lpass_anoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_lpass_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_east; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_avb_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_config; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_dc_noc_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = QCS615_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = QCS615_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = QCS615_MASTER_QSPI, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = QCS615_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = QCS615_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = QCS615_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = QCS615_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = QCS615_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_LPASS_SNOC }, + .link_nodes = { &qns_lpass_snoc }, }; static struct qcom_icc_node xm_emac_avb = { .name = "xm_emac_avb", - .id = QCS615_MASTER_EMAC_EVB, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = QCS615_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes = { &qns_pcie_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = QCS615_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = QCS615_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = QCS615_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = QCS615_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb2 = { .name = "xm_usb2", - .id = QCS615_MASTER_USB2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = QCS615_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = QCS615_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = QCS615_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = QCS615_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = QCS615_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = QCS615_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 39, - .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, - QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, - QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, - QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, - QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, - QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, - QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, - QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, - QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, - QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, - QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, - QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, - QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, - QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, - QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, - QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, - QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, - QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, - QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, - QCS615_SLAVE_SERVICE_CNOC }, + .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = QCS615_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 40, - .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, - QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, - QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, - QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, - QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, - QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, - QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, - QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, - QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, - QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, - QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, - QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, - QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, - QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, - QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, - QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, - QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, - QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, - QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, - QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC }, + .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, &srvc_cnoc }, }; static struct qcom_icc_node qhm_cnoc = { .name = "qhm_cnoc", - .id = QCS615_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG }, + .link_nodes = { &qhs_dc_noc_gemnoc, &qhs_llcc }, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = QCS615_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC, - QCS615_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, + &qns_sys_pcie }, }; static struct qcom_icc_node acm_gpu_tcu = { .name = "acm_gpu_tcu", - .id = QCS615_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = QCS615_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = QCS615_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_NOC }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = QCS615_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = QCS615_MASTER_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = QCS615_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = QCS615_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = QCS615_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS615_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = QCS615_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = QCS615_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = QCS615_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = QCS615_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = QCS615_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = QCS615_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = QCS615_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = QCS615_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = QCS615_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = QCS615_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = QCS615_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 8, - .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, - QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = QCS615_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM, - QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qxs_imem, &qxs_pimem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = QCS615_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qnm_lpass_anoc = { .name = "qnm_lpass_anoc", - .id = QCS615_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 8, .num_links = 7, - .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, - QCS615_SLAVE_QDSS_STM }, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_pcie_anoc = { .name = "qnm_pcie_anoc", - .id = QCS615_MASTER_ANOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_QDSS_STM }, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = QCS615_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, + .link_nodes = { &qns_memnoc_gc, &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = QCS615_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, + .link_nodes = { &qns_memnoc_gc, &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = QCS615_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS615_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_lpass_snoc = { .name = "qns_lpass_snoc", - .id = QCS615_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_anoc }, }; static struct qcom_icc_node qns_pcie_snoc = { .name = "qns_pcie_snoc", - .id = QCS615_SLAVE_ANOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_ANOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie_anoc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = QCS615_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = QCS615_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = QCS615_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy_east = { .name = "qhs_ahb2phy_east", - .id = QCS615_SLAVE_AHB2PHY_EAST, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy_west = { .name = "qhs_ahb2phy_west", - .id = QCS615_SLAVE_AHB2PHY_WEST, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = QCS615_SLAVE_AOP, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = QCS615_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = QCS615_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = QCS615_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = QCS615_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = QCS615_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = QCS615_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = QCS615_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = QCS615_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_emac_avb_cfg = { .name = "qhs_emac_avb_cfg", - .id = QCS615_SLAVE_EMAC_AVB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = QCS615_SLAVE_GLM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = QCS615_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = QCS615_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = QCS615_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = QCS615_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pcie_config = { .name = "qhs_pcie_config", - .id = QCS615_SLAVE_PCIE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = QCS615_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = QCS615_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = QCS615_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = QCS615_SLAVE_QSPI, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = QCS615_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = QCS615_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = QCS615_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = QCS615_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = QCS615_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = QCS615_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = QCS615_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm_east = { .name = "qhs_tlmm_east", - .id = QCS615_SLAVE_TLMM_EAST, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = QCS615_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm_west = { .name = "qhs_tlmm_west", - .id = QCS615_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = QCS615_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb2 = { .name = "qhs_usb2", - .id = QCS615_SLAVE_USB2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = QCS615_SLAVE_USB3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = QCS615_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = QCS615_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = QCS615_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = QCS615_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_dc_noc_gemnoc = { .name = "qhs_dc_noc_gemnoc", - .id = QCS615_SLAVE_DC_NOC_GEMNOC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS615_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = QCS615_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = QCS615_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = QCS615_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS615_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = QCS615_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = QCS615_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = QCS615_SLAVE_EBI1, .channels = 2, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = QCS615_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = QCS615_SLAVE_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS615_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = QCS615_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = QCS615_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = QCS615_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = QCS615_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS615_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_memnoc_gc = { .name = "qns_memnoc_gc", - .id = QCS615_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS615_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = QCS615_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = QCS615_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = QCS615_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = QCS615_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = QCS615_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = QCS615_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -1263,6 +1214,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1281,6 +1233,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc qcs615_camnoc_virt = { + .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1339,6 +1292,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1352,6 +1306,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1381,6 +1336,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1398,6 +1354,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc qcs615_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1426,6 +1383,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1468,6 +1426,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs615.h b/drivers/interconnect/qcom/qcs615.h deleted file mode 100644 index 66e66c7e23d4..000000000000 --- a/drivers/interconnect/qcom/qcs615.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H -#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H - -#define QCS615_MASTER_A1NOC_CFG 1 -#define QCS615_MASTER_A1NOC_SNOC 2 -#define QCS615_MASTER_ANOC_PCIE_SNOC 3 -#define QCS615_MASTER_APPSS_PROC 4 -#define QCS615_MASTER_BLSP_1 5 -#define QCS615_MASTER_CAMNOC_HF0 6 -#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7 -#define QCS615_MASTER_CAMNOC_HF1 8 -#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9 -#define QCS615_MASTER_CAMNOC_SF 10 -#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11 -#define QCS615_MASTER_CNOC_A2NOC 12 -#define QCS615_MASTER_CNOC_DC_NOC 13 -#define QCS615_MASTER_CNOC_MNOC_CFG 14 -#define QCS615_MASTER_CRYPTO 15 -#define QCS615_MASTER_EMAC_EVB 16 -#define QCS615_MASTER_GEM_NOC_CFG 17 -#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18 -#define QCS615_MASTER_GEM_NOC_SNOC 19 -#define QCS615_MASTER_GFX3D 20 -#define QCS615_MASTER_GIC 21 -#define QCS615_MASTER_GPU_TCU 22 -#define QCS615_MASTER_IPA 23 -#define QCS615_MASTER_IPA_CORE 24 -#define QCS615_MASTER_LLCC 25 -#define QCS615_MASTER_LPASS_ANOC 26 -#define QCS615_MASTER_MDP0 27 -#define QCS615_MASTER_MNOC_HF_MEM_NOC 28 -#define QCS615_MASTER_MNOC_SF_MEM_NOC 29 -#define QCS615_MASTER_PCIE 30 -#define QCS615_MASTER_PIMEM 31 -#define QCS615_MASTER_QDSS_BAM 32 -#define QCS615_MASTER_QDSS_DAP 33 -#define QCS615_MASTER_QDSS_ETR 34 -#define QCS615_MASTER_QSPI 35 -#define QCS615_MASTER_QUP_0 36 -#define QCS615_MASTER_ROTATOR 37 -#define QCS615_MASTER_SDCC_1 38 -#define QCS615_MASTER_SDCC_2 39 -#define QCS615_MASTER_SNOC_CFG 40 -#define QCS615_MASTER_SNOC_CNOC 41 -#define QCS615_MASTER_SNOC_GC_MEM_NOC 42 -#define QCS615_MASTER_SNOC_SF_MEM_NOC 43 -#define QCS615_MASTER_SPDM 44 -#define QCS615_MASTER_SYS_TCU 45 -#define QCS615_MASTER_UFS_MEM 46 -#define QCS615_MASTER_USB2 47 -#define QCS615_MASTER_USB3_0 48 -#define QCS615_MASTER_VIDEO_P0 49 -#define QCS615_MASTER_VIDEO_PROC 50 -#define QCS615_SLAVE_A1NOC_CFG 51 -#define QCS615_SLAVE_A1NOC_SNOC 52 -#define QCS615_SLAVE_AHB2PHY_EAST 53 -#define QCS615_SLAVE_AHB2PHY_WEST 54 -#define QCS615_SLAVE_ANOC_PCIE_SNOC 55 -#define QCS615_SLAVE_AOP 56 -#define QCS615_SLAVE_AOSS 57 -#define QCS615_SLAVE_APPSS 58 -#define QCS615_SLAVE_CAMERA_CFG 59 -#define QCS615_SLAVE_CAMNOC_UNCOMP 60 -#define QCS615_SLAVE_CLK_CTL 61 -#define QCS615_SLAVE_CNOC_A2NOC 62 -#define QCS615_SLAVE_CNOC_DDRSS 63 -#define QCS615_SLAVE_CNOC_MNOC_CFG 64 -#define QCS615_SLAVE_CRYPTO_0_CFG 65 -#define QCS615_SLAVE_DC_NOC_GEMNOC 66 -#define QCS615_SLAVE_DISPLAY_CFG 67 -#define QCS615_SLAVE_EBI1 68 -#define QCS615_SLAVE_EMAC_AVB_CFG 69 -#define QCS615_SLAVE_GEM_NOC_SNOC 70 -#define QCS615_SLAVE_GFX3D_CFG 71 -#define QCS615_SLAVE_GLM 72 -#define QCS615_SLAVE_IMEM 73 -#define QCS615_SLAVE_IMEM_CFG 74 -#define QCS615_SLAVE_IPA_CFG 75 -#define QCS615_SLAVE_IPA_CORE 76 -#define QCS615_SLAVE_LLCC 77 -#define QCS615_SLAVE_LLCC_CFG 78 -#define QCS615_SLAVE_LPASS_SNOC 79 -#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80 -#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81 -#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82 -#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83 -#define QCS615_SLAVE_PCIE_0 84 -#define QCS615_SLAVE_PCIE_CFG 85 -#define QCS615_SLAVE_PIMEM 86 -#define QCS615_SLAVE_PIMEM_CFG 87 -#define QCS615_SLAVE_PRNG 88 -#define QCS615_SLAVE_QDSS_CFG 89 -#define QCS615_SLAVE_QDSS_STM 90 -#define QCS615_SLAVE_QSPI 91 -#define QCS615_SLAVE_QUP_0 92 -#define QCS615_SLAVE_QUP_1 93 -#define QCS615_SLAVE_RBCPR_CX_CFG 94 -#define QCS615_SLAVE_RBCPR_MX_CFG 95 -#define QCS615_SLAVE_SDCC_1 96 -#define QCS615_SLAVE_SDCC_2 97 -#define QCS615_SLAVE_SERVICE_A2NOC 98 -#define QCS615_SLAVE_SERVICE_CNOC 99 -#define QCS615_SLAVE_SERVICE_GEM_NOC 100 -#define QCS615_SLAVE_SERVICE_MNOC 101 -#define QCS615_SLAVE_SERVICE_SNOC 102 -#define QCS615_SLAVE_SNOC_CFG 103 -#define QCS615_SLAVE_SNOC_CNOC 104 -#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105 -#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106 -#define QCS615_SLAVE_SPDM_WRAPPER 107 -#define QCS615_SLAVE_TCSR 108 -#define QCS615_SLAVE_TCU 109 -#define QCS615_SLAVE_TLMM_EAST 110 -#define QCS615_SLAVE_TLMM_SOUTH 111 -#define QCS615_SLAVE_TLMM_WEST 112 -#define QCS615_SLAVE_UFS_MEM_CFG 113 -#define QCS615_SLAVE_USB2 114 -#define QCS615_SLAVE_USB3 115 -#define QCS615_SLAVE_VENUS_CFG 116 -#define QCS615_SLAVE_VSENSE_CTRL_CFG 117 - -#endif - From 874be3339c85392528628f284d2f7e6f2e6b8a29 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:25 +0200 Subject: [PATCH 144/304] interconnect: qcom: qcs8300: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-9-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/qcs8300.c | 684 +++++++++++++--------------- drivers/interconnect/qcom/qcs8300.h | 177 ------- 2 files changed, 305 insertions(+), 556 deletions(-) delete mode 100644 drivers/interconnect/qcom/qcs8300.h diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c index e7a1b2fc69ba..077f4beb4bd1 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -13,1465 +13,1378 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "qcs8300.h" + +static struct qcom_icc_node qxm_qup3; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2_2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto_0; +static struct qcom_icc_node qxm_crypto_1; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup3_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpdsp_sail; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_sailss_md0; +static struct qcom_icc_node qxm_dsp0; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mnoc_hf_cfg; +static struct qcom_icc_node qnm_mnoc_sf_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup3_core_slave; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_ahb2phy3; +static struct qcom_icc_node qhs_anoc_throttle_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_cpr_nsphmx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display0_rt_throttle_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_gp_dsp0_cfg; +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg; +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_lpass_throttle_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg; +static struct qcom_icc_node qhs_pcie_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pke_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup3; +static struct qcom_icc_node qhs_sail_throttle_cfg; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_throttle_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg; +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gpdsp_noc_cfg; +static struct qcom_icc_node qns_mnoc_hf_cfg; +static struct qcom_icc_node qns_mnoc_sf_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc_2; +static struct qcom_icc_node qns_gp_dsp_sail_noc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc_hf; +static struct qcom_icc_node srvc_mnoc_sf; +static struct qcom_icc_node qns_hcp; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qxm_qup3 = { .name = "qxm_qup3", - .id = QCS8300_MASTER_QUP_3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", - .id = QCS8300_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = QCS8300_MASTER_SDC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = QCS8300_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb2_2 = { .name = "xm_usb2_2", - .id = QCS8300_MASTER_USB2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = QCS8300_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = QCS8300_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = QCS8300_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = QCS8300_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", - .id = QCS8300_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto_0 = { .name = "qxm_crypto_0", - .id = QCS8300_MASTER_CRYPTO_CORE0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto_1 = { .name = "qxm_crypto_1", - .id = QCS8300_MASTER_CRYPTO_CORE1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = QCS8300_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = QCS8300_MASTER_QDSS_ETR_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = QCS8300_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = QCS8300_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = QCS8300_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup3_core_master = { .name = "qup3_core_master", - .id = QCS8300_MASTER_QUP_CORE_3, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_QUP_CORE_3 }, + .link_nodes = { &qup3_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = QCS8300_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 71, - .links = { QCS8300_SLAVE_AHB2PHY_2, QCS8300_SLAVE_AHB2PHY_3, - QCS8300_SLAVE_ANOC_THROTTLE_CFG, QCS8300_SLAVE_AOSS, - QCS8300_SLAVE_APPSS, QCS8300_SLAVE_BOOT_ROM, - QCS8300_SLAVE_CAMERA_CFG, QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG, - QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, QCS8300_SLAVE_CLK_CTL, - QCS8300_SLAVE_CDSP_CFG, QCS8300_SLAVE_RBCPR_CX_CFG, - QCS8300_SLAVE_RBCPR_MMCX_CFG, QCS8300_SLAVE_RBCPR_MX_CFG, - QCS8300_SLAVE_CPR_NSPCX, QCS8300_SLAVE_CPR_NSPHMX, - QCS8300_SLAVE_CRYPTO_0_CFG, QCS8300_SLAVE_CX_RDPM, - QCS8300_SLAVE_DISPLAY_CFG, QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG, - QCS8300_SLAVE_EMAC_CFG, QCS8300_SLAVE_GP_DSP0_CFG, - QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG, - QCS8300_SLAVE_GFX3D_CFG, QCS8300_SLAVE_HWKM, - QCS8300_SLAVE_IMEM_CFG, QCS8300_SLAVE_IPA_CFG, - QCS8300_SLAVE_IPC_ROUTER_CFG, QCS8300_SLAVE_LPASS, - QCS8300_SLAVE_LPASS_THROTTLE_CFG, QCS8300_SLAVE_MX_RDPM, - QCS8300_SLAVE_MXC_RDPM, QCS8300_SLAVE_PCIE_0_CFG, - QCS8300_SLAVE_PCIE_1_CFG, QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG, - QCS8300_SLAVE_PCIE_THROTTLE_CFG, QCS8300_SLAVE_PDM, - QCS8300_SLAVE_PIMEM_CFG, QCS8300_SLAVE_PKA_WRAPPER_CFG, - QCS8300_SLAVE_QDSS_CFG, QCS8300_SLAVE_QM_CFG, - QCS8300_SLAVE_QM_MPU_CFG, QCS8300_SLAVE_QUP_0, - QCS8300_SLAVE_QUP_1, QCS8300_SLAVE_QUP_3, - QCS8300_SLAVE_SAIL_THROTTLE_CFG, QCS8300_SLAVE_SDC1, - QCS8300_SLAVE_SECURITY, QCS8300_SLAVE_SNOC_THROTTLE_CFG, - QCS8300_SLAVE_TCSR, QCS8300_SLAVE_TLMM, - QCS8300_SLAVE_TSC_CFG, QCS8300_SLAVE_UFS_MEM_CFG, - QCS8300_SLAVE_USB2, QCS8300_SLAVE_USB3_0, - QCS8300_SLAVE_VENUS_CFG, QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG, - QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG, - QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG, - QCS8300_SLAVE_DDRSS_CFG, QCS8300_SLAVE_GPDSP_NOC_CFG, - QCS8300_SLAVE_CNOC_MNOC_HF_CFG, QCS8300_SLAVE_CNOC_MNOC_SF_CFG, - QCS8300_SLAVE_PCIE_ANOC_CFG, QCS8300_SLAVE_SNOC_CFG, - QCS8300_SLAVE_BOOT_IMEM, QCS8300_SLAVE_IMEM, - QCS8300_SLAVE_PIMEM, QCS8300_SLAVE_QDSS_STM, - QCS8300_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mx, + &qhs_cpr_nspcx, &qhs_cpr_nsphmx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_gp_dsp0_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg, + &qhs_gpuss_cfg, &qhs_hwkm, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_lpass_throttle_cfg, &qhs_mx_rdpm, + &qhs_mxc_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_qup0, + &qhs_qup1, &qhs_qup3, + &qhs_sail_throttle_cfg, &qhs_sdc1, + &qhs_security, &qhs_snoc_throttle_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_tsc_cfg, &qhs_ufs_mem_cfg, + &qhs_usb2_0, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_venus_cvp_throttle_cfg, + &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, + &qns_ddrss_cfg, &qns_gpdsp_noc_cfg, + &qns_mnoc_hf_cfg, &qns_mnoc_sf_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = QCS8300_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { QCS8300_SLAVE_PCIE_0, QCS8300_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = QCS8300_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { QCS8300_SLAVE_LLCC_CFG, QCS8300_SLAVE_GEM_NOC_CFG }, + .link_nodes = { &qhs_llcc, &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = QCS8300_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", - .id = QCS8300_MASTER_PCIE_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = QCS8300_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = QCS8300_MASTER_APPSS_PROC, .channels = 4, .buswidth = 32, .num_links = 3, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC, - QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc0 = { .name = "qnm_cmpnoc0", - .id = QCS8300_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = QCS8300_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 4, - .links = { QCS8300_SLAVE_SERVICE_GEM_NOC_1, QCS8300_SLAVE_SERVICE_GEM_NOC_2, - QCS8300_SLAVE_SERVICE_GEM_NOC, QCS8300_SLAVE_SERVICE_GEM_NOC2 }, + .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, }; static struct qcom_icc_node qnm_gpdsp_sail = { .name = "qnm_gpdsp_sail", - .id = QCS8300_MASTER_GPDSP_SAIL, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = QCS8300_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = QCS8300_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QCS8300_SLAVE_LLCC, QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_llcc, &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = QCS8300_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC, - QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = QCS8300_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = QCS8300_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = QCS8300_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC, - QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_sailss_md0 = { .name = "qnm_sailss_md0", - .id = QCS8300_MASTER_SAILSS_MD0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC }, + .link_nodes = { &qns_gp_dsp_sail_noc }, }; static struct qcom_icc_node qxm_dsp0 = { .name = "qxm_dsp0", - .id = QCS8300_MASTER_DSP0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_SLAVE_GP_DSP_SAIL_NOC }, + .link_nodes = { &qns_gp_dsp_sail_noc }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = QCS8300_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { QCS8300_SLAVE_LPASS_CORE_CFG, QCS8300_SLAVE_LPASS_LPI_CFG, - QCS8300_SLAVE_LPASS_MPU_CFG, QCS8300_SLAVE_LPASS_TOP_CFG, - QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = QCS8300_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { QCS8300_SLAVE_LPASS_TOP_CFG, QCS8300_SLAVE_LPASS_SNOC, - QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = QCS8300_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = QCS8300_MASTER_CAMNOC_HF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = QCS8300_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = QCS8300_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp0_0 = { .name = "qnm_mdp0_0", - .id = QCS8300_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_1 = { .name = "qnm_mdp0_1", - .id = QCS8300_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_hf_cfg = { .name = "qnm_mnoc_hf_cfg", - .id = QCS8300_MASTER_CNOC_MNOC_HF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_SERVICE_MNOC_HF }, + .link_nodes = { &srvc_mnoc_hf }, }; static struct qcom_icc_node qnm_mnoc_sf_cfg = { .name = "qnm_mnoc_sf_cfg", - .id = QCS8300_MASTER_CNOC_MNOC_SF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_SERVICE_MNOC_SF }, + .link_nodes = { &srvc_mnoc_sf }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = QCS8300_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = QCS8300_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = QCS8300_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = QCS8300_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = QCS8300_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, - .num_links = 2, - .links = { QCS8300_SLAVE_HCP_A, QCS8300_SLAVE_CDSP_MEM_NOC }, + .num_links = 1, + .link_nodes = { &qns_hcp, &qns_nsp_gemnoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = QCS8300_MASTER_PCIE_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = QCS8300_MASTER_PCIE_1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = QCS8300_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = QCS8300_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = QCS8300_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = QCS8300_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = QCS8300_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = QCS8300_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = QCS8300_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = QCS8300_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = QCS8300_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = QCS8300_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = QCS8300_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup3_core_slave = { .name = "qup3_core_slave", - .id = QCS8300_SLAVE_QUP_CORE_3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = QCS8300_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy3 = { .name = "qhs_ahb2phy3", - .id = QCS8300_SLAVE_AHB2PHY_3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_anoc_throttle_cfg = { .name = "qhs_anoc_throttle_cfg", - .id = QCS8300_SLAVE_ANOC_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = QCS8300_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = QCS8300_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", - .id = QCS8300_SLAVE_BOOT_ROM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = QCS8300_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { .name = "qhs_camera_nrt_throttle_cfg", - .id = QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = QCS8300_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_compute0_cfg = { .name = "qhs_compute0_cfg", - .id = QCS8300_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = QCS8300_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = QCS8300_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = QCS8300_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = QCS8300_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nsphmx = { .name = "qhs_cpr_nsphmx", - .id = QCS8300_SLAVE_CPR_NSPHMX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = QCS8300_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = QCS8300_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display0_cfg = { .name = "qhs_display0_cfg", - .id = QCS8300_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { .name = "qhs_display0_rt_throttle_cfg", - .id = QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_emac0_cfg = { .name = "qhs_emac0_cfg", - .id = QCS8300_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gp_dsp0_cfg = { .name = "qhs_gp_dsp0_cfg", - .id = QCS8300_SLAVE_GP_DSP0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { .name = "qhs_gpdsp0_throttle_cfg", - .id = QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { .name = "qhs_gpu_tcu_throttle_cfg", - .id = QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = QCS8300_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = QCS8300_SLAVE_HWKM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = QCS8300_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = QCS8300_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = QCS8300_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = QCS8300_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_lpass_throttle_cfg = { .name = "qhs_lpass_throttle_cfg", - .id = QCS8300_SLAVE_LPASS_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = QCS8300_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mxc_rdpm = { .name = "qhs_mxc_rdpm", - .id = QCS8300_SLAVE_MXC_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = QCS8300_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = QCS8300_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { .name = "qhs_pcie_tcu_throttle_cfg", - .id = QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_throttle_cfg = { .name = "qhs_pcie_throttle_cfg", - .id = QCS8300_SLAVE_PCIE_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = QCS8300_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = QCS8300_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pke_wrapper_cfg = { .name = "qhs_pke_wrapper_cfg", - .id = QCS8300_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = QCS8300_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qm_cfg = { .name = "qhs_qm_cfg", - .id = QCS8300_SLAVE_QM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qm_mpu_cfg = { .name = "qhs_qm_mpu_cfg", - .id = QCS8300_SLAVE_QM_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = QCS8300_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = QCS8300_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup3 = { .name = "qhs_qup3", - .id = QCS8300_SLAVE_QUP_3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sail_throttle_cfg = { .name = "qhs_sail_throttle_cfg", - .id = QCS8300_SLAVE_SAIL_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = QCS8300_SLAVE_SDC1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = QCS8300_SLAVE_SECURITY, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_snoc_throttle_cfg = { .name = "qhs_snoc_throttle_cfg", - .id = QCS8300_SLAVE_SNOC_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = QCS8300_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = QCS8300_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tsc_cfg = { .name = "qhs_tsc_cfg", - .id = QCS8300_SLAVE_TSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = QCS8300_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb2_0 = { .name = "qhs_usb2_0", - .id = QCS8300_SLAVE_USB2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = QCS8300_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = QCS8300_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { .name = "qhs_venus_cvp_throttle_cfg", - .id = QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { .name = "qhs_venus_v_cpu_throttle_cfg", - .id = QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { .name = "qhs_venus_vcodec_throttle_cfg", - .id = QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = QCS8300_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qns_gpdsp_noc_cfg = { .name = "qns_gpdsp_noc_cfg", - .id = QCS8300_SLAVE_GPDSP_NOC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mnoc_hf_cfg = { .name = "qns_mnoc_hf_cfg", - .id = QCS8300_SLAVE_CNOC_MNOC_HF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_CNOC_MNOC_HF_CFG }, + .link_nodes = { &qnm_mnoc_hf_cfg }, }; static struct qcom_icc_node qns_mnoc_sf_cfg = { .name = "qns_mnoc_sf_cfg", - .id = QCS8300_SLAVE_CNOC_MNOC_SF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_CNOC_MNOC_SF_CFG }, + .link_nodes = { &qnm_mnoc_sf_cfg }, }; static struct qcom_icc_node qns_pcie_anoc_cfg = { .name = "qns_pcie_anoc_cfg", - .id = QCS8300_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = QCS8300_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = QCS8300_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = QCS8300_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = QCS8300_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = QCS8300_SLAVE_PCIE_0, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = QCS8300_SLAVE_PCIE_1, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = QCS8300_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = QCS8300_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = QCS8300_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = QCS8300_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QCS8300_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = QCS8300_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = QCS8300_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = QCS8300_SLAVE_GEM_NOC_PCIE_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = QCS8300_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = QCS8300_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = QCS8300_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_sys_gemnoc_2 = { .name = "srvc_sys_gemnoc_2", - .id = QCS8300_SLAVE_SERVICE_GEM_NOC2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gp_dsp_sail_noc = { .name = "qns_gp_dsp_sail_noc", - .id = QCS8300_SLAVE_GP_DSP_SAIL_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_GPDSP_SAIL }, + .link_nodes = { &qnm_gpdsp_sail }, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = QCS8300_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = QCS8300_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = QCS8300_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = QCS8300_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = QCS8300_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = QCS8300_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = QCS8300_SLAVE_EBI1, .channels = 8, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = QCS8300_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { QCS8300_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = QCS8300_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { QCS8300_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc_hf = { .name = "srvc_mnoc_hf", - .id = QCS8300_SLAVE_SERVICE_MNOC_HF, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_mnoc_sf = { .name = "srvc_mnoc_sf", - .id = QCS8300_SLAVE_SERVICE_MNOC_SF, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_hcp = { .name = "qns_hcp", - .id = QCS8300_SLAVE_HCP_A, .channels = 2, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = QCS8300_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { QCS8300_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc0 }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = QCS8300_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = QCS8300_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { QCS8300_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = QCS8300_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QCS8300_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = QCS8300_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QCS8300_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = QCS8300_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -1687,6 +1600,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1712,6 +1626,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1734,6 +1649,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc qcs8300_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1828,6 +1744,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1841,6 +1758,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1874,6 +1792,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1891,6 +1810,7 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_gpdsp_anoc = { + .alloc_dyn_id = true, .nodes = gpdsp_anoc_nodes, .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), .bcms = gpdsp_anoc_bcms, @@ -1914,6 +1834,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1931,6 +1852,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc qcs8300_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1960,6 +1882,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1980,6 +1903,7 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_nspa_noc = { + .alloc_dyn_id = true, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -1997,6 +1921,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_pcie_anoc = { + .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -2025,6 +1950,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs8300.h b/drivers/interconnect/qcom/qcs8300.h deleted file mode 100644 index 6b9e2b424c2a..000000000000 --- a/drivers/interconnect/qcom/qcs8300.h +++ /dev/null @@ -1,177 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS8300_H -#define __DRIVERS_INTERCONNECT_QCOM_QCS8300_H - -#define QCS8300_MASTER_GPU_TCU 0 -#define QCS8300_MASTER_PCIE_TCU 1 -#define QCS8300_MASTER_SYS_TCU 2 -#define QCS8300_MASTER_APPSS_PROC 3 -#define QCS8300_MASTER_LLCC 4 -#define QCS8300_MASTER_CNOC_LPASS_AG_NOC 5 -#define QCS8300_MASTER_GIC_AHB 6 -#define QCS8300_MASTER_CDSP_NOC_CFG 7 -#define QCS8300_MASTER_QDSS_BAM 8 -#define QCS8300_MASTER_QUP_0 9 -#define QCS8300_MASTER_QUP_1 10 -#define QCS8300_MASTER_A1NOC_SNOC 11 -#define QCS8300_MASTER_A2NOC_SNOC 12 -#define QCS8300_MASTER_CAMNOC_HF 13 -#define QCS8300_MASTER_CAMNOC_ICP 14 -#define QCS8300_MASTER_CAMNOC_SF 15 -#define QCS8300_MASTER_COMPUTE_NOC 16 -#define QCS8300_MASTER_CNOC_A2NOC 17 -#define QCS8300_MASTER_CNOC_DC_NOC 18 -#define QCS8300_MASTER_GEM_NOC_CFG 19 -#define QCS8300_MASTER_GEM_NOC_CNOC 20 -#define QCS8300_MASTER_GEM_NOC_PCIE_SNOC 21 -#define QCS8300_MASTER_GPDSP_SAIL 22 -#define QCS8300_MASTER_GFX3D 23 -#define QCS8300_MASTER_LPASS_ANOC 24 -#define QCS8300_MASTER_MDP0 25 -#define QCS8300_MASTER_MDP1 26 -#define QCS8300_MASTER_MNOC_HF_MEM_NOC 27 -#define QCS8300_MASTER_CNOC_MNOC_HF_CFG 28 -#define QCS8300_MASTER_MNOC_SF_MEM_NOC 29 -#define QCS8300_MASTER_CNOC_MNOC_SF_CFG 30 -#define QCS8300_MASTER_ANOC_PCIE_GEM_NOC 31 -#define QCS8300_MASTER_SAILSS_MD0 32 -#define QCS8300_MASTER_SNOC_CFG 33 -#define QCS8300_MASTER_SNOC_GC_MEM_NOC 34 -#define QCS8300_MASTER_SNOC_SF_MEM_NOC 35 -#define QCS8300_MASTER_VIDEO_P0 36 -#define QCS8300_MASTER_VIDEO_PROC 37 -#define QCS8300_MASTER_VIDEO_V_PROC 38 -#define QCS8300_MASTER_QUP_CORE_0 39 -#define QCS8300_MASTER_QUP_CORE_1 40 -#define QCS8300_MASTER_QUP_CORE_3 41 -#define QCS8300_MASTER_CRYPTO_CORE0 42 -#define QCS8300_MASTER_CRYPTO_CORE1 43 -#define QCS8300_MASTER_DSP0 44 -#define QCS8300_MASTER_IPA 45 -#define QCS8300_MASTER_LPASS_PROC 46 -#define QCS8300_MASTER_CDSP_PROC 47 -#define QCS8300_MASTER_PIMEM 48 -#define QCS8300_MASTER_QUP_3 49 -#define QCS8300_MASTER_EMAC 50 -#define QCS8300_MASTER_GIC 51 -#define QCS8300_MASTER_PCIE_0 52 -#define QCS8300_MASTER_PCIE_1 53 -#define QCS8300_MASTER_QDSS_ETR_0 54 -#define QCS8300_MASTER_QDSS_ETR_1 55 -#define QCS8300_MASTER_SDC 56 -#define QCS8300_MASTER_UFS_MEM 57 -#define QCS8300_MASTER_USB2 58 -#define QCS8300_MASTER_USB3_0 59 -#define QCS8300_SLAVE_EBI1 60 -#define QCS8300_SLAVE_AHB2PHY_2 61 -#define QCS8300_SLAVE_AHB2PHY_3 62 -#define QCS8300_SLAVE_ANOC_THROTTLE_CFG 63 -#define QCS8300_SLAVE_AOSS 64 -#define QCS8300_SLAVE_APPSS 65 -#define QCS8300_SLAVE_BOOT_ROM 66 -#define QCS8300_SLAVE_CAMERA_CFG 67 -#define QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG 68 -#define QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG 69 -#define QCS8300_SLAVE_CLK_CTL 70 -#define QCS8300_SLAVE_CDSP_CFG 71 -#define QCS8300_SLAVE_RBCPR_CX_CFG 72 -#define QCS8300_SLAVE_RBCPR_MMCX_CFG 73 -#define QCS8300_SLAVE_RBCPR_MX_CFG 74 -#define QCS8300_SLAVE_CPR_NSPCX 75 -#define QCS8300_SLAVE_CPR_NSPHMX 76 -#define QCS8300_SLAVE_CRYPTO_0_CFG 77 -#define QCS8300_SLAVE_CX_RDPM 78 -#define QCS8300_SLAVE_DISPLAY_CFG 79 -#define QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG 80 -#define QCS8300_SLAVE_EMAC_CFG 81 -#define QCS8300_SLAVE_GP_DSP0_CFG 82 -#define QCS8300_SLAVE_GPDSP0_THROTTLE_CFG 83 -#define QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG 84 -#define QCS8300_SLAVE_GFX3D_CFG 85 -#define QCS8300_SLAVE_HWKM 86 -#define QCS8300_SLAVE_IMEM_CFG 87 -#define QCS8300_SLAVE_IPA_CFG 88 -#define QCS8300_SLAVE_IPC_ROUTER_CFG 89 -#define QCS8300_SLAVE_LLCC_CFG 90 -#define QCS8300_SLAVE_LPASS 91 -#define QCS8300_SLAVE_LPASS_CORE_CFG 92 -#define QCS8300_SLAVE_LPASS_LPI_CFG 93 -#define QCS8300_SLAVE_LPASS_MPU_CFG 94 -#define QCS8300_SLAVE_LPASS_THROTTLE_CFG 95 -#define QCS8300_SLAVE_LPASS_TOP_CFG 96 -#define QCS8300_SLAVE_MX_RDPM 97 -#define QCS8300_SLAVE_MXC_RDPM 98 -#define QCS8300_SLAVE_PCIE_0_CFG 99 -#define QCS8300_SLAVE_PCIE_1_CFG 100 -#define QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG 101 -#define QCS8300_SLAVE_PCIE_THROTTLE_CFG 102 -#define QCS8300_SLAVE_PDM 103 -#define QCS8300_SLAVE_PIMEM_CFG 104 -#define QCS8300_SLAVE_PKA_WRAPPER_CFG 105 -#define QCS8300_SLAVE_QDSS_CFG 106 -#define QCS8300_SLAVE_QM_CFG 107 -#define QCS8300_SLAVE_QM_MPU_CFG 108 -#define QCS8300_SLAVE_QUP_0 109 -#define QCS8300_SLAVE_QUP_1 110 -#define QCS8300_SLAVE_QUP_3 111 -#define QCS8300_SLAVE_SAIL_THROTTLE_CFG 112 -#define QCS8300_SLAVE_SDC1 113 -#define QCS8300_SLAVE_SECURITY 114 -#define QCS8300_SLAVE_SNOC_THROTTLE_CFG 115 -#define QCS8300_SLAVE_TCSR 116 -#define QCS8300_SLAVE_TLMM 117 -#define QCS8300_SLAVE_TSC_CFG 118 -#define QCS8300_SLAVE_UFS_MEM_CFG 119 -#define QCS8300_SLAVE_USB2 120 -#define QCS8300_SLAVE_USB3_0 121 -#define QCS8300_SLAVE_VENUS_CFG 122 -#define QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG 123 -#define QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG 124 -#define QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG 125 -#define QCS8300_SLAVE_A1NOC_SNOC 126 -#define QCS8300_SLAVE_A2NOC_SNOC 127 -#define QCS8300_SLAVE_DDRSS_CFG 128 -#define QCS8300_SLAVE_GEM_NOC_CNOC 129 -#define QCS8300_SLAVE_GEM_NOC_CFG 130 -#define QCS8300_SLAVE_SNOC_GEM_NOC_GC 131 -#define QCS8300_SLAVE_SNOC_GEM_NOC_SF 132 -#define QCS8300_SLAVE_GP_DSP_SAIL_NOC 133 -#define QCS8300_SLAVE_GPDSP_NOC_CFG 134 -#define QCS8300_SLAVE_HCP_A 135 -#define QCS8300_SLAVE_LLCC 136 -#define QCS8300_SLAVE_MNOC_HF_MEM_NOC 137 -#define QCS8300_SLAVE_MNOC_SF_MEM_NOC 138 -#define QCS8300_SLAVE_CNOC_MNOC_HF_CFG 139 -#define QCS8300_SLAVE_CNOC_MNOC_SF_CFG 140 -#define QCS8300_SLAVE_CDSP_MEM_NOC 141 -#define QCS8300_SLAVE_GEM_NOC_PCIE_CNOC 142 -#define QCS8300_SLAVE_PCIE_ANOC_CFG 143 -#define QCS8300_SLAVE_ANOC_PCIE_GEM_NOC 144 -#define QCS8300_SLAVE_SNOC_CFG 145 -#define QCS8300_SLAVE_LPASS_SNOC 146 -#define QCS8300_SLAVE_QUP_CORE_0 147 -#define QCS8300_SLAVE_QUP_CORE_1 148 -#define QCS8300_SLAVE_QUP_CORE_3 149 -#define QCS8300_SLAVE_BOOT_IMEM 150 -#define QCS8300_SLAVE_IMEM 151 -#define QCS8300_SLAVE_PIMEM 152 -#define QCS8300_SLAVE_SERVICE_NSP_NOC 153 -#define QCS8300_SLAVE_SERVICE_GEM_NOC_1 154 -#define QCS8300_SLAVE_SERVICE_MNOC_HF 155 -#define QCS8300_SLAVE_SERVICE_MNOC_SF 156 -#define QCS8300_SLAVE_SERVICES_LPASS_AML_NOC 157 -#define QCS8300_SLAVE_SERVICE_LPASS_AG_NOC 158 -#define QCS8300_SLAVE_SERVICE_GEM_NOC_2 159 -#define QCS8300_SLAVE_SERVICE_SNOC 160 -#define QCS8300_SLAVE_SERVICE_GEM_NOC 161 -#define QCS8300_SLAVE_SERVICE_GEM_NOC2 162 -#define QCS8300_SLAVE_PCIE_0 163 -#define QCS8300_SLAVE_PCIE_1 164 -#define QCS8300_SLAVE_QDSS_STM 165 -#define QCS8300_SLAVE_TCU 166 - -#endif From 4709fc2f5309a89a353008f9245be9108b4af340 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:26 +0200 Subject: [PATCH 145/304] interconnect: qcom: qdu1000: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-10-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/qdu1000.c | 352 ++++++++++++---------------- drivers/interconnect/qcom/qdu1000.h | 95 -------- 2 files changed, 155 insertions(+), 292 deletions(-) delete mode 100644 drivers/interconnect/qcom/qdu1000.h diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index a7392eb73d4a..4de0f17e4c57 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -15,756 +15,710 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "qdu1000.h" + +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_ecpri_dma; +static struct qcom_icc_node qnm_fec_2_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_mdsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_system_noc_cfg; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_aggre_noc_gsi; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_modem_slave; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ecpri_gsi; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_ecpri_dma; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_modem_slave; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_ahb2phy0_south; +static struct qcom_icc_node qhs_ahb2phy1_north; +static struct qcom_icc_node qhs_ahb2phy2_east; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_ecpri_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_smbus_cfg; +static struct qcom_icc_node qhs_system_noc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_anoc_snoc_gsi; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_ecpri_gemnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_modem; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_ethernet_ss; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = QDU1000_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = QDU1000_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = QDU1000_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = QDU1000_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 4, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave, &qns_pcie }, }; static struct qcom_icc_node qnm_ecpri_dma = { .name = "qnm_ecpri_dma", - .id = QDU1000_MASTER_GEMNOC_ECPRI_DMA, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_fec_2_gemnoc = { .name = "qnm_fec_2_gemnoc", - .id = QDU1000_MASTER_FEC_2_GEMNOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 3, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = QDU1000_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = QDU1000_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 4, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave, &qns_pcie }, }; static struct qcom_icc_node qxm_mdsp = { .name = "qxm_mdsp", - .id = QDU1000_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = QDU1000_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = QDU1000_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = QDU1000_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = QDU1000_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = QDU1000_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = QDU1000_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = QDU1000_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_system_noc_cfg = { .name = "qhm_system_noc_cfg", - .id = QDU1000_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_system_noc }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = QDU1000_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre_noc_gsi = { .name = "qnm_aggre_noc_gsi", - .id = QDU1000_MASTER_ANOC_GSI, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = QDU1000_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 36, - .links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH, - QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS, - QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG, - QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG, - QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG, - QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS, - QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM, - QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG, - QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC, - QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0, - QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2, - QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG, - QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM, - QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG, - QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG, - QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM, - QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS, - QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north, + &qhs_ahb2phy2_east, &qhs_aoss, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto_cfg, + &qhs_ecpri_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc2, + &qhs_smbus_cfg, &qhs_system_noc_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_tsc_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qxs_imem, + &qxs_pimem, &xs_ethernet_ss, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_modem_slave = { .name = "qnm_gemnoc_modem_slave", - .id = QDU1000_MASTER_GEMNOC_MODEM_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_SLAVE_MODEM_OFFLINE }, + .link_nodes = { &qns_modem }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = QDU1000_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_ecpri_gsi = { .name = "qxm_ecpri_gsi", - .id = QDU1000_MASTER_ECPRI_GSI, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 }, + .link_nodes = { &qns_anoc_snoc_gsi, &xs_pcie }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = QDU1000_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_ecpri_dma = { .name = "xm_ecpri_dma", - .id = QDU1000_MASTER_SNOC_ECPRI_DMA, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 }, + .link_nodes = { &qns_ecpri_gemnoc, &xs_pcie }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = QDU1000_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = QDU1000_MASTER_PCIE, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_qdss_etr0 = { .name = "xm_qdss_etr0", - .id = QDU1000_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node xm_qdss_etr1 = { .name = "xm_qdss_etr1", - .id = QDU1000_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node xm_sdc = { .name = "xm_sdc", - .id = QDU1000_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = QDU1000_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = QDU1000_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = QDU1000_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = QDU1000_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = QDU1000_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_modem_slave = { .name = "qns_modem_slave", - .id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC }, + .link_nodes = { &qnm_gemnoc_modem_slave }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = QDU1000_SLAVE_EBI1, .channels = 8, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0_south = { .name = "qhs_ahb2phy0_south", - .id = QDU1000_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1_north = { .name = "qhs_ahb2phy1_north", - .id = QDU1000_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy2_east = { .name = "qhs_ahb2phy2_east", - .id = QDU1000_SLAVE_AHB2PHY_EAST, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = QDU1000_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = QDU1000_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = QDU1000_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = QDU1000_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto_cfg = { .name = "qhs_crypto_cfg", - .id = QDU1000_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ecpri_cfg = { .name = "qhs_ecpri_cfg", - .id = QDU1000_SLAVE_ECPRI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = QDU1000_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = QDU1000_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = QDU1000_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_cfg = { .name = "qhs_pcie_cfg", - .id = QDU1000_SLAVE_PCIE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = QDU1000_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = QDU1000_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = QDU1000_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = QDU1000_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = QDU1000_SLAVE_QPIC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = QDU1000_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = QDU1000_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = QDU1000_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = QDU1000_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_smbus_cfg = { .name = "qhs_smbus_cfg", - .id = QDU1000_SLAVE_SMBUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_system_noc_cfg = { .name = "qhs_system_noc_cfg", - .id = QDU1000_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_system_noc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = QDU1000_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = QDU1000_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = QDU1000_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tsc_cfg = { .name = "qhs_tsc_cfg", - .id = QDU1000_SLAVE_TSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = QDU1000_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = QDU1000_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = QDU1000_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_anoc_snoc_gsi = { .name = "qns_anoc_snoc_gsi", - .id = QDU1000_SLAVE_ANOC_SNOC_GSI, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_MASTER_ANOC_GSI }, + .link_nodes = { &qnm_aggre_noc_gsi }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = QDU1000_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_ecpri_gemnoc = { .name = "qns_ecpri_gemnoc", - .id = QDU1000_SLAVE_ECPRI_GEMNOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA }, + .link_nodes = { &qnm_ecpri_dma }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = QDU1000_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = QDU1000_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_modem = { .name = "qns_modem", - .id = QDU1000_SLAVE_MODEM_OFFLINE, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", - .id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = QDU1000_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = QDU1000_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_system_noc = { .name = "srvc_system_noc", - .id = QDU1000_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_ethernet_ss = { .name = "xs_ethernet_ss", - .id = QDU1000_SLAVE_ETHERNET_SS, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = QDU1000_SLAVE_PCIE_0, .channels = 1, .buswidth = 64, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = QDU1000_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = QDU1000_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -880,6 +834,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc qdu1000_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -907,6 +862,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc qdu1000_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -924,6 +880,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc qdu1000_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1010,6 +967,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc qdu1000_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/qdu1000.h b/drivers/interconnect/qcom/qdu1000.h deleted file mode 100644 index e75a6419df23..000000000000 --- a/drivers/interconnect/qcom/qdu1000.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H -#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H - -#define QDU1000_MASTER_SYS_TCU 0 -#define QDU1000_MASTER_APPSS_PROC 1 -#define QDU1000_MASTER_LLCC 2 -#define QDU1000_MASTER_GIC_AHB 3 -#define QDU1000_MASTER_QDSS_BAM 4 -#define QDU1000_MASTER_QPIC 5 -#define QDU1000_MASTER_QSPI_0 6 -#define QDU1000_MASTER_QUP_0 7 -#define QDU1000_MASTER_QUP_1 8 -#define QDU1000_MASTER_SNOC_CFG 9 -#define QDU1000_MASTER_ANOC_SNOC 10 -#define QDU1000_MASTER_ANOC_GSI 11 -#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12 -#define QDU1000_MASTER_FEC_2_GEMNOC 13 -#define QDU1000_MASTER_GEM_NOC_CNOC 14 -#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15 -#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16 -#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17 -#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18 -#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19 -#define QDU1000_MASTER_QUP_CORE_0 20 -#define QDU1000_MASTER_QUP_CORE_1 21 -#define QDU1000_MASTER_CRYPTO 22 -#define QDU1000_MASTER_ECPRI_GSI 23 -#define QDU1000_MASTER_MSS_PROC 24 -#define QDU1000_MASTER_PIMEM 25 -#define QDU1000_MASTER_SNOC_ECPRI_DMA 26 -#define QDU1000_MASTER_GIC 27 -#define QDU1000_MASTER_PCIE 28 -#define QDU1000_MASTER_QDSS_ETR 29 -#define QDU1000_MASTER_QDSS_ETR_1 30 -#define QDU1000_MASTER_SDCC_1 31 -#define QDU1000_MASTER_USB3 32 -#define QDU1000_SLAVE_EBI1 512 -#define QDU1000_SLAVE_AHB2PHY_SOUTH 513 -#define QDU1000_SLAVE_AHB2PHY_NORTH 514 -#define QDU1000_SLAVE_AHB2PHY_EAST 515 -#define QDU1000_SLAVE_AOSS 516 -#define QDU1000_SLAVE_CLK_CTL 517 -#define QDU1000_SLAVE_RBCPR_CX_CFG 518 -#define QDU1000_SLAVE_RBCPR_MX_CFG 519 -#define QDU1000_SLAVE_CRYPTO_0_CFG 520 -#define QDU1000_SLAVE_ECPRI_CFG 521 -#define QDU1000_SLAVE_IMEM_CFG 522 -#define QDU1000_SLAVE_IPC_ROUTER_CFG 523 -#define QDU1000_SLAVE_CNOC_MSS 524 -#define QDU1000_SLAVE_PCIE_CFG 525 -#define QDU1000_SLAVE_PDM 526 -#define QDU1000_SLAVE_PIMEM_CFG 527 -#define QDU1000_SLAVE_PRNG 528 -#define QDU1000_SLAVE_QDSS_CFG 529 -#define QDU1000_SLAVE_QPIC 530 -#define QDU1000_SLAVE_QSPI_0 531 -#define QDU1000_SLAVE_QUP_0 532 -#define QDU1000_SLAVE_QUP_1 533 -#define QDU1000_SLAVE_SDCC_2 534 -#define QDU1000_SLAVE_SMBUS_CFG 535 -#define QDU1000_SLAVE_SNOC_CFG 536 -#define QDU1000_SLAVE_TCSR 537 -#define QDU1000_SLAVE_TLMM 538 -#define QDU1000_SLAVE_TME_CFG 539 -#define QDU1000_SLAVE_TSC_CFG 540 -#define QDU1000_SLAVE_USB3_0 541 -#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542 -#define QDU1000_SLAVE_A1NOC_SNOC 543 -#define QDU1000_SLAVE_ANOC_SNOC_GSI 544 -#define QDU1000_SLAVE_DDRSS_CFG 545 -#define QDU1000_SLAVE_ECPRI_GEMNOC 546 -#define QDU1000_SLAVE_GEM_NOC_CNOC 547 -#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548 -#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549 -#define QDU1000_SLAVE_LLCC 550 -#define QDU1000_SLAVE_MODEM_OFFLINE 551 -#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552 -#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553 -#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554 -#define QDU1000_SLAVE_QUP_CORE_0 555 -#define QDU1000_SLAVE_QUP_CORE_1 556 -#define QDU1000_SLAVE_IMEM 557 -#define QDU1000_SLAVE_PIMEM 558 -#define QDU1000_SLAVE_SERVICE_SNOC 559 -#define QDU1000_SLAVE_ETHERNET_SS 560 -#define QDU1000_SLAVE_PCIE_0 561 -#define QDU1000_SLAVE_QDSS_STM 562 -#define QDU1000_SLAVE_TCU 563 - -#endif From aa4e3ba69edeac0fb59a0bb39c773c92232cb3a5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:27 +0200 Subject: [PATCH 146/304] interconnect: qcom: sar2130p: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-11-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sar2130p.c | 639 ++++++++++----------------- 1 file changed, 238 insertions(+), 401 deletions(-) diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qcom/sar2130p.c index 9eac0ac76812..a0b04929058f 100644 --- a/drivers/interconnect/qcom/sar2130p.c +++ b/drivers/interconnect/qcom/sar2130p.c @@ -20,125 +20,123 @@ #include "icc-common.h" #include "icc-rpmh.h" -enum { - SAR2130P_MASTER_QUP_CORE_0, - SAR2130P_MASTER_QUP_CORE_1, - SAR2130P_MASTER_GEM_NOC_CNOC, - SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, - SAR2130P_MASTER_QDSS_DAP, - SAR2130P_MASTER_GPU_TCU, - SAR2130P_MASTER_SYS_TCU, - SAR2130P_MASTER_APPSS_PROC, - SAR2130P_MASTER_GFX3D, - SAR2130P_MASTER_MNOC_HF_MEM_NOC, - SAR2130P_MASTER_MNOC_SF_MEM_NOC, - SAR2130P_MASTER_COMPUTE_NOC, - SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, - SAR2130P_MASTER_SNOC_GC_MEM_NOC, - SAR2130P_MASTER_SNOC_SF_MEM_NOC, - SAR2130P_MASTER_WLAN_Q6, - SAR2130P_MASTER_CNOC_LPASS_AG_NOC, - SAR2130P_MASTER_LPASS_PROC, - SAR2130P_MASTER_LLCC, - SAR2130P_MASTER_CAMNOC_HF, - SAR2130P_MASTER_CAMNOC_ICP, - SAR2130P_MASTER_CAMNOC_SF, - SAR2130P_MASTER_LSR, - SAR2130P_MASTER_MDP, - SAR2130P_MASTER_CNOC_MNOC_CFG, - SAR2130P_MASTER_VIDEO, - SAR2130P_MASTER_VIDEO_CV_PROC, - SAR2130P_MASTER_VIDEO_PROC, - SAR2130P_MASTER_VIDEO_V_PROC, - SAR2130P_MASTER_CDSP_NOC_CFG, - SAR2130P_MASTER_CDSP_PROC, - SAR2130P_MASTER_PCIE_0, - SAR2130P_MASTER_PCIE_1, - SAR2130P_MASTER_GIC_AHB, - SAR2130P_MASTER_QDSS_BAM, - SAR2130P_MASTER_QSPI_0, - SAR2130P_MASTER_QUP_0, - SAR2130P_MASTER_QUP_1, - SAR2130P_MASTER_A2NOC_SNOC, - SAR2130P_MASTER_CNOC_DATAPATH, - SAR2130P_MASTER_LPASS_ANOC, - SAR2130P_MASTER_SNOC_CFG, - SAR2130P_MASTER_CRYPTO, - SAR2130P_MASTER_PIMEM, - SAR2130P_MASTER_GIC, - SAR2130P_MASTER_QDSS_ETR, - SAR2130P_MASTER_QDSS_ETR_1, - SAR2130P_MASTER_SDCC_1, - SAR2130P_MASTER_USB3_0, - SAR2130P_SLAVE_QUP_CORE_0, - SAR2130P_SLAVE_QUP_CORE_1, - SAR2130P_SLAVE_AHB2PHY_SOUTH, - SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, - SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, - SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, - SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, - SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, - SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, - SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, - SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, - SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, - SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, - SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, - SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, - SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, - SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, - SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, - SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, - SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, - SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, - SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, - SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, - SAR2130P_SLAVE_PCIE_0, - SAR2130P_SLAVE_PCIE_1, - SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU, - SAR2130P_SLAVE_GEM_NOC_CNOC, - SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, - SAR2130P_SLAVE_LPASS_CORE_CFG, - SAR2130P_SLAVE_LPASS_LPI_CFG, - SAR2130P_SLAVE_LPASS_MPU_CFG, - SAR2130P_SLAVE_LPASS_TOP_CFG, - SAR2130P_SLAVE_LPASS_SNOC, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, - SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, - SAR2130P_SLAVE_EBI1, - SAR2130P_SLAVE_MNOC_HF_MEM_NOC, - SAR2130P_SLAVE_MNOC_SF_MEM_NOC, - SAR2130P_SLAVE_SERVICE_MNOC, - SAR2130P_SLAVE_CDSP_MEM_NOC, - SAR2130P_SLAVE_SERVICE_NSP_NOC, - SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, - SAR2130P_SLAVE_A2NOC_SNOC, - SAR2130P_SLAVE_SNOC_GEM_NOC_GC, - SAR2130P_SLAVE_SNOC_GEM_NOC_SF, - SAR2130P_SLAVE_SERVICE_SNOC, -}; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_wlan_q6; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_lsr; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_wlan_q6; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static const struct regmap_config icc_regmap_config = { .reg_bits = 32, @@ -149,89 +147,84 @@ static const struct regmap_config icc_regmap_config = { static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SAR2130P_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SAR2130P_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SAR2130P_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 43, - .links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SAR2130P_SLAVE_PCIE_0, SAR2130P_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SAR2130P_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 43, - .links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static const struct qcom_icc_qosbox alm_gpu_tcu_qos = { @@ -244,12 +237,11 @@ static const struct qcom_icc_qosbox alm_gpu_tcu_qos = { static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SAR2130P_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .qosbox = &alm_gpu_tcu_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static const struct qcom_icc_qosbox alm_sys_tcu_qos = { @@ -262,22 +254,20 @@ static const struct qcom_icc_qosbox alm_sys_tcu_qos = { static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SAR2130P_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .qosbox = &alm_sys_tcu_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SAR2130P_MASTER_APPSS_PROC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static const struct qcom_icc_qosbox qnm_gpu_qos = { @@ -290,12 +280,11 @@ static const struct qcom_icc_qosbox qnm_gpu_qos = { static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SAR2130P_MASTER_GFX3D, .channels = 2, .buswidth = 32, .qosbox = &qnm_gpu_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = { @@ -307,12 +296,11 @@ static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = { static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SAR2130P_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = { @@ -324,12 +312,11 @@ static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = { static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SAR2130P_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { @@ -342,12 +329,11 @@ static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SAR2130P_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .qosbox = &qnm_nsp_gemnoc_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static const struct qcom_icc_qosbox qnm_pcie_qos = { @@ -359,12 +345,11 @@ static const struct qcom_icc_qosbox qnm_pcie_qos = { static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &qnm_pcie_qos, .num_links = 2, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static const struct qcom_icc_qosbox qnm_snoc_gc_qos = { @@ -376,12 +361,11 @@ static const struct qcom_icc_qosbox qnm_snoc_gc_qos = { static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SAR2130P_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .qosbox = &qnm_snoc_gc_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static const struct qcom_icc_qosbox qnm_snoc_sf_qos = { @@ -393,53 +377,48 @@ static const struct qcom_icc_qosbox qnm_snoc_sf_qos = { static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SAR2130P_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &qnm_snoc_sf_qos, .num_links = 3, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qxm_wlan_q6 = { .name = "qxm_wlan_q6", - .id = SAR2130P_MASTER_WLAN_Q6, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SAR2130P_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SAR2130P_SLAVE_LPASS_CORE_CFG, SAR2130P_SLAVE_LPASS_LPI_CFG, - SAR2130P_SLAVE_LPASS_MPU_CFG, SAR2130P_SLAVE_LPASS_TOP_CFG, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = SAR2130P_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SAR2130P_SLAVE_LPASS_TOP_CFG, SAR2130P_SLAVE_LPASS_SNOC, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SAR2130P_MASTER_LLCC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = { @@ -451,12 +430,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = { static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SAR2130P_MASTER_CAMNOC_HF, .channels = 1, .buswidth = 32, .qosbox = &qnm_camnoc_hf_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = { @@ -468,12 +446,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = { static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SAR2130P_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .qosbox = &qnm_camnoc_icp_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = { @@ -485,12 +462,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = { static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SAR2130P_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .qosbox = &qnm_camnoc_sf_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static const struct qcom_icc_qosbox qnm_lsr_qos = { @@ -502,12 +478,11 @@ static const struct qcom_icc_qosbox qnm_lsr_qos = { static struct qcom_icc_node qnm_lsr = { .name = "qnm_lsr", - .id = SAR2130P_MASTER_LSR, .channels = 2, .buswidth = 32, .qosbox = &qnm_lsr_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static const struct qcom_icc_qosbox qnm_mdp_qos = { @@ -519,21 +494,19 @@ static const struct qcom_icc_qosbox qnm_mdp_qos = { static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SAR2130P_MASTER_MDP, .channels = 2, .buswidth = 32, .qosbox = &qnm_mdp_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SAR2130P_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static const struct qcom_icc_qosbox qnm_video_qos = { @@ -545,12 +518,11 @@ static const struct qcom_icc_qosbox qnm_video_qos = { static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SAR2130P_MASTER_VIDEO, .channels = 2, .buswidth = 32, .qosbox = &qnm_video_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { @@ -562,12 +534,11 @@ static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SAR2130P_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .qosbox = &qnm_video_cv_cpu_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static const struct qcom_icc_qosbox qnm_video_cvp_qos = { @@ -579,12 +550,11 @@ static const struct qcom_icc_qosbox qnm_video_cvp_qos = { static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SAR2130P_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .qosbox = &qnm_video_cvp_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = { @@ -596,30 +566,27 @@ static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = { static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SAR2130P_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .qosbox = &qnm_video_v_cpu_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SAR2130P_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SAR2130P_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SAR2130P_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static const struct qcom_icc_qosbox xm_pcie3_0_qos = { @@ -632,12 +599,11 @@ static const struct qcom_icc_qosbox xm_pcie3_0_qos = { static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SAR2130P_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .qosbox = &xm_pcie3_0_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static const struct qcom_icc_qosbox xm_pcie3_1_qos = { @@ -650,12 +616,11 @@ static const struct qcom_icc_qosbox xm_pcie3_1_qos = { static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SAR2130P_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .qosbox = &xm_pcie3_1_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static const struct qcom_icc_qosbox qhm_gic_qos = { @@ -668,12 +633,11 @@ static const struct qcom_icc_qosbox qhm_gic_qos = { static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SAR2130P_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .qosbox = &qhm_gic_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static const struct qcom_icc_qosbox qhm_qdss_bam_qos = { @@ -686,12 +650,11 @@ static const struct qcom_icc_qosbox qhm_qdss_bam_qos = { static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SAR2130P_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .qosbox = &qhm_qdss_bam_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox qhm_qspi_qos = { @@ -704,12 +667,11 @@ static const struct qcom_icc_qosbox qhm_qspi_qos = { static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SAR2130P_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .qosbox = &qhm_qspi_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox qhm_qup0_qos = { @@ -722,12 +684,11 @@ static const struct qcom_icc_qosbox qhm_qup0_qos = { static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SAR2130P_MASTER_QUP_0, .channels = 1, .buswidth = 4, .qosbox = &qhm_qup0_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox qhm_qup1_qos = { @@ -740,21 +701,19 @@ static const struct qcom_icc_qosbox qhm_qup1_qos = { static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SAR2130P_MASTER_QUP_1, .channels = 1, .buswidth = 4, .qosbox = &qhm_qup1_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SAR2130P_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { @@ -767,12 +726,11 @@ static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", - .id = SAR2130P_MASTER_CNOC_DATAPATH, .channels = 1, .buswidth = 8, .qosbox = &qnm_cnoc_datapath_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox qnm_lpass_noc_qos = { @@ -785,21 +743,19 @@ static const struct qcom_icc_qosbox qnm_lpass_noc_qos = { static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = SAR2130P_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .qosbox = &qnm_lpass_noc_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SAR2130P_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static const struct qcom_icc_qosbox qxm_crypto_qos = { @@ -812,12 +768,11 @@ static const struct qcom_icc_qosbox qxm_crypto_qos = { static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SAR2130P_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .qosbox = &qxm_crypto_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox qxm_pimem_qos = { @@ -830,12 +785,11 @@ static const struct qcom_icc_qosbox qxm_pimem_qos = { static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SAR2130P_MASTER_PIMEM, .channels = 1, .buswidth = 8, .qosbox = &qxm_pimem_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static const struct qcom_icc_qosbox xm_gic_qos = { @@ -848,12 +802,11 @@ static const struct qcom_icc_qosbox xm_gic_qos = { static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SAR2130P_MASTER_GIC, .channels = 1, .buswidth = 8, .qosbox = &xm_gic_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = { @@ -866,12 +819,11 @@ static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = { static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SAR2130P_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .qosbox = &xm_qdss_etr_0_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = { @@ -884,12 +836,11 @@ static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = { static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SAR2130P_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .qosbox = &xm_qdss_etr_1_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox xm_sdc1_qos = { @@ -902,12 +853,11 @@ static const struct qcom_icc_qosbox xm_sdc1_qos = { static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SAR2130P_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .qosbox = &xm_sdc1_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static const struct qcom_icc_qosbox xm_usb3_0_qos = { @@ -920,571 +870,449 @@ static const struct qcom_icc_qosbox xm_usb3_0_qos = { static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SAR2130P_MASTER_USB3_0, .channels = 1, .buswidth = 8, .qosbox = &xm_usb3_0_qos, .num_links = 1, - .links = { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SAR2130P_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SAR2130P_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SAR2130P_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SAR2130P_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SAR2130P_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SAR2130P_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SAR2130P_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SAR2130P_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SAR2130P_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SAR2130P_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SAR2130P_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SAR2130P_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SAR2130P_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SAR2130P_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SAR2130P_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SAR2130P_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SAR2130P_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SAR2130P_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SAR2130P_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SAR2130P_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SAR2130P_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SAR2130P_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SAR2130P_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SAR2130P_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SAR2130P_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SAR2130P_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SAR2130P_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SAR2130P_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SAR2130P_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SAR2130P_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SAR2130P_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SAR2130P_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SAR2130P_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SAR2130P_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SAR2130P_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SAR2130P_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_wlan_q6 = { .name = "qhs_wlan_q6", - .id = SAR2130P_SLAVE_WLAN_Q6_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SAR2130P_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SAR2130P_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SAR2130P_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SAR2130P_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SAR2130P_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SAR2130P_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SAR2130P_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SAR2130P_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SAR2130P_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SAR2130P_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SAR2130P_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SAR2130P_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SAR2130P_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SAR2130P_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SAR2130P_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SAR2130P_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SAR2130P_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SAR2130P_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = SAR2130P_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SAR2130P_SLAVE_EBI1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SAR2130P_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SAR2130P_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SAR2130P_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SAR2130P_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SAR2130P_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SAR2130P_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SAR2130P_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SAR2130P_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SAR2130P_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SAR2130P_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SAR2130P_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SAR2130P_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SAR2130P_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SAR2130P_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -1646,6 +1474,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sar2130p_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1708,6 +1537,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_config_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), @@ -1738,6 +1568,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_gem_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), @@ -1761,6 +1592,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_lpass_ag_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1779,6 +1611,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sar2130p_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1807,6 +1640,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_mmss_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), @@ -1826,6 +1660,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_nsp_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), @@ -1844,6 +1679,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_pcie_anoc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), @@ -1883,6 +1719,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_system_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), From c6040ccb0af746091f823a4fb4053ecc2894b203 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:28 +0200 Subject: [PATCH 147/304] interconnect: qcom: sc7180: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-12-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc7180.c | 690 ++++++++++++++--------------- drivers/interconnect/qcom/sc7180.h | 149 ------- 2 files changed, 344 insertions(+), 495 deletions(-) delete mode 100644 drivers/interconnect/qcom/sc7180.h diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index af2be1543840..9f94b987c444 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -14,1224 +14,1210 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7180.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qhm_usb3; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps0; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qup_core_master_1; +static struct qcom_icc_node qup_core_master_2; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_rt_throttle_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_npu_dma_throttle_cfg; +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_1; +static struct qcom_icc_node qhs_tlmm_2; +static struct qcom_icc_node qhs_tlmm_3; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qup_core_slave_1; +static struct qcom_icc_node qup_core_slave_2; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SC7180_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SC7180_MASTER_QSPI, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup_0 = { .name = "qhm_qup_0", - .id = SC7180_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SC7180_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SC7180_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SC7180_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SC7180_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SC7180_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup_1 = { .name = "qhm_qup_1", - .id = SC7180_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SC7180_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SC7180_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SC7180_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_usb3 = { .name = "qhm_usb3", - .id = SC7180_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SC7180_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SC7180_MASTER_NPU, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qxm_npu_dsp = { .name = "qxm_npu_dsp", - .id = SC7180_MASTER_NPU_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SC7180_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 51, - .links = { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SC7180_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 51, - .links = { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SC7180_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_CFG, - SC7180_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_gemnoc, + &qhs_llcc }, }; static struct qcom_icc_node acm_apps0 = { .name = "acm_apps0", - .id = SC7180_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SC7180_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SC7180_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, - SC7180_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, + &srvc_gemnoc }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SC7180_MASTER_COMPUTE_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SC7180_MASTER_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SC7180_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SC7180_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SC7180_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SC7180_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SC7180_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SC7180_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SC7180_MASTER_CAMNOC_HF0, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SC7180_MASTER_CAMNOC_HF1, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SC7180_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SC7180_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SC7180_MASTER_ROTATOR, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SC7180_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SC7180_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node amm_npu_sys = { .name = "amm_npu_sys", - .id = SC7180_MASTER_NPU_SYS, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node qhm_npu_cfg = { .name = "qhm_npu_cfg", - .id = SC7180_MASTER_NPU_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 8, - .links = { SC7180_SLAVE_NPU_CAL_DP0, - SC7180_SLAVE_NPU_CP, - SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_DPM, - SC7180_SLAVE_ISENSE_CFG, - SC7180_SLAVE_NPU_LLM_CFG, - SC7180_SLAVE_NPU_TCM, - SC7180_SLAVE_SERVICE_NPU_NOC - }, + .link_nodes = { &qhs_cal_dp0, + &qhs_cp, + &qhs_dma_bwmon, + &qhs_dpm, + &qhs_isense, + &qhs_llm, + &qhs_tcm, + &srvc_noc }, }; static struct qcom_icc_node qup_core_master_1 = { .name = "qup_core_master_1", - .id = SC7180_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup_core_slave_1 }, }; static struct qcom_icc_node qup_core_master_2 = { .name = "qup_core_master_2", - .id = SC7180_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup_core_slave_2 }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SC7180_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SC7180_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SC7180_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SC7180_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SC7180_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC, - SC7180_SLAVE_IMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SC7180_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SC7180_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SC7180_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SC7180_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SC7180_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_cdsp_gemnoc = { .name = "qns_cdsp_gemnoc", - .id = SC7180_SLAVE_CDSP_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SC7180_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SC7180_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SC7180_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SC7180_SLAVE_AHB2PHY_CENTER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SC7180_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SC7180_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", - .id = SC7180_SLAVE_BOOT_ROM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SC7180_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { .name = "qhs_camera_nrt_throttle_cfg", - .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SC7180_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SC7180_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SC7180_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SC7180_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SC7180_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SC7180_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SC7180_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_rt_throttle_cfg = { .name = "qhs_display_rt_throttle_cfg", - .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_throttle_cfg = { .name = "qhs_display_throttle_cfg", - .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SC7180_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SC7180_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SC7180_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SC7180_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SC7180_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SC7180_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SC7180_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SC7180_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_NPU_NOC_CFG }, + .link_nodes = { &qhm_npu_cfg }, }; static struct qcom_icc_node qhs_npu_dma_throttle_cfg = { .name = "qhs_npu_dma_throttle_cfg", - .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = { .name = "qhs_npu_dsp_throttle_cfg", - .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SC7180_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SC7180_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SC7180_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SC7180_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_cfg = { .name = "qhs_qm_cfg", - .id = SC7180_SLAVE_QM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_mpu_cfg = { .name = "qhs_qm_mpu_cfg", - .id = SC7180_SLAVE_QM_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SC7180_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SC7180_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SC7180_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SC7180_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SC7180_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SC7180_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SC7180_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_1 = { .name = "qhs_tlmm_1", - .id = SC7180_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_2 = { .name = "qhs_tlmm_2", - .id = SC7180_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_3 = { .name = "qhs_tlmm_3", - .id = SC7180_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SC7180_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SC7180_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SC7180_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_throttle_cfg = { .name = "qhs_venus_throttle_cfg", - .id = SC7180_SLAVE_VENUS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SC7180_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SC7180_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gemnoc = { .name = "qhs_gemnoc", - .id = SC7180_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SC7180_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SC7180_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SC7180_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SC7180_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SC7180_SLAVE_EBI1, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SC7180_SLAVE_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SC7180_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SC7180_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp0 = { .name = "qhs_cal_dp0", - .id = SC7180_SLAVE_NPU_CAL_DP0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cp = { .name = "qhs_cp", - .id = SC7180_SLAVE_NPU_CP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dma_bwmon = { .name = "qhs_dma_bwmon", - .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dpm = { .name = "qhs_dpm", - .id = SC7180_SLAVE_NPU_DPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_isense = { .name = "qhs_isense", - .id = SC7180_SLAVE_ISENSE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llm = { .name = "qhs_llm", - .id = SC7180_SLAVE_NPU_LLM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcm = { .name = "qhs_tcm", - .id = SC7180_SLAVE_NPU_TCM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_npu_sys = { .name = "qns_npu_sys", - .id = SC7180_SLAVE_NPU_COMPUTE_NOC, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node srvc_noc = { .name = "srvc_noc", - .id = SC7180_SLAVE_SERVICE_NPU_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup_core_slave_1 = { .name = "qup_core_slave_1", - .id = SC7180_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup_core_slave_2 = { .name = "qup_core_slave_2", - .id = SC7180_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SC7180_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SC7180_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SC7180_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SC7180_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SC7180_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SC7180_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SC7180_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SC7180_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SC7180_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1485,6 +1471,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1508,6 +1495,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1526,6 +1514,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc sc7180_camnoc_virt = { + .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1545,6 +1534,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_compute_noc = { + .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1613,6 +1603,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1626,6 +1617,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1654,6 +1646,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1671,6 +1664,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sc7180_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1698,6 +1692,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1719,6 +1714,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_npu_noc = { + .alloc_dyn_id = true, .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), }; @@ -1735,6 +1731,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = { }; static const struct qcom_icc_desc sc7180_qup_virt = { + .alloc_dyn_id = true, .nodes = qup_virt_nodes, .num_nodes = ARRAY_SIZE(qup_virt_nodes), .bcms = qup_virt_bcms, @@ -1770,6 +1767,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h deleted file mode 100644 index 2b718922c109..000000000000 --- a/drivers/interconnect/qcom/sc7180.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7180 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H - -#define SC7180_MASTER_APPSS_PROC 0 -#define SC7180_MASTER_SYS_TCU 1 -#define SC7180_MASTER_NPU_SYS 2 -/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC7180_MASTER_LLCC 4 -#define SC7180_MASTER_A1NOC_CFG 5 -#define SC7180_MASTER_A2NOC_CFG 6 -#define SC7180_MASTER_CNOC_DC_NOC 7 -#define SC7180_MASTER_GEM_NOC_CFG 8 -#define SC7180_MASTER_CNOC_MNOC_CFG 9 -#define SC7180_MASTER_NPU_NOC_CFG 10 -#define SC7180_MASTER_QDSS_BAM 11 -#define SC7180_MASTER_QSPI 12 -#define SC7180_MASTER_QUP_0 13 -#define SC7180_MASTER_QUP_1 14 -#define SC7180_MASTER_SNOC_CFG 15 -#define SC7180_MASTER_A1NOC_SNOC 16 -#define SC7180_MASTER_A2NOC_SNOC 17 -#define SC7180_MASTER_COMPUTE_NOC 18 -#define SC7180_MASTER_GEM_NOC_SNOC 19 -#define SC7180_MASTER_MNOC_HF_MEM_NOC 20 -#define SC7180_MASTER_MNOC_SF_MEM_NOC 21 -#define SC7180_MASTER_NPU 22 -#define SC7180_MASTER_SNOC_CNOC 23 -#define SC7180_MASTER_SNOC_GC_MEM_NOC 24 -#define SC7180_MASTER_SNOC_SF_MEM_NOC 25 -#define SC7180_MASTER_QUP_CORE_0 26 -#define SC7180_MASTER_QUP_CORE_1 27 -#define SC7180_MASTER_CAMNOC_HF0 28 -#define SC7180_MASTER_CAMNOC_HF1 29 -#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30 -#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31 -#define SC7180_MASTER_CAMNOC_SF 32 -#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33 -#define SC7180_MASTER_CRYPTO 34 -#define SC7180_MASTER_GFX3D 35 -#define SC7180_MASTER_IPA 36 -#define SC7180_MASTER_MDP0 37 -#define SC7180_MASTER_NPU_PROC 38 -#define SC7180_MASTER_PIMEM 39 -#define SC7180_MASTER_ROTATOR 40 -#define SC7180_MASTER_VIDEO_P0 41 -#define SC7180_MASTER_VIDEO_PROC 42 -#define SC7180_MASTER_QDSS_DAP 43 -#define SC7180_MASTER_QDSS_ETR 44 -#define SC7180_MASTER_SDCC_2 45 -#define SC7180_MASTER_UFS_MEM 46 -#define SC7180_MASTER_USB3 47 -#define SC7180_MASTER_EMMC 48 -#define SC7180_SLAVE_EBI1 49 -/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC7180_SLAVE_A1NOC_CFG 51 -#define SC7180_SLAVE_A2NOC_CFG 52 -#define SC7180_SLAVE_AHB2PHY_SOUTH 53 -#define SC7180_SLAVE_AHB2PHY_CENTER 54 -#define SC7180_SLAVE_AOP 55 -#define SC7180_SLAVE_AOSS 56 -#define SC7180_SLAVE_APPSS 57 -#define SC7180_SLAVE_BOOT_ROM 58 -#define SC7180_SLAVE_NPU_CAL_DP0 59 -#define SC7180_SLAVE_CAMERA_CFG 60 -#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61 -#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62 -#define SC7180_SLAVE_CLK_CTL 63 -#define SC7180_SLAVE_NPU_CP 64 -#define SC7180_SLAVE_RBCPR_CX_CFG 65 -#define SC7180_SLAVE_RBCPR_MX_CFG 66 -#define SC7180_SLAVE_CRYPTO_0_CFG 67 -#define SC7180_SLAVE_DCC_CFG 68 -#define SC7180_SLAVE_CNOC_DDRSS 69 -#define SC7180_SLAVE_DISPLAY_CFG 70 -#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71 -#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72 -#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73 -#define SC7180_SLAVE_NPU_DPM 74 -#define SC7180_SLAVE_EMMC_CFG 75 -#define SC7180_SLAVE_GEM_NOC_CFG 76 -#define SC7180_SLAVE_GLM 77 -#define SC7180_SLAVE_GFX3D_CFG 78 -#define SC7180_SLAVE_IMEM_CFG 79 -#define SC7180_SLAVE_IPA_CFG 80 -#define SC7180_SLAVE_ISENSE_CFG 81 -#define SC7180_SLAVE_LLCC_CFG 82 -#define SC7180_SLAVE_NPU_LLM_CFG 83 -#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84 -#define SC7180_SLAVE_CNOC_MNOC_CFG 85 -#define SC7180_SLAVE_CNOC_MSS 86 -#define SC7180_SLAVE_NPU_CFG 87 -#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88 -#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89 -#define SC7180_SLAVE_PDM 90 -#define SC7180_SLAVE_PIMEM_CFG 91 -#define SC7180_SLAVE_PRNG 92 -#define SC7180_SLAVE_QDSS_CFG 93 -#define SC7180_SLAVE_QM_CFG 94 -#define SC7180_SLAVE_QM_MPU_CFG 95 -#define SC7180_SLAVE_QSPI_0 96 -#define SC7180_SLAVE_QUP_0 97 -#define SC7180_SLAVE_QUP_1 98 -#define SC7180_SLAVE_SDCC_2 99 -#define SC7180_SLAVE_SECURITY 100 -#define SC7180_SLAVE_SNOC_CFG 101 -#define SC7180_SLAVE_NPU_TCM 102 -#define SC7180_SLAVE_TCSR 103 -#define SC7180_SLAVE_TLMM_WEST 104 -#define SC7180_SLAVE_TLMM_NORTH 105 -#define SC7180_SLAVE_TLMM_SOUTH 106 -#define SC7180_SLAVE_UFS_MEM_CFG 107 -#define SC7180_SLAVE_USB3 108 -#define SC7180_SLAVE_VENUS_CFG 109 -#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110 -#define SC7180_SLAVE_VSENSE_CTRL_CFG 111 -#define SC7180_SLAVE_A1NOC_SNOC 112 -#define SC7180_SLAVE_A2NOC_SNOC 113 -#define SC7180_SLAVE_CAMNOC_UNCOMP 114 -#define SC7180_SLAVE_CDSP_GEM_NOC 115 -#define SC7180_SLAVE_SNOC_CNOC 116 -#define SC7180_SLAVE_GEM_NOC_SNOC 117 -#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118 -#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119 -#define SC7180_SLAVE_LLCC 120 -#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121 -#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122 -#define SC7180_SLAVE_NPU_COMPUTE_NOC 123 -#define SC7180_SLAVE_QUP_CORE_0 124 -#define SC7180_SLAVE_QUP_CORE_1 125 -#define SC7180_SLAVE_IMEM 126 -#define SC7180_SLAVE_PIMEM 127 -#define SC7180_SLAVE_SERVICE_A1NOC 128 -#define SC7180_SLAVE_SERVICE_A2NOC 129 -#define SC7180_SLAVE_SERVICE_CNOC 130 -#define SC7180_SLAVE_SERVICE_GEM_NOC 131 -#define SC7180_SLAVE_SERVICE_MNOC 132 -#define SC7180_SLAVE_SERVICE_NPU_NOC 133 -#define SC7180_SLAVE_SERVICE_SNOC 134 -#define SC7180_SLAVE_QDSS_STM 135 -#define SC7180_SLAVE_TCU 136 - -#endif From f6f8220797a0c8916d1000fe3fac940a13a4a88e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:29 +0200 Subject: [PATCH 148/304] interconnect: qcom: sdm670: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-13-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdm670.c | 530 ++++++++++++++--------------- drivers/interconnect/qcom/sdm670.h | 128 ------- 2 files changed, 262 insertions(+), 396 deletions(-) delete mode 100644 drivers/interconnect/qcom/sdm670.h diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index 907e1ff4ff81..5e6a5c54f485 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -13,1034 +13,1020 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm670.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SDM670_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SDM670_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SDM670_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SDM670_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SDM670_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SDM670_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SDM670_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SDM670_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDM670_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SDM670_MASTER_BLSP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SDM670_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDM670_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SDM670_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDM670_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SDM670_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SDM670_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SDM670_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SDM670_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SDM670_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SDM670_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 38, - .links = { SDM670_SLAVE_TLMM_SOUTH, - SDM670_SLAVE_CAMERA_CFG, - SDM670_SLAVE_SDCC_4, - SDM670_SLAVE_SDCC_2, - SDM670_SLAVE_CNOC_MNOC_CFG, - SDM670_SLAVE_UFS_MEM_CFG, - SDM670_SLAVE_GLM, - SDM670_SLAVE_PDM, - SDM670_SLAVE_A2NOC_CFG, - SDM670_SLAVE_QDSS_CFG, - SDM670_SLAVE_DISPLAY_CFG, - SDM670_SLAVE_TCSR, - SDM670_SLAVE_DCC_CFG, - SDM670_SLAVE_CNOC_DDRSS, - SDM670_SLAVE_SNOC_CFG, - SDM670_SLAVE_SOUTH_PHY_CFG, - SDM670_SLAVE_GRAPHICS_3D_CFG, - SDM670_SLAVE_VENUS_CFG, - SDM670_SLAVE_TSIF, - SDM670_SLAVE_CDSP_CFG, - SDM670_SLAVE_AOP, - SDM670_SLAVE_BLSP_2, - SDM670_SLAVE_SERVICE_CNOC, - SDM670_SLAVE_USB3, - SDM670_SLAVE_IPA_CFG, - SDM670_SLAVE_RBCPR_CX_CFG, - SDM670_SLAVE_A1NOC_CFG, - SDM670_SLAVE_AOSS, - SDM670_SLAVE_PRNG, - SDM670_SLAVE_VSENSE_CTRL_CFG, - SDM670_SLAVE_EMMC_CFG, - SDM670_SLAVE_BLSP_1, - SDM670_SLAVE_SPDM_WRAPPER, - SDM670_SLAVE_CRYPTO_0_CFG, - SDM670_SLAVE_PIMEM_CFG, - SDM670_SLAVE_TLMM_NORTH, - SDM670_SLAVE_CLK_CTL, - SDM670_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_south, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_aop, + &qhs_qupv3_north, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_qupv3_south, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_cnoc = { .name = "qhm_cnoc", - .id = SDM670_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM670_SLAVE_MEM_NOC_CFG, - SDM670_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_memnoc, + &qhs_llcc }, }; static struct qcom_icc_node acm_l3 = { .name = "acm_l3", - .id = SDM670_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDM670_SLAVE_SERVICE_GNOC, - SDM670_SLAVE_GNOC_SNOC, - SDM670_SLAVE_GNOC_MEM_NOC - }, + .link_nodes = { &srvc_gnoc, + &qns_gladiator_sodv, + &qns_gnoc_memnoc }, }; static struct qcom_icc_node pm_gnoc_cfg = { .name = "pm_gnoc_cfg", - .id = SDM670_MASTER_GNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_GNOC }, + .link_nodes = { &srvc_gnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDM670_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDM670_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_memnoc_cfg = { .name = "qhm_memnoc_cfg", - .id = SDM670_MASTER_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM670_SLAVE_SERVICE_MEM_NOC, - SDM670_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &srvc_memnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_apps = { .name = "qnm_apps", - .id = SDM670_MASTER_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SDM670_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SDM670_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDM670_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SDM670_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SDM670_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SDM670_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SDM670_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SDM670_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SDM670_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SDM670_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SDM670_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SDM670_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SDM670_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SDM670_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SDM670_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDM670_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SDM670_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_SF, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qns_memnoc_sf, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SDM670_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_SF, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_TCU, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qns_memnoc_sf, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gladiator_sodv = { .name = "qnm_gladiator_sodv", - .id = SDM670_MASTER_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_TCU, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDM670_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_imem, + &qhs_apss, + &qxs_pimem, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SDM670_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_GC - }, + .link_nodes = { &qxs_imem, + &qns_memnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SDM670_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_GC - }, + .link_nodes = { &qxs_imem, + &qns_memnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SDM670_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SDM670_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SDM670_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SDM670_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SDM670_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SDM670_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SDM670_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SDM670_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDM670_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SDM670_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDM670_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp_cfg = { .name = "qhs_compute_dsp_cfg", - .id = SDM670_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SDM670_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDM670_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SDM670_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc }, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDM670_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SDM670_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SDM670_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SDM670_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SDM670_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDM670_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDM670_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SDM670_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDM670_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_phy_refgen_south = { .name = "qhs_phy_refgen_south", - .id = SDM670_SLAVE_SOUTH_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SDM670_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDM670_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDM670_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SDM670_SLAVE_BLSP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_south = { .name = "qhs_qupv3_south", - .id = SDM670_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SDM670_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SDM670_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDM670_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SDM670_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDM670_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SDM670_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SDM670_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SDM670_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SDM670_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SDM670_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SDM670_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SDM670_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SDM670_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SDM670_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SDM670_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SDM670_SLAVE_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_MEM_NOC_CFG }, + .link_nodes = { &qhm_memnoc_cfg }, }; static struct qcom_icc_node qns_gladiator_sodv = { .name = "qns_gladiator_sodv", - .id = SDM670_SLAVE_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_GNOC_SNOC }, + .link_nodes = { &qnm_gladiator_sodv }, }; static struct qcom_icc_node qns_gnoc_memnoc = { .name = "qns_gnoc_memnoc", - .id = SDM670_SLAVE_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_MASTER_GNOC_MEM_NOC }, + .link_nodes = { &qnm_apps }, }; static struct qcom_icc_node srvc_gnoc = { .name = "srvc_gnoc", - .id = SDM670_SLAVE_SERVICE_GNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDM670_SLAVE_EBI_CH0, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_apps_io = { .name = "qns_apps_io", - .id = SDM670_SLAVE_MEM_NOC_GNOC, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDM670_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDM670_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node srvc_memnoc = { .name = "srvc_memnoc", - .id = SDM670_SLAVE_SERVICE_MEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SDM670_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SDM670_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SDM670_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDM670_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SDM670_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_memnoc_gc = { .name = "qns_memnoc_gc", - .id = SDM670_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_memnoc_sf = { .name = "qns_memnoc_sf", - .id = SDM670_SLAVE_SNOC_MEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDM670_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SDM670_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDM670_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDM670_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDM670_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1280,6 +1266,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1306,6 +1293,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1361,6 +1349,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1377,6 +1366,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1395,6 +1385,7 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_gladiator_noc = { + .alloc_dyn_id = true, .nodes = gladiator_noc_nodes, .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), .bcms = gladiator_noc_bcms, @@ -1430,6 +1421,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_mem_noc = { + .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -1460,6 +1452,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1504,6 +1497,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm670.h b/drivers/interconnect/qcom/sdm670.h deleted file mode 100644 index 14155f244c43..000000000000 --- a/drivers/interconnect/qcom/sdm670.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SDM670 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H -#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H - -#define SDM670_MASTER_A1NOC_CFG 0 -#define SDM670_MASTER_A1NOC_SNOC 1 -#define SDM670_MASTER_A2NOC_CFG 2 -#define SDM670_MASTER_A2NOC_SNOC 3 -#define SDM670_MASTER_AMPSS_M0 4 -#define SDM670_MASTER_BLSP_1 5 -#define SDM670_MASTER_BLSP_2 6 -#define SDM670_MASTER_CAMNOC_HF0 7 -#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SDM670_MASTER_CAMNOC_HF1 9 -#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SDM670_MASTER_CAMNOC_SF 11 -#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12 -#define SDM670_MASTER_CNOC_A2NOC 13 -#define SDM670_MASTER_CNOC_DC_NOC 14 -#define SDM670_MASTER_CNOC_MNOC_CFG 15 -#define SDM670_MASTER_CRYPTO_CORE_0 16 -#define SDM670_MASTER_EMMC 17 -#define SDM670_MASTER_GIC 18 -#define SDM670_MASTER_GNOC_CFG 19 -#define SDM670_MASTER_GNOC_MEM_NOC 20 -#define SDM670_MASTER_GNOC_SNOC 21 -#define SDM670_MASTER_GRAPHICS_3D 22 -#define SDM670_MASTER_IPA 23 -#define SDM670_MASTER_LLCC 24 -#define SDM670_MASTER_MDP_PORT0 25 -#define SDM670_MASTER_MDP_PORT1 26 -#define SDM670_MASTER_MEM_NOC_CFG 27 -#define SDM670_MASTER_MEM_NOC_SNOC 28 -#define SDM670_MASTER_MNOC_HF_MEM_NOC 29 -#define SDM670_MASTER_MNOC_SF_MEM_NOC 30 -#define SDM670_MASTER_PIMEM 31 -#define SDM670_MASTER_QDSS_BAM 32 -#define SDM670_MASTER_QDSS_ETR 33 -#define SDM670_MASTER_ROTATOR 34 -#define SDM670_MASTER_SDCC_2 35 -#define SDM670_MASTER_SDCC_4 36 -#define SDM670_MASTER_SNOC_CFG 37 -#define SDM670_MASTER_SNOC_CNOC 38 -#define SDM670_MASTER_SNOC_GC_MEM_NOC 39 -#define SDM670_MASTER_SNOC_SF_MEM_NOC 40 -#define SDM670_MASTER_SPDM 41 -#define SDM670_MASTER_TCU_0 42 -#define SDM670_MASTER_TSIF 43 -#define SDM670_MASTER_UFS_MEM 44 -#define SDM670_MASTER_USB3 45 -#define SDM670_MASTER_VIDEO_P0 46 -#define SDM670_MASTER_VIDEO_P1 47 -#define SDM670_MASTER_VIDEO_PROC 48 -#define SDM670_SLAVE_A1NOC_CFG 49 -#define SDM670_SLAVE_A1NOC_SNOC 50 -#define SDM670_SLAVE_A2NOC_CFG 51 -#define SDM670_SLAVE_A2NOC_SNOC 52 -#define SDM670_SLAVE_AOP 53 -#define SDM670_SLAVE_AOSS 54 -#define SDM670_SLAVE_APPSS 55 -#define SDM670_SLAVE_BLSP_1 56 -#define SDM670_SLAVE_BLSP_2 57 -#define SDM670_SLAVE_CAMERA_CFG 58 -#define SDM670_SLAVE_CAMNOC_UNCOMP 59 -#define SDM670_SLAVE_CDSP_CFG 60 -#define SDM670_SLAVE_CLK_CTL 61 -#define SDM670_SLAVE_CNOC_A2NOC 62 -#define SDM670_SLAVE_CNOC_DDRSS 63 -#define SDM670_SLAVE_CNOC_MNOC_CFG 64 -#define SDM670_SLAVE_CRYPTO_0_CFG 65 -#define SDM670_SLAVE_DCC_CFG 66 -#define SDM670_SLAVE_DISPLAY_CFG 67 -#define SDM670_SLAVE_EBI_CH0 68 -#define SDM670_SLAVE_EMMC_CFG 69 -#define SDM670_SLAVE_GLM 70 -#define SDM670_SLAVE_GNOC_MEM_NOC 71 -#define SDM670_SLAVE_GNOC_SNOC 72 -#define SDM670_SLAVE_GRAPHICS_3D_CFG 73 -#define SDM670_SLAVE_IMEM_CFG 74 -#define SDM670_SLAVE_IPA_CFG 75 -#define SDM670_SLAVE_LLCC 76 -#define SDM670_SLAVE_LLCC_CFG 77 -#define SDM670_SLAVE_MEM_NOC_CFG 78 -#define SDM670_SLAVE_MEM_NOC_GNOC 79 -#define SDM670_SLAVE_MEM_NOC_SNOC 80 -#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81 -#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82 -#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83 -#define SDM670_SLAVE_OCIMEM 84 -#define SDM670_SLAVE_PDM 85 -#define SDM670_SLAVE_PIMEM 86 -#define SDM670_SLAVE_PIMEM_CFG 87 -#define SDM670_SLAVE_PRNG 88 -#define SDM670_SLAVE_QDSS_CFG 89 -#define SDM670_SLAVE_QDSS_STM 90 -#define SDM670_SLAVE_RBCPR_CX_CFG 91 -#define SDM670_SLAVE_SDCC_2 92 -#define SDM670_SLAVE_SDCC_4 93 -#define SDM670_SLAVE_SERVICE_A1NOC 94 -#define SDM670_SLAVE_SERVICE_A2NOC 95 -#define SDM670_SLAVE_SERVICE_CNOC 96 -#define SDM670_SLAVE_SERVICE_GNOC 97 -#define SDM670_SLAVE_SERVICE_MEM_NOC 98 -#define SDM670_SLAVE_SERVICE_MNOC 99 -#define SDM670_SLAVE_SERVICE_SNOC 100 -#define SDM670_SLAVE_SNOC_CFG 101 -#define SDM670_SLAVE_SNOC_CNOC 102 -#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103 -#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104 -#define SDM670_SLAVE_SOUTH_PHY_CFG 105 -#define SDM670_SLAVE_SPDM_WRAPPER 106 -#define SDM670_SLAVE_TCSR 107 -#define SDM670_SLAVE_TCU 108 -#define SDM670_SLAVE_TLMM_NORTH 109 -#define SDM670_SLAVE_TLMM_SOUTH 110 -#define SDM670_SLAVE_TSIF 111 -#define SDM670_SLAVE_UFS_MEM_CFG 112 -#define SDM670_SLAVE_USB3 113 -#define SDM670_SLAVE_VENUS_CFG 114 -#define SDM670_SLAVE_VSENSE_CTRL_CFG 115 - -#endif From aa270959aacf6eff05a6c50c9d4506dd1ec3a0d0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:30 +0200 Subject: [PATCH 149/304] interconnect: qcom: sdx55: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-14-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdx55.c | 492 +++++++++++++++--------------- drivers/interconnect/qcom/sdx55.h | 70 ----- 2 files changed, 242 insertions(+), 320 deletions(-) delete mode 100644 drivers/interconnect/qcom/sdx55.h diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 4117db046fa0..b1a69e430ef4 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -17,628 +17,617 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx55.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDX55_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDX55_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDX55_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_apps_rdwr = { .name = "xm_apps_rdwr", - .id = SDX55_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", - .id = SDX55_MASTER_AUDIO, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_blsp1 = { .name = "qhm_blsp1", - .id = SDX55_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDX55_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 28, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = SDX55_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 5, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes = { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDX55_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qhm_spmi_fetcher1 = { .name = "qhm_spmi_fetcher1", - .id = SDX55_MASTER_SPMI_FETCHER, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = SDX55_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 30, - .links = { SDX55_SLAVE_PCIE_0, - SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_USB3, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &xs_pcie, + &qhs_snoc_cfg, + &qhs_sdc1, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_usb3, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qnm_ipa = { .name = "qnm_ipa", - .id = SDX55_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 27, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_tlmm, + &qhs_prng, + &qhs_crypto0_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDX55_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 29, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qnm_memnoc_pcie = { .name = "qnm_memnoc_pcie", - .id = SDX55_MASTER_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDX55_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop }, }; static struct qcom_icc_node xm_emac = { .name = "xm_emac", - .id = SDX55_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node xm_ipa2pcie_slv = { .name = "xm_ipa2pcie_slv", - .id = SDX55_MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = SDX55_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDX55_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 28, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SDX55_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes = { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = SDX55_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDX55_SLAVE_EBI_CH0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDX55_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX55_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDX55_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_memnoc_pcie }, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SDX55_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDX55_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDX55_SLAVE_APPSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", - .id = SDX55_SLAVE_AUDIO, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_blsp1 = { .name = "qhs_blsp1", - .id = SDX55_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDX55_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDX55_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDX55_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ecc_cfg = { .name = "qhs_ecc_cfg", - .id = SDX55_SLAVE_ECC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac_cfg = { .name = "qhs_emac_cfg", - .id = SDX55_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDX55_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDX55_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SDX55_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_parf = { .name = "qhs_pcie_parf", - .id = SDX55_SLAVE_PCIE_PARF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDX55_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDX55_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDX55_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = SDX55_SLAVE_QPIC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SDX55_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDX55_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spmi_fetcher = { .name = "qhs_spmi_fetcher", - .id = SDX55_SLAVE_SPMI_FETCHER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", - .id = SDX55_SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDX55_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SDX55_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SDX55_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", - .id = SDX55_SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_aggre_noc = { .name = "qns_aggre_noc", - .id = SDX55_SLAVE_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_snoc_memnoc = { .name = "qns_snoc_memnoc", - .id = SDX55_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDX55_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDX55_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = SDX55_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDX55_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDX55_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -793,6 +782,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sdx55_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -815,6 +805,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdx55_mem_noc = { + .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -894,6 +885,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdx55_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx55.h b/drivers/interconnect/qcom/sdx55.h deleted file mode 100644 index 46cbabec8aa1..000000000000 --- a/drivers/interconnect/qcom/sdx55.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H - -/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SDX55_MASTER_LLCC 1 -#define SDX55_MASTER_TCU_0 2 -#define SDX55_MASTER_SNOC_GC_MEM_NOC 3 -#define SDX55_MASTER_AMPSS_M0 4 -#define SDX55_MASTER_AUDIO 5 -#define SDX55_MASTER_BLSP_1 6 -#define SDX55_MASTER_QDSS_BAM 7 -#define SDX55_MASTER_QPIC 8 -#define SDX55_MASTER_SNOC_CFG 9 -#define SDX55_MASTER_SPMI_FETCHER 10 -#define SDX55_MASTER_ANOC_SNOC 11 -#define SDX55_MASTER_IPA 12 -#define SDX55_MASTER_MEM_NOC_SNOC 13 -#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14 -#define SDX55_MASTER_CRYPTO_CORE_0 15 -#define SDX55_MASTER_EMAC 16 -#define SDX55_MASTER_IPA_PCIE 17 -#define SDX55_MASTER_PCIE 18 -#define SDX55_MASTER_QDSS_ETR 19 -#define SDX55_MASTER_SDCC_1 20 -#define SDX55_MASTER_USB3 21 -/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SDX55_SLAVE_EBI_CH0 23 -#define SDX55_SLAVE_LLCC 24 -#define SDX55_SLAVE_MEM_NOC_SNOC 25 -#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26 -#define SDX55_SLAVE_ANOC_SNOC 27 -#define SDX55_SLAVE_SNOC_CFG 28 -#define SDX55_SLAVE_EMAC_CFG 29 -#define SDX55_SLAVE_USB3 30 -#define SDX55_SLAVE_TLMM 31 -#define SDX55_SLAVE_SPMI_FETCHER 32 -#define SDX55_SLAVE_QDSS_CFG 33 -#define SDX55_SLAVE_PDM 34 -#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35 -#define SDX55_SLAVE_TCSR 36 -#define SDX55_SLAVE_CNOC_DDRSS 37 -#define SDX55_SLAVE_SPMI_VGI_COEX 38 -#define SDX55_SLAVE_QPIC 39 -#define SDX55_SLAVE_OCIMEM 40 -#define SDX55_SLAVE_IPA_CFG 41 -#define SDX55_SLAVE_USB3_PHY_CFG 42 -#define SDX55_SLAVE_AOP 43 -#define SDX55_SLAVE_BLSP_1 44 -#define SDX55_SLAVE_SDCC_1 45 -#define SDX55_SLAVE_CNOC_MSS 46 -#define SDX55_SLAVE_PCIE_PARF 47 -#define SDX55_SLAVE_ECC_CFG 48 -#define SDX55_SLAVE_AUDIO 49 -#define SDX55_SLAVE_AOSS 51 -#define SDX55_SLAVE_PRNG 52 -#define SDX55_SLAVE_CRYPTO_0_CFG 53 -#define SDX55_SLAVE_TCU 54 -#define SDX55_SLAVE_CLK_CTL 55 -#define SDX55_SLAVE_IMEM_CFG 56 -#define SDX55_SLAVE_SERVICE_SNOC 57 -#define SDX55_SLAVE_PCIE_0 58 -#define SDX55_SLAVE_QDSS_STM 59 -#define SDX55_SLAVE_APPSS 60 - -#endif From 049aac02ea4ada336800eede6f34069cc8bead7f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:31 +0200 Subject: [PATCH 150/304] interconnect: qcom: sdx65: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-15-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdx65.c | 460 +++++++++++++++--------------- drivers/interconnect/qcom/sdx65.h | 65 ----- 2 files changed, 226 insertions(+), 299 deletions(-) delete mode 100644 drivers/interconnect/qcom/sdx65.h diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index d3a6c6c148e5..7c8798174e02 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -13,593 +13,582 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx65.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDX65_MASTER_LLCC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDX65_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDX65_SLAVE_LLCC, - SDX65_SLAVE_MEM_NOC_SNOC, - SDX65_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDX65_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX65_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_apps_rdwr = { .name = "xm_apps_rdwr", - .id = SDX65_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX65_SLAVE_LLCC, - SDX65_SLAVE_MEM_NOC_SNOC, - SDX65_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", - .id = SDX65_MASTER_AUDIO, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_blsp1 = { .name = "qhm_blsp1", - .id = SDX65_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDX65_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 26, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = SDX65_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 4, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_ipa, + &qns_aggre_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDX65_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qhm_spmi_fetcher1 = { .name = "qhm_spmi_fetcher1", - .id = SDX65_MASTER_SPMI_FETCHER, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = SDX65_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 29, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_APPSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_PCIE_0, - SDX65_SLAVE_QDSS_STM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_pcie, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_ipa = { .name = "qnm_ipa", - .id = SDX65_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 26, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_PCIE_0, - SDX65_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_pcie, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDX65_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 27, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_APPSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_QDSS_STM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qxs_imem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_memnoc_pcie = { .name = "qnm_memnoc_pcie", - .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDX65_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc }, }; static struct qcom_icc_node xm_ipa2pcie_slv = { .name = "xm_ipa2pcie_slv", - .id = SDX65_MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = SDX65_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDX65_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 26, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SDX65_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_ipa, + &qns_aggre_noc }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = SDX65_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDX65_SLAVE_EBI1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDX65_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX65_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDX65_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_memnoc_pcie }, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDX65_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDX65_SLAVE_APPSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", - .id = SDX65_SLAVE_AUDIO, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_blsp1 = { .name = "qhs_blsp1", - .id = SDX65_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDX65_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDX65_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDX65_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ecc_cfg = { .name = "qhs_ecc_cfg", - .id = SDX65_SLAVE_ECC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDX65_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDX65_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SDX65_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_parf = { .name = "qhs_pcie_parf", - .id = SDX65_SLAVE_PCIE_PARF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDX65_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDX65_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDX65_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = SDX65_SLAVE_QPIC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SDX65_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDX65_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spmi_fetcher = { .name = "qhs_spmi_fetcher", - .id = SDX65_SLAVE_SPMI_FETCHER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", - .id = SDX65_SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDX65_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SDX65_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SDX65_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", - .id = SDX65_SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_aggre_noc = { .name = "qns_aggre_noc", - .id = SDX65_SLAVE_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_snoc_memnoc = { .name = "qns_snoc_memnoc", - .id = SDX65_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX65_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDX65_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDX65_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = SDX65_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDX65_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDX65_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -780,6 +769,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sdx65_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -802,6 +792,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdx65_mem_noc = { + .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -878,6 +869,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdx65_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx65.h b/drivers/interconnect/qcom/sdx65.h deleted file mode 100644 index 5dca6e8b32c9..000000000000 --- a/drivers/interconnect/qcom/sdx65.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H - -#define SDX65_MASTER_TCU_0 0 -#define SDX65_MASTER_LLCC 1 -#define SDX65_MASTER_AUDIO 2 -#define SDX65_MASTER_BLSP_1 3 -#define SDX65_MASTER_QDSS_BAM 4 -#define SDX65_MASTER_QPIC 5 -#define SDX65_MASTER_SNOC_CFG 6 -#define SDX65_MASTER_SPMI_FETCHER 7 -#define SDX65_MASTER_ANOC_SNOC 8 -#define SDX65_MASTER_IPA 9 -#define SDX65_MASTER_MEM_NOC_SNOC 10 -#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11 -#define SDX65_MASTER_SNOC_GC_MEM_NOC 12 -#define SDX65_MASTER_CRYPTO 13 -#define SDX65_MASTER_APPSS_PROC 14 -#define SDX65_MASTER_IPA_PCIE 15 -#define SDX65_MASTER_PCIE_0 16 -#define SDX65_MASTER_QDSS_ETR 17 -#define SDX65_MASTER_SDCC_1 18 -#define SDX65_MASTER_USB3 19 -#define SDX65_SLAVE_EBI1 512 -#define SDX65_SLAVE_AOSS 513 -#define SDX65_SLAVE_APPSS 514 -#define SDX65_SLAVE_AUDIO 515 -#define SDX65_SLAVE_BLSP_1 516 -#define SDX65_SLAVE_CLK_CTL 517 -#define SDX65_SLAVE_CRYPTO_0_CFG 518 -#define SDX65_SLAVE_CNOC_DDRSS 519 -#define SDX65_SLAVE_ECC_CFG 520 -#define SDX65_SLAVE_IMEM_CFG 521 -#define SDX65_SLAVE_IPA_CFG 522 -#define SDX65_SLAVE_CNOC_MSS 523 -#define SDX65_SLAVE_PCIE_PARF 524 -#define SDX65_SLAVE_PDM 525 -#define SDX65_SLAVE_PRNG 526 -#define SDX65_SLAVE_QDSS_CFG 527 -#define SDX65_SLAVE_QPIC 528 -#define SDX65_SLAVE_SDCC_1 529 -#define SDX65_SLAVE_SNOC_CFG 530 -#define SDX65_SLAVE_SPMI_FETCHER 531 -#define SDX65_SLAVE_SPMI_VGI_COEX 532 -#define SDX65_SLAVE_TCSR 533 -#define SDX65_SLAVE_TLMM 534 -#define SDX65_SLAVE_USB3 535 -#define SDX65_SLAVE_USB3_PHY_CFG 536 -#define SDX65_SLAVE_ANOC_SNOC 537 -#define SDX65_SLAVE_LLCC 538 -#define SDX65_SLAVE_MEM_NOC_SNOC 539 -#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540 -#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541 -#define SDX65_SLAVE_IMEM 542 -#define SDX65_SLAVE_SERVICE_SNOC 543 -#define SDX65_SLAVE_PCIE_0 544 -#define SDX65_SLAVE_QDSS_STM 545 -#define SDX65_SLAVE_TCU 546 - -#endif From 98e4284d2eaf44f0db12943aed0c2a7f021aab1e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:32 +0200 Subject: [PATCH 151/304] interconnect: qcom: sdx75: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-16-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdx75.c | 384 ++++++++++++++---------------- drivers/interconnect/qcom/sdx75.h | 97 -------- 2 files changed, 174 insertions(+), 307 deletions(-) delete mode 100644 drivers/interconnect/qcom/sdx75.h diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c index 7ef1f17f3292..3721d8f503a0 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -14,782 +14,740 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sdx75.h" + +static struct qcom_icc_node qpic_core_master; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_ipa2pcie; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_pcie_rscc; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_system_noc_cfg; +static struct qcom_icc_node qnm_system_noc_pcie_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_mvmss; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qpic_core_slave; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qhs_lagg; +static struct qcom_icc_node qhs_mccc_master; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qss_snoop_bwmon; +static struct qcom_icc_node qns_gemnoc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node ps_eth0_cfg; +static struct qcom_icc_node ps_eth1_cfg; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mvmss_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_a1noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_system_noc_cfg; +static struct qcom_icc_node qns_system_noc_pcie_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_pcie_system_noc; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qpic_core_master = { .name = "qpic_core_master", - .id = SDX75_MASTER_QPIC_CORE, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_QPIC_CORE }, + .link_nodes = { &qpic_core_slave }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SDX75_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SDX75_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 4, - .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER, - SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON }, + .link_nodes = { &qhs_lagg, &qhs_mccc_master, + &qns_gemnoc, &qss_snoop_bwmon }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SDX75_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SDX75_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SDX75_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SERVICE_GEM_NOC }, + .link_nodes = { &srvc_gemnoc }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SDX75_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SDX75_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SDX75_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_ipa2pcie = { .name = "xm_ipa2pcie", - .id = SDX75_MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_pcie }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDX75_MASTER_LLCC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SDX75_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SDX75_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_pcie3_2 = { .name = "xm_pcie3_2", - .id = SDX75_MASTER_PCIE_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", - .id = SDX75_MASTER_AUDIO, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SDX75_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_pcie_rscc = { .name = "qhm_pcie_rscc", - .id = SDX75_MASTER_PCIE_RSCC, .channels = 1, .buswidth = 4, .num_links = 31, - .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM, - SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG, - SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0, - SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4, - SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR, - SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3, - SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG, - SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG, - SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM, - SDX75_SLAVE_TCU }, + .link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pdm, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc1, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_usb3, + &qhs_usb3_phy, &qns_ddrss_cfg, + &qns_system_noc_cfg, &qns_system_noc_pcie_cfg, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDX75_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = SDX75_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SDX75_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = SDX75_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SDX75_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 32, - .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG, - SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG, - SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC, - SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1, - SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX, - SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM, - SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG, - SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG, - SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM, - SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU }, + .link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc1, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_usb3, &qhs_usb3_phy, + &qns_ddrss_cfg, &qns_system_noc_cfg, + &qns_system_noc_pcie_cfg, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1, - SDX75_SLAVE_PCIE_2 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2 }, }; static struct qcom_icc_node qnm_system_noc_cfg = { .name = "qnm_system_noc_cfg", - .id = SDX75_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_system_noc }, }; static struct qcom_icc_node qnm_system_noc_pcie_cfg = { .name = "qnm_system_noc_pcie_cfg", - .id = SDX75_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_system_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDX75_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SDX75_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qxm_mvmss = { .name = "qxm_mvmss", - .id = SDX75_MASTER_MVMSS, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", - .id = SDX75_MASTER_EMAC_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", - .id = SDX75_MASTER_EMAC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_qdss_etr0 = { .name = "xm_qdss_etr0", - .id = SDX75_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_qdss_etr1 = { .name = "xm_qdss_etr1", - .id = SDX75_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SDX75_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SDX75_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = SDX75_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qpic_core_slave = { .name = "qpic_core_slave", - .id = SDX75_SLAVE_QPIC_CORE, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SDX75_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lagg = { .name = "qhs_lagg", - .id = SDX75_SLAVE_LAGG_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mccc_master = { .name = "qhs_mccc_master", - .id = SDX75_SLAVE_MCCC_MASTER, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SDX75_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_snoop_bwmon = { .name = "qss_snoop_bwmon", - .id = SDX75_SLAVE_SNOOP_BWMON, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_cnoc = { .name = "qns_gemnoc_cnoc", - .id = SDX75_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDX75_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SDX75_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDX75_SLAVE_EBI1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", - .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node ps_eth0_cfg = { .name = "ps_eth0_cfg", - .id = SDX75_SLAVE_ETH0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ps_eth1_cfg = { .name = "ps_eth1_cfg", - .id = SDX75_SLAVE_ETH1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", - .id = SDX75_SLAVE_AUDIO, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDX75_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto_cfg = { .name = "qhs_crypto_cfg", - .id = SDX75_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDX75_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDX75_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SDX75_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SDX75_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mvmss_cfg = { .name = "qhs_mvmss_cfg", - .id = SDX75_SLAVE_ICBDI_MVMSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SDX75_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SDX75_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie2_cfg = { .name = "qhs_pcie2_cfg", - .id = SDX75_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rscc = { .name = "qhs_pcie_rscc", - .id = SDX75_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDX75_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDX75_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDX75_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = SDX75_SLAVE_QPIC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SDX75_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SDX75_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SDX75_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", - .id = SDX75_SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDX75_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SDX75_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SDX75_SLAVE_USB3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", - .id = SDX75_SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1noc = { .name = "qns_a1noc", - .id = SDX75_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SDX75_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SDX75_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_system_noc_cfg = { .name = "qns_system_noc_cfg", - .id = SDX75_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_system_noc_cfg }, }; static struct qcom_icc_node qns_system_noc_pcie_cfg = { .name = "qns_system_noc_pcie_cfg", - .id = SDX75_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qnm_system_noc_pcie_cfg }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDX75_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_pcie_system_noc = { .name = "srvc_pcie_system_noc", - .id = SDX75_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_system_noc = { .name = "srvc_system_noc", - .id = SDX75_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SDX75_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SDX75_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_2 = { .name = "xs_pcie_2", - .id = SDX75_SLAVE_PCIE_2, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDX75_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDX75_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_bcm bcm_ce0 = { @@ -910,6 +868,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sdx75_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -925,6 +884,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sdx75_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -951,6 +911,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sdx75_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -967,6 +928,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sdx75_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -986,6 +948,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sdx75_pcie_anoc = { + .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1064,6 +1027,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdx75_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h deleted file mode 100644 index 24e887159920..000000000000 --- a/drivers/interconnect/qcom/sdx75.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H - -#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0 -#define SDX75_MASTER_ANOC_SNOC 1 -#define SDX75_MASTER_APPSS_PROC 2 -#define SDX75_MASTER_AUDIO 3 -#define SDX75_MASTER_CNOC_DC_NOC 4 -#define SDX75_MASTER_CRYPTO 5 -#define SDX75_MASTER_EMAC_0 6 -#define SDX75_MASTER_EMAC_1 7 -#define SDX75_MASTER_GEM_NOC_CFG 8 -#define SDX75_MASTER_GEM_NOC_CNOC 9 -#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10 -#define SDX75_MASTER_GIC 11 -#define SDX75_MASTER_GIC_AHB 12 -#define SDX75_MASTER_IPA 13 -#define SDX75_MASTER_IPA_PCIE 14 -#define SDX75_MASTER_LLCC 15 -#define SDX75_MASTER_MSS_PROC 16 -#define SDX75_MASTER_MVMSS 17 -#define SDX75_MASTER_PCIE_0 18 -#define SDX75_MASTER_PCIE_1 19 -#define SDX75_MASTER_PCIE_2 20 -#define SDX75_MASTER_PCIE_ANOC_CFG 21 -#define SDX75_MASTER_PCIE_RSCC 22 -#define SDX75_MASTER_QDSS_BAM 23 -#define SDX75_MASTER_QDSS_ETR 24 -#define SDX75_MASTER_QDSS_ETR_1 25 -#define SDX75_MASTER_QPIC 26 -#define SDX75_MASTER_QPIC_CORE 27 -#define SDX75_MASTER_QUP_0 28 -#define SDX75_MASTER_QUP_CORE_0 29 -#define SDX75_MASTER_SDCC_1 30 -#define SDX75_MASTER_SDCC_4 31 -#define SDX75_MASTER_SNOC_CFG 32 -#define SDX75_MASTER_SNOC_SF_MEM_NOC 33 -#define SDX75_MASTER_SYS_TCU 34 -#define SDX75_MASTER_USB3_0 35 -#define SDX75_SLAVE_A1NOC_CFG 36 -#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37 -#define SDX75_SLAVE_AUDIO 38 -#define SDX75_SLAVE_CLK_CTL 39 -#define SDX75_SLAVE_CRYPTO_0_CFG 40 -#define SDX75_SLAVE_CNOC_MSS 41 -#define SDX75_SLAVE_DDRSS_CFG 42 -#define SDX75_SLAVE_EBI1 43 -#define SDX75_SLAVE_ETH0_CFG 44 -#define SDX75_SLAVE_ETH1_CFG 45 -#define SDX75_SLAVE_GEM_NOC_CFG 46 -#define SDX75_SLAVE_GEM_NOC_CNOC 47 -#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48 -#define SDX75_SLAVE_IMEM 49 -#define SDX75_SLAVE_IMEM_CFG 50 -#define SDX75_SLAVE_IPA_CFG 51 -#define SDX75_SLAVE_IPC_ROUTER_CFG 52 -#define SDX75_SLAVE_LAGG_CFG 53 -#define SDX75_SLAVE_LLCC 54 -#define SDX75_SLAVE_MCCC_MASTER 55 -#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56 -#define SDX75_SLAVE_PCIE_0 57 -#define SDX75_SLAVE_PCIE_1 58 -#define SDX75_SLAVE_PCIE_2 59 -#define SDX75_SLAVE_PCIE_0_CFG 60 -#define SDX75_SLAVE_PCIE_1_CFG 61 -#define SDX75_SLAVE_PCIE_2_CFG 62 -#define SDX75_SLAVE_PCIE_ANOC_CFG 63 -#define SDX75_SLAVE_PCIE_RSC_CFG 64 -#define SDX75_SLAVE_PDM 65 -#define SDX75_SLAVE_PRNG 66 -#define SDX75_SLAVE_QDSS_CFG 67 -#define SDX75_SLAVE_QDSS_STM 68 -#define SDX75_SLAVE_QPIC 69 -#define SDX75_SLAVE_QPIC_CORE 70 -#define SDX75_SLAVE_QUP_0 71 -#define SDX75_SLAVE_QUP_CORE_0 72 -#define SDX75_SLAVE_SDCC_1 73 -#define SDX75_SLAVE_SDCC_4 74 -#define SDX75_SLAVE_SERVICE_GEM_NOC 75 -#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76 -#define SDX75_SLAVE_SERVICE_SNOC 77 -#define SDX75_SLAVE_SNOC_CFG 78 -#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79 -#define SDX75_SLAVE_SNOOP_BWMON 80 -#define SDX75_SLAVE_SPMI_VGI_COEX 81 -#define SDX75_SLAVE_TCSR 82 -#define SDX75_SLAVE_TCU 83 -#define SDX75_SLAVE_TLMM 84 -#define SDX75_SLAVE_USB3 85 -#define SDX75_SLAVE_USB3_PHY_CFG 86 - -#endif From 3d1a6b4c8c5346e6a304ca1d74687e1790bdde72 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:33 +0200 Subject: [PATCH 152/304] interconnect: qcom: sm6350: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-17-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm6350.c | 639 ++++++++++++++--------------- drivers/interconnect/qcom/sm6350.h | 139 ------- 2 files changed, 317 insertions(+), 461 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm6350.h diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index f41d7e19ba26..df2511dbfa96 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -13,1151 +13,1136 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm6350.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_icp_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SM6350_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup_0 = { .name = "qhm_qup_0", - .id = SM6350_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SM6350_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM6350_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM6350_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM6350_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup_1 = { .name = "qhm_qup_1", - .id = SM6350_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM6350_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM6350_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM6350_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM6350_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM6350_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SM6350_MASTER_CAMNOC_HF0_UNCOMP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_icp_uncomp = { .name = "qxm_camnoc_icp_uncomp", - .id = SM6350_MASTER_CAMNOC_ICP_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SM6350_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM6350_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM6350_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM6350_MASTER_NPU, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qxm_npu_dsp = { .name = "qxm_npu_dsp", - .id = SM6350_MASTER_NPU_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM6350_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 42, - .links = { SM6350_SLAVE_CAMERA_CFG, - SM6350_SLAVE_SDCC_2, - SM6350_SLAVE_CNOC_MNOC_CFG, - SM6350_SLAVE_UFS_MEM_CFG, - SM6350_SLAVE_QM_CFG, - SM6350_SLAVE_SNOC_CFG, - SM6350_SLAVE_QM_MPU_CFG, - SM6350_SLAVE_GLM, - SM6350_SLAVE_PDM, - SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM6350_SLAVE_A2NOC_CFG, - SM6350_SLAVE_QDSS_CFG, - SM6350_SLAVE_VSENSE_CTRL_CFG, - SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM6350_SLAVE_DISPLAY_CFG, - SM6350_SLAVE_TCSR, - SM6350_SLAVE_DCC_CFG, - SM6350_SLAVE_CNOC_DDRSS, - SM6350_SLAVE_DISPLAY_THROTTLE_CFG, - SM6350_SLAVE_NPU_CFG, - SM6350_SLAVE_AHB2PHY, - SM6350_SLAVE_GRAPHICS_3D_CFG, - SM6350_SLAVE_BOOT_ROM, - SM6350_SLAVE_VENUS_CFG, - SM6350_SLAVE_IPA_CFG, - SM6350_SLAVE_SECURITY, - SM6350_SLAVE_IMEM_CFG, - SM6350_SLAVE_CNOC_MSS, - SM6350_SLAVE_SERVICE_CNOC, - SM6350_SLAVE_USB3, - SM6350_SLAVE_VENUS_THROTTLE_CFG, - SM6350_SLAVE_RBCPR_CX_CFG, - SM6350_SLAVE_A1NOC_CFG, - SM6350_SLAVE_AOSS, - SM6350_SLAVE_PRNG, - SM6350_SLAVE_EMMC_CFG, - SM6350_SLAVE_CRYPTO_0_CFG, - SM6350_SLAVE_PIMEM_CFG, - SM6350_SLAVE_RBCPR_MX_CFG, - SM6350_SLAVE_QUP_0, - SM6350_SLAVE_QUP_1, - SM6350_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_camera_cfg, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qm_cfg, + &qhs_snoc_cfg, + &qhs_qm_mpu_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_throttle_cfg, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_gpuss_cfg, + &qhs_boot_rom, + &qhs_venus_cfg, + &qhs_ipa, + &qhs_security, + &qhs_imem_cfg, + &qhs_mss_cfg, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_emmc_cfg, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_clk_ctl }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM6350_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 42, - .links = { SM6350_SLAVE_CAMERA_CFG, - SM6350_SLAVE_SDCC_2, - SM6350_SLAVE_CNOC_MNOC_CFG, - SM6350_SLAVE_UFS_MEM_CFG, - SM6350_SLAVE_QM_CFG, - SM6350_SLAVE_SNOC_CFG, - SM6350_SLAVE_QM_MPU_CFG, - SM6350_SLAVE_GLM, - SM6350_SLAVE_PDM, - SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM6350_SLAVE_A2NOC_CFG, - SM6350_SLAVE_QDSS_CFG, - SM6350_SLAVE_VSENSE_CTRL_CFG, - SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM6350_SLAVE_DISPLAY_CFG, - SM6350_SLAVE_TCSR, - SM6350_SLAVE_DCC_CFG, - SM6350_SLAVE_CNOC_DDRSS, - SM6350_SLAVE_DISPLAY_THROTTLE_CFG, - SM6350_SLAVE_NPU_CFG, - SM6350_SLAVE_AHB2PHY, - SM6350_SLAVE_GRAPHICS_3D_CFG, - SM6350_SLAVE_BOOT_ROM, - SM6350_SLAVE_VENUS_CFG, - SM6350_SLAVE_IPA_CFG, - SM6350_SLAVE_SECURITY, - SM6350_SLAVE_IMEM_CFG, - SM6350_SLAVE_CNOC_MSS, - SM6350_SLAVE_SERVICE_CNOC, - SM6350_SLAVE_USB3, - SM6350_SLAVE_VENUS_THROTTLE_CFG, - SM6350_SLAVE_RBCPR_CX_CFG, - SM6350_SLAVE_A1NOC_CFG, - SM6350_SLAVE_AOSS, - SM6350_SLAVE_PRNG, - SM6350_SLAVE_EMMC_CFG, - SM6350_SLAVE_CRYPTO_0_CFG, - SM6350_SLAVE_PIMEM_CFG, - SM6350_SLAVE_RBCPR_MX_CFG, - SM6350_SLAVE_QUP_0, - SM6350_SLAVE_QUP_1, - SM6350_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_camera_cfg, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qm_cfg, + &qhs_snoc_cfg, + &qhs_qm_mpu_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_throttle_cfg, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_gpuss_cfg, + &qhs_boot_rom, + &qhs_venus_cfg, + &qhs_ipa, + &qhs_security, + &qhs_imem_cfg, + &qhs_mss_cfg, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_emmc_cfg, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_clk_ctl }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM6350_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM6350_SLAVE_LLCC_CFG, - SM6350_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qhs_gemnoc }, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = SM6350_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SM6350_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM6350_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SM6350_SLAVE_MCDMA_MS_MPU_CFG, - SM6350_SLAVE_SERVICE_GEM_NOC, - SM6350_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &qhs_mcdma_ms_mpu_cfg, + &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM6350_MASTER_COMPUTE_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM6350_MASTER_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM6350_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM6350_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM6350_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SM6350_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM6350_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM6350_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SM6350_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM6350_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", - .id = SM6350_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", - .id = SM6350_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SM6350_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM6350_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node amm_npu_sys = { .name = "amm_npu_sys", - .id = SM6350_MASTER_NPU_SYS, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node qhm_npu_cfg = { .name = "qhm_npu_cfg", - .id = SM6350_MASTER_NPU_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 8, - .links = { SM6350_SLAVE_SERVICE_NPU_NOC, - SM6350_SLAVE_ISENSE_CFG, - SM6350_SLAVE_NPU_LLM_CFG, - SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, - SM6350_SLAVE_NPU_CP, - SM6350_SLAVE_NPU_TCM, - SM6350_SLAVE_NPU_CAL_DP0, - SM6350_SLAVE_NPU_DPM - }, + .link_nodes = { &srvc_noc, + &qhs_isense, + &qhs_llm, + &qhs_dma_bwmon, + &qhs_cp, + &qhs_tcm, + &qhs_cal_dp0, + &qhs_dpm }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM6350_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM6350_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, - SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM6350_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, - SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_TCU, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM6350_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_TCU, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM6350_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC, - SM6350_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM6350_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM6350_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM6350_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM6350_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM6350_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SM6350_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM6350_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM6350_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cdsp_gemnoc = { .name = "qns_cdsp_gemnoc", - .id = SM6350_SLAVE_CDSP_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM6350_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM6350_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM6350_SLAVE_AHB2PHY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SM6350_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM6350_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", - .id = SM6350_SLAVE_BOOT_ROM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM6350_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { .name = "qhs_camera_nrt_thrott_cfg", - .id = SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM6350_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM6350_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM6350_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM6350_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SM6350_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM6350_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM6350_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_throttle_cfg = { .name = "qhs_display_throttle_cfg", - .id = SM6350_SLAVE_DISPLAY_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SM6350_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SM6350_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM6350_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM6350_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM6350_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM6350_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM6350_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SM6350_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_NPU_NOC_CFG }, + .link_nodes = { &qhm_npu_cfg }, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM6350_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM6350_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM6350_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM6350_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_cfg = { .name = "qhs_qm_cfg", - .id = SM6350_SLAVE_QM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_mpu_cfg = { .name = "qhs_qm_mpu_cfg", - .id = SM6350_SLAVE_QM_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM6350_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM6350_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM6350_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SM6350_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM6350_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM6350_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM6350_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM6350_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM6350_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_throttle_cfg = { .name = "qhs_venus_throttle_cfg", - .id = SM6350_SLAVE_VENUS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM6350_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM6350_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gemnoc = { .name = "qhs_gemnoc", - .id = SM6350_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM6350_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = { .name = "qhs_mcdma_ms_mpu_cfg", - .id = SM6350_SLAVE_MCDMA_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM6350_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM6350_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SM6350_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM6350_SLAVE_EBI_CH0, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM6350_SLAVE_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM6350_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM6350_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp0 = { .name = "qhs_cal_dp0", - .id = SM6350_SLAVE_NPU_CAL_DP0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cp = { .name = "qhs_cp", - .id = SM6350_SLAVE_NPU_CP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dma_bwmon = { .name = "qhs_dma_bwmon", - .id = SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dpm = { .name = "qhs_dpm", - .id = SM6350_SLAVE_NPU_DPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_isense = { .name = "qhs_isense", - .id = SM6350_SLAVE_ISENSE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llm = { .name = "qhs_llm", - .id = SM6350_SLAVE_NPU_LLM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcm = { .name = "qhs_tcm", - .id = SM6350_SLAVE_NPU_TCM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_npu_sys = { .name = "qns_npu_sys", - .id = SM6350_SLAVE_NPU_COMPUTE_NOC, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node srvc_noc = { .name = "srvc_noc", - .id = SM6350_SLAVE_SERVICE_NPU_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM6350_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM6350_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM6350_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM6350_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM6350_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM6350_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM6350_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM6350_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM6350_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1404,6 +1389,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1429,6 +1415,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1456,6 +1443,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm6350_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1475,6 +1463,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_compute_noc = { + .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1535,6 +1524,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1551,6 +1541,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1582,6 +1573,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1609,6 +1601,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1633,6 +1626,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_npu_noc = { + .alloc_dyn_id = true, .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), .bcms = npu_noc_bcms, @@ -1669,6 +1663,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm6350.h b/drivers/interconnect/qcom/sm6350.h deleted file mode 100644 index 43cf2930c88a..000000000000 --- a/drivers/interconnect/qcom/sm6350.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM6350 interconnect IDs - * - * Copyright (C) 2022 Luca Weiss - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H -#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H - -#define SM6350_A1NOC_SNOC_MAS 0 -#define SM6350_A1NOC_SNOC_SLV 1 -#define SM6350_A2NOC_SNOC_MAS 2 -#define SM6350_A2NOC_SNOC_SLV 3 -#define SM6350_MASTER_A1NOC_CFG 4 -#define SM6350_MASTER_A2NOC_CFG 5 -#define SM6350_MASTER_AMPSS_M0 6 -#define SM6350_MASTER_CAMNOC_HF 7 -#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM6350_MASTER_CAMNOC_ICP 9 -#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10 -#define SM6350_MASTER_CAMNOC_SF 11 -#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM6350_MASTER_CNOC_DC_NOC 13 -#define SM6350_MASTER_CNOC_MNOC_CFG 14 -#define SM6350_MASTER_COMPUTE_NOC 15 -#define SM6350_MASTER_CRYPTO_CORE_0 16 -#define SM6350_MASTER_EMMC 17 -#define SM6350_MASTER_GEM_NOC_CFG 18 -#define SM6350_MASTER_GEM_NOC_SNOC 19 -#define SM6350_MASTER_GIC 20 -#define SM6350_MASTER_GRAPHICS_3D 21 -#define SM6350_MASTER_IPA 22 -#define SM6350_MASTER_LLCC 23 -#define SM6350_MASTER_MDP_PORT0 24 -#define SM6350_MASTER_MNOC_HF_MEM_NOC 25 -#define SM6350_MASTER_MNOC_SF_MEM_NOC 26 -#define SM6350_MASTER_NPU 27 -#define SM6350_MASTER_NPU_NOC_CFG 28 -#define SM6350_MASTER_NPU_PROC 29 -#define SM6350_MASTER_NPU_SYS 30 -#define SM6350_MASTER_PIMEM 31 -#define SM6350_MASTER_QDSS_BAM 32 -#define SM6350_MASTER_QDSS_DAP 33 -#define SM6350_MASTER_QDSS_ETR 34 -#define SM6350_MASTER_QUP_0 35 -#define SM6350_MASTER_QUP_1 36 -#define SM6350_MASTER_QUP_CORE_0 37 -#define SM6350_MASTER_QUP_CORE_1 38 -#define SM6350_MASTER_SDCC_2 39 -#define SM6350_MASTER_SNOC_CFG 40 -#define SM6350_MASTER_SNOC_GC_MEM_NOC 41 -#define SM6350_MASTER_SNOC_SF_MEM_NOC 42 -#define SM6350_MASTER_SYS_TCU 43 -#define SM6350_MASTER_UFS_MEM 44 -#define SM6350_MASTER_USB3 45 -#define SM6350_MASTER_VIDEO_P0 46 -#define SM6350_MASTER_VIDEO_PROC 47 -#define SM6350_SLAVE_A1NOC_CFG 48 -#define SM6350_SLAVE_A2NOC_CFG 49 -#define SM6350_SLAVE_AHB2PHY 50 -#define SM6350_SLAVE_AHB2PHY_2 51 -#define SM6350_SLAVE_AOSS 52 -#define SM6350_SLAVE_APPSS 53 -#define SM6350_SLAVE_BOOT_ROM 54 -#define SM6350_SLAVE_CAMERA_CFG 55 -#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56 -#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57 -#define SM6350_SLAVE_CAMNOC_UNCOMP 58 -#define SM6350_SLAVE_CDSP_GEM_NOC 59 -#define SM6350_SLAVE_CLK_CTL 60 -#define SM6350_SLAVE_CNOC_DDRSS 61 -#define SM6350_SLAVE_CNOC_MNOC_CFG 62 -#define SM6350_SLAVE_CNOC_MSS 63 -#define SM6350_SLAVE_CRYPTO_0_CFG 64 -#define SM6350_SLAVE_DCC_CFG 65 -#define SM6350_SLAVE_DISPLAY_CFG 66 -#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67 -#define SM6350_SLAVE_EBI_CH0 68 -#define SM6350_SLAVE_EMMC_CFG 69 -#define SM6350_SLAVE_GEM_NOC_CFG 70 -#define SM6350_SLAVE_GEM_NOC_SNOC 71 -#define SM6350_SLAVE_GLM 72 -#define SM6350_SLAVE_GRAPHICS_3D_CFG 73 -#define SM6350_SLAVE_IMEM_CFG 74 -#define SM6350_SLAVE_IPA_CFG 75 -#define SM6350_SLAVE_ISENSE_CFG 76 -#define SM6350_SLAVE_LLCC 77 -#define SM6350_SLAVE_LLCC_CFG 78 -#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79 -#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80 -#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81 -#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82 -#define SM6350_SLAVE_NPU_CAL_DP0 83 -#define SM6350_SLAVE_NPU_CFG 84 -#define SM6350_SLAVE_NPU_COMPUTE_NOC 85 -#define SM6350_SLAVE_NPU_CP 86 -#define SM6350_SLAVE_NPU_DPM 87 -#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88 -#define SM6350_SLAVE_NPU_LLM_CFG 89 -#define SM6350_SLAVE_NPU_TCM 90 -#define SM6350_SLAVE_OCIMEM 91 -#define SM6350_SLAVE_PDM 92 -#define SM6350_SLAVE_PIMEM 93 -#define SM6350_SLAVE_PIMEM_CFG 94 -#define SM6350_SLAVE_PRNG 95 -#define SM6350_SLAVE_QDSS_CFG 96 -#define SM6350_SLAVE_QDSS_STM 97 -#define SM6350_SLAVE_QM_CFG 98 -#define SM6350_SLAVE_QM_MPU_CFG 99 -#define SM6350_SLAVE_QUP_0 100 -#define SM6350_SLAVE_QUP_1 101 -#define SM6350_SLAVE_QUP_CORE_0 102 -#define SM6350_SLAVE_QUP_CORE_1 103 -#define SM6350_SLAVE_RBCPR_CX_CFG 104 -#define SM6350_SLAVE_RBCPR_MX_CFG 105 -#define SM6350_SLAVE_SDCC_2 106 -#define SM6350_SLAVE_SECURITY 107 -#define SM6350_SLAVE_SERVICE_A1NOC 108 -#define SM6350_SLAVE_SERVICE_A2NOC 109 -#define SM6350_SLAVE_SERVICE_CNOC 110 -#define SM6350_SLAVE_SERVICE_GEM_NOC 111 -#define SM6350_SLAVE_SERVICE_MNOC 112 -#define SM6350_SLAVE_SERVICE_NPU_NOC 113 -#define SM6350_SLAVE_SERVICE_SNOC 114 -#define SM6350_SLAVE_SNOC_CFG 115 -#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116 -#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117 -#define SM6350_SLAVE_TCSR 118 -#define SM6350_SLAVE_TCU 119 -#define SM6350_SLAVE_UFS_MEM_CFG 120 -#define SM6350_SLAVE_USB3 121 -#define SM6350_SLAVE_VENUS_CFG 122 -#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123 -#define SM6350_SLAVE_VSENSE_CTRL_CFG 124 -#define SM6350_SNOC_CNOC_MAS 125 -#define SM6350_SNOC_CNOC_SLV 126 - -#endif From 5b83f48e4c1bd48fd0578f3470df8e27b277d245 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:34 +0200 Subject: [PATCH 153/304] interconnect: qcom: sm7150: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-18-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm7150.c | 663 ++++++++++++++--------------- drivers/interconnect/qcom/sm7150.h | 140 ------ 2 files changed, 329 insertions(+), 474 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm7150.h diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c index c8c77407cd50..296cf350a08f 100644 --- a/drivers/interconnect/qcom/sm7150.c +++ b/drivers/interconnect/qcom/sm7150.c @@ -14,1169 +14,1154 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm7150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup_center; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_north; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_rt_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qxm_camnoc_nrt_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_nrt; +static struct qcom_icc_node qxm_camnoc_rt; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_north; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_center; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { - .name = "qhm-a1noc-cfg", - .id = SM7150_MASTER_A1NOC_CFG, + .name = "qhm_a1noc_cfg", .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup_center = { .name = "qhm_qup_center", - .id = SM7150_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SM7150_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SM7150_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM7150_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM7150_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM7150_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM7150_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM7150_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup_north = { .name = "qhm_qup_north", - .id = SM7150_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SM7150_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM7150_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM7150_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM7150_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM7150_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM7150_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SM7150_MASTER_CAMNOC_HF0_UNCOMP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_rt_uncomp = { .name = "qxm_camnoc_rt_uncomp", - .id = SM7150_MASTER_CAMNOC_RT_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SM7150_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_nrt_uncomp = { .name = "qxm_camnoc_nrt_uncomp", - .id = SM7150_MASTER_CAMNOC_NRT_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM7150_MASTER_NPU, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SM7150_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM7150_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 47, - .links = { SM7150_SLAVE_TLMM_SOUTH, - SM7150_SLAVE_CAMERA_CFG, - SM7150_SLAVE_SDCC_4, - SM7150_SLAVE_SDCC_2, - SM7150_SLAVE_CNOC_MNOC_CFG, - SM7150_SLAVE_UFS_MEM_CFG, - SM7150_SLAVE_QUP_0, - SM7150_SLAVE_GLM, - SM7150_SLAVE_PDM, - SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM7150_SLAVE_A2NOC_CFG, - SM7150_SLAVE_QDSS_CFG, - SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM7150_SLAVE_DISPLAY_CFG, - SM7150_SLAVE_PCIE_CFG, - SM7150_SLAVE_DISPLAY_THROTTLE_CFG, - SM7150_SLAVE_TCSR, - SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, - SM7150_SLAVE_CNOC_DDRSS, - SM7150_SLAVE_AHB2PHY_NORTH, - SM7150_SLAVE_SNOC_CFG, - SM7150_SLAVE_GRAPHICS_3D_CFG, - SM7150_SLAVE_VENUS_CFG, - SM7150_SLAVE_TSIF, - SM7150_SLAVE_CDSP_CFG, - SM7150_SLAVE_CLK_CTL, - SM7150_SLAVE_AOP, - SM7150_SLAVE_QUP_1, - SM7150_SLAVE_AHB2PHY_SOUTH, - SM7150_SLAVE_SERVICE_CNOC, - SM7150_SLAVE_AHB2PHY_WEST, - SM7150_SLAVE_USB3, - SM7150_SLAVE_VENUS_THROTTLE_CFG, - SM7150_SLAVE_IPA_CFG, - SM7150_SLAVE_RBCPR_CX_CFG, - SM7150_SLAVE_TLMM_WEST, - SM7150_SLAVE_A1NOC_CFG, - SM7150_SLAVE_AOSS, - SM7150_SLAVE_PRNG, - SM7150_SLAVE_VSENSE_CTRL_CFG, - SM7150_SLAVE_EMMC_CFG, - SM7150_SLAVE_SPDM_WRAPPER, - SM7150_SLAVE_CRYPTO_0_CFG, - SM7150_SLAVE_PIMEM_CFG, - SM7150_SLAVE_TLMM_NORTH, - SM7150_SLAVE_RBCPR_MX_CFG, - SM7150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qupv3_center, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_pcie_cfg, + &qhs_display_throttle_cfg, + &qhs_tcsr, + &qhs_venus_cvp_throttle_cfg, + &qhs_ddrss_cfg, + &qhs_ahb2phy_north, + &qhs_snoc_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &srvc_cnoc, + &qhs_ahb2phy_west, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM7150_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 48, - .links = { SM7150_SLAVE_TLMM_SOUTH, - SM7150_SLAVE_CAMERA_CFG, - SM7150_SLAVE_SDCC_4, - SM7150_SLAVE_SDCC_2, - SM7150_SLAVE_CNOC_MNOC_CFG, - SM7150_SLAVE_UFS_MEM_CFG, - SM7150_SLAVE_QUP_0, - SM7150_SLAVE_GLM, - SM7150_SLAVE_PDM, - SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM7150_SLAVE_A2NOC_CFG, - SM7150_SLAVE_QDSS_CFG, - SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM7150_SLAVE_DISPLAY_CFG, - SM7150_SLAVE_PCIE_CFG, - SM7150_SLAVE_DISPLAY_THROTTLE_CFG, - SM7150_SLAVE_TCSR, - SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, - SM7150_SLAVE_CNOC_DDRSS, - SM7150_SLAVE_CNOC_A2NOC, - SM7150_SLAVE_AHB2PHY_NORTH, - SM7150_SLAVE_SNOC_CFG, - SM7150_SLAVE_GRAPHICS_3D_CFG, - SM7150_SLAVE_VENUS_CFG, - SM7150_SLAVE_TSIF, - SM7150_SLAVE_CDSP_CFG, - SM7150_SLAVE_CLK_CTL, - SM7150_SLAVE_AOP, - SM7150_SLAVE_QUP_1, - SM7150_SLAVE_AHB2PHY_SOUTH, - SM7150_SLAVE_SERVICE_CNOC, - SM7150_SLAVE_AHB2PHY_WEST, - SM7150_SLAVE_USB3, - SM7150_SLAVE_VENUS_THROTTLE_CFG, - SM7150_SLAVE_IPA_CFG, - SM7150_SLAVE_RBCPR_CX_CFG, - SM7150_SLAVE_TLMM_WEST, - SM7150_SLAVE_A1NOC_CFG, - SM7150_SLAVE_AOSS, - SM7150_SLAVE_PRNG, - SM7150_SLAVE_VSENSE_CTRL_CFG, - SM7150_SLAVE_EMMC_CFG, - SM7150_SLAVE_SPDM_WRAPPER, - SM7150_SLAVE_CRYPTO_0_CFG, - SM7150_SLAVE_PIMEM_CFG, - SM7150_SLAVE_TLMM_NORTH, - SM7150_SLAVE_RBCPR_MX_CFG, - SM7150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qupv3_center, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_pcie_cfg, + &qhs_display_throttle_cfg, + &qhs_tcsr, + &qhs_venus_cvp_throttle_cfg, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_ahb2phy_north, + &qhs_snoc_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &srvc_cnoc, + &qhs_ahb2phy_west, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM7150_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM7150_SLAVE_LLCC_CFG, - SM7150_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qhs_gemnoc }, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = SM7150_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SM7150_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM7150_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM7150_SLAVE_SERVICE_GEM_NOC, - SM7150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM7150_MASTER_COMPUTE_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM7150_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM7150_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM7150_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM7150_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM7150_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SM7150_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM7150_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM7150_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", - .id = SM7150_MASTER_CAMNOC_HF0, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_nrt = { .name = "qxm_camnoc_nrt", - .id = SM7150_MASTER_CAMNOC_NRT, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_camnoc_rt = { .name = "qxm_camnoc_rt", - .id = SM7150_MASTER_CAMNOC_RT, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SM7150_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM7150_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM7150_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM7150_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SM7150_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SM7150_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SM7150_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM7150_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM7150_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF, - SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM7150_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF, - SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_TCU, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM7150_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_TCU, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM7150_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC, - SM7150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM7150_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC, - SM7150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM7150_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM7150_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM7150_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", - .id = SM7150_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM7150_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SM7150_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_cdsp_gemnoc = { .name = "qns_cdsp_gemnoc", - .id = SM7150_SLAVE_CDSP_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM7150_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM7150_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy_north = { .name = "qhs_ahb2phy_north", - .id = SM7150_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy_south = { .name = "qhs_ahb2phy_south", - .id = SM7150_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy_west = { .name = "qhs_ahb2phy_west", - .id = SM7150_SLAVE_AHB2PHY_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SM7150_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM7150_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM7150_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { .name = "qhs_camera_nrt_thrott_cfg", - .id = SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM7150_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp_cfg = { .name = "qhs_compute_dsp_cfg", - .id = SM7150_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM7150_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM7150_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM7150_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM7150_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM7150_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_throttle_cfg = { .name = "qhs_display_throttle_cfg", - .id = SM7150_SLAVE_DISPLAY_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SM7150_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SM7150_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM7150_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM7150_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM7150_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM7150_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pcie_cfg = { .name = "qhs_pcie_cfg", - .id = SM7150_SLAVE_PCIE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM7150_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM7150_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM7150_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM7150_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_center = { .name = "qhs_qupv3_center", - .id = SM7150_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SM7150_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM7150_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM7150_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM7150_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SM7150_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM7150_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SM7150_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SM7150_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_west = { .name = "qhs_tlmm_west", - .id = SM7150_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SM7150_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM7150_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM7150_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM7150_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { .name = "qhs_venus_cvp_throttle_cfg", - .id = SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_throttle_cfg = { .name = "qhs_venus_throttle_cfg", - .id = SM7150_SLAVE_VENUS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM7150_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SM7150_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM7150_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gemnoc = { .name = "qhs_gemnoc", - .id = SM7150_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM7150_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM7150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM7150_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM7150_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SM7150_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SM7150_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM7150_SLAVE_EBI_CH0, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SM7150_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM7150_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM7150_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM7150_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM7150_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM7150_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM7150_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM7150_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM7150_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM7150_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM7150_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM7150_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1446,6 +1431,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1475,6 +1461,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1494,6 +1481,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc sm7150_camnoc_virt = { + .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1511,6 +1499,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_compute_noc = { + .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1576,6 +1565,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1592,6 +1582,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1623,6 +1614,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1640,6 +1632,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm7150_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1671,6 +1664,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1707,6 +1701,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm7150.h b/drivers/interconnect/qcom/sm7150.h deleted file mode 100644 index e00a9b0c1279..000000000000 --- a/drivers/interconnect/qcom/sm7150.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Qualcomm #define SM7150 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2024, Danila Tikhonov - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H - -#define SM7150_A1NOC_SNOC_MAS 0 -#define SM7150_A1NOC_SNOC_SLV 1 -#define SM7150_A2NOC_SNOC_MAS 2 -#define SM7150_A2NOC_SNOC_SLV 3 -#define SM7150_MASTER_A1NOC_CFG 4 -#define SM7150_MASTER_A2NOC_CFG 5 -#define SM7150_MASTER_AMPSS_M0 6 -#define SM7150_MASTER_CAMNOC_HF0 7 -#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM7150_MASTER_CAMNOC_NRT 9 -#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10 -#define SM7150_MASTER_CAMNOC_RT 11 -#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12 -#define SM7150_MASTER_CAMNOC_SF 13 -#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14 -#define SM7150_MASTER_CNOC_A2NOC 15 -#define SM7150_MASTER_CNOC_DC_NOC 16 -#define SM7150_MASTER_CNOC_MNOC_CFG 17 -#define SM7150_MASTER_COMPUTE_NOC 18 -#define SM7150_MASTER_CRYPTO_CORE_0 19 -#define SM7150_MASTER_EMMC 20 -#define SM7150_MASTER_GEM_NOC_CFG 21 -#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22 -#define SM7150_MASTER_GEM_NOC_SNOC 23 -#define SM7150_MASTER_GIC 24 -#define SM7150_MASTER_GRAPHICS_3D 25 -#define SM7150_MASTER_IPA 26 -#define SM7150_MASTER_LLCC 27 -#define SM7150_MASTER_MDP_PORT0 28 -#define SM7150_MASTER_MDP_PORT1 29 -#define SM7150_MASTER_MNOC_HF_MEM_NOC 30 -#define SM7150_MASTER_MNOC_SF_MEM_NOC 31 -#define SM7150_MASTER_NPU 32 -#define SM7150_MASTER_PCIE 33 -#define SM7150_MASTER_PIMEM 34 -#define SM7150_MASTER_QDSS_BAM 35 -#define SM7150_MASTER_QDSS_DAP 36 -#define SM7150_MASTER_QDSS_ETR 37 -#define SM7150_MASTER_QUP_0 38 -#define SM7150_MASTER_QUP_1 39 -#define SM7150_MASTER_ROTATOR 40 -#define SM7150_MASTER_SDCC_2 41 -#define SM7150_MASTER_SDCC_4 42 -#define SM7150_MASTER_SNOC_CFG 43 -#define SM7150_MASTER_SNOC_GC_MEM_NOC 44 -#define SM7150_MASTER_SNOC_SF_MEM_NOC 45 -#define SM7150_MASTER_SPDM 46 -#define SM7150_MASTER_SYS_TCU 47 -#define SM7150_MASTER_TSIF 48 -#define SM7150_MASTER_UFS_MEM 49 -#define SM7150_MASTER_USB3 50 -#define SM7150_MASTER_VIDEO_P0 51 -#define SM7150_MASTER_VIDEO_P1 52 -#define SM7150_MASTER_VIDEO_PROC 53 -#define SM7150_SLAVE_A1NOC_CFG 54 -#define SM7150_SLAVE_A2NOC_CFG 55 -#define SM7150_SLAVE_AHB2PHY_NORTH 56 -#define SM7150_SLAVE_AHB2PHY_SOUTH 57 -#define SM7150_SLAVE_AHB2PHY_WEST 58 -#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59 -#define SM7150_SLAVE_AOP 60 -#define SM7150_SLAVE_AOSS 61 -#define SM7150_SLAVE_APPSS 62 -#define SM7150_SLAVE_CAMERA_CFG 63 -#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64 -#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65 -#define SM7150_SLAVE_CAMNOC_UNCOMP 66 -#define SM7150_SLAVE_CDSP_CFG 67 -#define SM7150_SLAVE_CDSP_GEM_NOC 68 -#define SM7150_SLAVE_CLK_CTL 69 -#define SM7150_SLAVE_CNOC_A2NOC 70 -#define SM7150_SLAVE_CNOC_DDRSS 71 -#define SM7150_SLAVE_CNOC_MNOC_CFG 72 -#define SM7150_SLAVE_CRYPTO_0_CFG 73 -#define SM7150_SLAVE_DISPLAY_CFG 74 -#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75 -#define SM7150_SLAVE_EBI_CH0 76 -#define SM7150_SLAVE_EMMC_CFG 77 -#define SM7150_SLAVE_GEM_NOC_CFG 78 -#define SM7150_SLAVE_GEM_NOC_SNOC 79 -#define SM7150_SLAVE_GLM 80 -#define SM7150_SLAVE_GRAPHICS_3D_CFG 81 -#define SM7150_SLAVE_IMEM_CFG 82 -#define SM7150_SLAVE_IPA_CFG 83 -#define SM7150_SLAVE_LLCC 84 -#define SM7150_SLAVE_LLCC_CFG 85 -#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86 -#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87 -#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88 -#define SM7150_SLAVE_OCIMEM 89 -#define SM7150_SLAVE_PCIE_CFG 90 -#define SM7150_SLAVE_PDM 91 -#define SM7150_SLAVE_PIMEM 92 -#define SM7150_SLAVE_PIMEM_CFG 93 -#define SM7150_SLAVE_PRNG 94 -#define SM7150_SLAVE_QDSS_CFG 95 -#define SM7150_SLAVE_QDSS_STM 96 -#define SM7150_SLAVE_QUP_0 97 -#define SM7150_SLAVE_QUP_1 98 -#define SM7150_SLAVE_RBCPR_CX_CFG 99 -#define SM7150_SLAVE_RBCPR_MX_CFG 100 -#define SM7150_SLAVE_SDCC_2 101 -#define SM7150_SLAVE_SDCC_4 102 -#define SM7150_SLAVE_SERVICE_A1NOC 103 -#define SM7150_SLAVE_SERVICE_A2NOC 104 -#define SM7150_SLAVE_SERVICE_CNOC 105 -#define SM7150_SLAVE_SERVICE_GEM_NOC 106 -#define SM7150_SLAVE_SERVICE_MNOC 107 -#define SM7150_SLAVE_SERVICE_SNOC 108 -#define SM7150_SLAVE_SNOC_CFG 109 -#define SM7150_SLAVE_SNOC_GEM_NOC_GC 110 -#define SM7150_SLAVE_SNOC_GEM_NOC_SF 111 -#define SM7150_SLAVE_SPDM_WRAPPER 112 -#define SM7150_SLAVE_TCSR 113 -#define SM7150_SLAVE_TCU 114 -#define SM7150_SLAVE_TLMM_NORTH 115 -#define SM7150_SLAVE_TLMM_SOUTH 116 -#define SM7150_SLAVE_TLMM_WEST 117 -#define SM7150_SLAVE_TSIF 118 -#define SM7150_SLAVE_UFS_MEM_CFG 119 -#define SM7150_SLAVE_USB3 120 -#define SM7150_SLAVE_VENUS_CFG 121 -#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG 122 -#define SM7150_SLAVE_VENUS_THROTTLE_CFG 123 -#define SM7150_SLAVE_VSENSE_CTRL_CFG 124 -#define SM7150_SNOC_CNOC_MAS 125 -#define SM7150_SNOC_CNOC_SLV 126 - -#endif From 0b2b044bbe8a2eb57e44ae385158250acf474923 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:35 +0200 Subject: [PATCH 154/304] interconnect: qcom: sm8150: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-19-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8150.c | 716 ++++++++++++++--------------- drivers/interconnect/qcom/sm8150.h | 152 ------ 2 files changed, 355 insertions(+), 513 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm8150.h diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index edfe824cad35..58a6643921bb 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -14,1268 +14,1252 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_sensorss_ahb; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_ecc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_phy_refgen_north; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qupv3_east; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_ssc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_ecc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SM8150_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8150_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac = { .name = "xm_emac", - .id = SM8150_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8150_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8150_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SM8150_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM8150_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8150_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8150_MASTER_QSPI, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8150_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8150_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_sensorss_ahb = { .name = "qhm_sensorss_ahb", - .id = SM8150_MASTER_SENSORS_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SM8150_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SM8150_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8150_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8150_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8150_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8150_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM8150_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8150_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8150_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SM8150_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SM8150_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SM8150_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM8150_MASTER_NPU, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_cdsp_mem_noc }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SM8150_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM8150_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 50, - .links = { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM8150_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 51, - .links = { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_CNOC_A2NOC, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM8150_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8150_SLAVE_GEM_NOC_CFG, - SM8150_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_memnoc, + &qhs_llcc }, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = SM8150_MASTER_AMPSS_M0, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_gpu_tcu = { .name = "acm_gpu_tcu", - .id = SM8150_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SM8150_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM8150_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8150_SLAVE_SERVICE_GEM_NOC, - SM8150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM8150_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8150_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8150_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8150_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8150_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8150_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8150_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_ecc = { .name = "qxm_ecc", - .id = SM8150_MASTER_ECC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8150_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM8150_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SM8150_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SM8150_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SM8150_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM8150_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM8150_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM8150_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SM8150_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SM8150_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SM8150_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM8150_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8150_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8150_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_PCIE_0, - SM8150_SLAVE_PCIE_1, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_pcie_0, + &xs_pcie_1, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM8150_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8150_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8150_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8150_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8150_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8150_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8150_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SM8150_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_cdsp_mem_noc = { .name = "qns_cdsp_mem_noc", - .id = SM8150_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM8150_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM8150_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy_south = { .name = "qhs_ahb2phy_south", - .id = SM8150_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SM8150_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8150_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8150_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8150_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp = { .name = "qhs_compute_dsp", - .id = SM8150_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8150_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8150_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM8150_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8150_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM8150_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8150_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac_cfg = { .name = "qhs_emac_cfg", - .id = SM8150_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SM8150_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8150_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8150_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8150_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM8150_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SM8150_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8150_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8150_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_phy_refgen_north = { .name = "qhs_phy_refgen_north", - .id = SM8150_SLAVE_NORTH_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8150_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8150_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8150_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8150_SLAVE_QSPI, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_east = { .name = "qhs_qupv3_east", - .id = SM8150_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SM8150_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_south = { .name = "qhs_qupv3_south", - .id = SM8150_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8150_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8150_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM8150_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SM8150_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8150_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ssc_cfg = { .name = "qhs_ssc_cfg", - .id = SM8150_SLAVE_SSC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8150_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_east = { .name = "qhs_tlmm_east", - .id = SM8150_SLAVE_TLMM_EAST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SM8150_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SM8150_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_west = { .name = "qhs_tlmm_west", - .id = SM8150_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SM8150_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SM8150_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8150_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8150_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SM8150_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8150_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8150_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SM8150_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8150_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM8150_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SM8150_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ecc = { .name = "qns_ecc", - .id = SM8150_SLAVE_ECC, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM8150_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8150_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8150_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SM8150_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8150_SLAVE_EBI_CH0, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SM8150_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8150_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8150_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8150_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM8150_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8150_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8150_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8150_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8150_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8150_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8150_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8150_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8150_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8150_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1554,6 +1538,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1589,6 +1574,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1607,6 +1593,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8150_camnoc_virt = { + .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1624,6 +1611,7 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_compute_noc = { + .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1692,6 +1680,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1708,6 +1697,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1743,6 +1733,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1760,6 +1751,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8150_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1790,6 +1782,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1831,6 +1824,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h deleted file mode 100644 index 1d587c94eb06..000000000000 --- a/drivers/interconnect/qcom/sm8150.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H - -#define SM8150_A1NOC_SNOC_MAS 0 -#define SM8150_A1NOC_SNOC_SLV 1 -#define SM8150_A2NOC_SNOC_MAS 2 -#define SM8150_A2NOC_SNOC_SLV 3 -#define SM8150_MASTER_A1NOC_CFG 4 -#define SM8150_MASTER_A2NOC_CFG 5 -#define SM8150_MASTER_AMPSS_M0 6 -#define SM8150_MASTER_CAMNOC_HF0 7 -#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM8150_MASTER_CAMNOC_HF1 9 -#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SM8150_MASTER_CAMNOC_SF 11 -#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM8150_MASTER_CNOC_A2NOC 13 -#define SM8150_MASTER_CNOC_DC_NOC 14 -#define SM8150_MASTER_CNOC_MNOC_CFG 15 -#define SM8150_MASTER_COMPUTE_NOC 16 -#define SM8150_MASTER_CRYPTO_CORE_0 17 -#define SM8150_MASTER_ECC 18 -#define SM8150_MASTER_EMAC 19 -#define SM8150_MASTER_GEM_NOC_CFG 20 -#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SM8150_MASTER_GEM_NOC_SNOC 22 -#define SM8150_MASTER_GIC 23 -#define SM8150_MASTER_GPU_TCU 24 -#define SM8150_MASTER_GRAPHICS_3D 25 -#define SM8150_MASTER_IPA 26 -/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_MASTER_LLCC 28 -#define SM8150_MASTER_MDP_PORT0 29 -#define SM8150_MASTER_MDP_PORT1 30 -#define SM8150_MASTER_MNOC_HF_MEM_NOC 31 -#define SM8150_MASTER_MNOC_SF_MEM_NOC 32 -#define SM8150_MASTER_NPU 33 -#define SM8150_MASTER_PCIE 34 -#define SM8150_MASTER_PCIE_1 35 -#define SM8150_MASTER_PIMEM 36 -#define SM8150_MASTER_QDSS_BAM 37 -#define SM8150_MASTER_QDSS_DAP 38 -#define SM8150_MASTER_QDSS_ETR 39 -#define SM8150_MASTER_QSPI 40 -#define SM8150_MASTER_QUP_0 41 -#define SM8150_MASTER_QUP_1 42 -#define SM8150_MASTER_QUP_2 43 -#define SM8150_MASTER_ROTATOR 44 -#define SM8150_MASTER_SDCC_2 45 -#define SM8150_MASTER_SDCC_4 46 -#define SM8150_MASTER_SENSORS_AHB 47 -#define SM8150_MASTER_SNOC_CFG 48 -#define SM8150_MASTER_SNOC_GC_MEM_NOC 49 -#define SM8150_MASTER_SNOC_SF_MEM_NOC 50 -#define SM8150_MASTER_SPDM 51 -#define SM8150_MASTER_SYS_TCU 52 -#define SM8150_MASTER_TSIF 53 -#define SM8150_MASTER_UFS_MEM 54 -#define SM8150_MASTER_USB3 55 -#define SM8150_MASTER_USB3_1 56 -#define SM8150_MASTER_VIDEO_P0 57 -#define SM8150_MASTER_VIDEO_P1 58 -#define SM8150_MASTER_VIDEO_PROC 59 -#define SM8150_SLAVE_A1NOC_CFG 60 -#define SM8150_SLAVE_A2NOC_CFG 61 -#define SM8150_SLAVE_AHB2PHY_SOUTH 62 -#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8150_SLAVE_AOP 64 -#define SM8150_SLAVE_AOSS 65 -#define SM8150_SLAVE_APPSS 66 -#define SM8150_SLAVE_CAMERA_CFG 67 -#define SM8150_SLAVE_CAMNOC_UNCOMP 68 -#define SM8150_SLAVE_CDSP_CFG 69 -#define SM8150_SLAVE_CDSP_MEM_NOC 70 -#define SM8150_SLAVE_CLK_CTL 71 -#define SM8150_SLAVE_CNOC_A2NOC 72 -#define SM8150_SLAVE_CNOC_DDRSS 73 -#define SM8150_SLAVE_CNOC_MNOC_CFG 74 -#define SM8150_SLAVE_CRYPTO_0_CFG 75 -#define SM8150_SLAVE_DISPLAY_CFG 76 -#define SM8150_SLAVE_EBI_CH0 77 -#define SM8150_SLAVE_ECC 78 -#define SM8150_SLAVE_EMAC_CFG 79 -#define SM8150_SLAVE_GEM_NOC_CFG 80 -#define SM8150_SLAVE_GEM_NOC_SNOC 81 -#define SM8150_SLAVE_GLM 82 -#define SM8150_SLAVE_GRAPHICS_3D_CFG 83 -#define SM8150_SLAVE_IMEM_CFG 84 -#define SM8150_SLAVE_IPA_CFG 85 -/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_SLAVE_LLCC 87 -#define SM8150_SLAVE_LLCC_CFG 88 -#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89 -#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90 -#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91 -#define SM8150_SLAVE_NORTH_PHY_CFG 92 -#define SM8150_SLAVE_NPU_CFG 93 -#define SM8150_SLAVE_OCIMEM 94 -#define SM8150_SLAVE_PCIE_0 95 -#define SM8150_SLAVE_PCIE_0_CFG 96 -#define SM8150_SLAVE_PCIE_1 97 -#define SM8150_SLAVE_PCIE_1_CFG 98 -#define SM8150_SLAVE_PIMEM 99 -#define SM8150_SLAVE_PIMEM_CFG 100 -#define SM8150_SLAVE_PRNG 101 -#define SM8150_SLAVE_QDSS_CFG 102 -#define SM8150_SLAVE_QDSS_STM 103 -#define SM8150_SLAVE_QSPI 104 -#define SM8150_SLAVE_QUP_0 105 -#define SM8150_SLAVE_QUP_1 106 -#define SM8150_SLAVE_QUP_2 107 -#define SM8150_SLAVE_RBCPR_CX_CFG 108 -#define SM8150_SLAVE_RBCPR_MMCX_CFG 109 -#define SM8150_SLAVE_RBCPR_MX_CFG 110 -#define SM8150_SLAVE_SDCC_2 111 -#define SM8150_SLAVE_SDCC_4 112 -#define SM8150_SLAVE_SERVICE_A1NOC 113 -#define SM8150_SLAVE_SERVICE_A2NOC 114 -#define SM8150_SLAVE_SERVICE_CNOC 115 -#define SM8150_SLAVE_SERVICE_GEM_NOC 116 -#define SM8150_SLAVE_SERVICE_MNOC 117 -#define SM8150_SLAVE_SERVICE_SNOC 118 -#define SM8150_SLAVE_SNOC_CFG 119 -#define SM8150_SLAVE_SNOC_GEM_NOC_GC 120 -#define SM8150_SLAVE_SNOC_GEM_NOC_SF 121 -#define SM8150_SLAVE_SPDM_WRAPPER 122 -#define SM8150_SLAVE_SPSS_CFG 123 -#define SM8150_SLAVE_SSC_CFG 124 -#define SM8150_SLAVE_TCSR 125 -#define SM8150_SLAVE_TCU 126 -#define SM8150_SLAVE_TLMM_EAST 127 -#define SM8150_SLAVE_TLMM_NORTH 128 -#define SM8150_SLAVE_TLMM_SOUTH 129 -#define SM8150_SLAVE_TLMM_WEST 130 -#define SM8150_SLAVE_TSIF 131 -#define SM8150_SLAVE_UFS_CARD_CFG 132 -#define SM8150_SLAVE_UFS_MEM_CFG 133 -#define SM8150_SLAVE_USB3 134 -#define SM8150_SLAVE_USB3_1 135 -#define SM8150_SLAVE_VENUS_CFG 136 -#define SM8150_SLAVE_VSENSE_CTRL_CFG 137 -#define SM8150_SNOC_CNOC_MAS 138 -#define SM8150_SNOC_CNOC_SLV 139 - -#endif From 0b27e5cae0a28ef51970d84c0cb109bcdd94cdd9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:36 +0200 Subject: [PATCH 155/304] interconnect: qcom: sm8350: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-20-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8350.c | 694 ++++++++++++++--------------- drivers/interconnect/qcom/sm8350.h | 158 ------- 2 files changed, 345 insertions(+), 507 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm8350.h diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 38105ead4f29..75a9b0ddb8d5 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -13,1255 +13,1241 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8350.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qhs_modem_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8350_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8350_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8350_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8350_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SM8350_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8350_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8350_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8350_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SM8350_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8350_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SM8350_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8350_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8350_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8350_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8350_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM8350_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8350_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SM8350_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8350_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 56, - .links = { SM8350_SLAVE_AHB2PHY_SOUTH, - SM8350_SLAVE_AHB2PHY_NORTH, - SM8350_SLAVE_AOSS, - SM8350_SLAVE_APPSS, - SM8350_SLAVE_CAMERA_CFG, - SM8350_SLAVE_CLK_CTL, - SM8350_SLAVE_CDSP_CFG, - SM8350_SLAVE_RBCPR_CX_CFG, - SM8350_SLAVE_RBCPR_MMCX_CFG, - SM8350_SLAVE_RBCPR_MX_CFG, - SM8350_SLAVE_CRYPTO_0_CFG, - SM8350_SLAVE_CX_RDPM, - SM8350_SLAVE_DCC_CFG, - SM8350_SLAVE_DISPLAY_CFG, - SM8350_SLAVE_GFX3D_CFG, - SM8350_SLAVE_HWKM, - SM8350_SLAVE_IMEM_CFG, - SM8350_SLAVE_IPA_CFG, - SM8350_SLAVE_IPC_ROUTER_CFG, - SM8350_SLAVE_LPASS, - SM8350_SLAVE_CNOC_MSS, - SM8350_SLAVE_MX_RDPM, - SM8350_SLAVE_PCIE_0_CFG, - SM8350_SLAVE_PCIE_1_CFG, - SM8350_SLAVE_PDM, - SM8350_SLAVE_PIMEM_CFG, - SM8350_SLAVE_PKA_WRAPPER_CFG, - SM8350_SLAVE_PMU_WRAPPER_CFG, - SM8350_SLAVE_QDSS_CFG, - SM8350_SLAVE_QSPI_0, - SM8350_SLAVE_QUP_0, - SM8350_SLAVE_QUP_1, - SM8350_SLAVE_QUP_2, - SM8350_SLAVE_SDCC_2, - SM8350_SLAVE_SDCC_4, - SM8350_SLAVE_SECURITY, - SM8350_SLAVE_SPSS_CFG, - SM8350_SLAVE_TCSR, - SM8350_SLAVE_TLMM, - SM8350_SLAVE_UFS_CARD_CFG, - SM8350_SLAVE_UFS_MEM_CFG, - SM8350_SLAVE_USB3_0, - SM8350_SLAVE_USB3_1, - SM8350_SLAVE_VENUS_CFG, - SM8350_SLAVE_VSENSE_CTRL_CFG, - SM8350_SLAVE_A1NOC_CFG, - SM8350_SLAVE_A2NOC_CFG, - SM8350_SLAVE_DDRSS_CFG, - SM8350_SLAVE_CNOC_MNOC_CFG, - SM8350_SLAVE_SNOC_CFG, - SM8350_SLAVE_BOOT_IMEM, - SM8350_SLAVE_IMEM, - SM8350_SLAVE_PIMEM, - SM8350_SLAVE_SERVICE_CNOC, - SM8350_SLAVE_QDSS_STM, - SM8350_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qxs_boot_imem, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8350_SLAVE_PCIE_0, - SM8350_SLAVE_PCIE_1 - }, + .link_nodes = { &xs_pcie_0, + &xs_pcie_1 }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM8350_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 56, - .links = { SM8350_SLAVE_AHB2PHY_SOUTH, - SM8350_SLAVE_AHB2PHY_NORTH, - SM8350_SLAVE_AOSS, - SM8350_SLAVE_APPSS, - SM8350_SLAVE_CAMERA_CFG, - SM8350_SLAVE_CLK_CTL, - SM8350_SLAVE_CDSP_CFG, - SM8350_SLAVE_RBCPR_CX_CFG, - SM8350_SLAVE_RBCPR_MMCX_CFG, - SM8350_SLAVE_RBCPR_MX_CFG, - SM8350_SLAVE_CRYPTO_0_CFG, - SM8350_SLAVE_CX_RDPM, - SM8350_SLAVE_DCC_CFG, - SM8350_SLAVE_DISPLAY_CFG, - SM8350_SLAVE_GFX3D_CFG, - SM8350_SLAVE_HWKM, - SM8350_SLAVE_IMEM_CFG, - SM8350_SLAVE_IPA_CFG, - SM8350_SLAVE_IPC_ROUTER_CFG, - SM8350_SLAVE_LPASS, - SM8350_SLAVE_CNOC_MSS, - SM8350_SLAVE_MX_RDPM, - SM8350_SLAVE_PCIE_0_CFG, - SM8350_SLAVE_PCIE_1_CFG, - SM8350_SLAVE_PDM, - SM8350_SLAVE_PIMEM_CFG, - SM8350_SLAVE_PKA_WRAPPER_CFG, - SM8350_SLAVE_PMU_WRAPPER_CFG, - SM8350_SLAVE_QDSS_CFG, - SM8350_SLAVE_QSPI_0, - SM8350_SLAVE_QUP_0, - SM8350_SLAVE_QUP_1, - SM8350_SLAVE_QUP_2, - SM8350_SLAVE_SDCC_2, - SM8350_SLAVE_SDCC_4, - SM8350_SLAVE_SECURITY, - SM8350_SLAVE_SPSS_CFG, - SM8350_SLAVE_TCSR, - SM8350_SLAVE_TLMM, - SM8350_SLAVE_UFS_CARD_CFG, - SM8350_SLAVE_UFS_MEM_CFG, - SM8350_SLAVE_USB3_0, - SM8350_SLAVE_USB3_1, - SM8350_SLAVE_VENUS_CFG, - SM8350_SLAVE_VSENSE_CTRL_CFG, - SM8350_SLAVE_A1NOC_CFG, - SM8350_SLAVE_A2NOC_CFG, - SM8350_SLAVE_DDRSS_CFG, - SM8350_SLAVE_CNOC_MNOC_CFG, - SM8350_SLAVE_SNOC_CFG, - SM8350_SLAVE_BOOT_IMEM, - SM8350_SLAVE_IMEM, - SM8350_SLAVE_PIMEM, - SM8350_SLAVE_SERVICE_CNOC, - SM8350_SLAVE_QDSS_STM, - SM8350_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qxs_boot_imem, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SM8350_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8350_SLAVE_LLCC_CFG, - SM8350_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8350_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8350_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8350_MASTER_APPSS_PROC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC, - SM8350_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM8350_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SM8350_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 5, - .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, - SM8350_SLAVE_MCDMA_MS_MPU_CFG, - SM8350_SLAVE_SERVICE_GEM_NOC_1, - SM8350_SLAVE_SERVICE_GEM_NOC_2, - SM8350_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, + &qhs_modem_ms_mpu_cfg, + &srvc_even_gemnoc, + &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8350_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8350_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8350_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8350_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8350_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC, - SM8350_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SM8350_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SM8350_SLAVE_LPASS_CORE_CFG, - SM8350_SLAVE_LPASS_LPI_CFG, - SM8350_SLAVE_LPASS_MPU_CFG, - SM8350_SLAVE_LPASS_TOP_CFG, - SM8350_SLAVE_SERVICES_LPASS_AML_NOC, - SM8350_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_core, + &qhs_lpass_lpi, + &qhs_lpass_mpu, + &qhs_lpass_top, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8350_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8350_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8350_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8350_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SM8350_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SM8350_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SM8350_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8350_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM8350_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM8350_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM8350_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SM8350_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SM8350_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8350_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8350_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SM8350_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8350_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8350_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8350_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8350_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8350_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8350_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8350_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8350_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8350_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8350_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8350_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8350_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SM8350_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8350_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8350_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM8350_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8350_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8350_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SM8350_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8350_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8350_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SM8350_SLAVE_HWKM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8350_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8350_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8350_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SM8350_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8350_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8350_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8350_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8350_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8350_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8350_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pka_wrapper_cfg = { .name = "qhs_pka_wrapper_cfg", - .id = SM8350_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pmu_wrapper_cfg = { .name = "qhs_pmu_wrapper_cfg", - .id = SM8350_SLAVE_PMU_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8350_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8350_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM8350_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8350_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8350_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8350_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8350_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SM8350_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8350_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8350_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8350_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SM8350_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8350_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8350_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SM8350_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8350_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8350_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SM8350_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SM8350_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SM8350_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SM8350_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SM8350_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SM8350_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8350_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8350_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8350_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8350_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8350_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8350_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8350_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM8350_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SM8350_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { .name = "qhs_modem_ms_mpu_cfg", - .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8350_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8350_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SM8350_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SM8350_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SM8350_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SM8350_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SM8350_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SM8350_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SM8350_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8350_SLAVE_EBI1, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8350_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8350_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8350_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8350_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SM8350_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8350_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8350_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8350_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; @@ -1511,6 +1497,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1542,6 +1529,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1621,6 +1609,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1637,6 +1626,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_dc_noc = { + .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1673,6 +1663,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1693,6 +1684,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1710,6 +1702,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8350_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1740,6 +1733,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1759,6 +1753,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_compute_noc = { + .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1784,6 +1779,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8350.h b/drivers/interconnect/qcom/sm8350.h deleted file mode 100644 index 074c6131ab36..000000000000 --- a/drivers/interconnect/qcom/sm8350.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm SM8350 interconnect IDs - * - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H - -#define SM8350_MASTER_GPU_TCU 0 -#define SM8350_MASTER_SYS_TCU 1 -#define SM8350_MASTER_APPSS_PROC 2 -#define SM8350_MASTER_LLCC 3 -#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4 -#define SM8350_MASTER_CDSP_NOC_CFG 5 -#define SM8350_MASTER_QDSS_BAM 6 -#define SM8350_MASTER_QSPI_0 7 -#define SM8350_MASTER_QUP_0 8 -#define SM8350_MASTER_QUP_1 9 -#define SM8350_MASTER_QUP_2 10 -#define SM8350_MASTER_A1NOC_CFG 11 -#define SM8350_MASTER_A2NOC_CFG 12 -#define SM8350_MASTER_A1NOC_SNOC 13 -#define SM8350_MASTER_A2NOC_SNOC 14 -#define SM8350_MASTER_CAMNOC_HF 15 -#define SM8350_MASTER_CAMNOC_ICP 16 -#define SM8350_MASTER_CAMNOC_SF 17 -#define SM8350_MASTER_COMPUTE_NOC 18 -#define SM8350_MASTER_CNOC_DC_NOC 19 -#define SM8350_MASTER_GEM_NOC_CFG 20 -#define SM8350_MASTER_GEM_NOC_CNOC 21 -#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22 -#define SM8350_MASTER_GFX3D 23 -#define SM8350_MASTER_CNOC_MNOC_CFG 24 -#define SM8350_MASTER_MNOC_HF_MEM_NOC 25 -#define SM8350_MASTER_MNOC_SF_MEM_NOC 26 -#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27 -#define SM8350_MASTER_SNOC_CFG 28 -#define SM8350_MASTER_SNOC_GC_MEM_NOC 29 -#define SM8350_MASTER_SNOC_SF_MEM_NOC 30 -#define SM8350_MASTER_VIDEO_P0 31 -#define SM8350_MASTER_VIDEO_P1 32 -#define SM8350_MASTER_VIDEO_PROC 33 -#define SM8350_MASTER_QUP_CORE_0 34 -#define SM8350_MASTER_QUP_CORE_1 35 -#define SM8350_MASTER_QUP_CORE_2 36 -#define SM8350_MASTER_CRYPTO 37 -#define SM8350_MASTER_IPA 38 -#define SM8350_MASTER_MDP0 39 -#define SM8350_MASTER_MDP1 40 -#define SM8350_MASTER_CDSP_PROC 41 -#define SM8350_MASTER_PIMEM 42 -#define SM8350_MASTER_ROTATOR 43 -#define SM8350_MASTER_GIC 44 -#define SM8350_MASTER_PCIE_0 45 -#define SM8350_MASTER_PCIE_1 46 -#define SM8350_MASTER_QDSS_DAP 47 -#define SM8350_MASTER_QDSS_ETR 48 -#define SM8350_MASTER_SDCC_2 49 -#define SM8350_MASTER_SDCC_4 50 -#define SM8350_MASTER_UFS_CARD 51 -#define SM8350_MASTER_UFS_MEM 52 -#define SM8350_MASTER_USB3_0 53 -#define SM8350_MASTER_USB3_1 54 -#define SM8350_SLAVE_EBI1 55 -#define SM8350_SLAVE_AHB2PHY_SOUTH 56 -#define SM8350_SLAVE_AHB2PHY_NORTH 57 -#define SM8350_SLAVE_AOSS 58 -#define SM8350_SLAVE_APPSS 59 -#define SM8350_SLAVE_CAMERA_CFG 60 -#define SM8350_SLAVE_CLK_CTL 61 -#define SM8350_SLAVE_CDSP_CFG 62 -#define SM8350_SLAVE_RBCPR_CX_CFG 63 -#define SM8350_SLAVE_RBCPR_MMCX_CFG 64 -#define SM8350_SLAVE_RBCPR_MX_CFG 65 -#define SM8350_SLAVE_CRYPTO_0_CFG 66 -#define SM8350_SLAVE_CX_RDPM 67 -#define SM8350_SLAVE_DCC_CFG 68 -#define SM8350_SLAVE_DISPLAY_CFG 69 -#define SM8350_SLAVE_GFX3D_CFG 70 -#define SM8350_SLAVE_HWKM 71 -#define SM8350_SLAVE_IMEM_CFG 72 -#define SM8350_SLAVE_IPA_CFG 73 -#define SM8350_SLAVE_IPC_ROUTER_CFG 74 -#define SM8350_SLAVE_LLCC_CFG 75 -#define SM8350_SLAVE_LPASS 76 -#define SM8350_SLAVE_LPASS_CORE_CFG 77 -#define SM8350_SLAVE_LPASS_LPI_CFG 78 -#define SM8350_SLAVE_LPASS_MPU_CFG 79 -#define SM8350_SLAVE_LPASS_TOP_CFG 80 -#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81 -#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82 -#define SM8350_SLAVE_CNOC_MSS 83 -#define SM8350_SLAVE_MX_RDPM 84 -#define SM8350_SLAVE_PCIE_0_CFG 85 -#define SM8350_SLAVE_PCIE_1_CFG 86 -#define SM8350_SLAVE_PDM 87 -#define SM8350_SLAVE_PIMEM_CFG 88 -#define SM8350_SLAVE_PKA_WRAPPER_CFG 89 -#define SM8350_SLAVE_PMU_WRAPPER_CFG 90 -#define SM8350_SLAVE_QDSS_CFG 91 -#define SM8350_SLAVE_QSPI_0 92 -#define SM8350_SLAVE_QUP_0 93 -#define SM8350_SLAVE_QUP_1 94 -#define SM8350_SLAVE_QUP_2 95 -#define SM8350_SLAVE_SDCC_2 96 -#define SM8350_SLAVE_SDCC_4 97 -#define SM8350_SLAVE_SECURITY 98 -#define SM8350_SLAVE_SPSS_CFG 99 -#define SM8350_SLAVE_TCSR 100 -#define SM8350_SLAVE_TLMM 101 -#define SM8350_SLAVE_UFS_CARD_CFG 102 -#define SM8350_SLAVE_UFS_MEM_CFG 103 -#define SM8350_SLAVE_USB3_0 104 -#define SM8350_SLAVE_USB3_1 105 -#define SM8350_SLAVE_VENUS_CFG 106 -#define SM8350_SLAVE_VSENSE_CTRL_CFG 107 -#define SM8350_SLAVE_A1NOC_CFG 108 -#define SM8350_SLAVE_A1NOC_SNOC 109 -#define SM8350_SLAVE_A2NOC_CFG 110 -#define SM8350_SLAVE_A2NOC_SNOC 111 -#define SM8350_SLAVE_DDRSS_CFG 112 -#define SM8350_SLAVE_GEM_NOC_CNOC 113 -#define SM8350_SLAVE_GEM_NOC_CFG 114 -#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115 -#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116 -#define SM8350_SLAVE_LLCC 117 -#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118 -#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119 -#define SM8350_SLAVE_CNOC_MNOC_CFG 120 -#define SM8350_SLAVE_CDSP_MEM_NOC 121 -#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122 -#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123 -#define SM8350_SLAVE_SNOC_CFG 124 -#define SM8350_SLAVE_QUP_CORE_0 125 -#define SM8350_SLAVE_QUP_CORE_1 126 -#define SM8350_SLAVE_QUP_CORE_2 127 -#define SM8350_SLAVE_BOOT_IMEM 128 -#define SM8350_SLAVE_IMEM 129 -#define SM8350_SLAVE_PIMEM 130 -#define SM8350_SLAVE_SERVICE_NSP_NOC 131 -#define SM8350_SLAVE_SERVICE_A1NOC 132 -#define SM8350_SLAVE_SERVICE_A2NOC 133 -#define SM8350_SLAVE_SERVICE_CNOC 134 -#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135 -#define SM8350_SLAVE_SERVICE_MNOC 136 -#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137 -#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138 -#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139 -#define SM8350_SLAVE_SERVICE_SNOC 140 -#define SM8350_SLAVE_SERVICE_GEM_NOC 141 -#define SM8350_SLAVE_PCIE_0 142 -#define SM8350_SLAVE_PCIE_1 143 -#define SM8350_SLAVE_QDSS_STM 144 -#define SM8350_SLAVE_TCU 145 - -#endif From 51513bec806fbe1cf9254baed97f115a480bbb53 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:37 +0200 Subject: [PATCH 156/304] interconnect: qcom: sm8450: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-21-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8450.c | 612 +++++++++++++---------------- drivers/interconnect/qcom/sm8450.h | 169 -------- 2 files changed, 280 insertions(+), 501 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm8450.h diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index eb7e17df32ba..dd61e03b5a81 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -16,1325 +16,1262 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8450.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sensorss_q6; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_rot; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_mnoc_hf_disp; +static struct qcom_icc_node qnm_mnoc_sf_disp; +static struct qcom_icc_node qnm_pcie_disp; +static struct qcom_icc_node llcc_mc_disp; +static struct qcom_icc_node qnm_mdp_disp; +static struct qcom_icc_node qnm_rot_disp; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node qns_llcc_disp; +static struct qcom_icc_node ebi_disp; +static struct qcom_icc_node qns_mem_noc_hf_disp; +static struct qcom_icc_node qns_mem_noc_sf_disp; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8450_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8450_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SM8450_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8450_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8450_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8450_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8450_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8450_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8450_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SM8450_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8450_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8450_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sensorss_q6 = { .name = "qxm_sensorss_q6", - .id = SM8450_MASTER_SENSORS_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8450_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8450_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8450_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8450_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8450_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8450_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8450_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8450_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 51, - .links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH, - SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG, - SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG, - SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG, - SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG, - SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM, - SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG, - SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG, - SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS, - SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM, - SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG, - SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG, - SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG, - SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0, - SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2, - SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4, - SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR, - SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG, - SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0, - SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG, - SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG, - SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG, - SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG, - SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM, - SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM, - SM8450_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_compute_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_ddrss_cfg, &qns_mnoc_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8450_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8450_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8450_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8450_MASTER_APPSS_PROC, .channels = 3, .buswidth = 32, .num_links = 3, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8450_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8450_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8450_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8450_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8450_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8450_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8450_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SM8450_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG, - SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG, - SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = SM8450_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC, - SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8450_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8450_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8450_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8450_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8450_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SM8450_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_rot = { .name = "qnm_rot", - .id = SM8450_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8450_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SM8450_MASTER_VIDEO, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8450_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8450_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8450_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SM8450_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SM8450_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_pcie_anoc_cfg = { .name = "qnm_pcie_anoc_cfg", - .id = SM8450_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8450_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8450_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SM8450_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8450_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8450_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = SM8450_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SM8450_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8450_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8450_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qnm_mnoc_hf_disp = { .name = "qnm_mnoc_hf_disp", - .id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_LLCC_DISP }, + .link_nodes = { &qns_llcc_disp }, }; static struct qcom_icc_node qnm_mnoc_sf_disp = { .name = "qnm_mnoc_sf_disp", - .id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_LLCC_DISP }, + .link_nodes = { &qns_llcc_disp }, }; static struct qcom_icc_node qnm_pcie_disp = { .name = "qnm_pcie_disp", - .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_LLCC_DISP }, + .link_nodes = { &qns_llcc_disp }, }; static struct qcom_icc_node llcc_mc_disp = { .name = "llcc_mc_disp", - .id = SM8450_MASTER_LLCC_DISP, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_EBI1_DISP }, + .link_nodes = { &ebi_disp }, }; static struct qcom_icc_node qnm_mdp_disp = { .name = "qnm_mdp_disp", - .id = SM8450_MASTER_MDP_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP }, + .link_nodes = { &qns_mem_noc_hf_disp }, }; static struct qcom_icc_node qnm_rot_disp = { .name = "qnm_rot_disp", - .id = SM8450_MASTER_ROTATOR_DISP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP }, + .link_nodes = { &qns_mem_noc_sf_disp }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8450_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8450_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8450_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8450_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8450_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8450_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8450_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8450_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8450_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8450_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8450_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8450_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SM8450_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { MASTER_CDSP_NOC_CFG }, + .link_nodes = { MASTER_CDSP_NOC_CFG }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8450_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8450_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SM8450_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SM8450_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8450_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8450_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8450_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8450_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8450_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8450_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8450_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SM8450_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { MASTER_CNOC_LPASS_AG_NOC }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8450_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8450_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8450_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8450_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8450_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8450_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8450_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8450_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8450_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM8450_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8450_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8450_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8450_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8450_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8450_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8450_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8450_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8450_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8450_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8450_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8450_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8450_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SM8450_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_A1NOC_CFG }, + .link_nodes = { &qnm_a1noc_cfg }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SM8450_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_A2NOC_CFG }, + .link_nodes = { &qnm_a2noc_cfg }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SM8450_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 1, //FIXME where is link }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SM8450_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_pcie_anoc_cfg = { .name = "qns_pcie_anoc_cfg", - .id = SM8450_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qnm_pcie_anoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SM8450_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8450_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8450_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8450_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8450_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8450_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8450_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8450_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8450_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8450_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SM8450_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SM8450_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SM8450_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SM8450_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = SM8450_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8450_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8450_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8450_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8450_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8450_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SM8450_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8450_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8450_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8450_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8450_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_llcc_disp = { .name = "qns_llcc_disp", - .id = SM8450_SLAVE_LLCC_DISP, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_LLCC_DISP }, + .link_nodes = { &llcc_mc_disp }, }; static struct qcom_icc_node ebi_disp = { .name = "ebi_disp", - .id = SM8450_SLAVE_EBI1_DISP, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf_disp = { .name = "qns_mem_noc_hf_disp", - .id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP }, + .link_nodes = { &qnm_mnoc_hf_disp }, }; static struct qcom_icc_node qns_mem_noc_sf_disp = { .name = "qns_mem_noc_sf_disp", - .id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP }, + .link_nodes = { &qnm_mnoc_sf_disp }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1553,6 +1490,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1580,6 +1518,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1602,6 +1541,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8450_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1671,6 +1611,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1706,6 +1647,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1728,6 +1670,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1749,6 +1692,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8450_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1784,6 +1728,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1802,6 +1747,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_nsp_noc = { + .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1821,6 +1767,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8450_pcie_anoc = { + .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1849,6 +1796,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8450.h b/drivers/interconnect/qcom/sm8450.h deleted file mode 100644 index a5790ec6767b..000000000000 --- a/drivers/interconnect/qcom/sm8450.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8450 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H - -#define SM8450_MASTER_GPU_TCU 0 -#define SM8450_MASTER_SYS_TCU 1 -#define SM8450_MASTER_APPSS_PROC 2 -#define SM8450_MASTER_LLCC 3 -#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4 -#define SM8450_MASTER_GIC_AHB 5 -#define SM8450_MASTER_CDSP_NOC_CFG 6 -#define SM8450_MASTER_QDSS_BAM 7 -#define SM8450_MASTER_QSPI_0 8 -#define SM8450_MASTER_QUP_0 9 -#define SM8450_MASTER_QUP_1 10 -#define SM8450_MASTER_QUP_2 11 -#define SM8450_MASTER_A1NOC_CFG 12 -#define SM8450_MASTER_A2NOC_CFG 13 -#define SM8450_MASTER_A1NOC_SNOC 14 -#define SM8450_MASTER_A2NOC_SNOC 15 -#define SM8450_MASTER_CAMNOC_HF 16 -#define SM8450_MASTER_CAMNOC_ICP 17 -#define SM8450_MASTER_CAMNOC_SF 18 -#define SM8450_MASTER_GEM_NOC_CNOC 19 -#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20 -#define SM8450_MASTER_GFX3D 21 -#define SM8450_MASTER_LPASS_ANOC 22 -#define SM8450_MASTER_MDP 23 -#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP -#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP -#define SM8450_MASTER_MSS_PROC 24 -#define SM8450_MASTER_CNOC_MNOC_CFG 25 -#define SM8450_MASTER_MNOC_HF_MEM_NOC 26 -#define SM8450_MASTER_MNOC_SF_MEM_NOC 27 -#define SM8450_MASTER_COMPUTE_NOC 28 -#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29 -#define SM8450_MASTER_PCIE_ANOC_CFG 30 -#define SM8450_MASTER_ROTATOR 31 -#define SM8450_MASTER_SNOC_CFG 32 -#define SM8450_MASTER_SNOC_GC_MEM_NOC 33 -#define SM8450_MASTER_SNOC_SF_MEM_NOC 34 -#define SM8450_MASTER_CDSP_HCP 35 -#define SM8450_MASTER_VIDEO 36 -#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO -#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO -#define SM8450_MASTER_VIDEO_CV_PROC 37 -#define SM8450_MASTER_VIDEO_PROC 38 -#define SM8450_MASTER_VIDEO_V_PROC 39 -#define SM8450_MASTER_QUP_CORE_0 40 -#define SM8450_MASTER_QUP_CORE_1 41 -#define SM8450_MASTER_QUP_CORE_2 42 -#define SM8450_MASTER_CRYPTO 43 -#define SM8450_MASTER_IPA 44 -#define SM8450_MASTER_LPASS_PROC 45 -#define SM8450_MASTER_CDSP_PROC 46 -#define SM8450_MASTER_PIMEM 47 -#define SM8450_MASTER_SENSORS_PROC 48 -#define SM8450_MASTER_SP 49 -#define SM8450_MASTER_GIC 50 -#define SM8450_MASTER_PCIE_0 51 -#define SM8450_MASTER_PCIE_1 52 -#define SM8450_MASTER_QDSS_ETR 53 -#define SM8450_MASTER_QDSS_ETR_1 54 -#define SM8450_MASTER_SDCC_2 55 -#define SM8450_MASTER_SDCC_4 56 -#define SM8450_MASTER_UFS_MEM 57 -#define SM8450_MASTER_USB3_0 58 -#define SM8450_SLAVE_EBI1 512 -#define SM8450_SLAVE_AHB2PHY_SOUTH 513 -#define SM8450_SLAVE_AHB2PHY_NORTH 514 -#define SM8450_SLAVE_AOSS 515 -#define SM8450_SLAVE_CAMERA_CFG 516 -#define SM8450_SLAVE_CLK_CTL 517 -#define SM8450_SLAVE_CDSP_CFG 518 -#define SM8450_SLAVE_RBCPR_CX_CFG 519 -#define SM8450_SLAVE_RBCPR_MMCX_CFG 520 -#define SM8450_SLAVE_RBCPR_MXA_CFG 521 -#define SM8450_SLAVE_RBCPR_MXC_CFG 522 -#define SM8450_SLAVE_CRYPTO_0_CFG 523 -#define SM8450_SLAVE_CX_RDPM 524 -#define SM8450_SLAVE_DISPLAY_CFG 525 -#define SM8450_SLAVE_GFX3D_CFG 526 -#define SM8450_SLAVE_IMEM_CFG 527 -#define SM8450_SLAVE_IPA_CFG 528 -#define SM8450_SLAVE_IPC_ROUTER_CFG 529 -#define SM8450_SLAVE_LPASS 530 -#define SM8450_SLAVE_LPASS_CORE_CFG 531 -#define SM8450_SLAVE_LPASS_LPI_CFG 532 -#define SM8450_SLAVE_LPASS_MPU_CFG 533 -#define SM8450_SLAVE_LPASS_TOP_CFG 534 -#define SM8450_SLAVE_CNOC_MSS 535 -#define SM8450_SLAVE_MX_RDPM 536 -#define SM8450_SLAVE_PCIE_0_CFG 537 -#define SM8450_SLAVE_PCIE_1_CFG 538 -#define SM8450_SLAVE_PDM 539 -#define SM8450_SLAVE_PIMEM_CFG 540 -#define SM8450_SLAVE_PRNG 541 -#define SM8450_SLAVE_QDSS_CFG 542 -#define SM8450_SLAVE_QSPI_0 543 -#define SM8450_SLAVE_QUP_0 544 -#define SM8450_SLAVE_QUP_1 545 -#define SM8450_SLAVE_QUP_2 546 -#define SM8450_SLAVE_SDCC_2 547 -#define SM8450_SLAVE_SDCC_4 548 -#define SM8450_SLAVE_SPSS_CFG 549 -#define SM8450_SLAVE_TCSR 550 -#define SM8450_SLAVE_TLMM 551 -#define SM8450_SLAVE_TME_CFG 552 -#define SM8450_SLAVE_UFS_MEM_CFG 553 -#define SM8450_SLAVE_USB3_0 554 -#define SM8450_SLAVE_VENUS_CFG 555 -#define SM8450_SLAVE_VSENSE_CTRL_CFG 556 -#define SM8450_SLAVE_A1NOC_CFG 557 -#define SM8450_SLAVE_A1NOC_SNOC 558 -#define SM8450_SLAVE_A2NOC_CFG 559 -#define SM8450_SLAVE_A2NOC_SNOC 560 -#define SM8450_SLAVE_DDRSS_CFG 561 -#define SM8450_SLAVE_GEM_NOC_CNOC 562 -#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563 -#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564 -#define SM8450_SLAVE_LLCC 565 -#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566 -#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567 -#define SM8450_SLAVE_CNOC_MNOC_CFG 568 -#define SM8450_SLAVE_CDSP_MEM_NOC 569 -#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570 -#define SM8450_SLAVE_PCIE_ANOC_CFG 571 -#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572 -#define SM8450_SLAVE_SNOC_CFG 573 -#define SM8450_SLAVE_LPASS_SNOC 574 -#define SM8450_SLAVE_QUP_CORE_0 575 -#define SM8450_SLAVE_QUP_CORE_1 576 -#define SM8450_SLAVE_QUP_CORE_2 577 -#define SM8450_SLAVE_IMEM 578 -#define SM8450_SLAVE_PIMEM 579 -#define SM8450_SLAVE_SERVICE_NSP_NOC 580 -#define SM8450_SLAVE_SERVICE_A1NOC 581 -#define SM8450_SLAVE_SERVICE_A2NOC 582 -#define SM8450_SLAVE_SERVICE_CNOC 583 -#define SM8450_SLAVE_SERVICE_MNOC 584 -#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585 -#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586 -#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587 -#define SM8450_SLAVE_SERVICE_SNOC 588 -#define SM8450_SLAVE_PCIE_0 589 -#define SM8450_SLAVE_PCIE_1 590 -#define SM8450_SLAVE_QDSS_STM 591 -#define SM8450_SLAVE_TCU 592 -#define SM8450_MASTER_LLCC_DISP 1000 -#define SM8450_MASTER_MDP_DISP 1001 -#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP -#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP -#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002 -#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003 -#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004 -#define SM8450_MASTER_ROTATOR_DISP 1005 -#define SM8450_SLAVE_EBI1_DISP 1512 -#define SM8450_SLAVE_LLCC_DISP 1513 -#define SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP 1514 -#define SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP 1515 - -#endif From e987b4c0d7945511d0b3cea9316c2d0ebd7a8b07 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:38 +0200 Subject: [PATCH 157/304] interconnect: qcom: sm8550: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Tested-by: Neil Armstrong # on QRD8550 Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-22-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8550.c | 515 +++++++++++++---------------- drivers/interconnect/qcom/sm8550.h | 138 -------- 2 files changed, 237 insertions(+), 416 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm8550.h diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index fdb97d1f1d07..24b682a5bdd1 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -18,1103 +18,1048 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8550.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_lpass_qtb_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8550_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8550_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8550_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8550_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8550_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8550_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8550_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8550_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8550_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8550_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8550_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8550_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8550_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8550_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8550_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8550_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = SM8550_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 44, - .links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH, - SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG, - SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG, - SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG, - SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX, - SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM, - SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG, - SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG, - SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG, - SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM, - SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG, - SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG, - SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG, - SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1, - SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2, - SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG, - SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM, - SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0, - SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG, - SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG, - SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG, - SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_apss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8550_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG, - SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG, - SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM }, + .link_nodes = { &qhs_aoss, &qhs_tme_cfg, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8550_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8550_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8550_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8550_MASTER_APPSS_PROC, .channels = 3, .buswidth = 32, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8550_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_lpass_gemnoc = { .name = "qnm_lpass_gemnoc", - .id = SM8550_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8550_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8550_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8550_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8550_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8550_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8550_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = SM8550_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = SM8550_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qxm_lpinoc_dsp_axim = { .name = "qxm_lpinoc_dsp_axim", - .id = SM8550_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8550_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8550_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8550_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8550_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8550_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8550_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SM8550_MASTER_VIDEO, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8550_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8550_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8550_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = SM8550_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SM8550_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qsm_pcie_anoc_cfg = { .name = "qsm_pcie_anoc_cfg", - .id = SM8550_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8550_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8550_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SM8550_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8550_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8550_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8550_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8550_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8550_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8550_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8550_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8550_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8550_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8550_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8550_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8550_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8550_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8550_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8550_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SM8550_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SM8550_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SM8550_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8550_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8550_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8550_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8550_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_i2c = { .name = "qhs_i2c", - .id = SM8550_SLAVE_I2C, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8550_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8550_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8550_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8550_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8550_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8550_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8550_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8550_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8550_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8550_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8550_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8550_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8550_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8550_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8550_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8550_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8550_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8550_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8550_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8550_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8550_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8550_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8550_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_lpass_qtb_cfg = { .name = "qss_lpass_qtb_cfg", - .id = SM8550_SLAVE_LPASS_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = SM8550_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { .name = "qss_nsp_qtb_cfg", - .id = SM8550_SLAVE_NSP_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_pcie_anoc_cfg = { .name = "qss_pcie_anoc_cfg", - .id = SM8550_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qsm_pcie_anoc_cfg }, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8550_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8550_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8550_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8550_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = SM8550_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qss_ddrss_cfg = { .name = "qss_ddrss_cfg", - .id = SM8550_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SM8550_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8550_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8550_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8550_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8550_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8550_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = SM8550_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass_gemnoc }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8550_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8550_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8550_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8550_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8550_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8550_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8550_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8550_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1296,6 +1241,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1319,6 +1265,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1341,6 +1288,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8550_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1401,6 +1349,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1425,6 +1374,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8550_cnoc_main = { + .alloc_dyn_id = true, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1455,6 +1405,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1470,6 +1421,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1486,6 +1438,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = { + .alloc_dyn_id = true, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1501,6 +1454,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = { + .alloc_dyn_id = true, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms = lpass_lpicx_noc_bcms, @@ -1518,6 +1472,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8550_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1546,6 +1501,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1562,6 +1518,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_nsp_noc = { + .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1581,6 +1538,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8550_pcie_anoc = { + .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1604,6 +1562,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8550.h b/drivers/interconnect/qcom/sm8550.h deleted file mode 100644 index c9b2986e1293..000000000000 --- a/drivers/interconnect/qcom/sm8550.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8450 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H - -#define SM8550_MASTER_A1NOC_SNOC 0 -#define SM8550_MASTER_A2NOC_SNOC 1 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8550_MASTER_APPSS_PROC 3 -#define SM8550_MASTER_CAMNOC_HF 4 -#define SM8550_MASTER_CAMNOC_ICP 5 -#define SM8550_MASTER_CAMNOC_SF 6 -#define SM8550_MASTER_CDSP_HCP 7 -#define SM8550_MASTER_CDSP_PROC 8 -#define SM8550_MASTER_CNOC_CFG 9 -#define SM8550_MASTER_CNOC_MNOC_CFG 10 -#define SM8550_MASTER_COMPUTE_NOC 11 -#define SM8550_MASTER_CRYPTO 12 -#define SM8550_MASTER_GEM_NOC_CNOC 13 -#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14 -#define SM8550_MASTER_GFX3D 15 -#define SM8550_MASTER_GIC 16 -#define SM8550_MASTER_GIC_AHB 17 -#define SM8550_MASTER_GPU_TCU 18 -#define SM8550_MASTER_IPA 19 -#define SM8550_MASTER_LLCC 20 -#define SM8550_MASTER_LPASS_GEM_NOC 21 -#define SM8550_MASTER_LPASS_LPINOC 22 -#define SM8550_MASTER_LPASS_PROC 23 -#define SM8550_MASTER_LPIAON_NOC 24 -#define SM8550_MASTER_MDP 25 -#define SM8550_MASTER_MNOC_HF_MEM_NOC 26 -#define SM8550_MASTER_MNOC_SF_MEM_NOC 27 -#define SM8550_MASTER_MSS_PROC 28 -#define SM8550_MASTER_PCIE_0 29 -#define SM8550_MASTER_PCIE_1 30 -#define SM8550_MASTER_PCIE_ANOC_CFG 31 -#define SM8550_MASTER_QDSS_BAM 32 -#define SM8550_MASTER_QDSS_ETR 33 -#define SM8550_MASTER_QDSS_ETR_1 34 -#define SM8550_MASTER_QSPI_0 35 -#define SM8550_MASTER_QUP_1 36 -#define SM8550_MASTER_QUP_2 37 -#define SM8550_MASTER_QUP_CORE_0 38 -#define SM8550_MASTER_QUP_CORE_1 39 -#define SM8550_MASTER_QUP_CORE_2 40 -#define SM8550_MASTER_SDCC_2 41 -#define SM8550_MASTER_SDCC_4 42 -#define SM8550_MASTER_SNOC_GC_MEM_NOC 43 -#define SM8550_MASTER_SNOC_SF_MEM_NOC 44 -#define SM8550_MASTER_SP 45 -#define SM8550_MASTER_SYS_TCU 46 -#define SM8550_MASTER_UFS_MEM 47 -#define SM8550_MASTER_USB3_0 48 -#define SM8550_MASTER_VIDEO 49 -#define SM8550_MASTER_VIDEO_CV_PROC 50 -#define SM8550_MASTER_VIDEO_PROC 51 -#define SM8550_MASTER_VIDEO_V_PROC 52 -#define SM8550_SLAVE_A1NOC_SNOC 53 -#define SM8550_SLAVE_A2NOC_SNOC 54 -#define SM8550_SLAVE_AHB2PHY_NORTH 55 -#define SM8550_SLAVE_AHB2PHY_SOUTH 56 -#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57 -#define SM8550_SLAVE_AOSS 58 -#define SM8550_SLAVE_APPSS 59 -#define SM8550_SLAVE_BOOT_IMEM 60 -#define SM8550_SLAVE_CAMERA_CFG 61 -#define SM8550_SLAVE_CDSP_MEM_NOC 62 -#define SM8550_SLAVE_CLK_CTL 63 -#define SM8550_SLAVE_CNOC_CFG 64 -#define SM8550_SLAVE_CNOC_MNOC_CFG 65 -#define SM8550_SLAVE_CNOC_MSS 66 -#define SM8550_SLAVE_CPR_NSPCX 67 -#define SM8550_SLAVE_CRYPTO_0_CFG 68 -#define SM8550_SLAVE_CX_RDPM 69 -#define SM8550_SLAVE_DDRSS_CFG 70 -#define SM8550_SLAVE_DISPLAY_CFG 71 -#define SM8550_SLAVE_EBI1 72 -#define SM8550_SLAVE_GEM_NOC_CNOC 73 -#define SM8550_SLAVE_GFX3D_CFG 74 -#define SM8550_SLAVE_I2C 75 -#define SM8550_SLAVE_IMEM 76 -#define SM8550_SLAVE_IMEM_CFG 77 -#define SM8550_SLAVE_IPA_CFG 78 -#define SM8550_SLAVE_IPC_ROUTER_CFG 79 -#define SM8550_SLAVE_LLCC 80 -#define SM8550_SLAVE_LPASS_GEM_NOC 81 -#define SM8550_SLAVE_LPASS_QTB_CFG 82 -#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83 -#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84 -#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87 -#define SM8550_SLAVE_MX_RDPM 88 -#define SM8550_SLAVE_NSP_QTB_CFG 89 -#define SM8550_SLAVE_PCIE_0 90 -#define SM8550_SLAVE_PCIE_0_CFG 91 -#define SM8550_SLAVE_PCIE_1 92 -#define SM8550_SLAVE_PCIE_1_CFG 93 -#define SM8550_SLAVE_PCIE_ANOC_CFG 94 -#define SM8550_SLAVE_PDM 95 -#define SM8550_SLAVE_PIMEM_CFG 96 -#define SM8550_SLAVE_PRNG 97 -#define SM8550_SLAVE_QDSS_CFG 98 -#define SM8550_SLAVE_QDSS_STM 99 -#define SM8550_SLAVE_QSPI_0 100 -#define SM8550_SLAVE_QUP_1 101 -#define SM8550_SLAVE_QUP_2 102 -#define SM8550_SLAVE_QUP_CORE_0 103 -#define SM8550_SLAVE_QUP_CORE_1 104 -#define SM8550_SLAVE_QUP_CORE_2 105 -#define SM8550_SLAVE_RBCPR_CX_CFG 106 -#define SM8550_SLAVE_RBCPR_MMCX_CFG 107 -#define SM8550_SLAVE_RBCPR_MXA_CFG 108 -#define SM8550_SLAVE_RBCPR_MXC_CFG 109 -#define SM8550_SLAVE_SDCC_2 110 -#define SM8550_SLAVE_SDCC_4 111 -#define SM8550_SLAVE_SERVICE_MNOC 112 -#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113 -#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114 -#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115 -#define SM8550_SLAVE_SPSS_CFG 116 -#define SM8550_SLAVE_TCSR 117 -#define SM8550_SLAVE_TCU 118 -#define SM8550_SLAVE_TLMM 119 -#define SM8550_SLAVE_TME_CFG 120 -#define SM8550_SLAVE_UFS_MEM_CFG 121 -#define SM8550_SLAVE_USB3_0 122 -#define SM8550_SLAVE_VENUS_CFG 123 -#define SM8550_SLAVE_VSENSE_CTRL_CFG 124 - -#endif From 82a0106a809217c474084f307038e9b644a35fe5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:39 +0200 Subject: [PATCH 158/304] interconnect: qcom: sm8650: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Tested-by: Neil Armstrong # on QRD8650 Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-23-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8650.c | 541 +++++++++++++---------------- drivers/interconnect/qcom/sm8650.h | 144 -------- 2 files changed, 247 insertions(+), 438 deletions(-) delete mode 100644 drivers/interconnect/qcom/sm8650.h diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c index b7c321f4e4b5..629ff30e7ee7 100644 --- a/drivers/interconnect/qcom/sm8650.c +++ b/drivers/interconnect/qcom/sm8650.c @@ -15,8 +15,138 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8650.h" +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node alm_ubwc_p_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_apss_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_hmx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_2_rdpm; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node srvc_cnoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; static const struct regmap_config icc_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -34,12 +164,11 @@ static struct qcom_icc_qosbox qhm_qspi_qos = { static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8650_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .qosbox = &qhm_qspi_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox qhm_qup1_qos = { @@ -52,21 +181,19 @@ static struct qcom_icc_qosbox qhm_qup1_qos = { static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8650_MASTER_QUP_1, .channels = 1, .buswidth = 4, .qosbox = &qhm_qup1_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_qup02 = { .name = "qxm_qup02", - .id = SM8650_MASTER_QUP_3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox xm_sdc4_qos = { @@ -79,12 +206,11 @@ static struct qcom_icc_qosbox xm_sdc4_qos = { static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8650_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .qosbox = &xm_sdc4_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox xm_ufs_mem_qos = { @@ -97,12 +223,11 @@ static struct qcom_icc_qosbox xm_ufs_mem_qos = { static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8650_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, .qosbox = &xm_ufs_mem_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox xm_usb3_0_qos = { @@ -115,12 +240,11 @@ static struct qcom_icc_qosbox xm_usb3_0_qos = { static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8650_MASTER_USB3_0, .channels = 1, .buswidth = 8, .qosbox = &xm_usb3_0_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_qosbox qhm_qdss_bam_qos = { @@ -133,12 +257,11 @@ static struct qcom_icc_qosbox qhm_qdss_bam_qos = { static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8650_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .qosbox = &qhm_qdss_bam_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qhm_qup2_qos = { @@ -151,12 +274,11 @@ static struct qcom_icc_qosbox qhm_qup2_qos = { static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8650_MASTER_QUP_2, .channels = 1, .buswidth = 4, .qosbox = &qhm_qup2_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qxm_crypto_qos = { @@ -169,12 +291,11 @@ static struct qcom_icc_qosbox qxm_crypto_qos = { static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8650_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .qosbox = &qxm_crypto_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox qxm_ipa_qos = { @@ -187,21 +308,19 @@ static struct qcom_icc_qosbox qxm_ipa_qos = { static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8650_MASTER_IPA, .channels = 1, .buswidth = 8, .qosbox = &qxm_ipa_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8650_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { @@ -214,12 +333,11 @@ static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8650_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .qosbox = &xm_qdss_etr_0_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { @@ -232,12 +350,11 @@ static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8650_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .qosbox = &xm_qdss_etr_1_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_qosbox xm_sdc2_qos = { @@ -250,92 +367,85 @@ static struct qcom_icc_qosbox xm_sdc2_qos = { static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8650_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .qosbox = &xm_sdc2_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8650_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8650_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8650_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = SM8650_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 46, - .links = { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH, - SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL, - SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX, - SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG, - SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX, - SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM, - SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG, - SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG, - SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG, - SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM, - SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG, - SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC, - SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG, - SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0, - SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1, - SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2, - SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG, - SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM, - SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0, - SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG, - SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG, - SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG, - SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_hmx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_mx_2_rdpm, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup02, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_cfg, &qss_nsp_qtb_cfg, + &qss_pcie_anoc_cfg, &srvc_cnoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8650_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG, - SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG, - SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG, - SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM, - SM8650_SLAVE_SERVICE_CNOC }, + .link_nodes = { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_tme_cfg, + &qss_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem, + &srvc_cnoc_main }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8650_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_qosbox alm_gpu_tcu_qos = { @@ -348,12 +458,11 @@ static struct qcom_icc_qosbox alm_gpu_tcu_qos = { static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8650_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .qosbox = &alm_gpu_tcu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox alm_sys_tcu_qos = { @@ -366,12 +475,11 @@ static struct qcom_icc_qosbox alm_sys_tcu_qos = { static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8650_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .qosbox = &alm_sys_tcu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = { @@ -384,22 +492,20 @@ static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = { static struct qcom_icc_node alm_ubwc_p_tcu = { .name = "alm_ubwc_p_tcu", - .id = SM8650_MASTER_UBWC_P_TCU, .channels = 1, .buswidth = 8, .qosbox = &alm_ubwc_p_tcu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8650_MASTER_APPSS_PROC, .channels = 3, .buswidth = 32, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_qosbox qnm_gpu_qos = { @@ -412,12 +518,11 @@ static struct qcom_icc_qosbox qnm_gpu_qos = { static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8650_MASTER_GFX3D, .channels = 2, .buswidth = 32, .qosbox = &qnm_gpu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { @@ -430,23 +535,21 @@ static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { static struct qcom_icc_node qnm_lpass_gemnoc = { .name = "qnm_lpass_gemnoc", - .id = SM8650_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &qnm_lpass_gemnoc_qos, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8650_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { @@ -459,12 +562,11 @@ static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8650_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { @@ -477,12 +579,11 @@ static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8650_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { @@ -495,13 +596,12 @@ static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8650_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .qosbox = &qnm_nsp_gemnoc_qos, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_qosbox qnm_pcie_qos = { @@ -514,12 +614,11 @@ static struct qcom_icc_qosbox qnm_pcie_qos = { static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8650_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &qnm_pcie_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_qosbox qnm_snoc_sf_qos = { @@ -532,13 +631,12 @@ static struct qcom_icc_qosbox qnm_snoc_sf_qos = { static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8650_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &qnm_snoc_sf_qos, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_qosbox qnm_ubwc_p_qos = { @@ -551,12 +649,11 @@ static struct qcom_icc_qosbox qnm_ubwc_p_qos = { static struct qcom_icc_node qnm_ubwc_p = { .name = "qnm_ubwc_p", - .id = SM8650_MASTER_UBWC_P, .channels = 1, .buswidth = 32, .qosbox = &qnm_ubwc_p_qos, .num_links = 1, - .links = { SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_qosbox xm_gic_qos = { @@ -569,48 +666,43 @@ static struct qcom_icc_qosbox xm_gic_qos = { static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8650_MASTER_GIC, .channels = 1, .buswidth = 8, .qosbox = &xm_gic_qos, .num_links = 1, - .links = { SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = SM8650_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = SM8650_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qxm_lpinoc_dsp_axim = { .name = "qxm_lpinoc_dsp_axim", - .id = SM8650_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8650_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { @@ -623,12 +715,11 @@ static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8650_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .qosbox = &qnm_camnoc_hf_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { @@ -641,12 +732,11 @@ static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8650_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .qosbox = &qnm_camnoc_icp_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { @@ -659,12 +749,11 @@ static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8650_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .qosbox = &qnm_camnoc_sf_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_mdp_qos = { @@ -677,21 +766,19 @@ static struct qcom_icc_qosbox qnm_mdp_qos = { static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8650_MASTER_MDP, .channels = 2, .buswidth = 32, .qosbox = &qnm_mdp_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8650_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_video_qos = { @@ -704,12 +791,11 @@ static struct qcom_icc_qosbox qnm_video_qos = { static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SM8650_MASTER_VIDEO, .channels = 2, .buswidth = 32, .qosbox = &qnm_video_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { @@ -722,12 +808,11 @@ static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8650_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .qosbox = &qnm_video_cv_cpu_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_video_cvp_qos = { @@ -740,12 +825,11 @@ static struct qcom_icc_qosbox qnm_video_cvp_qos = { static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8650_MASTER_VIDEO_PROC, .channels = 2, .buswidth = 32, .qosbox = &qnm_video_cvp_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_qosbox qnm_video_v_cpu_qos = { @@ -758,39 +842,35 @@ static struct qcom_icc_qosbox qnm_video_v_cpu_qos = { static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8650_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .qosbox = &qnm_video_v_cpu_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = SM8650_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_nsp = { .name = "qnm_nsp", - .id = SM8650_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qsm_pcie_anoc_cfg = { .name = "qsm_pcie_anoc_cfg", - .id = SM8650_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_qosbox xm_pcie3_0_qos = { @@ -803,12 +883,11 @@ static struct qcom_icc_qosbox xm_pcie3_0_qos = { static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8650_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .qosbox = &xm_pcie3_0_qos, .num_links = 1, - .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_qosbox xm_pcie3_1_qos = { @@ -821,30 +900,27 @@ static struct qcom_icc_qosbox xm_pcie3_1_qos = { static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8650_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .qosbox = &xm_pcie3_1_qos, .num_links = 1, - .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8650_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8650_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_qosbox qnm_apss_noc_qos = { @@ -857,636 +933,499 @@ static struct qcom_icc_qosbox qnm_apss_noc_qos = { static struct qcom_icc_node qnm_apss_noc = { .name = "qnm_apss_noc", - .id = SM8650_MASTER_APSS_NOC, .channels = 1, .buswidth = 4, .qosbox = &qnm_apss_noc_qos, .num_links = 1, - .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8650_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8650_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8650_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8650_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8650_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8650_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8650_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8650_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8650_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8650_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_hmx = { .name = "qhs_cpr_hmx", - .id = SM8650_SLAVE_CPR_HMX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8650_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SM8650_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SM8650_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SM8650_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8650_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8650_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8650_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8650_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_i2c = { .name = "qhs_i2c", - .id = SM8650_SLAVE_I2C, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_i3c_ibi0_cfg = { .name = "qhs_i3c_ibi0_cfg", - .id = SM8650_SLAVE_I3C_IBI0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_i3c_ibi1_cfg = { .name = "qhs_i3c_ibi1_cfg", - .id = SM8650_SLAVE_I3C_IBI1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8650_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8650_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_2_rdpm = { .name = "qhs_mx_2_rdpm", - .id = SM8650_SLAVE_MX_2_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8650_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8650_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8650_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rscc = { .name = "qhs_pcie_rscc", - .id = SM8650_SLAVE_PCIE_RSCC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8650_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8650_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8650_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8650_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup02 = { .name = "qhs_qup02", - .id = SM8650_SLAVE_QUP_3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8650_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8650_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8650_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8650_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8650_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8650_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8650_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8650_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8650_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8650_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8650_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = SM8650_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { .name = "qss_nsp_qtb_cfg", - .id = SM8650_SLAVE_NSP_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_pcie_anoc_cfg = { .name = "qss_pcie_anoc_cfg", - .id = SM8650_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qsm_pcie_anoc_cfg }, }; static struct qcom_icc_node srvc_cnoc_cfg = { .name = "srvc_cnoc_cfg", - .id = SM8650_SLAVE_SERVICE_CNOC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8650_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8650_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8650_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8650_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8650_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8650_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_apss = { .name = "qss_apss", - .id = SM8650_SLAVE_APPSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = SM8650_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qss_ddrss_cfg = { .name = "qss_ddrss_cfg", - .id = SM8650_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8650_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_cnoc_main = { .name = "srvc_cnoc_main", - .id = SM8650_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8650_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8650_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8650_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8650_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8650_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8650_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = SM8650_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass_gemnoc }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = SM8650_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8650_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8650_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8650_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8650_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8650_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8650_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8650_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8650_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1656,6 +1595,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_aggre1_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), @@ -1678,6 +1618,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_aggre2_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), @@ -1701,6 +1642,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8650_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1762,6 +1704,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_config_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), @@ -1790,6 +1733,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8650_cnoc_main = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), @@ -1823,6 +1767,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_gem_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), @@ -1836,6 +1781,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_ag_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1851,6 +1797,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), @@ -1864,6 +1811,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), @@ -1880,6 +1828,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8650_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1908,6 +1857,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_mmss_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), @@ -1925,6 +1875,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_nsp_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), @@ -1945,6 +1896,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8650_pcie_anoc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), @@ -1966,6 +1918,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_system_noc = { + .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sm8650.h b/drivers/interconnect/qcom/sm8650.h deleted file mode 100644 index b6610225b38a..000000000000 --- a/drivers/interconnect/qcom/sm8650.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8650 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H - -#define SM8650_MASTER_A1NOC_SNOC 0 -#define SM8650_MASTER_A2NOC_SNOC 1 -#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8650_MASTER_APPSS_PROC 3 -#define SM8650_MASTER_CAMNOC_HF 4 -#define SM8650_MASTER_CAMNOC_ICP 5 -#define SM8650_MASTER_CAMNOC_SF 6 -#define SM8650_MASTER_CDSP_HCP 7 -#define SM8650_MASTER_CDSP_PROC 8 -#define SM8650_MASTER_CNOC_CFG 9 -#define SM8650_MASTER_CNOC_MNOC_CFG 10 -#define SM8650_MASTER_COMPUTE_NOC 11 -#define SM8650_MASTER_CRYPTO 12 -#define SM8650_MASTER_GEM_NOC_CNOC 13 -#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14 -#define SM8650_MASTER_GFX3D 15 -#define SM8650_MASTER_GIC 16 -#define SM8650_MASTER_GPU_TCU 17 -#define SM8650_MASTER_IPA 18 -#define SM8650_MASTER_LLCC 19 -#define SM8650_MASTER_LPASS_GEM_NOC 20 -#define SM8650_MASTER_LPASS_LPINOC 21 -#define SM8650_MASTER_LPASS_PROC 22 -#define SM8650_MASTER_LPIAON_NOC 23 -#define SM8650_MASTER_MDP 24 -#define SM8650_MASTER_MNOC_HF_MEM_NOC 25 -#define SM8650_MASTER_MNOC_SF_MEM_NOC 26 -#define SM8650_MASTER_MSS_PROC 27 -#define SM8650_MASTER_PCIE_0 28 -#define SM8650_MASTER_PCIE_1 29 -#define SM8650_MASTER_PCIE_ANOC_CFG 30 -#define SM8650_MASTER_QDSS_BAM 31 -#define SM8650_MASTER_QDSS_ETR 32 -#define SM8650_MASTER_QDSS_ETR_1 33 -#define SM8650_MASTER_QSPI_0 34 -#define SM8650_MASTER_QUP_1 35 -#define SM8650_MASTER_QUP_2 36 -#define SM8650_MASTER_QUP_3 37 -#define SM8650_MASTER_QUP_CORE_0 38 -#define SM8650_MASTER_QUP_CORE_1 39 -#define SM8650_MASTER_QUP_CORE_2 40 -#define SM8650_MASTER_SDCC_2 41 -#define SM8650_MASTER_SDCC_4 42 -#define SM8650_MASTER_SNOC_SF_MEM_NOC 43 -#define SM8650_MASTER_SP 44 -#define SM8650_MASTER_SYS_TCU 45 -#define SM8650_MASTER_UBWC_P 46 -#define SM8650_MASTER_UBWC_P_TCU 47 -#define SM8650_MASTER_UFS_MEM 48 -#define SM8650_MASTER_USB3_0 49 -#define SM8650_MASTER_VIDEO 50 -#define SM8650_MASTER_VIDEO_CV_PROC 51 -#define SM8650_MASTER_VIDEO_PROC 52 -#define SM8650_MASTER_VIDEO_V_PROC 53 -#define SM8650_SLAVE_A1NOC_SNOC 54 -#define SM8650_SLAVE_A2NOC_SNOC 55 -#define SM8650_SLAVE_AHB2PHY_NORTH 56 -#define SM8650_SLAVE_AHB2PHY_SOUTH 57 -#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58 -#define SM8650_SLAVE_AOSS 59 -#define SM8650_SLAVE_APPSS 60 -#define SM8650_SLAVE_CAMERA_CFG 61 -#define SM8650_SLAVE_CDSP_MEM_NOC 62 -#define SM8650_SLAVE_CLK_CTL 63 -#define SM8650_SLAVE_CNOC_CFG 64 -#define SM8650_SLAVE_CNOC_MNOC_CFG 65 -#define SM8650_SLAVE_CNOC_MSS 66 -#define SM8650_SLAVE_CPR_HMX 67 -#define SM8650_SLAVE_CPR_NSPCX 68 -#define SM8650_SLAVE_CRYPTO_0_CFG 69 -#define SM8650_SLAVE_CX_RDPM 70 -#define SM8650_SLAVE_DDRSS_CFG 71 -#define SM8650_SLAVE_DISPLAY_CFG 72 -#define SM8650_SLAVE_EBI1 73 -#define SM8650_SLAVE_GEM_NOC_CNOC 74 -#define SM8650_SLAVE_GFX3D_CFG 75 -#define SM8650_SLAVE_I2C 76 -#define SM8650_SLAVE_I3C_IBI0_CFG 77 -#define SM8650_SLAVE_I3C_IBI1_CFG 78 -#define SM8650_SLAVE_IMEM 79 -#define SM8650_SLAVE_IMEM_CFG 80 -#define SM8650_SLAVE_IPA_CFG 81 -#define SM8650_SLAVE_IPC_ROUTER_CFG 82 -#define SM8650_SLAVE_LLCC 83 -#define SM8650_SLAVE_LPASS_GEM_NOC 84 -#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85 -#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86 -#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87 -#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88 -#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89 -#define SM8650_SLAVE_MX_2_RDPM 90 -#define SM8650_SLAVE_MX_RDPM 91 -#define SM8650_SLAVE_NSP_QTB_CFG 92 -#define SM8650_SLAVE_PCIE_0 93 -#define SM8650_SLAVE_PCIE_1 94 -#define SM8650_SLAVE_PCIE_0_CFG 95 -#define SM8650_SLAVE_PCIE_1_CFG 96 -#define SM8650_SLAVE_PCIE_ANOC_CFG 97 -#define SM8650_SLAVE_PCIE_RSCC 98 -#define SM8650_SLAVE_PDM 99 -#define SM8650_SLAVE_PRNG 100 -#define SM8650_SLAVE_QDSS_CFG 101 -#define SM8650_SLAVE_QDSS_STM 102 -#define SM8650_SLAVE_QSPI_0 103 -#define SM8650_SLAVE_QUP_1 104 -#define SM8650_SLAVE_QUP_2 105 -#define SM8650_SLAVE_QUP_3 106 -#define SM8650_SLAVE_QUP_CORE_0 107 -#define SM8650_SLAVE_QUP_CORE_1 108 -#define SM8650_SLAVE_QUP_CORE_2 109 -#define SM8650_SLAVE_RBCPR_CX_CFG 110 -#define SM8650_SLAVE_RBCPR_MMCX_CFG 111 -#define SM8650_SLAVE_RBCPR_MXA_CFG 112 -#define SM8650_SLAVE_RBCPR_MXC_CFG 113 -#define SM8650_SLAVE_SDCC_2 114 -#define SM8650_SLAVE_SDCC_4 115 -#define SM8650_SLAVE_SERVICE_CNOC 116 -#define SM8650_SLAVE_SERVICE_CNOC_CFG 117 -#define SM8650_SLAVE_SERVICE_MNOC 118 -#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119 -#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120 -#define SM8650_SLAVE_SPSS_CFG 121 -#define SM8650_SLAVE_TCSR 122 -#define SM8650_SLAVE_TCU 123 -#define SM8650_SLAVE_TLMM 124 -#define SM8650_SLAVE_TME_CFG 125 -#define SM8650_SLAVE_UFS_MEM_CFG 126 -#define SM8650_SLAVE_USB3_0 127 -#define SM8650_SLAVE_VENUS_CFG 128 -#define SM8650_SLAVE_VSENSE_CTRL_CFG 129 -#define SM8650_MASTER_APSS_NOC 130 - -#endif From 11660a5a20e4da5b05293ff7a404085d4a1a44d1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:40 +0200 Subject: [PATCH 159/304] interconnect: qcom: sm8750: convert to dynamic IDs Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-24-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8750.c | 616 +++++++++++------------------ 1 file changed, 230 insertions(+), 386 deletions(-) diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom/sm8750.c index 69bc22222075..a46c1553ce0f 100644 --- a/drivers/interconnect/qcom/sm8750.c +++ b/drivers/interconnect/qcom/sm8750.c @@ -14,1181 +14,1011 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#define SM8750_MASTER_GPU_TCU 0 -#define SM8750_MASTER_SYS_TCU 1 -#define SM8750_MASTER_APPSS_PROC 2 -#define SM8750_MASTER_LLCC 3 -#define SM8750_MASTER_QDSS_BAM 4 -#define SM8750_MASTER_QSPI_0 5 -#define SM8750_MASTER_QUP_1 6 -#define SM8750_MASTER_QUP_2 7 -#define SM8750_MASTER_A1NOC_SNOC 8 -#define SM8750_MASTER_A2NOC_SNOC 9 -#define SM8750_MASTER_CAMNOC_HF 10 -#define SM8750_MASTER_CAMNOC_NRT_ICP_SF 11 -#define SM8750_MASTER_CAMNOC_RT_CDM_SF 12 -#define SM8750_MASTER_CAMNOC_SF 13 -#define SM8750_MASTER_GEM_NOC_CNOC 14 -#define SM8750_MASTER_GEM_NOC_PCIE_SNOC 15 -#define SM8750_MASTER_GFX3D 16 -#define SM8750_MASTER_LPASS_GEM_NOC 17 -#define SM8750_MASTER_LPASS_LPINOC 18 -#define SM8750_MASTER_LPIAON_NOC 19 -#define SM8750_MASTER_LPASS_PROC 20 -#define SM8750_MASTER_MDP 21 -#define SM8750_MASTER_MSS_PROC 22 -#define SM8750_MASTER_MNOC_HF_MEM_NOC 23 -#define SM8750_MASTER_MNOC_SF_MEM_NOC 24 -#define SM8750_MASTER_CDSP_PROC 25 -#define SM8750_MASTER_COMPUTE_NOC 26 -#define SM8750_MASTER_ANOC_PCIE_GEM_NOC 27 -#define SM8750_MASTER_SNOC_SF_MEM_NOC 28 -#define SM8750_MASTER_UBWC_P 29 -#define SM8750_MASTER_CDSP_HCP 30 -#define SM8750_MASTER_VIDEO_CV_PROC 31 -#define SM8750_MASTER_VIDEO_EVA 32 -#define SM8750_MASTER_VIDEO_MVP 33 -#define SM8750_MASTER_VIDEO_V_PROC 34 -#define SM8750_MASTER_CNOC_CFG 35 -#define SM8750_MASTER_CNOC_MNOC_CFG 36 -#define SM8750_MASTER_PCIE_ANOC_CFG 37 -#define SM8750_MASTER_QUP_CORE_0 38 -#define SM8750_MASTER_QUP_CORE_1 39 -#define SM8750_MASTER_QUP_CORE_2 40 -#define SM8750_MASTER_CRYPTO 41 -#define SM8750_MASTER_IPA 42 -#define SM8750_MASTER_QUP_3 43 -#define SM8750_MASTER_SOCCP_AGGR_NOC 44 -#define SM8750_MASTER_SP 45 -#define SM8750_MASTER_GIC 46 -#define SM8750_MASTER_PCIE_0 47 -#define SM8750_MASTER_QDSS_ETR 48 -#define SM8750_MASTER_QDSS_ETR_1 49 -#define SM8750_MASTER_SDCC_2 50 -#define SM8750_MASTER_SDCC_4 51 -#define SM8750_MASTER_UFS_MEM 52 -#define SM8750_MASTER_USB3_0 53 -#define SM8750_SLAVE_UBWC_P 54 -#define SM8750_SLAVE_EBI1 55 -#define SM8750_SLAVE_AHB2PHY_SOUTH 56 -#define SM8750_SLAVE_AHB2PHY_NORTH 57 -#define SM8750_SLAVE_AOSS 58 -#define SM8750_SLAVE_CAMERA_CFG 59 -#define SM8750_SLAVE_CLK_CTL 60 -#define SM8750_SLAVE_CRYPTO_0_CFG 61 -#define SM8750_SLAVE_DISPLAY_CFG 62 -#define SM8750_SLAVE_EVA_CFG 63 -#define SM8750_SLAVE_GFX3D_CFG 64 -#define SM8750_SLAVE_I2C 65 -#define SM8750_SLAVE_I3C_IBI0_CFG 66 -#define SM8750_SLAVE_I3C_IBI1_CFG 67 -#define SM8750_SLAVE_IMEM_CFG 68 -#define SM8750_SLAVE_IPA_CFG 69 -#define SM8750_SLAVE_IPC_ROUTER_CFG 70 -#define SM8750_SLAVE_CNOC_MSS 71 -#define SM8750_SLAVE_PCIE_CFG 72 -#define SM8750_SLAVE_PRNG 73 -#define SM8750_SLAVE_QDSS_CFG 74 -#define SM8750_SLAVE_QSPI_0 75 -#define SM8750_SLAVE_QUP_3 76 -#define SM8750_SLAVE_QUP_1 77 -#define SM8750_SLAVE_QUP_2 78 -#define SM8750_SLAVE_SDCC_2 79 -#define SM8750_SLAVE_SDCC_4 80 -#define SM8750_SLAVE_SOCCP 81 -#define SM8750_SLAVE_SPSS_CFG 82 -#define SM8750_SLAVE_TCSR 83 -#define SM8750_SLAVE_TLMM 84 -#define SM8750_SLAVE_TME_CFG 85 -#define SM8750_SLAVE_UFS_MEM_CFG 86 -#define SM8750_SLAVE_USB3_0 87 -#define SM8750_SLAVE_VENUS_CFG 88 -#define SM8750_SLAVE_VSENSE_CTRL_CFG 89 -#define SM8750_SLAVE_A1NOC_SNOC 90 -#define SM8750_SLAVE_A2NOC_SNOC 91 -#define SM8750_SLAVE_APPSS 92 -#define SM8750_SLAVE_GEM_NOC_CNOC 93 -#define SM8750_SLAVE_SNOC_GEM_NOC_SF 94 -#define SM8750_SLAVE_LLCC 95 -#define SM8750_SLAVE_LPASS_GEM_NOC 96 -#define SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC 97 -#define SM8750_SLAVE_LPICX_NOC_LPIAON_NOC 98 -#define SM8750_SLAVE_MNOC_HF_MEM_NOC 99 -#define SM8750_SLAVE_MNOC_SF_MEM_NOC 100 -#define SM8750_SLAVE_CDSP_MEM_NOC 101 -#define SM8750_SLAVE_MEM_NOC_PCIE_SNOC 102 -#define SM8750_SLAVE_ANOC_PCIE_GEM_NOC 103 -#define SM8750_SLAVE_CNOC_CFG 104 -#define SM8750_SLAVE_DDRSS_CFG 105 -#define SM8750_SLAVE_CNOC_MNOC_CFG 106 -#define SM8750_SLAVE_PCIE_ANOC_CFG 107 -#define SM8750_SLAVE_QUP_CORE_0 108 -#define SM8750_SLAVE_QUP_CORE_1 109 -#define SM8750_SLAVE_QUP_CORE_2 110 -#define SM8750_SLAVE_BOOT_IMEM 111 -#define SM8750_SLAVE_IMEM 112 -#define SM8750_SLAVE_BOOT_IMEM_2 113 -#define SM8750_SLAVE_SERVICE_CNOC 114 -#define SM8750_SLAVE_SERVICE_MNOC 115 -#define SM8750_SLAVE_SERVICE_PCIE_ANOC 116 -#define SM8750_SLAVE_PCIE_0 117 -#define SM8750_SLAVE_QDSS_STM 118 -#define SM8750_SLAVE_TCU 119 +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_soccp; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf; +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_eva; +static struct qcom_icc_node qnm_video_mvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_eva_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_soccp; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_modem_boot_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node chs_ubwc_p; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8750_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8750_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_qup02 = { .name = "qxm_qup02", - .id = SM8750_MASTER_QUP_3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8750_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8750_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8750_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8750_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8750_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8750_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8750_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_soccp = { .name = "qxm_soccp", - .id = SM8750_MASTER_SOCCP_AGGR_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8750_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8750_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8750_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8750_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8750_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8750_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8750_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = SM8750_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 33, - .links = { SM8750_SLAVE_AHB2PHY_SOUTH, SM8750_SLAVE_AHB2PHY_NORTH, - SM8750_SLAVE_CAMERA_CFG, SM8750_SLAVE_CLK_CTL, - SM8750_SLAVE_CRYPTO_0_CFG, SM8750_SLAVE_DISPLAY_CFG, - SM8750_SLAVE_EVA_CFG, SM8750_SLAVE_GFX3D_CFG, - SM8750_SLAVE_I2C, SM8750_SLAVE_I3C_IBI0_CFG, - SM8750_SLAVE_I3C_IBI1_CFG, SM8750_SLAVE_IMEM_CFG, - SM8750_SLAVE_CNOC_MSS, SM8750_SLAVE_PCIE_CFG, - SM8750_SLAVE_PRNG, SM8750_SLAVE_QDSS_CFG, - SM8750_SLAVE_QSPI_0, SM8750_SLAVE_QUP_3, - SM8750_SLAVE_QUP_1, SM8750_SLAVE_QUP_2, - SM8750_SLAVE_SDCC_2, SM8750_SLAVE_SDCC_4, - SM8750_SLAVE_SPSS_CFG, SM8750_SLAVE_TCSR, - SM8750_SLAVE_TLMM, SM8750_SLAVE_UFS_MEM_CFG, - SM8750_SLAVE_USB3_0, SM8750_SLAVE_VENUS_CFG, - SM8750_SLAVE_VSENSE_CTRL_CFG, SM8750_SLAVE_CNOC_MNOC_CFG, - SM8750_SLAVE_PCIE_ANOC_CFG, SM8750_SLAVE_QDSS_STM, - SM8750_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup02, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8750_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 12, - .links = { SM8750_SLAVE_AOSS, SM8750_SLAVE_IPA_CFG, - SM8750_SLAVE_IPC_ROUTER_CFG, SM8750_SLAVE_SOCCP, - SM8750_SLAVE_TME_CFG, SM8750_SLAVE_APPSS, - SM8750_SLAVE_CNOC_CFG, SM8750_SLAVE_DDRSS_CFG, - SM8750_SLAVE_BOOT_IMEM, SM8750_SLAVE_IMEM, - SM8750_SLAVE_BOOT_IMEM_2, SM8750_SLAVE_SERVICE_CNOC }, + .link_nodes = { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_modem_boot_imem, &srvc_cnoc_main }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8750_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8750_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8750_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8750_MASTER_APPSS_PROC, .channels = 4, .buswidth = 32, .num_links = 4, - .links = { SM8750_SLAVE_UBWC_P, SM8750_SLAVE_GEM_NOC_CNOC, - SM8750_SLAVE_LLCC, SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &chs_ubwc_p, &qns_gem_noc_cnoc, + &qns_llcc, &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8750_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_lpass_gemnoc = { .name = "qnm_lpass_gemnoc", - .id = SM8750_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8750_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8750_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8750_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8750_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8750_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8750_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_ubwc_p = { .name = "qnm_ubwc_p", - .id = SM8750_MASTER_UBWC_P, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8750_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = SM8750_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = SM8750_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { .name = "qnm_lpinoc_dsp_qns4m", - .id = SM8750_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8750_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8750_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { .name = "qnm_camnoc_nrt_icp_sf", - .id = SM8750_MASTER_CAMNOC_NRT_ICP_SF, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { .name = "qnm_camnoc_rt_cdm_sf", - .id = SM8750_MASTER_CAMNOC_RT_CDM_SF, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8750_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8750_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8750_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8750_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_eva = { .name = "qnm_video_eva", - .id = SM8750_MASTER_VIDEO_EVA, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_mvp = { .name = "qnm_video_mvp", - .id = SM8750_MASTER_VIDEO_MVP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8750_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = SM8750_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_nsp = { .name = "qnm_nsp", - .id = SM8750_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qsm_pcie_anoc_cfg = { .name = "qsm_pcie_anoc_cfg", - .id = SM8750_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_node xm_pcie3 = { .name = "xm_pcie3", - .id = SM8750_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8750_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8750_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8750_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8750_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8750_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8750_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8750_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8750_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8750_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8750_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8750_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8750_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8750_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_eva_cfg = { .name = "qhs_eva_cfg", - .id = SM8750_SLAVE_EVA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8750_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_i2c = { .name = "qhs_i2c", - .id = SM8750_SLAVE_I2C, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_i3c_ibi0_cfg = { .name = "qhs_i3c_ibi0_cfg", - .id = SM8750_SLAVE_I3C_IBI0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_i3c_ibi1_cfg = { .name = "qhs_i3c_ibi1_cfg", - .id = SM8750_SLAVE_I3C_IBI1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8750_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8750_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_cfg = { .name = "qhs_pcie_cfg", - .id = SM8750_SLAVE_PCIE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8750_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8750_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8750_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup02 = { .name = "qhs_qup02", - .id = SM8750_SLAVE_QUP_3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8750_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8750_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8750_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8750_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8750_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8750_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8750_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8750_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8750_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8750_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8750_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = SM8750_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_pcie_anoc_cfg = { .name = "qss_pcie_anoc_cfg", - .id = SM8750_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qsm_pcie_anoc_cfg }, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8750_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8750_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8750_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8750_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8750_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_soccp = { .name = "qhs_soccp", - .id = SM8750_SLAVE_SOCCP, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8750_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_apss = { .name = "qns_apss", - .id = SM8750_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = SM8750_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8750_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qss_ddrss_cfg = { .name = "qss_ddrss_cfg", - .id = SM8750_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SM8750_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8750_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_modem_boot_imem = { .name = "qxs_modem_boot_imem", - .id = SM8750_SLAVE_BOOT_IMEM_2, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_cnoc_main = { .name = "srvc_cnoc_main", - .id = SM8750_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = SM8750_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node chs_ubwc_p = { .name = "chs_ubwc_p", - .id = SM8750_SLAVE_UBWC_P, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8750_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8750_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8750_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = SM8750_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass_gemnoc }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = SM8750_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8750_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8750_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8750_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8750_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8750_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8750_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8750_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8750_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8750_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8750_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8750_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1364,6 +1194,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_aggre1_noc = { + .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1386,6 +1217,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_aggre2_noc = { + .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1408,6 +1240,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8750_clk_virt = { + .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1457,6 +1290,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_config_noc = { + .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1486,6 +1320,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8750_cnoc_main = { + .alloc_dyn_id = true, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1519,6 +1354,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_gem_noc = { + .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1531,6 +1367,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_lpass_ag_noc = { + .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1545,6 +1382,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = { + .alloc_dyn_id = true, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1557,6 +1395,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = { + .alloc_dyn_id = true, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1572,6 +1411,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8750_mc_virt = { + .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1601,6 +1441,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_mmss_noc = { + .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1617,6 +1458,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_nsp_noc = { + .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1635,6 +1477,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8750_pcie_anoc = { + .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1654,6 +1497,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_system_noc = { + .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, From ed7a3886957af48e2cf7743c66925e1617205bda Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 31 Oct 2025 16:45:41 +0200 Subject: [PATCH 160/304] interconnect: qcom: icc-rpmh: drop support for non-dynamic IDS Now as all RPMh interconnect drivers were converted to using the dynamic IDs, drop support for non-dynamic ID allocation. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251031-rework-icc-v3-25-0575304c9624@oss.qualcomm.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/glymur.c | 21 --------------------- drivers/interconnect/qcom/icc-rpmh.c | 18 +++++------------- drivers/interconnect/qcom/icc-rpmh.h | 5 ----- drivers/interconnect/qcom/milos.c | 12 ------------ drivers/interconnect/qcom/qcs615.c | 8 -------- drivers/interconnect/qcom/qcs8300.c | 13 ------------- drivers/interconnect/qcom/qdu1000.c | 4 ---- drivers/interconnect/qcom/sa8775p.c | 14 -------------- drivers/interconnect/qcom/sar2130p.c | 9 --------- drivers/interconnect/qcom/sc7180.c | 12 ------------ drivers/interconnect/qcom/sc7280.c | 12 ------------ drivers/interconnect/qcom/sc8180x.c | 11 ----------- drivers/interconnect/qcom/sc8280xp.c | 12 ------------ drivers/interconnect/qcom/sdm670.c | 8 -------- drivers/interconnect/qcom/sdm845.c | 8 -------- drivers/interconnect/qcom/sdx55.c | 3 --- drivers/interconnect/qcom/sdx65.c | 3 --- drivers/interconnect/qcom/sdx75.c | 6 ------ drivers/interconnect/qcom/sm6350.c | 10 ---------- drivers/interconnect/qcom/sm7150.c | 10 ---------- drivers/interconnect/qcom/sm8150.c | 10 ---------- drivers/interconnect/qcom/sm8350.c | 10 ---------- drivers/interconnect/qcom/sm8450.c | 11 ----------- drivers/interconnect/qcom/sm8550.c | 14 -------------- drivers/interconnect/qcom/sm8650.c | 14 -------------- drivers/interconnect/qcom/sm8750.c | 14 -------------- drivers/interconnect/qcom/x1e80100.c | 19 ------------------- 27 files changed, 5 insertions(+), 286 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom/glymur.c index 104ac6c1bd36..e5c07795a6c6 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -1878,7 +1878,6 @@ static const struct qcom_icc_desc glymur_aggre1_noc = { .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_node * const aggre2_noc_nodes[] = { @@ -1900,7 +1899,6 @@ static const struct qcom_icc_desc glymur_aggre2_noc = { .config = &glymur_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), - .alloc_dyn_id = true, .qos_requires_clocks = true, }; @@ -1929,7 +1927,6 @@ static const struct qcom_icc_desc glymur_aggre3_noc = { .config = &glymur_aggre3_noc_regmap_config, .nodes = aggre3_noc_nodes, .num_nodes = ARRAY_SIZE(aggre3_noc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const aggre4_noc_bcms[] = { @@ -1958,7 +1955,6 @@ static const struct qcom_icc_desc glymur_aggre4_noc = { .num_nodes = ARRAY_SIZE(aggre4_noc_nodes), .bcms = aggre4_noc_bcms, .num_bcms = ARRAY_SIZE(aggre4_noc_bcms), - .alloc_dyn_id = true, .qos_requires_clocks = true, }; @@ -1982,7 +1978,6 @@ static const struct qcom_icc_desc glymur_clk_virt = { .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { @@ -2059,7 +2054,6 @@ static const struct qcom_icc_desc glymur_cnoc_cfg = { .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), .bcms = cnoc_cfg_bcms, .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const cnoc_main_bcms[] = { @@ -2092,7 +2086,6 @@ static const struct qcom_icc_desc glymur_cnoc_main = { .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, .num_bcms = ARRAY_SIZE(cnoc_main_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const hscnoc_bcms[] = { @@ -2136,7 +2129,6 @@ static const struct qcom_icc_desc glymur_hscnoc = { .num_nodes = ARRAY_SIZE(hscnoc_nodes), .bcms = hscnoc_bcms, .num_bcms = ARRAY_SIZE(hscnoc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { @@ -2156,7 +2148,6 @@ static const struct qcom_icc_desc glymur_lpass_ag_noc = { .config = &glymur_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { @@ -2182,7 +2173,6 @@ static const struct qcom_icc_desc glymur_lpass_lpiaon_noc = { .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { @@ -2202,7 +2192,6 @@ static const struct qcom_icc_desc glymur_lpass_lpicx_noc = { .config = &glymur_lpass_lpicx_noc_regmap_config, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const mc_virt_bcms[] = { @@ -2220,7 +2209,6 @@ static const struct qcom_icc_desc glymur_mc_virt = { .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const mmss_noc_bcms[] = { @@ -2259,7 +2247,6 @@ static const struct qcom_icc_desc glymur_mmss_noc = { .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_node * const nsinoc_nodes[] = { @@ -2280,7 +2267,6 @@ static const struct qcom_icc_desc glymur_nsinoc = { .config = &glymur_nsinoc_regmap_config, .nodes = nsinoc_nodes, .num_nodes = ARRAY_SIZE(nsinoc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const nsp_noc_bcms[] = { @@ -2306,7 +2292,6 @@ static const struct qcom_icc_desc glymur_nsp_noc = { .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_node * const oobm_ss_noc_nodes[] = { @@ -2326,7 +2311,6 @@ static const struct qcom_icc_desc glymur_oobm_ss_noc = { .config = &glymur_oobm_ss_noc_regmap_config, .nodes = oobm_ss_noc_nodes, .num_nodes = ARRAY_SIZE(oobm_ss_noc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] = { @@ -2356,7 +2340,6 @@ static const struct qcom_icc_desc glymur_pcie_east_anoc = { .num_nodes = ARRAY_SIZE(pcie_east_anoc_nodes), .bcms = pcie_east_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_east_anoc_bcms), - .alloc_dyn_id = true, .qos_requires_clocks = true, }; @@ -2388,7 +2371,6 @@ static const struct qcom_icc_desc glymur_pcie_east_slv_noc = { .num_nodes = ARRAY_SIZE(pcie_east_slv_noc_nodes), .bcms = pcie_east_slv_noc_bcms, .num_bcms = ARRAY_SIZE(pcie_east_slv_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = { @@ -2420,7 +2402,6 @@ static const struct qcom_icc_desc glymur_pcie_west_anoc = { .num_nodes = ARRAY_SIZE(pcie_west_anoc_nodes), .bcms = pcie_west_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms), - .alloc_dyn_id = true, .qos_requires_clocks = true, }; @@ -2454,7 +2435,6 @@ static const struct qcom_icc_desc glymur_pcie_west_slv_noc = { .num_nodes = ARRAY_SIZE(pcie_west_slv_noc_nodes), .bcms = pcie_west_slv_noc_bcms, .num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const system_noc_bcms[] = { @@ -2488,7 +2468,6 @@ static const struct qcom_icc_desc glymur_system_noc = { .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, .num_bcms = ARRAY_SIZE(system_noc_bcms), - .alloc_dyn_id = true, }; static const struct of_device_id qnoc_of_match[] = { diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 001404e91041..f90c29111f48 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -280,14 +280,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) if (!qn) continue; - if (desc->alloc_dyn_id) { - if (!qn->node) - qn->node = icc_node_create_dyn(); - node = qn->node; - } else { - node = icc_node_create(qn->id); - } + if (!qn->node) + qn->node = icc_node_create_dyn(); + node = qn->node; if (IS_ERR(node)) { ret = PTR_ERR(node); goto err_remove_nodes; @@ -302,12 +298,8 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) node->data = qn; icc_node_add(node, provider); - for (j = 0; j < qn->num_links; j++) { - if (desc->alloc_dyn_id) - icc_link_nodes(node, &qn->link_nodes[j]->node); - else - icc_link_create(node, qn->links[j]); - } + for (j = 0; j < qn->num_links; j++) + icc_link_nodes(node, &qn->link_nodes[j]->node); data->nodes[i] = node; } diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index b72939cceba3..09d8791402dc 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -81,8 +81,6 @@ struct qcom_icc_qosbox { /** * struct qcom_icc_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs - * @links: an array of nodes where we can go next while traversing - * @id: a unique node identifier * @link_nodes: links associated with this node * @node: icc_node associated with this node * @num_links: the total number of @links @@ -96,8 +94,6 @@ struct qcom_icc_qosbox { */ struct qcom_icc_node { const char *name; - u16 links[MAX_LINKS]; - u16 id; struct icc_node *node; u16 num_links; u16 channels; @@ -158,7 +154,6 @@ struct qcom_icc_desc { struct qcom_icc_bcm * const *bcms; size_t num_bcms; bool qos_requires_clocks; - bool alloc_dyn_id; }; int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, diff --git a/drivers/interconnect/qcom/milos.c b/drivers/interconnect/qcom/milos.c index 814ec0517f6b..d010b106728a 100644 --- a/drivers/interconnect/qcom/milos.c +++ b/drivers/interconnect/qcom/milos.c @@ -1522,7 +1522,6 @@ static const struct qcom_icc_desc milos_aggre1_noc = { .config = &milos_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1556,7 +1555,6 @@ static const struct qcom_icc_desc milos_aggre2_noc = { .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1576,7 +1574,6 @@ static const struct qcom_icc_desc milos_clk_virt = { .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { @@ -1637,7 +1634,6 @@ static const struct qcom_icc_desc milos_cnoc_cfg = { .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), .bcms = cnoc_cfg_bcms, .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const cnoc_main_bcms[] = { @@ -1680,7 +1676,6 @@ static const struct qcom_icc_desc milos_cnoc_main = { .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, .num_bcms = ARRAY_SIZE(cnoc_main_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const gem_noc_bcms[] = { @@ -1721,7 +1716,6 @@ static const struct qcom_icc_desc milos_gem_noc = { .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { @@ -1741,7 +1735,6 @@ static const struct qcom_icc_desc milos_lpass_ag_noc = { .config = &milos_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const mc_virt_bcms[] = { @@ -1759,7 +1752,6 @@ static const struct qcom_icc_desc milos_mc_virt = { .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const mmss_noc_bcms[] = { @@ -1795,7 +1787,6 @@ static const struct qcom_icc_desc milos_mmss_noc = { .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const nsp_noc_bcms[] = { @@ -1821,7 +1812,6 @@ static const struct qcom_icc_desc milos_nsp_noc = { .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { @@ -1850,7 +1840,6 @@ static const struct qcom_icc_desc milos_pcie_anoc = { .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const system_noc_bcms[] = { @@ -1885,7 +1874,6 @@ static const struct qcom_icc_desc milos_system_noc = { .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, .num_bcms = ARRAY_SIZE(system_noc_bcms), - .alloc_dyn_id = true, }; static const struct of_device_id qnoc_of_match[] = { diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c index fb0f623c0e64..797956eb6ff5 100644 --- a/drivers/interconnect/qcom/qcs615.c +++ b/drivers/interconnect/qcom/qcs615.c @@ -1214,7 +1214,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1233,7 +1232,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc qcs615_camnoc_virt = { - .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1292,7 +1290,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1306,7 +1303,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1336,7 +1332,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1354,7 +1349,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc qcs615_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1383,7 +1377,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1426,7 +1419,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc qcs615_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c index 077f4beb4bd1..70a377bbcf29 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -1600,7 +1600,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1626,7 +1625,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1649,7 +1647,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc qcs8300_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1744,7 +1741,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1758,7 +1754,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1792,7 +1787,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1810,7 +1804,6 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_gpdsp_anoc = { - .alloc_dyn_id = true, .nodes = gpdsp_anoc_nodes, .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), .bcms = gpdsp_anoc_bcms, @@ -1834,7 +1827,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1852,7 +1844,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc qcs8300_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1882,7 +1873,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1903,7 +1893,6 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_nspa_noc = { - .alloc_dyn_id = true, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -1921,7 +1910,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_pcie_anoc = { - .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1950,7 +1938,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc qcs8300_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index 4de0f17e4c57..0006413241dc 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -834,7 +834,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc qdu1000_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -862,7 +861,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc qdu1000_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -880,7 +878,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc qdu1000_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -967,7 +964,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc qdu1000_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index d144e8cb5d1e..8ce4e5fe05f2 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -1841,7 +1841,6 @@ static const struct qcom_icc_desc sa8775p_aggre1_noc = { .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1869,7 +1868,6 @@ static const struct qcom_icc_desc sa8775p_aggre2_noc = { .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1894,7 +1892,6 @@ static const struct qcom_icc_desc sa8775p_clk_virt = { .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const config_noc_bcms[] = { @@ -2000,7 +1997,6 @@ static const struct qcom_icc_desc sa8775p_config_noc = { .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const dc_noc_bcms[] = { @@ -2017,7 +2013,6 @@ static const struct qcom_icc_desc sa8775p_dc_noc = { .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, .num_bcms = ARRAY_SIZE(dc_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const gem_noc_bcms[] = { @@ -2054,7 +2049,6 @@ static const struct qcom_icc_desc sa8775p_gem_noc = { .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = { @@ -2073,7 +2067,6 @@ static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), .bcms = gpdsp_anoc_bcms, .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { @@ -2097,7 +2090,6 @@ static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const mc_virt_bcms[] = { @@ -2115,7 +2107,6 @@ static const struct qcom_icc_desc sa8775p_mc_virt = { .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const mmss_noc_bcms[] = { @@ -2148,7 +2139,6 @@ static const struct qcom_icc_desc sa8775p_mmss_noc = { .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const nspa_noc_bcms[] = { @@ -2169,7 +2159,6 @@ static const struct qcom_icc_desc sa8775p_nspa_noc = { .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, .num_bcms = ARRAY_SIZE(nspa_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const nspb_noc_bcms[] = { @@ -2190,7 +2179,6 @@ static const struct qcom_icc_desc sa8775p_nspb_noc = { .num_nodes = ARRAY_SIZE(nspb_noc_nodes), .bcms = nspb_noc_bcms, .num_bcms = ARRAY_SIZE(nspb_noc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { @@ -2208,7 +2196,6 @@ static const struct qcom_icc_desc sa8775p_pcie_anoc = { .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), - .alloc_dyn_id = true, }; static struct qcom_icc_bcm * const system_noc_bcms[] = { @@ -2237,7 +2224,6 @@ static const struct qcom_icc_desc sa8775p_system_noc = { .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, .num_bcms = ARRAY_SIZE(system_noc_bcms), - .alloc_dyn_id = true, }; static const struct of_device_id qnoc_of_match[] = { diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qcom/sar2130p.c index a0b04929058f..34cb3fc1f995 100644 --- a/drivers/interconnect/qcom/sar2130p.c +++ b/drivers/interconnect/qcom/sar2130p.c @@ -1474,7 +1474,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sar2130p_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1537,7 +1536,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_config_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), @@ -1568,7 +1566,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_gem_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), @@ -1592,7 +1589,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_lpass_ag_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1611,7 +1607,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sar2130p_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1640,7 +1635,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_mmss_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), @@ -1660,7 +1654,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_nsp_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), @@ -1679,7 +1672,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_pcie_anoc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), @@ -1719,7 +1711,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sar2130p_system_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index 9f94b987c444..0ea06facf81e 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1471,7 +1471,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1495,7 +1494,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1514,7 +1512,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc sc7180_camnoc_virt = { - .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1534,7 +1531,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_compute_noc = { - .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1603,7 +1599,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1617,7 +1612,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1646,7 +1640,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1664,7 +1657,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sc7180_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1692,7 +1684,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1714,7 +1705,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_npu_noc = { - .alloc_dyn_id = true, .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), }; @@ -1731,7 +1721,6 @@ static struct qcom_icc_node * const qup_virt_nodes[] = { }; static const struct qcom_icc_desc sc7180_qup_virt = { - .alloc_dyn_id = true, .nodes = qup_virt_nodes, .num_nodes = ARRAY_SIZE(qup_virt_nodes), .bcms = qup_virt_bcms, @@ -1767,7 +1756,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sc7180_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 3dc8b81f917d..c4cb6443f2d4 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1620,7 +1620,6 @@ static const struct regmap_config sc7280_aggre1_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_aggre1_noc = { - .alloc_dyn_id = true, .config = &sc7280_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), @@ -1653,7 +1652,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc7280_aggre2_noc = { - .alloc_dyn_id = true, .config = &sc7280_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), @@ -1675,7 +1673,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sc7280_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1746,7 +1743,6 @@ static const struct regmap_config sc7280_cnoc2_regmap_config = { }; static const struct qcom_icc_desc sc7280_cnoc2 = { - .alloc_dyn_id = true, .config = &sc7280_cnoc2_regmap_config, .nodes = cnoc2_nodes, .num_nodes = ARRAY_SIZE(cnoc2_nodes), @@ -1788,7 +1784,6 @@ static const struct regmap_config sc7280_cnoc3_regmap_config = { }; static const struct qcom_icc_desc sc7280_cnoc3 = { - .alloc_dyn_id = true, .config = &sc7280_cnoc3_regmap_config, .nodes = cnoc3_nodes, .num_nodes = ARRAY_SIZE(cnoc3_nodes), @@ -1814,7 +1809,6 @@ static const struct regmap_config sc7280_dc_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_dc_noc = { - .alloc_dyn_id = true, .config = &sc7280_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), @@ -1860,7 +1854,6 @@ static const struct regmap_config sc7280_gem_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_gem_noc = { - .alloc_dyn_id = true, .config = &sc7280_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), @@ -1890,7 +1883,6 @@ static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_lpass_ag_noc = { - .alloc_dyn_id = true, .config = &sc7280_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1917,7 +1909,6 @@ static const struct regmap_config sc7280_mc_virt_regmap_config = { }; static const struct qcom_icc_desc sc7280_mc_virt = { - .alloc_dyn_id = true, .config = &sc7280_mc_virt_regmap_config, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), @@ -1954,7 +1945,6 @@ static const struct regmap_config sc7280_mmss_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_mmss_noc = { - .alloc_dyn_id = true, .config = &sc7280_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), @@ -1983,7 +1973,6 @@ static const struct regmap_config sc7280_nsp_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_nsp_noc = { - .alloc_dyn_id = true, .config = &sc7280_nsp_noc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), @@ -2018,7 +2007,6 @@ static const struct regmap_config sc7280_system_noc_regmap_config = { }; static const struct qcom_icc_desc sc7280_system_noc = { - .alloc_dyn_id = true, .config = &sc7280_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index b80a255ba8c3..c9bf1af54e37 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1790,7 +1790,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sc8180x_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1798,7 +1797,6 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = { }; static const struct qcom_icc_desc sc8180x_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1806,7 +1804,6 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = { }; static const struct qcom_icc_desc sc8180x_camnoc_virt = { - .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1814,7 +1811,6 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt = { }; static const struct qcom_icc_desc sc8180x_compute_noc = { - .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1822,7 +1818,6 @@ static const struct qcom_icc_desc sc8180x_compute_noc = { }; static const struct qcom_icc_desc sc8180x_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1830,13 +1825,11 @@ static const struct qcom_icc_desc sc8180x_config_noc = { }; static const struct qcom_icc_desc sc8180x_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; static const struct qcom_icc_desc sc8180x_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1844,7 +1837,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = { }; static const struct qcom_icc_desc sc8180x_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1852,7 +1844,6 @@ static const struct qcom_icc_desc sc8180x_mc_virt = { }; static const struct qcom_icc_desc sc8180x_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1860,7 +1851,6 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = { }; static const struct qcom_icc_desc sc8180x_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1881,7 +1871,6 @@ static struct qcom_icc_node * const qup_virt_nodes[] = { }; static const struct qcom_icc_desc sc8180x_qup_virt = { - .alloc_dyn_id = true, .nodes = qup_virt_nodes, .num_nodes = ARRAY_SIZE(qup_virt_nodes), .bcms = qup_virt_bcms, diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index c46846191e63..ed2161da37bf 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -1998,7 +1998,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -2035,7 +2034,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -2058,7 +2056,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -2163,7 +2160,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -2180,7 +2176,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -2215,7 +2210,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -2239,7 +2233,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -2257,7 +2250,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -2289,7 +2281,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -2310,7 +2301,6 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_nspa_noc = { - .alloc_dyn_id = true, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -2331,7 +2321,6 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_nspb_noc = { - .alloc_dyn_id = true, .nodes = nspb_noc_nodes, .num_nodes = ARRAY_SIZE(nspb_noc_nodes), .bcms = nspb_noc_bcms, @@ -2361,7 +2350,6 @@ static struct qcom_icc_node * const system_noc_main_nodes[] = { }; static const struct qcom_icc_desc sc8280xp_system_noc_main = { - .alloc_dyn_id = true, .nodes = system_noc_main_nodes, .num_nodes = ARRAY_SIZE(system_noc_main_nodes), .bcms = system_noc_main_bcms, diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index 5e6a5c54f485..88f4768b765c 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1266,7 +1266,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1293,7 +1292,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1349,7 +1347,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1366,7 +1363,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1385,7 +1381,6 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_gladiator_noc = { - .alloc_dyn_id = true, .nodes = gladiator_noc_nodes, .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), .bcms = gladiator_noc_bcms, @@ -1421,7 +1416,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_mem_noc = { - .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -1452,7 +1446,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1497,7 +1490,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdm670_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 83d7a611cdf7..6d5bbeda0689 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1514,7 +1514,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1544,7 +1543,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1606,7 +1604,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1623,7 +1620,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1642,7 +1638,6 @@ static struct qcom_icc_node * const gladiator_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_gladiator_noc = { - .alloc_dyn_id = true, .nodes = gladiator_noc_nodes, .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), .bcms = gladiator_noc_bcms, @@ -1678,7 +1673,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_mem_noc = { - .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -1713,7 +1707,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1760,7 +1753,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdm845_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index b1a69e430ef4..75ced1286919 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -782,7 +782,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sdx55_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -805,7 +804,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdx55_mem_noc = { - .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -885,7 +883,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdx55_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index 7c8798174e02..6c5b4e1ec82f 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -769,7 +769,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sdx65_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -792,7 +791,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = { }; static const struct qcom_icc_desc sdx65_mem_noc = { - .alloc_dyn_id = true, .nodes = mem_noc_nodes, .num_nodes = ARRAY_SIZE(mem_noc_nodes), .bcms = mem_noc_bcms, @@ -869,7 +867,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdx65_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c index 3721d8f503a0..e56202b9bc4b 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -868,7 +868,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sdx75_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -884,7 +883,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sdx75_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -911,7 +909,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sdx75_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -928,7 +925,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sdx75_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -948,7 +944,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sdx75_pcie_anoc = { - .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1027,7 +1022,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sdx75_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index df2511dbfa96..99c435a5968f 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1389,7 +1389,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1415,7 +1414,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1443,7 +1441,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm6350_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1463,7 +1460,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_compute_noc = { - .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1524,7 +1520,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1541,7 +1536,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1573,7 +1567,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1601,7 +1594,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1626,7 +1618,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_npu_noc = { - .alloc_dyn_id = true, .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), .bcms = npu_noc_bcms, @@ -1663,7 +1654,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm6350_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c index 296cf350a08f..0390d0468b48 100644 --- a/drivers/interconnect/qcom/sm7150.c +++ b/drivers/interconnect/qcom/sm7150.c @@ -1431,7 +1431,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1461,7 +1460,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1481,7 +1479,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc sm7150_camnoc_virt = { - .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1499,7 +1496,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_compute_noc = { - .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1565,7 +1561,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1582,7 +1577,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1614,7 +1608,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1632,7 +1625,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm7150_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1664,7 +1656,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1701,7 +1692,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm7150_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 58a6643921bb..ae732afbd155 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1538,7 +1538,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1574,7 +1573,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1593,7 +1591,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8150_camnoc_virt = { - .alloc_dyn_id = true, .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -1611,7 +1608,6 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_compute_noc = { - .alloc_dyn_id = true, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1680,7 +1676,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1697,7 +1692,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1733,7 +1727,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1751,7 +1744,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8150_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1782,7 +1774,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1824,7 +1815,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8150_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 75a9b0ddb8d5..bb793d724893 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1497,7 +1497,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1529,7 +1528,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1609,7 +1607,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1626,7 +1623,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_dc_noc = { - .alloc_dyn_id = true, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1663,7 +1659,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1684,7 +1679,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1702,7 +1696,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8350_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1733,7 +1726,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1753,7 +1745,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_compute_noc = { - .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1779,7 +1770,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8350_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index dd61e03b5a81..669a638bf3ef 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1490,7 +1490,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1518,7 +1517,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1541,7 +1539,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8450_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1611,7 +1608,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1647,7 +1643,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1670,7 +1665,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1692,7 +1686,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8450_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1728,7 +1721,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1747,7 +1739,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_nsp_noc = { - .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1767,7 +1758,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8450_pcie_anoc = { - .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1796,7 +1786,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8450_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 24b682a5bdd1..d01762e13272 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1241,7 +1241,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1265,7 +1264,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1288,7 +1286,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8550_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1349,7 +1346,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1374,7 +1370,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8550_cnoc_main = { - .alloc_dyn_id = true, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1405,7 +1400,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1421,7 +1415,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1438,7 +1431,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = { - .alloc_dyn_id = true, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1454,7 +1446,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = { - .alloc_dyn_id = true, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms = lpass_lpicx_noc_bcms, @@ -1472,7 +1463,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8550_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1501,7 +1491,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1518,7 +1507,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_nsp_noc = { - .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1538,7 +1526,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8550_pcie_anoc = { - .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1562,7 +1549,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8550_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c index 629ff30e7ee7..cf3ae734d4c3 100644 --- a/drivers/interconnect/qcom/sm8650.c +++ b/drivers/interconnect/qcom/sm8650.c @@ -1595,7 +1595,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_aggre1_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), @@ -1618,7 +1617,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_aggre2_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), @@ -1642,7 +1640,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8650_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1704,7 +1701,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_config_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), @@ -1733,7 +1729,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8650_cnoc_main = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), @@ -1767,7 +1762,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_gem_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), @@ -1781,7 +1775,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_ag_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1797,7 +1790,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), @@ -1811,7 +1803,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), @@ -1828,7 +1819,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8650_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1857,7 +1847,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_mmss_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), @@ -1875,7 +1864,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_nsp_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), @@ -1896,7 +1884,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8650_pcie_anoc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), @@ -1918,7 +1905,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_system_noc = { - .alloc_dyn_id = true, .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom/sm8750.c index a46c1553ce0f..1486c0b8f4c1 100644 --- a/drivers/interconnect/qcom/sm8750.c +++ b/drivers/interconnect/qcom/sm8750.c @@ -1194,7 +1194,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1217,7 +1216,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1240,7 +1238,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc sm8750_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1290,7 +1287,6 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_config_noc = { - .alloc_dyn_id = true, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1320,7 +1316,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8750_cnoc_main = { - .alloc_dyn_id = true, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1354,7 +1349,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1367,7 +1361,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1382,7 +1375,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = { - .alloc_dyn_id = true, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1395,7 +1387,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = { - .alloc_dyn_id = true, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1411,7 +1402,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc sm8750_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1441,7 +1431,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1458,7 +1447,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_nsp_noc = { - .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1477,7 +1465,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8750_pcie_anoc = { - .alloc_dyn_id = true, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1497,7 +1484,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc sm8750_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c index d5df26f02675..2ba2823c7860 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -1467,7 +1467,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_aggre1_noc = { - .alloc_dyn_id = true, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1490,7 +1489,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_aggre2_noc = { - .alloc_dyn_id = true, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1513,7 +1511,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = { }; static const struct qcom_icc_desc x1e80100_clk_virt = { - .alloc_dyn_id = true, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1577,7 +1574,6 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = { }; static const struct qcom_icc_desc x1e80100_cnoc_cfg = { - .alloc_dyn_id = true, .nodes = cnoc_cfg_nodes, .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), .bcms = cnoc_cfg_bcms, @@ -1608,7 +1604,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc x1e80100_cnoc_main = { - .alloc_dyn_id = true, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1639,7 +1634,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_gem_noc = { - .alloc_dyn_id = true, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1655,7 +1649,6 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_lpass_ag_noc = { - .alloc_dyn_id = true, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1672,7 +1665,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = { - .alloc_dyn_id = true, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1688,7 +1680,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = { - .alloc_dyn_id = true, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms = lpass_lpicx_noc_bcms, @@ -1706,7 +1697,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = { }; static const struct qcom_icc_desc x1e80100_mc_virt = { - .alloc_dyn_id = true, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1735,7 +1725,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_mmss_noc = { - .alloc_dyn_id = true, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1752,7 +1741,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_nsp_noc = { - .alloc_dyn_id = true, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1770,7 +1758,6 @@ static struct qcom_icc_node * const pcie_center_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_pcie_center_anoc = { - .alloc_dyn_id = true, .nodes = pcie_center_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes), .bcms = pcie_center_anoc_bcms, @@ -1788,7 +1775,6 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_pcie_north_anoc = { - .alloc_dyn_id = true, .nodes = pcie_north_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes), .bcms = pcie_north_anoc_bcms, @@ -1808,7 +1794,6 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_pcie_south_anoc = { - .alloc_dyn_id = true, .nodes = pcie_south_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes), .bcms = pcie_south_anoc_bcms, @@ -1831,7 +1816,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_system_noc = { - .alloc_dyn_id = true, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1848,7 +1832,6 @@ static struct qcom_icc_node * const usb_center_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_usb_center_anoc = { - .alloc_dyn_id = true, .nodes = usb_center_anoc_nodes, .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes), .bcms = usb_center_anoc_bcms, @@ -1865,7 +1848,6 @@ static struct qcom_icc_node * const usb_north_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_usb_north_anoc = { - .alloc_dyn_id = true, .nodes = usb_north_anoc_nodes, .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes), .bcms = usb_north_anoc_bcms, @@ -1886,7 +1868,6 @@ static struct qcom_icc_node * const usb_south_anoc_nodes[] = { }; static const struct qcom_icc_desc x1e80100_usb_south_anoc = { - .alloc_dyn_id = true, .nodes = usb_south_anoc_nodes, .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes), .bcms = usb_south_anoc_bcms, From 74db54b28abae4dc39e63c84003762577cfca698 Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Tue, 16 Sep 2025 08:51:52 -0700 Subject: [PATCH 161/304] MAINTAINERS: change maintainer for Intel MAX10 BMC secure updates Xu Yilun has kindly agreed to take over maintaining Intel MAX10 BMC secure updates, since I will be leaving Altera. Signed-off-by: Matthew Gerlach Signed-off-by: Xu Yilun --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..1769457de3e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12734,7 +12734,7 @@ F: drivers/mfd/intel-m10-bmc* F: include/linux/mfd/intel-m10-bmc.h INTEL MAX10 BMC SECURE UPDATES -M: Matthew Gerlach +M: Xu Yilun L: linux-fpga@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update From 35501ac3c7d40a7bb9568c2f89d6b56beaf9bed3 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 21 Oct 2025 16:45:25 +0800 Subject: [PATCH 162/304] coresight: ETR: Fix ETR buffer use-after-free issue When ETR is enabled as CS_MODE_SYSFS, if the buffer size is changed and enabled again, currently sysfs_buf will point to the newly allocated memory(buf_new) and free the old memory(buf_old). But the etr_buf that is being used by the ETR remains pointed to buf_old, not updated to buf_new. In this case, it will result in a memory use-after-free issue. Fix this by checking ETR's mode before updating and releasing buf_old, if the mode is CS_MODE_SYSFS, then skip updating and releasing it. Fixes: bd2767ec3df2 ("coresight: Fix run time warnings while reusing ETR buffer") Signed-off-by: Xiaoqi Zhuang Signed-off-by: Suzuki K Poulose Tested-by: Leo Yan Link: https://lore.kernel.org/r/20251021-fix_etr_issue-v3-1-99a2d066fee2@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..800be06598c1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1250,6 +1250,13 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) * with the lock released. */ raw_spin_lock_irqsave(&drvdata->spinlock, flags); + + /* + * If the ETR is already enabled, continue with the existing buffer. + */ + if (coresight_get_mode(csdev) == CS_MODE_SYSFS) + goto out; + sysfs_buf = READ_ONCE(drvdata->sysfs_buf); if (!sysfs_buf || (sysfs_buf->size != drvdata->size)) { raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); From 8d204b6f1f7a6d5c74e5cbf09539e6081ee0a9be Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 28 Oct 2025 18:11:40 +0800 Subject: [PATCH 163/304] dt-bindings: arm: document the static TPDM compatible The static TPDM device is intended for sources that do not require MMIO mapping. Its compatible string should be documented clearly, along with an example illustrating how to define a static TPDM node in the DT. Reviewed-by: Rob Herring (Arm) Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20251028-add_static_tpdm_support-v4-1-84e21b98e727@oss.qualcomm.com Signed-off-by: Suzuki K Poulose --- .../bindings/arm/qcom,coresight-tpdm.yaml | 23 ++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 4edc47483851..c349306f0d52 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -36,9 +36,12 @@ properties: $nodename: pattern: "^tpdm(@[0-9a-f]+)$" compatible: - items: - - const: qcom,coresight-tpdm - - const: arm,primecell + oneOf: + - items: + - const: qcom,coresight-static-tpdm + - items: + - const: qcom,coresight-tpdm + - const: arm,primecell reg: maxItems: 1 @@ -147,4 +150,18 @@ examples: }; }; }; + + turing-llm-tpdm { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + turing_llm_tpdm_out: endpoint { + remote-endpoint = <&turing0_funnel_in1>; + }; + }; + }; + }; ... From 14ae052f794715c1d78113d87f3d42adf2ae24d0 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 28 Oct 2025 18:11:41 +0800 Subject: [PATCH 164/304] coresight: tpdm: add static tpdm support The static TPDM function as a dummy source, however, it is essential to enable the port connected to the TPDA and configure the element size. Without this, the TPDA cannot correctly receive trace data from the static TPDM. Since the static TPDM does not require MMIO mapping to access its registers, a clock controller is not mandatory for its operation. Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20251028-add_static_tpdm_support-v4-2-84e21b98e727@oss.qualcomm.com Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tpda.c | 7 - drivers/hwtracing/coresight/coresight-tpdm.c | 174 +++++++++++++++---- drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++ 3 files changed, 154 insertions(+), 39 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 333b3cb23685..3a3825d27f86 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -22,13 +22,6 @@ DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); -static bool coresight_device_is_tpdm(struct coresight_device *csdev) -{ - return (coresight_is_device_source(csdev)) && - (csdev->subtype.source_subtype == - CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); -} - static void tpda_clear_element_size(struct coresight_device *csdev) { struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 7214e65097ec..0e3896c12f07 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -470,6 +470,9 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) */ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { + if (coresight_is_static_tpdm(drvdata->csdev)) + return; + CS_UNLOCK(drvdata->base); tpdm_enable_dsb(drvdata); @@ -532,6 +535,9 @@ static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) /* TPDM disable operations */ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { + if (coresight_is_static_tpdm(drvdata->csdev)) + return; + CS_UNLOCK(drvdata->base); tpdm_disable_dsb(drvdata); @@ -595,6 +601,30 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) return 0; } +static int static_tpdm_datasets_setup(struct tpdm_drvdata *drvdata, struct device *dev) +{ + /* setup datasets for static TPDM */ + if (fwnode_property_present(dev->fwnode, "qcom,dsb-element-bits") && + (!drvdata->dsb)) { + drvdata->dsb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->dsb), GFP_KERNEL); + + if (!drvdata->dsb) + return -ENOMEM; + } + + if (fwnode_property_present(dev->fwnode, "qcom,cmb-element-bits") && + (!drvdata->cmb)) { + drvdata->cmb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->cmb), GFP_KERNEL); + + if (!drvdata->cmb) + return -ENOMEM; + } + + return 0; +} + static ssize_t reset_dataset_store(struct device *dev, struct device_attribute *attr, const char *buf, @@ -1342,10 +1372,9 @@ static const struct attribute_group *tpdm_attr_grps[] = { NULL, }; -static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) +static int tpdm_probe(struct device *dev, struct resource *res) { void __iomem *base; - struct device *dev = &adev->dev; struct coresight_platform_data *pdata; struct tpdm_drvdata *drvdata; struct coresight_desc desc = { 0 }; @@ -1354,32 +1383,37 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) return PTR_ERR(pdata); - adev->dev.platform_data = pdata; + dev->platform_data = pdata; /* driver data*/ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; - drvdata->dev = &adev->dev; + drvdata->dev = dev; dev_set_drvdata(dev, drvdata); - base = devm_ioremap_resource(dev, &adev->res); - if (IS_ERR(base)) - return PTR_ERR(base); + if (res) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); - drvdata->base = base; + drvdata->base = base; + ret = tpdm_datasets_setup(drvdata); + if (ret) + return ret; - ret = tpdm_datasets_setup(drvdata); - if (ret) - return ret; + if (drvdata && tpdm_has_dsb_dataset(drvdata)) + of_property_read_u32(drvdata->dev->of_node, + "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); - if (drvdata && tpdm_has_dsb_dataset(drvdata)) - of_property_read_u32(drvdata->dev->of_node, - "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); - - if (drvdata && tpdm_has_cmb_dataset(drvdata)) - of_property_read_u32(drvdata->dev->of_node, - "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); + if (drvdata && tpdm_has_cmb_dataset(drvdata)) + of_property_read_u32(drvdata->dev->of_node, + "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); + } else { + ret = static_tpdm_datasets_setup(drvdata, dev); + if (ret) + return ret; + } /* Set up coresight component description */ desc.name = coresight_alloc_device_name(&tpdm_devs, dev); @@ -1388,34 +1422,51 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) desc.type = CORESIGHT_DEV_TYPE_SOURCE; desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; desc.ops = &tpdm_cs_ops; - desc.pdata = adev->dev.platform_data; - desc.dev = &adev->dev; + desc.pdata = dev->platform_data; + desc.dev = dev; desc.access = CSDEV_ACCESS_IOMEM(base); - desc.groups = tpdm_attr_grps; + if (res) + desc.groups = tpdm_attr_grps; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); spin_lock_init(&drvdata->spinlock); - /* Decrease pm refcount when probe is done.*/ - pm_runtime_put(&adev->dev); + return 0; +} + +static int tpdm_remove(struct device *dev) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev); + + coresight_unregister(drvdata->csdev); return 0; } -static void tpdm_remove(struct amba_device *adev) +static int dynamic_tpdm_probe(struct amba_device *adev, + const struct amba_id *id) { - struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + int ret; - coresight_unregister(drvdata->csdev); + ret = tpdm_probe(&adev->dev, &adev->res); + if (!ret) + pm_runtime_put(&adev->dev); + + return ret; +} + +static void dynamic_tpdm_remove(struct amba_device *adev) +{ + tpdm_remove(&adev->dev); } /* * Different TPDM has different periph id. * The difference is 0-7 bits' value. So ignore 0-7 bits. */ -static const struct amba_id tpdm_ids[] = { +static const struct amba_id dynamic_tpdm_ids[] = { { .id = 0x001f0e00, .mask = 0x00ffff00, @@ -1423,17 +1474,76 @@ static const struct amba_id tpdm_ids[] = { { 0, 0, NULL }, }; -static struct amba_driver tpdm_driver = { +MODULE_DEVICE_TABLE(amba, dynamic_tpdm_ids); + +static struct amba_driver dynamic_tpdm_driver = { .drv = { .name = "coresight-tpdm", .suppress_bind_attrs = true, }, - .probe = tpdm_probe, - .id_table = tpdm_ids, - .remove = tpdm_remove, + .probe = dynamic_tpdm_probe, + .id_table = dynamic_tpdm_ids, + .remove = dynamic_tpdm_remove, }; -module_amba_driver(tpdm_driver); +static int tpdm_platform_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + int ret; + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + ret = tpdm_probe(&pdev->dev, res); + pm_runtime_put(&pdev->dev); + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static void tpdm_platform_remove(struct platform_device *pdev) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(&pdev->dev); + + if (WARN_ON(!drvdata)) + return; + + tpdm_remove(&pdev->dev); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id static_tpdm_match[] = { + {.compatible = "qcom,coresight-static-tpdm"}, + {} +}; + +MODULE_DEVICE_TABLE(of, static_tpdm_match); + +static struct platform_driver static_tpdm_driver = { + .probe = tpdm_platform_probe, + .remove = tpdm_platform_remove, + .driver = { + .name = "coresight-static-tpdm", + .of_match_table = static_tpdm_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init tpdm_init(void) +{ + return coresight_init_driver("tpdm", &dynamic_tpdm_driver, &static_tpdm_driver, + THIS_MODULE); +} + +static void __exit tpdm_exit(void) +{ + coresight_remove_driver(&dynamic_tpdm_driver, &static_tpdm_driver); +} + +module_init(tpdm_init); +module_exit(tpdm_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index b11754389734..2867f3ab8186 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -343,4 +343,16 @@ struct tpdm_dataset_attribute { enum dataset_mem mem; u32 idx; }; + +static inline bool coresight_device_is_tpdm(struct coresight_device *csdev) +{ + return (coresight_is_device_source(csdev)) && + (csdev->subtype.source_subtype == + CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); +} + +static inline bool coresight_is_static_tpdm(struct coresight_device *csdev) +{ + return (coresight_device_is_tpdm(csdev) && !csdev->access.base); +} #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ From 3112b589d3a99a52467a034db6abd35fee5c7c7c Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Sun, 10 Aug 2025 18:21:51 -0400 Subject: [PATCH 165/304] peci: controller: peci-aspeed: convert from round_rate() to determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch appended to the "under-the-cut" portion of the patch. Signed-off-by: Brian Masney Reviewed-by: Iwona Winiarska Link: https://lore.kernel.org/r/20250810-peci-round-rate-v1-1-ec96d216a455@redhat.com Signed-off-by: Iwona Winiarska --- drivers/peci/controller/peci-aspeed.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/peci/controller/peci-aspeed.c b/drivers/peci/controller/peci-aspeed.c index ad3a7d71ed4c..a0c99ecf7f38 100644 --- a/drivers/peci/controller/peci-aspeed.c +++ b/drivers/peci/controller/peci-aspeed.c @@ -362,12 +362,14 @@ static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } -static long clk_aspeed_peci_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_aspeed_peci_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - int div = clk_aspeed_peci_get_div(rate, prate); + int div = clk_aspeed_peci_get_div(req->rate, &req->best_parent_rate); - return DIV_ROUND_UP_ULL(*prate, div); + req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div); + + return 0; } static unsigned long clk_aspeed_peci_recalc_rate(struct clk_hw *hw, unsigned long prate) @@ -394,7 +396,7 @@ static unsigned long clk_aspeed_peci_recalc_rate(struct clk_hw *hw, unsigned lon static const struct clk_ops clk_aspeed_peci_ops = { .set_rate = clk_aspeed_peci_set_rate, - .round_rate = clk_aspeed_peci_round_rate, + .determine_rate = clk_aspeed_peci_determine_rate, .recalc_rate = clk_aspeed_peci_recalc_rate, }; From aa5edd1b5ece68aa806b2af6508b4b8006026da0 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Fri, 7 Nov 2025 14:16:39 +0800 Subject: [PATCH 166/304] coresight: tpdm: remove redundant check for drvdata Remove the redundant check for drvdata data because the drvdata here already has been guarranted to be non-NULL. Signed-off-by: Jie Gan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251107-fix_tpdm_redundant_check-v1-1-b63468a2dd73@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-tpdm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 0e3896c12f07..06e0a905a67d 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -1402,11 +1402,11 @@ static int tpdm_probe(struct device *dev, struct resource *res) if (ret) return ret; - if (drvdata && tpdm_has_dsb_dataset(drvdata)) + if (tpdm_has_dsb_dataset(drvdata)) of_property_read_u32(drvdata->dev->of_node, "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); - if (drvdata && tpdm_has_cmb_dataset(drvdata)) + if (tpdm_has_cmb_dataset(drvdata)) of_property_read_u32(drvdata->dev->of_node, "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); } else { From 6f3d8de8886dae587467e1a2600d3bff4ad23e30 Mon Sep 17 00:00:00 2001 From: Jianping Shen Date: Thu, 9 Oct 2025 17:31:49 +0200 Subject: [PATCH 167/304] iio: imu: smi330: Add driver Add the iio driver for bosch imu smi330. The smi330 is a combined three axis angular rate and three axis acceleration sensor. Signed-off-by: Jianping Shen Signed-off-by: Jonathan Cameron --- drivers/iio/imu/Kconfig | 1 + drivers/iio/imu/Makefile | 1 + drivers/iio/imu/smi330/Kconfig | 33 + drivers/iio/imu/smi330/Makefile | 7 + drivers/iio/imu/smi330/smi330.h | 25 + drivers/iio/imu/smi330/smi330_core.c | 918 +++++++++++++++++++++++++++ drivers/iio/imu/smi330/smi330_i2c.c | 133 ++++ drivers/iio/imu/smi330/smi330_spi.c | 85 +++ 8 files changed, 1203 insertions(+) create mode 100644 drivers/iio/imu/smi330/Kconfig create mode 100644 drivers/iio/imu/smi330/Makefile create mode 100644 drivers/iio/imu/smi330/smi330.h create mode 100644 drivers/iio/imu/smi330/smi330_core.c create mode 100644 drivers/iio/imu/smi330/smi330_i2c.c create mode 100644 drivers/iio/imu/smi330/smi330_spi.c diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig index 9d732bed9fcd..7e0181c27bb6 100644 --- a/drivers/iio/imu/Kconfig +++ b/drivers/iio/imu/Kconfig @@ -125,6 +125,7 @@ config SMI240 This driver can also be built as a module. If so, the module will be called smi240. +source "drivers/iio/imu/smi330/Kconfig" source "drivers/iio/imu/st_lsm6dsx/Kconfig" source "drivers/iio/imu/st_lsm9ds0/Kconfig" diff --git a/drivers/iio/imu/Makefile b/drivers/iio/imu/Makefile index 2ae6344f8469..13fb7846e9c9 100644 --- a/drivers/iio/imu/Makefile +++ b/drivers/iio/imu/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_KMX61) += kmx61.o obj-$(CONFIG_SMI240) += smi240.o +obj-y += smi330/ obj-y += st_lsm6dsx/ obj-y += st_lsm9ds0/ diff --git a/drivers/iio/imu/smi330/Kconfig b/drivers/iio/imu/smi330/Kconfig new file mode 100644 index 000000000000..856a315e15aa --- /dev/null +++ b/drivers/iio/imu/smi330/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# SMI330 IMU driver +# + +config SMI330 + tristate + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + +config SMI330_I2C + tristate "Bosch SMI330 I2C driver" + depends on I2C + select SMI330 + select REGMAP_I2C + help + Enable support for the Bosch SMI330 6-Axis IMU connected to I2C + interface. + + This driver can also be built as a module. If so, the module will be + called smi330_i2c. + +config SMI330_SPI + tristate "Bosch SMI330 SPI driver" + depends on SPI + select SMI330 + select REGMAP_SPI + help + Enable support for the Bosch SMI330 6-Axis IMU connected to SPI + interface. + + This driver can also be built as a module. If so, the module will be + called smi330_spi. diff --git a/drivers/iio/imu/smi330/Makefile b/drivers/iio/imu/smi330/Makefile new file mode 100644 index 000000000000..c663dcb5a9f2 --- /dev/null +++ b/drivers/iio/imu/smi330/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for Bosch SMI330 IMU +# +obj-$(CONFIG_SMI330) += smi330_core.o +obj-$(CONFIG_SMI330_I2C) += smi330_i2c.o +obj-$(CONFIG_SMI330_SPI) += smi330_spi.o diff --git a/drivers/iio/imu/smi330/smi330.h b/drivers/iio/imu/smi330/smi330.h new file mode 100644 index 000000000000..a5c765645aaa --- /dev/null +++ b/drivers/iio/imu/smi330/smi330.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ +/* + * Copyright (c) 2025 Robert Bosch GmbH. + */ +#ifndef _SMI330_H +#define _SMI330_H + +#include + +enum { + SMI330_SCAN_ACCEL_X, + SMI330_SCAN_ACCEL_Y, + SMI330_SCAN_ACCEL_Z, + SMI330_SCAN_GYRO_X, + SMI330_SCAN_GYRO_Y, + SMI330_SCAN_GYRO_Z, + SMI330_SCAN_TIMESTAMP, + SMI330_SCAN_LEN = SMI330_SCAN_TIMESTAMP, +}; + +extern const struct regmap_config smi330_regmap_config; + +int smi330_core_probe(struct device *dev, struct regmap *regmap); + +#endif /* _SMI330_H */ diff --git a/drivers/iio/imu/smi330/smi330_core.c b/drivers/iio/imu/smi330/smi330_core.c new file mode 100644 index 000000000000..7564f12543e0 --- /dev/null +++ b/drivers/iio/imu/smi330/smi330_core.c @@ -0,0 +1,918 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2025 Robert Bosch GmbH. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "smi330.h" + +/* Register map */ +#define SMI330_CHIP_ID_REG 0x00 +#define SMI330_ERR_REG 0x01 +#define SMI330_STATUS_REG 0x02 +#define SMI330_ACCEL_X_REG 0x03 +#define SMI330_GYRO_X_REG 0x06 +#define SMI330_TEMP_REG 0x09 +#define SMI330_INT1_STATUS_REG 0x0D +#define SMI330_ACCEL_CFG_REG 0x20 +#define SMI330_GYRO_CFG_REG 0x21 +#define SMI330_IO_INT_CTRL_REG 0x38 +#define SMI330_INT_CONF_REG 0x39 +#define SMI330_INT_MAP1_REG 0x3A +#define SMI330_INT_MAP2_REG 0x3B +#define SMI330_CMD_REG 0x7E + +/* Register mask */ +#define SMI330_CHIP_ID_MASK GENMASK(7, 0) +#define SMI330_ERR_FATAL_MASK BIT(0) +#define SMI330_ERR_ACC_CONF_MASK BIT(5) +#define SMI330_ERR_GYR_CONF_MASK BIT(6) +#define SMI330_STATUS_POR_MASK BIT(0) +#define SMI330_INT_STATUS_ACC_GYR_DRDY_MASK GENMASK(13, 12) +#define SMI330_CFG_ODR_MASK GENMASK(3, 0) +#define SMI330_CFG_RANGE_MASK GENMASK(6, 4) +#define SMI330_CFG_BW_MASK BIT(7) +#define SMI330_CFG_AVG_NUM_MASK GENMASK(10, 8) +#define SMI330_CFG_MODE_MASK GENMASK(14, 12) +#define SMI330_IO_INT_CTRL_INT1_MASK GENMASK(2, 0) +#define SMI330_IO_INT_CTRL_INT2_MASK GENMASK(10, 8) +#define SMI330_INT_CONF_LATCH_MASK BIT(0) +#define SMI330_INT_MAP2_ACC_DRDY_MASK GENMASK(11, 10) +#define SMI330_INT_MAP2_GYR_DRDY_MASK GENMASK(9, 8) + +/* Register values */ +#define SMI330_IO_INT_CTRL_LVL BIT(0) +#define SMI330_IO_INT_CTRL_OD BIT(1) +#define SMI330_IO_INT_CTRL_EN BIT(2) +#define SMI330_CMD_SOFT_RESET 0xDEAF + +/* T°C = (temp / 512) + 23 */ +#define SMI330_TEMP_OFFSET 11776 /* 23 * 512 */ +#define SMI330_TEMP_SCALE 1953125 /* (1 / 512) * 1e9 */ + +#define SMI330_CHIP_ID 0x42 +#define SMI330_SOFT_RESET_DELAY 2000 + +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +#define smi330_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define smi330_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +#define SMI330_ACCEL_CHANNEL(_axis) { \ + .type = IIO_ACCEL, \ + .modified = 1, \ + .channel2 = IIO_MOD_##_axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .info_mask_shared_by_dir_available = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = SMI330_SCAN_ACCEL_##_axis, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ +} + +#define SMI330_GYRO_CHANNEL(_axis) { \ + .type = IIO_ANGL_VEL, \ + .modified = 1, \ + .channel2 = IIO_MOD_##_axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .info_mask_shared_by_dir_available = \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = SMI330_SCAN_GYRO_##_axis, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ +} + +#define SMI330_TEMP_CHANNEL(_index) { \ + .type = IIO_TEMP, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ +} + +enum smi330_accel_range { + SMI330_ACCEL_RANGE_2G = 0x00, + SMI330_ACCEL_RANGE_4G = 0x01, + SMI330_ACCEL_RANGE_8G = 0x02, + SMI330_ACCEL_RANGE_16G = 0x03 +}; + +enum smi330_gyro_range { + SMI330_GYRO_RANGE_125 = 0x0, + SMI330_GYRO_RANGE_250 = 0x01, + SMI330_GYRO_RANGE_500 = 0x02 +}; + +enum smi330_odr { + SMI330_ODR_12_5_HZ = 0x05, + SMI330_ODR_25_HZ = 0x06, + SMI330_ODR_50_HZ = 0x07, + SMI330_ODR_100_HZ = 0x08, + SMI330_ODR_200_HZ = 0x09, + SMI330_ODR_400_HZ = 0x0A, + SMI330_ODR_800_HZ = 0x0B, + SMI330_ODR_1600_HZ = 0x0C, + SMI330_ODR_3200_HZ = 0x0D, + SMI330_ODR_6400_HZ = 0x0E +}; + +enum smi330_avg_num { + SMI330_AVG_NUM_1 = 0x00, + SMI330_AVG_NUM_2 = 0x01, + SMI330_AVG_NUM_4 = 0x02, + SMI330_AVG_NUM_8 = 0x03, + SMI330_AVG_NUM_16 = 0x04, + SMI330_AVG_NUM_32 = 0x05, + SMI330_AVG_NUM_64 = 0x06 +}; + +enum smi330_mode { + SMI330_MODE_SUSPEND = 0x00, + SMI330_MODE_GYRO_DRIVE = 0x01, + SMI330_MODE_LOW_POWER = 0x03, + SMI330_MODE_NORMAL = 0x04, + SMI330_MODE_HIGH_PERF = 0x07 +}; + +enum smi330_bw { + SMI330_BW_2 = 0x00, /* ODR/2 */ + SMI330_BW_4 = 0x01 /* ODR/4 */ +}; + +enum smi330_operation_mode { + SMI330_POLLING, + SMI330_DATA_READY, +}; + +enum smi330_sensor { + SMI330_ACCEL, + SMI330_GYRO, +}; + +enum smi330_sensor_conf_select { + SMI330_ODR, + SMI330_RANGE, + SMI330_BW, + SMI330_AVG_NUM, +}; + +enum smi330_int_out { + SMI330_INT_DISABLED, + SMI330_INT_1, + SMI330_INT_2, +}; + +struct smi330_attributes { + int *reg_vals; + int *vals; + int len; + int type; + int mask; +}; + +struct smi330_cfg { + enum smi330_operation_mode op_mode; + enum smi330_int_out data_irq; +}; + +struct smi330_data { + struct regmap *regmap; + struct smi330_cfg cfg; + struct iio_trigger *trig; + IIO_DECLARE_BUFFER_WITH_TS(__le16, buf, SMI330_SCAN_LEN); +}; + +const struct regmap_config smi330_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; +EXPORT_SYMBOL_NS_GPL(smi330_regmap_config, "IIO_SMI330"); + +static const struct iio_chan_spec smi330_channels[] = { + SMI330_ACCEL_CHANNEL(X), + SMI330_ACCEL_CHANNEL(Y), + SMI330_ACCEL_CHANNEL(Z), + SMI330_GYRO_CHANNEL(X), + SMI330_GYRO_CHANNEL(Y), + SMI330_GYRO_CHANNEL(Z), + SMI330_TEMP_CHANNEL(-1), /* No buffer support */ + IIO_CHAN_SOFT_TIMESTAMP(SMI330_SCAN_TIMESTAMP), +}; + +static const unsigned long smi330_avail_scan_masks[] = { + (BIT(SMI330_SCAN_ACCEL_X) | BIT(SMI330_SCAN_ACCEL_Y) | + BIT(SMI330_SCAN_ACCEL_Z) | BIT(SMI330_SCAN_GYRO_X) | + BIT(SMI330_SCAN_GYRO_Y) | BIT(SMI330_SCAN_GYRO_Z)), + 0 +}; + +static const struct smi330_attributes smi330_accel_scale_attr = { + .reg_vals = (int[]){ SMI330_ACCEL_RANGE_2G, SMI330_ACCEL_RANGE_4G, + SMI330_ACCEL_RANGE_8G, SMI330_ACCEL_RANGE_16G }, + .vals = (int[]){ 0, 61035, 0, 122070, 0, 244140, 0, 488281 }, + .len = 8, + .type = IIO_VAL_INT_PLUS_NANO, + .mask = SMI330_CFG_RANGE_MASK +}; + +static const struct smi330_attributes smi330_gyro_scale_attr = { + .reg_vals = (int[]){ SMI330_GYRO_RANGE_125, SMI330_GYRO_RANGE_250, + SMI330_GYRO_RANGE_500 }, + .vals = (int[]){ 0, 3814697, 0, 7629395, 0, 15258789 }, + .len = 6, + .type = IIO_VAL_INT_PLUS_NANO, + .mask = SMI330_CFG_RANGE_MASK +}; + +static const struct smi330_attributes smi330_average_attr = { + .reg_vals = (int[]){ SMI330_AVG_NUM_1, SMI330_AVG_NUM_2, + SMI330_AVG_NUM_4, SMI330_AVG_NUM_8, + SMI330_AVG_NUM_16, SMI330_AVG_NUM_32, + SMI330_AVG_NUM_64 }, + .vals = (int[]){ 1, 2, 4, 8, 16, 32, 64 }, + .len = 7, + .type = IIO_VAL_INT, + .mask = SMI330_CFG_AVG_NUM_MASK +}; + +static const struct smi330_attributes smi330_bandwidth_attr = { + .reg_vals = (int[]){ SMI330_BW_2, SMI330_BW_4 }, + .vals = (int[]){ 2, 4 }, + .len = 2, + .type = IIO_VAL_INT, + .mask = SMI330_CFG_BW_MASK +}; + +static const struct smi330_attributes smi330_odr_attr = { + .reg_vals = (int[]){ SMI330_ODR_12_5_HZ, SMI330_ODR_25_HZ, + SMI330_ODR_50_HZ, SMI330_ODR_100_HZ, + SMI330_ODR_200_HZ, SMI330_ODR_400_HZ, + SMI330_ODR_800_HZ, SMI330_ODR_1600_HZ, + SMI330_ODR_3200_HZ, SMI330_ODR_6400_HZ }, + .vals = (int[]){ 12, 25, 50, 100, 200, 400, 800, 1600, 3200, 6400 }, + .len = 10, + .type = IIO_VAL_INT, + .mask = SMI330_CFG_ODR_MASK +}; + +static int smi330_get_attributes(enum smi330_sensor_conf_select config, + enum smi330_sensor sensor, + const struct smi330_attributes **attr) +{ + switch (config) { + case SMI330_ODR: + *attr = &smi330_odr_attr; + return 0; + case SMI330_RANGE: + if (sensor == SMI330_ACCEL) + *attr = &smi330_accel_scale_attr; + else + *attr = &smi330_gyro_scale_attr; + return 0; + case SMI330_BW: + *attr = &smi330_bandwidth_attr; + return 0; + case SMI330_AVG_NUM: + *attr = &smi330_average_attr; + return 0; + default: + return -EINVAL; + } +} + +static int smi330_get_config_reg(enum smi330_sensor sensor, int *reg) +{ + switch (sensor) { + case SMI330_ACCEL: + *reg = SMI330_ACCEL_CFG_REG; + return 0; + case SMI330_GYRO: + *reg = SMI330_GYRO_CFG_REG; + return 0; + default: + return -EINVAL; + } +} + +static int smi330_get_sensor_config(struct smi330_data *data, + enum smi330_sensor sensor, + enum smi330_sensor_conf_select config, + int *value) + +{ + int ret, reg, reg_val, i; + const struct smi330_attributes *attr; + + ret = smi330_get_config_reg(sensor, ®); + if (ret) + return ret; + + ret = regmap_read(data->regmap, reg, ®_val); + if (ret) + return ret; + + ret = smi330_get_attributes(config, sensor, &attr); + if (ret) + return ret; + + reg_val = smi330_field_get(attr->mask, reg_val); + + if (attr->type == IIO_VAL_INT) { + for (i = 0; i < attr->len; i++) { + if (attr->reg_vals[i] == reg_val) { + *value = attr->vals[i]; + return 0; + } + } + } else { + for (i = 0; i < attr->len / 2; i++) { + if (attr->reg_vals[i] == reg_val) { + *value = attr->vals[2 * i + 1]; + return 0; + } + } + } + + return -EINVAL; +} + +static int smi330_set_sensor_config(struct smi330_data *data, + enum smi330_sensor sensor, + enum smi330_sensor_conf_select config, + int value) +{ + int ret, i, reg, reg_val, error; + const struct smi330_attributes *attr; + + ret = smi330_get_attributes(config, sensor, &attr); + if (ret) + return ret; + + for (i = 0; i < attr->len; i++) { + if (attr->vals[i] == value) { + if (attr->type == IIO_VAL_INT) + reg_val = attr->reg_vals[i]; + else + reg_val = attr->reg_vals[i / 2]; + break; + } + } + if (i == attr->len) + return -EINVAL; + + ret = smi330_get_config_reg(sensor, ®); + if (ret) + return ret; + + reg_val = smi330_field_prep(attr->mask, reg_val); + ret = regmap_update_bits(data->regmap, reg, attr->mask, reg_val); + if (ret) + return ret; + + ret = regmap_read(data->regmap, SMI330_ERR_REG, &error); + if (ret) + return ret; + + if (FIELD_GET(SMI330_ERR_ACC_CONF_MASK, error) || + FIELD_GET(SMI330_ERR_GYR_CONF_MASK, error)) + return -EIO; + + return 0; +} + +static int smi330_get_data(struct smi330_data *data, int chan_type, int axis, + int *val) +{ + u8 reg; + int ret, sample; + + switch (chan_type) { + case IIO_ACCEL: + reg = SMI330_ACCEL_X_REG + (axis - IIO_MOD_X); + break; + case IIO_ANGL_VEL: + reg = SMI330_GYRO_X_REG + (axis - IIO_MOD_X); + break; + case IIO_TEMP: + reg = SMI330_TEMP_REG; + break; + default: + return -EINVAL; + } + + ret = regmap_read(data->regmap, reg, &sample); + if (ret) + return ret; + + *val = sign_extend32(sample, 15); + + return 0; +} + +static int smi330_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, const int **vals, + int *type, int *length, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + if (chan->type == IIO_ACCEL) { + *vals = smi330_accel_scale_attr.vals; + *length = smi330_accel_scale_attr.len; + *type = smi330_accel_scale_attr.type; + } else { + *vals = smi330_gyro_scale_attr.vals; + *length = smi330_gyro_scale_attr.len; + *type = smi330_gyro_scale_attr.type; + } + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals = smi330_average_attr.vals; + *length = smi330_average_attr.len; + *type = smi330_average_attr.type; + *type = IIO_VAL_INT; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + *vals = smi330_bandwidth_attr.vals; + *length = smi330_bandwidth_attr.len; + *type = smi330_bandwidth_attr.type; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SAMP_FREQ: + *vals = smi330_odr_attr.vals; + *length = smi330_odr_attr.len; + *type = smi330_odr_attr.type; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int smi330_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + int ret; + struct smi330_data *data = iio_priv(indio_dev); + enum smi330_sensor sensor; + + /* valid for all channel types */ + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret = smi330_get_data(data, chan->type, chan->channel2, val); + iio_device_release_direct(indio_dev); + return ret ? ret : IIO_VAL_INT; + default: + break; + } + + switch (chan->type) { + case IIO_ACCEL: + sensor = SMI330_ACCEL; + break; + case IIO_ANGL_VEL: + sensor = SMI330_GYRO; + break; + case IIO_TEMP: + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *val = SMI330_TEMP_SCALE / GIGA; + *val2 = SMI330_TEMP_SCALE % GIGA; + return IIO_VAL_INT_PLUS_NANO; + case IIO_CHAN_INFO_OFFSET: + *val = SMI330_TEMP_OFFSET; + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } + + /* valid for acc and gyro channels */ + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret = smi330_get_sensor_config(data, sensor, SMI330_AVG_NUM, + val); + return ret ? ret : IIO_VAL_INT; + + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + ret = smi330_get_sensor_config(data, sensor, SMI330_BW, val); + return ret ? ret : IIO_VAL_INT; + + case IIO_CHAN_INFO_SAMP_FREQ: + ret = smi330_get_sensor_config(data, sensor, SMI330_ODR, val); + return ret ? ret : IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + *val = 0; + ret = smi330_get_sensor_config(data, sensor, SMI330_RANGE, + val2); + return ret ? ret : IIO_VAL_INT_PLUS_NANO; + + default: + return -EINVAL; + } +} + +static int smi330_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct smi330_data *data = iio_priv(indio_dev); + enum smi330_sensor sensor; + + switch (chan->type) { + case IIO_ACCEL: + sensor = SMI330_ACCEL; + break; + case IIO_ANGL_VEL: + sensor = SMI330_GYRO; + break; + default: + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return smi330_set_sensor_config(data, sensor, SMI330_RANGE, + val2); + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return smi330_set_sensor_config(data, sensor, SMI330_AVG_NUM, + val); + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + return smi330_set_sensor_config(data, sensor, SMI330_BW, val); + case IIO_CHAN_INFO_SAMP_FREQ: + return smi330_set_sensor_config(data, sensor, SMI330_ODR, val); + default: + return -EINVAL; + } +} + +static int smi330_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } +} + +static int smi330_soft_reset(struct smi330_data *data) +{ + int ret, dummy_byte; + + ret = regmap_write(data->regmap, SMI330_CMD_REG, SMI330_CMD_SOFT_RESET); + if (ret) + return ret; + fsleep(SMI330_SOFT_RESET_DELAY); + + /* Performing a dummy read after a soft-reset */ + regmap_read(data->regmap, SMI330_CHIP_ID_REG, &dummy_byte); + + return 0; +} + +static irqreturn_t smi330_trigger_handler(int irq, void *p) +{ + int ret; + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct smi330_data *data = iio_priv(indio_dev); + + ret = regmap_bulk_read(data->regmap, SMI330_ACCEL_X_REG, data->buf, + SMI330_SCAN_LEN); + if (ret) + goto out; + + iio_push_to_buffers_with_timestamp(indio_dev, data->buf, pf->timestamp); + +out: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static irqreturn_t smi330_irq_thread_handler(int irq, void *indio_dev_) +{ + int ret, int_stat; + s16 int_status[2] = { 0 }; + struct iio_dev *indio_dev = indio_dev_; + struct smi330_data *data = iio_priv(indio_dev); + + ret = regmap_bulk_read(data->regmap, SMI330_INT1_STATUS_REG, int_status, 2); + if (ret) + return IRQ_NONE; + + int_stat = int_status[0] | int_status[1]; + + if (FIELD_GET(SMI330_INT_STATUS_ACC_GYR_DRDY_MASK, int_stat)) { + indio_dev->pollfunc->timestamp = iio_get_time_ns(indio_dev); + iio_trigger_poll_nested(data->trig); + } + + return IRQ_HANDLED; +} + +static int smi330_set_int_pin_config(struct smi330_data *data, + enum smi330_int_out irq_num, + bool active_high, bool open_drain, + bool latch) +{ + int ret, val; + + val = active_high ? SMI330_IO_INT_CTRL_LVL : 0; + val |= open_drain ? SMI330_IO_INT_CTRL_OD : 0; + val |= SMI330_IO_INT_CTRL_EN; + + switch (irq_num) { + case SMI330_INT_1: + val = FIELD_PREP(SMI330_IO_INT_CTRL_INT1_MASK, val); + ret = regmap_update_bits(data->regmap, SMI330_IO_INT_CTRL_REG, + SMI330_IO_INT_CTRL_INT1_MASK, val); + if (ret) + return ret; + break; + case SMI330_INT_2: + val = FIELD_PREP(SMI330_IO_INT_CTRL_INT2_MASK, val); + ret = regmap_update_bits(data->regmap, SMI330_IO_INT_CTRL_REG, + SMI330_IO_INT_CTRL_INT2_MASK, val); + if (ret) + return ret; + break; + default: + return -EINVAL; + } + + return regmap_update_bits(data->regmap, SMI330_INT_CONF_REG, + SMI330_INT_CONF_LATCH_MASK, + FIELD_PREP(SMI330_INT_CONF_LATCH_MASK, + latch)); +} + +static int smi330_setup_irq(struct device *dev, struct iio_dev *indio_dev, + int irq, enum smi330_int_out irq_num) +{ + int ret, irq_type; + bool open_drain, active_high, latch; + struct smi330_data *data = iio_priv(indio_dev); + struct irq_data *desc; + + desc = irq_get_irq_data(irq); + if (!desc) + return -EINVAL; + + irq_type = irqd_get_trigger_type(desc); + switch (irq_type) { + case IRQF_TRIGGER_RISING: + latch = false; + active_high = true; + break; + case IRQF_TRIGGER_HIGH: + latch = true; + active_high = true; + break; + case IRQF_TRIGGER_FALLING: + latch = false; + active_high = false; + break; + case IRQF_TRIGGER_LOW: + latch = true; + active_high = false; + break; + default: + return -EINVAL; + } + + open_drain = device_property_read_bool(dev, "drive-open-drain"); + + ret = smi330_set_int_pin_config(data, irq_num, active_high, open_drain, + latch); + if (ret) + return ret; + + return devm_request_threaded_irq(dev, irq, NULL, + smi330_irq_thread_handler, + irq_type | IRQF_ONESHOT, + indio_dev->name, indio_dev); +} + +static int smi330_register_irq(struct device *dev, struct iio_dev *indio_dev) +{ + int ret, irq; + struct smi330_data *data = iio_priv(indio_dev); + struct fwnode_handle *fwnode; + + fwnode = dev_fwnode(dev); + if (!fwnode) + return -ENODEV; + + data->cfg.data_irq = SMI330_INT_DISABLED; + + irq = fwnode_irq_get_byname(fwnode, "INT1"); + if (irq > 0) { + ret = smi330_setup_irq(dev, indio_dev, irq, SMI330_INT_1); + if (ret) + return ret; + data->cfg.data_irq = SMI330_INT_1; + } else { + irq = fwnode_irq_get_byname(fwnode, "INT2"); + if (irq > 0) { + ret = smi330_setup_irq(dev, indio_dev, irq, + SMI330_INT_2); + if (ret) + return ret; + data->cfg.data_irq = SMI330_INT_2; + } + } + + return 0; +} + +static int smi330_set_drdy_trigger_state(struct iio_trigger *trig, bool enable) +{ + int val; + struct smi330_data *data = iio_trigger_get_drvdata(trig); + + if (enable) + data->cfg.op_mode = SMI330_DATA_READY; + else + data->cfg.op_mode = SMI330_POLLING; + + val = FIELD_PREP(SMI330_INT_MAP2_ACC_DRDY_MASK, + enable ? data->cfg.data_irq : 0); + val |= FIELD_PREP(SMI330_INT_MAP2_GYR_DRDY_MASK, + enable ? data->cfg.data_irq : 0); + return regmap_update_bits(data->regmap, SMI330_INT_MAP2_REG, + SMI330_INT_MAP2_ACC_DRDY_MASK | + SMI330_INT_MAP2_GYR_DRDY_MASK, + val); +} + +static const struct iio_trigger_ops smi330_trigger_ops = { + .set_trigger_state = &smi330_set_drdy_trigger_state, +}; + +static struct iio_info smi330_info = { + .read_avail = smi330_read_avail, + .read_raw = smi330_read_raw, + .write_raw = smi330_write_raw, + .write_raw_get_fmt = smi330_write_raw_get_fmt, +}; + +static int smi330_dev_init(struct smi330_data *data) +{ + int ret, chip_id, val, mode; + struct device *dev = regmap_get_device(data->regmap); + + ret = regmap_read(data->regmap, SMI330_CHIP_ID_REG, &chip_id); + if (ret) + return ret; + + chip_id = FIELD_GET(SMI330_CHIP_ID_MASK, chip_id); + if (chip_id != SMI330_CHIP_ID) + dev_info(dev, "Unknown chip id: 0x%04x\n", chip_id); + + ret = regmap_read(data->regmap, SMI330_ERR_REG, &val); + if (ret) + return ret; + if (FIELD_GET(SMI330_ERR_FATAL_MASK, val)) + return -ENODEV; + + ret = regmap_read(data->regmap, SMI330_STATUS_REG, &val); + if (ret) + return ret; + if (FIELD_GET(SMI330_STATUS_POR_MASK, val) == 0) + return -ENODEV; + + mode = FIELD_PREP(SMI330_CFG_MODE_MASK, SMI330_MODE_NORMAL); + + ret = regmap_update_bits(data->regmap, SMI330_ACCEL_CFG_REG, + SMI330_CFG_MODE_MASK, mode); + if (ret) + return ret; + + return regmap_update_bits(data->regmap, SMI330_GYRO_CFG_REG, + SMI330_CFG_MODE_MASK, mode); +} + +int smi330_core_probe(struct device *dev, struct regmap *regmap) +{ + int ret; + struct iio_dev *indio_dev; + struct smi330_data *data; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + data->regmap = regmap; + + ret = smi330_soft_reset(data); + if (ret) + return dev_err_probe(dev, ret, "Soft reset failed\n"); + + indio_dev->channels = smi330_channels; + indio_dev->num_channels = ARRAY_SIZE(smi330_channels); + indio_dev->available_scan_masks = smi330_avail_scan_masks; + indio_dev->name = "smi330"; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &smi330_info; + + data->cfg.op_mode = SMI330_POLLING; + + ret = smi330_dev_init(data); + if (ret) + return dev_err_probe(dev, ret, "Init failed\n"); + + ret = smi330_register_irq(dev, indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Register IRQ failed\n"); + + if (data->cfg.data_irq != SMI330_INT_DISABLED) { + data->trig = devm_iio_trigger_alloc(dev, "%s-drdy-trigger", + indio_dev->name); + if (!data->trig) + return -ENOMEM; + + data->trig->ops = &smi330_trigger_ops; + iio_trigger_set_drvdata(data->trig, data); + + ret = devm_iio_trigger_register(dev, data->trig); + if (ret) + return dev_err_probe(dev, ret, + "IIO register trigger failed\n"); + + /* Set default operation mode to data ready. */ + indio_dev->trig = iio_trigger_get(data->trig); + } + + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + smi330_trigger_handler, NULL); + if (ret) + return dev_err_probe(dev, ret, "IIO buffer setup failed\n"); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Register IIO device failed\n"); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(smi330_core_probe, "IIO_SMI330"); + +MODULE_AUTHOR("Stefan Gutmann "); +MODULE_AUTHOR("Roman Huber "); +MODULE_AUTHOR("Filip Andrei "); +MODULE_AUTHOR("Drimbarean Avram Andrei "); +MODULE_DESCRIPTION("Bosch SMI330 IMU driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/iio/imu/smi330/smi330_i2c.c b/drivers/iio/imu/smi330/smi330_i2c.c new file mode 100644 index 000000000000..e5f1825beb71 --- /dev/null +++ b/drivers/iio/imu/smi330/smi330_i2c.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2025 Robert Bosch GmbH. + */ +#include +#include +#include +#include + +#include "smi330.h" + +#define SMI330_NUM_DUMMY_BYTES 2 +#define SMI330_I2C_MAX_RX_BUFFER_SIZE \ + (SMI330_NUM_DUMMY_BYTES + SMI330_SCAN_LEN * sizeof(s16)) + +struct smi330_i2c_priv { + struct i2c_client *i2c; + u8 rx_buffer[SMI330_I2C_MAX_RX_BUFFER_SIZE]; +}; + +static int smi330_regmap_i2c_read(void *context, const void *reg_buf, + size_t reg_size, void *val_buf, + size_t val_size) +{ + struct smi330_i2c_priv *priv = context; + int ret; + + if (SMI330_NUM_DUMMY_BYTES + val_size > SMI330_I2C_MAX_RX_BUFFER_SIZE) + return -EINVAL; + + /* + * SMI330 I2C read frame: + * + * ... + * + * Remark: Slave address is not considered part of the frame in the following definitions + */ + struct i2c_msg msgs[] = { + { + .addr = priv->i2c->addr, + .flags = priv->i2c->flags, + .len = reg_size, + .buf = (u8 *)reg_buf, + }, + { + .addr = priv->i2c->addr, + .flags = priv->i2c->flags | I2C_M_RD, + .len = SMI330_NUM_DUMMY_BYTES + val_size, + .buf = priv->rx_buffer, + }, + }; + + ret = i2c_transfer(priv->i2c->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret < 0) + return ret; + + memcpy(val_buf, priv->rx_buffer + SMI330_NUM_DUMMY_BYTES, val_size); + + return 0; +} + +static int smi330_regmap_i2c_write(void *context, const void *data, + size_t count) +{ + struct smi330_i2c_priv *priv = context; + u8 reg; + + /* + * SMI330 I2C write frame: + * ... + * + * Remark: Slave address is not considered part of the frame in the following definitions + */ + reg = *(u8 *)data; + return i2c_smbus_write_i2c_block_data(priv->i2c, reg, + count - sizeof(u8), + data + sizeof(u8)); +} + +static const struct regmap_bus smi330_regmap_bus = { + .read = smi330_regmap_i2c_read, + .write = smi330_regmap_i2c_write, +}; + +static int smi330_i2c_probe(struct i2c_client *i2c) +{ + struct device *dev = &i2c->dev; + struct smi330_i2c_priv *priv; + struct regmap *regmap; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->i2c = i2c; + regmap = devm_regmap_init(dev, &smi330_regmap_bus, priv, + &smi330_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to initialize I2C Regmap\n"); + + return smi330_core_probe(dev, regmap); +} + +static const struct i2c_device_id smi330_i2c_device_id[] = { + { .name = "smi330" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, smi330_i2c_device_id); + +static const struct of_device_id smi330_of_match[] = { + { .compatible = "bosch,smi330" }, + { } +}; +MODULE_DEVICE_TABLE(of, smi330_of_match); + +static struct i2c_driver smi330_i2c_driver = { + .probe = smi330_i2c_probe, + .id_table = smi330_i2c_device_id, + .driver = { + .of_match_table = smi330_of_match, + .name = "smi330_i2c", + }, +}; +module_i2c_driver(smi330_i2c_driver); + +MODULE_AUTHOR("Stefan Gutmann "); +MODULE_AUTHOR("Roman Huber "); +MODULE_AUTHOR("Filip Andrei "); +MODULE_AUTHOR("Drimbarean Avram Andrei "); +MODULE_DESCRIPTION("Bosch SMI330 I2C driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_IMPORT_NS("IIO_SMI330"); diff --git a/drivers/iio/imu/smi330/smi330_spi.c b/drivers/iio/imu/smi330/smi330_spi.c new file mode 100644 index 000000000000..a6044e02b451 --- /dev/null +++ b/drivers/iio/imu/smi330/smi330_spi.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2025 Robert Bosch GmbH. + */ +#include +#include +#include +#include + +#include "smi330.h" + +static int smi330_regmap_spi_read(void *context, const void *reg_buf, + size_t reg_size, void *val_buf, + size_t val_size) +{ + struct spi_device *spi = context; + + /* Insert pad byte for reading */ + u8 reg[] = { *(u8 *)reg_buf, 0 }; + + if (reg_size + 1 != ARRAY_SIZE(reg)) { + dev_err(&spi->dev, "Invalid register size %zu\n", reg_size); + return -EINVAL; + } + + return spi_write_then_read(spi, reg, ARRAY_SIZE(reg), val_buf, + val_size); +} + +static int smi330_regmap_spi_write(void *context, const void *data, + size_t count) +{ + struct spi_device *spi = context; + + return spi_write(spi, data, count); +} + +static const struct regmap_bus smi330_regmap_bus = { + .read = smi330_regmap_spi_read, + .write = smi330_regmap_spi_write, + .read_flag_mask = 0x80, +}; + +static int smi330_spi_probe(struct spi_device *spi) +{ + struct regmap *regmap; + + regmap = devm_regmap_init(&spi->dev, &smi330_regmap_bus, &spi->dev, + &smi330_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(regmap), + "Failed to initialize SPI Regmap\n"); + + return smi330_core_probe(&spi->dev, regmap); +} + +static const struct spi_device_id smi330_spi_device_id[] = { + { .name = "smi330" }, + { } +}; +MODULE_DEVICE_TABLE(spi, smi330_spi_device_id); + +static const struct of_device_id smi330_of_match[] = { + { .compatible = "bosch,smi330" }, + { } +}; +MODULE_DEVICE_TABLE(of, smi330_of_match); + +static struct spi_driver smi330_spi_driver = { + .probe = smi330_spi_probe, + .id_table = smi330_spi_device_id, + .driver = { + .of_match_table = smi330_of_match, + .name = "smi330_spi", + }, +}; +module_spi_driver(smi330_spi_driver); + +MODULE_AUTHOR("Stefan Gutmann "); +MODULE_AUTHOR("Roman Huber "); +MODULE_AUTHOR("Filip Andrei "); +MODULE_AUTHOR("Drimbarean Avram Andrei "); +MODULE_DESCRIPTION("Bosch SMI330 SPI driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_IMPORT_NS("IIO_SMI330"); From db52c405f352f809b6ff96466fe5456b0220e354 Mon Sep 17 00:00:00 2001 From: Petre Rodan Date: Tue, 21 Oct 2025 13:31:49 +0300 Subject: [PATCH 168/304] iio: accel: bma220: move set_wdt() out of bma220_core Move bma220_set_wdt() into bma220_i2c.c instead of using a conditional based on i2c_verify_client() in bma220_core.c that would make core always depend on the i2c module. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202510102117.Jqxrw1vF-lkp@intel.com/ Signed-off-by: Petre Rodan Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bma220.h | 6 ++++++ drivers/iio/accel/bma220_core.c | 19 ------------------- drivers/iio/accel/bma220_i2c.c | 14 +++++++++++++- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/iio/accel/bma220.h b/drivers/iio/accel/bma220.h index e53ca63de54b..00dfe275256b 100644 --- a/drivers/iio/accel/bma220.h +++ b/drivers/iio/accel/bma220.h @@ -11,6 +11,12 @@ #include #include +#define BMA220_REG_WDT 0x17 +#define BMA220_WDT_MASK GENMASK(2, 1) +#define BMA220_WDT_OFF 0x0 +#define BMA220_WDT_1MS 0x2 +#define BMA220_WDT_10MS 0x3 + struct device; extern const struct regmap_config bma220_i2c_regmap_config; diff --git a/drivers/iio/accel/bma220_core.c b/drivers/iio/accel/bma220_core.c index 871342d21456..f32d875b994e 100644 --- a/drivers/iio/accel/bma220_core.c +++ b/drivers/iio/accel/bma220_core.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -78,11 +77,6 @@ #define BMA220_FILTER_MASK GENMASK(3, 0) #define BMA220_REG_RANGE 0x11 #define BMA220_RANGE_MASK GENMASK(1, 0) -#define BMA220_REG_WDT 0x17 -#define BMA220_WDT_MASK GENMASK(2, 1) -#define BMA220_WDT_OFF 0x0 -#define BMA220_WDT_1MS 0x2 -#define BMA220_WDT_10MS 0x3 #define BMA220_REG_SUSPEND 0x18 #define BMA220_REG_SOFTRESET 0x19 @@ -443,12 +437,6 @@ static int bma220_power(struct bma220_data *data, bool up) return -EBUSY; } -static int bma220_set_wdt(struct bma220_data *data, const u8 val) -{ - return regmap_update_bits(data->regmap, BMA220_REG_WDT, BMA220_WDT_MASK, - FIELD_PREP(BMA220_WDT_MASK, val)); -} - static int bma220_init(struct device *dev, struct bma220_data *data) { int ret; @@ -477,13 +465,6 @@ static int bma220_init(struct device *dev, struct bma220_data *data) if (ret) return dev_err_probe(dev, ret, "Failed to soft reset chip\n"); - if (i2c_verify_client(dev)) { - ret = bma220_set_wdt(data, BMA220_WDT_1MS); - if (ret) - return dev_err_probe(dev, ret, - "Failed to set i2c watchdog\n"); - } - return 0; } diff --git a/drivers/iio/accel/bma220_i2c.c b/drivers/iio/accel/bma220_i2c.c index 2b85d4921768..8b6f8e305c8c 100644 --- a/drivers/iio/accel/bma220_i2c.c +++ b/drivers/iio/accel/bma220_i2c.c @@ -8,6 +8,7 @@ * I2C address is either 0x0b or 0x0a depending on CSB (pin 10) */ +#include #include #include #include @@ -16,16 +17,27 @@ #include "bma220.h" +static int bma220_set_wdt(struct regmap *regmap, const u8 val) +{ + return regmap_update_bits(regmap, BMA220_REG_WDT, BMA220_WDT_MASK, + FIELD_PREP(BMA220_WDT_MASK, val)); +} + static int bma220_i2c_probe(struct i2c_client *client) { struct regmap *regmap; + int ret; regmap = devm_regmap_init_i2c(client, &bma220_i2c_regmap_config); if (IS_ERR(regmap)) return dev_err_probe(&client->dev, PTR_ERR(regmap), "failed to create regmap\n"); - return bma220_common_probe(&client->dev, regmap, client->irq); + ret = bma220_common_probe(&client->dev, regmap, client->irq); + if (ret) + return ret; + + return bma220_set_wdt(regmap, BMA220_WDT_1MS); } static const struct of_device_id bma220_i2c_match[] = { From f11de95215311816595a1f2ee81cf8239d9b660a Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Oct 2025 10:53:43 +0000 Subject: [PATCH 169/304] dt-bindings: iio: adc: adi,ad4080: add support for AD4083 Add device tree binding support for the AD4083 16-bit SAR ADC. Add adi,ad4083 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4083 has different resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (5 vs 7), requiring different driver configuration. Signed-off-by: Antoniu Miclaus Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index a9fa068189ea..9d2b4b8edf42 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -27,6 +27,7 @@ properties: enum: - adi,ad4080 - adi,ad4081 + - adi,ad4083 - adi,ad4084 reg: From 4028cbcf3415f6e0810326d87c6e0b494814ae12 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Oct 2025 10:53:44 +0000 Subject: [PATCH 170/304] iio: adc: ad4080: add support for AD4083 Add support for AD4083 16-bit SAR ADC. The AD4083 differs from AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count maximum (5 vs 7). Changes: - Add AD4083_CHIP_ID definition (0x0053) - Create ad4083_channel with 16-bit resolution and storage - Add ad4083_chip_info with lvds_cnv_clk_cnt_max = 5 - Register AD4083 in device ID and OF match tables Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index 5940651655df..e2cdca2e9174 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -127,6 +127,7 @@ #define AD4080_SPI_READ BIT(7) #define AD4080_CHIP_ID 0x0050 #define AD4081_CHIP_ID 0x0051 +#define AD4083_CHIP_ID 0x0053 #define AD4084_CHIP_ID 0x0054 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 @@ -439,6 +440,8 @@ static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32) static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32); +static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16); + static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16); static const struct ad4080_chip_info ad4080_chip_info = { @@ -461,6 +464,16 @@ static const struct ad4080_chip_info ad4081_chip_info = { .lvds_cnv_clk_cnt_max = 2, }; +static const struct ad4080_chip_info ad4083_chip_info = { + .name = "ad4083", + .product_id = AD4083_CHIP_ID, + .scale_table = ad4080_scale_table, + .num_scales = ARRAY_SIZE(ad4080_scale_table), + .num_channels = 1, + .channels = &ad4083_channel, + .lvds_cnv_clk_cnt_max = 5, +}; + static const struct ad4080_chip_info ad4084_chip_info = { .name = "ad4084", .product_id = AD4084_CHIP_ID, @@ -627,6 +640,7 @@ static int ad4080_probe(struct spi_device *spi) static const struct spi_device_id ad4080_id[] = { { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, { "ad4081", (kernel_ulong_t)&ad4081_chip_info }, + { "ad4083", (kernel_ulong_t)&ad4083_chip_info }, { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, { } }; @@ -635,6 +649,7 @@ MODULE_DEVICE_TABLE(spi, ad4080_id); static const struct of_device_id ad4080_of_match[] = { { .compatible = "adi,ad4080", &ad4080_chip_info }, { .compatible = "adi,ad4081", &ad4081_chip_info }, + { .compatible = "adi,ad4083", &ad4083_chip_info }, { .compatible = "adi,ad4084", &ad4084_chip_info }, { } }; From 45e81d6ac0e1af349e5da050dc0be48a72fad9dd Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Oct 2025 10:53:45 +0000 Subject: [PATCH 171/304] dt-bindings: iio: adc: adi,ad4080: add support for AD4086 Add device tree binding support for the AD4086 14-bit SAR ADC. Add adi,ad4086 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4086 has different resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (4 vs 7), requiring different driver configuration. Signed-off-by: Antoniu Miclaus Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index 9d2b4b8edf42..db136bff45b7 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -29,6 +29,7 @@ properties: - adi,ad4081 - adi,ad4083 - adi,ad4084 + - adi,ad4086 reg: maxItems: 1 From 916354e7c7c08aedff37bdf322e049836aa8d2aa Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Oct 2025 10:53:46 +0000 Subject: [PATCH 172/304] iio: adc: ad4080: add support for AD4086 Add support for AD4086 14-bit SAR ADC. The AD4086 differs from AD4080 in resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (4 vs 7). Changes: - Add AD4086_CHIP_ID definition (0x0056) - Create ad4086_channel with 14-bit resolution and 16-bit storage - Add ad4086_chip_info with lvds_cnv_clk_cnt_max = 4 - Register AD4086 in device ID and OF match tables Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index e2cdca2e9174..d6d0688adc3d 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -129,6 +129,7 @@ #define AD4081_CHIP_ID 0x0051 #define AD4083_CHIP_ID 0x0053 #define AD4084_CHIP_ID 0x0054 +#define AD4086_CHIP_ID 0x0056 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 @@ -444,6 +445,8 @@ static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16) static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16); +static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16); + static const struct ad4080_chip_info ad4080_chip_info = { .name = "ad4080", .product_id = AD4080_CHIP_ID, @@ -484,6 +487,16 @@ static const struct ad4080_chip_info ad4084_chip_info = { .lvds_cnv_clk_cnt_max = 2, }; +static const struct ad4080_chip_info ad4086_chip_info = { + .name = "ad4086", + .product_id = AD4086_CHIP_ID, + .scale_table = ad4080_scale_table, + .num_scales = ARRAY_SIZE(ad4080_scale_table), + .num_channels = 1, + .channels = &ad4086_channel, + .lvds_cnv_clk_cnt_max = 4, +}; + static int ad4080_setup(struct iio_dev *indio_dev) { struct ad4080_state *st = iio_priv(indio_dev); @@ -642,6 +655,7 @@ static const struct spi_device_id ad4080_id[] = { { "ad4081", (kernel_ulong_t)&ad4081_chip_info }, { "ad4083", (kernel_ulong_t)&ad4083_chip_info }, { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, + { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4080_id); @@ -651,6 +665,7 @@ static const struct of_device_id ad4080_of_match[] = { { .compatible = "adi,ad4081", &ad4081_chip_info }, { .compatible = "adi,ad4083", &ad4083_chip_info }, { .compatible = "adi,ad4084", &ad4084_chip_info }, + { .compatible = "adi,ad4086", &ad4086_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4080_of_match); From 24e6d7e9f2fce0afc1a63593d1470dbb6df5e9c3 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Oct 2025 10:53:47 +0000 Subject: [PATCH 173/304] dt-bindings: iio: adc: adi,ad4080: add support for AD4087 Add device tree binding support for the AD4087 14-bit SAR ADC. Add adi,ad4087 to the compatible enum. A fallback compatible string to adi,ad4080 is not appropriate as the AD4087 has different resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (1 vs 7), requiring different driver configuration. Signed-off-by: Antoniu Miclaus Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index db136bff45b7..ccd6a0ac1539 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -30,6 +30,7 @@ properties: - adi,ad4083 - adi,ad4084 - adi,ad4086 + - adi,ad4087 reg: maxItems: 1 From 451a9c4a415dae08f88792e6874e85b025eb9420 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Oct 2025 10:53:48 +0000 Subject: [PATCH 174/304] iio: adc: ad4080: add support for AD4087 Add support for AD4087 14-bit SAR ADC. The AD4087 differs from AD4080 in resolution (14-bit vs 20-bit) and LVDS CNV clock count maximum (1 vs 7). Changes: - Add AD4087_CHIP_ID definition (0x0057) - Create ad4087_channel with 14-bit resolution and 16-bit storage - Add ad4087_chip_info with lvds_cnv_clk_cnt_max = 1 - Register AD4087 in device ID and OF match tables Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad4080.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index d6d0688adc3d..7cf3b6ed7940 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -130,6 +130,7 @@ #define AD4083_CHIP_ID 0x0053 #define AD4084_CHIP_ID 0x0054 #define AD4086_CHIP_ID 0x0056 +#define AD4087_CHIP_ID 0x0057 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 @@ -447,6 +448,8 @@ static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16) static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16); +static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16); + static const struct ad4080_chip_info ad4080_chip_info = { .name = "ad4080", .product_id = AD4080_CHIP_ID, @@ -497,6 +500,16 @@ static const struct ad4080_chip_info ad4086_chip_info = { .lvds_cnv_clk_cnt_max = 4, }; +static const struct ad4080_chip_info ad4087_chip_info = { + .name = "ad4087", + .product_id = AD4087_CHIP_ID, + .scale_table = ad4080_scale_table, + .num_scales = ARRAY_SIZE(ad4080_scale_table), + .num_channels = 1, + .channels = &ad4087_channel, + .lvds_cnv_clk_cnt_max = 1, +}; + static int ad4080_setup(struct iio_dev *indio_dev) { struct ad4080_state *st = iio_priv(indio_dev); @@ -656,6 +669,7 @@ static const struct spi_device_id ad4080_id[] = { { "ad4083", (kernel_ulong_t)&ad4083_chip_info }, { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, + { "ad4087", (kernel_ulong_t)&ad4087_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4080_id); @@ -666,6 +680,7 @@ static const struct of_device_id ad4080_of_match[] = { { .compatible = "adi,ad4083", &ad4083_chip_info }, { .compatible = "adi,ad4084", &ad4084_chip_info }, { .compatible = "adi,ad4086", &ad4086_chip_info }, + { .compatible = "adi,ad4087", &ad4087_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4080_of_match); From 3ddda1db1514f3cb5efd1c95c35b24fd7e4ef7ff Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 22 Oct 2025 00:31:07 +0200 Subject: [PATCH 175/304] dt-bindings: iio: adc: Add rockchip,rk3506-saradc variant The SARADC of the RK3506 is similar to the one found in the RK3528 in terms of number of channels and the other implementation details. So add a variant compatible for it, that reflects this fact. Signed-off-by: Heiko Stuebner Acked-by: Conor Dooley Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml index f776041fd08f..6769d679c907 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml @@ -16,6 +16,9 @@ properties: - const: rockchip,rk3066-tsadc - const: rockchip,rk3399-saradc - const: rockchip,rk3528-saradc + - items: + - const: rockchip,rk3506-saradc + - const: rockchip,rk3528-saradc - const: rockchip,rk3562-saradc - const: rockchip,rk3588-saradc - items: From c6763b15c49edc4926a8c6cd8cd2f01d49134d74 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 22 Oct 2025 14:02:20 +0300 Subject: [PATCH 176/304] iio: imu: inv_icm45600: Add a missing return statement in probe() The intention here was clearly to return -ENODEV but the return statement was missing. It would result in an off by one read in i3c_chip_info[] on the next line. Add the return statement. Fixes: 1bef24e9007e ("iio: imu: inv_icm45600: add I3C driver for inv_icm45600 driver") Signed-off-by: Dan Carpenter Reviewed-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c index b5df06b97d44..9247eae9b3e2 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_i3c.c @@ -57,7 +57,8 @@ static int inv_icm45600_i3c_probe(struct i3c_device *i3cdev) } if (chip == nb_chip) - dev_err_probe(&i3cdev->dev, -ENODEV, "Failed to match part id %d\n", whoami); + return dev_err_probe(&i3cdev->dev, -ENODEV, + "Failed to match part id %d\n", whoami); return inv_icm45600_core_probe(regmap, i3c_chip_info[chip], false, NULL); } From 97289f6accca405d63149e56774912c8be85f76b Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 22 Oct 2025 10:15:05 -0500 Subject: [PATCH 177/304] iio: adc: ad7124: fix possible OOB array access Reorder the channel bounds check before using it to index into the channels array in ad7124_release_config_slot(). This prevents reading past the end of the array. The value read from invalid memory was not used, so this was mostly harmless, but we still should not be reading out of bounds in the first place. Reported-by: Dan Carpenter Closes: https://lore.kernel.org/linux-iio/aPi6V-hcaKReSNWK@stanley.mountain/ Fixes: 9065197e0d41 ("iio: adc: ad7124: change setup reg allocation strategy") Signed-off-by: David Lechner Reviewed-by: Marcelo Schmitt Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ad7124.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 9d58ced7371d..ed828a82acb7 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -586,13 +586,18 @@ static int ad7124_request_config_slot(struct ad7124_state *st, u8 channel) static void ad7124_release_config_slot(struct ad7124_state *st, u8 channel) { - unsigned int slot = st->channels[channel].cfg.cfg_slot; + unsigned int slot; /* - * All of these conditions can happen at probe when all channels are - * disabled. Otherwise, they should not happen normally. + * All of these early return conditions can happen at probe when all + * channels are disabled. Otherwise, they should not happen normally. */ - if (channel >= st->num_channels || slot == AD7124_CFG_SLOT_UNASSIGNED || + if (channel >= st->num_channels) + return; + + slot = st->channels[channel].cfg.cfg_slot; + + if (slot == AD7124_CFG_SLOT_UNASSIGNED || st->cfg_slot_use_count[slot] == 0) return; From f9c30b3e6735bf8ff26414f6452f482d45b179e9 Mon Sep 17 00:00:00 2001 From: Akhilesh Patil Date: Sat, 25 Oct 2025 11:48:41 +0530 Subject: [PATCH 178/304] dt-bindings: iio: pressure: Add Aosong adp810 Add bindings for adp810 differential pressure and temperature sensor. This sensor communicates over I2C with CRC support and can measure pressure in the range -500 to 500Pa and temperature in the range -40 to +85 degree celsius. Signed-off-by: Akhilesh Patil Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jonathan Cameron --- .../bindings/iio/pressure/aosong,adp810.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/pressure/aosong,adp810.yaml diff --git a/Documentation/devicetree/bindings/iio/pressure/aosong,adp810.yaml b/Documentation/devicetree/bindings/iio/pressure/aosong,adp810.yaml new file mode 100644 index 000000000000..ad5f26ce5043 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/pressure/aosong,adp810.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/aosong,adp810.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: aosong adp810 differential pressure sensor + +maintainers: + - Akhilesh Patil + +description: + ADP810 is differential pressure and temperature sensor. It has I2C bus + interface with fixed address of 0x25. This sensor supports 8 bit CRC for + reliable data transfer. It can measure differential pressure in the + range -500 to 500Pa and temperate in the range -40 to +85 degree celsius. + +properties: + compatible: + enum: + - aosong,adp810 + + reg: + maxItems: 1 + + vdd-supply: true + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + pressure-sensor@25 { + compatible = "aosong,adp810"; + reg = <0x25>; + vdd-supply = <&vdd_regulator>; + }; + }; From bb578dd7a01ebbb186dd6d1c27285b29f7fdba37 Mon Sep 17 00:00:00 2001 From: Akhilesh Patil Date: Sat, 25 Oct 2025 11:50:55 +0530 Subject: [PATCH 179/304] iio: pressure: adp810: Add driver for adp810 sensor Add driver for Aosong adp810 differential pressure and temperature sensor. This sensor provides an I2C interface for reading data. Calculate CRC of the data received using standard crc8 library to verify data integrity. Tested on TI am62x sk board with sensor connected at i2c-2. Signed-off-by: Akhilesh Patil Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- MAINTAINERS | 7 ++ drivers/iio/pressure/Kconfig | 12 ++ drivers/iio/pressure/Makefile | 1 + drivers/iio/pressure/adp810.c | 225 ++++++++++++++++++++++++++++++++++ 4 files changed, 245 insertions(+) create mode 100644 drivers/iio/pressure/adp810.c diff --git a/MAINTAINERS b/MAINTAINERS index 940889b158eb..9f3413e05c83 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3745,6 +3745,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/chemical/aosong,ags02ma.yaml F: drivers/iio/chemical/ags02ma.c +AOSONG ADP810 DIFFERENTIAL PRESSURE SENSOR DRIVER +M: Akhilesh Patil +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/pressure/aosong,adp810.yaml +F: drivers/iio/pressure/adp810.c + ASC7621 HARDWARE MONITOR DRIVER M: George Joseph L: linux-hwmon@vger.kernel.org diff --git a/drivers/iio/pressure/Kconfig b/drivers/iio/pressure/Kconfig index d2cb8c871f6a..2fe9dc90cceb 100644 --- a/drivers/iio/pressure/Kconfig +++ b/drivers/iio/pressure/Kconfig @@ -339,4 +339,16 @@ config ZPA2326_SPI tristate select REGMAP_SPI +config ADP810 + tristate "Aosong adp810 differential pressure and temperature sensor" + depends on I2C + select CRC8 + help + Say yes here to build adp810 differential pressure and temperature + sensor driver. ADP810 can measure pressure range up to 500Pa. + It supports an I2C interface for data communication. + + To compile this driver as a module, choose M here: the module will + be called adp810 + endmenu diff --git a/drivers/iio/pressure/Makefile b/drivers/iio/pressure/Makefile index 6482288e07ee..47bf7656f975 100644 --- a/drivers/iio/pressure/Makefile +++ b/drivers/iio/pressure/Makefile @@ -5,6 +5,7 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_ABP060MG) += abp060mg.o +obj-$(CONFIG_ADP810) += adp810.o obj-$(CONFIG_ROHM_BM1390) += rohm-bm1390.o obj-$(CONFIG_BMP280) += bmp280.o bmp280-objs := bmp280-core.o bmp280-regmap.o diff --git a/drivers/iio/pressure/adp810.c b/drivers/iio/pressure/adp810.c new file mode 100644 index 000000000000..5282612d1309 --- /dev/null +++ b/drivers/iio/pressure/adp810.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Akhilesh Patil + * + * Driver for adp810 pressure and temperature sensor + * Datasheet: + * https://aosong.com/userfiles/files/media/Datasheet%20ADP810-Digital.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * Refer section 5.4 checksum calculation from datasheet. + * This sensor uses CRC polynomial x^8 + x^5 + x^4 + 1 (0x31) + */ +#define ADP810_CRC8_POLYNOMIAL 0x31 + +DECLARE_CRC8_TABLE(crc_table); + +/* + * Buffer declaration which holds 9 bytes of measurement data read + * from the sensor. Use __packed to avoid any paddings, as data sent + * from the sensor is strictly contiguous 9 bytes. + */ +struct adp810_read_buf { + __be16 dp; + u8 dp_crc; + __be16 tmp; + u8 tmp_crc; + __be16 sf; + u8 sf_crc; +} __packed; + +struct adp810_data { + struct i2c_client *client; + /* Use lock to synchronize access to device during read sequence */ + struct mutex lock; +}; + +static int adp810_measure(struct adp810_data *data, struct adp810_read_buf *buf) +{ + struct i2c_client *client = data->client; + struct device *dev = &client->dev; + int ret; + u8 trig_cmd[2] = {0x37, 0x2d}; + + /* Send trigger command to the sensor for measurement */ + ret = i2c_master_send(client, trig_cmd, sizeof(trig_cmd)); + if (ret < 0) { + dev_err(dev, "Error sending trigger command\n"); + return ret; + } + if (ret != sizeof(trig_cmd)) + return -EIO; + + /* + * Wait for the sensor to acquire data. As per datasheet section 5.3.1, + * at least 10ms delay before reading from the sensor is recommended. + * Here, we wait for 20ms to have some safe margin on the top + * of recommendation and to compensate for any possible variations. + */ + msleep(20); + + /* Read sensor values */ + ret = i2c_master_recv(client, (char *)buf, sizeof(*buf)); + if (ret < 0) { + dev_err(dev, "Error reading from sensor\n"); + return ret; + } + if (ret != sizeof(*buf)) + return -EIO; + + /* CRC checks */ + crc8_populate_msb(crc_table, ADP810_CRC8_POLYNOMIAL); + if (buf->dp_crc != crc8(crc_table, (u8 *)&buf->dp, 0x2, CRC8_INIT_VALUE)) { + dev_err(dev, "CRC error for pressure\n"); + return -EIO; + } + + if (buf->tmp_crc != crc8(crc_table, (u8 *)&buf->tmp, 0x2, CRC8_INIT_VALUE)) { + dev_err(dev, "CRC error for temperature\n"); + return -EIO; + } + + if (buf->sf_crc != crc8(crc_table, (u8 *)&buf->sf, 0x2, CRC8_INIT_VALUE)) { + dev_err(dev, "CRC error for scale\n"); + return -EIO; + } + + return 0; +} + +static int adp810_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct adp810_data *data = iio_priv(indio_dev); + struct device *dev = &data->client->dev; + struct adp810_read_buf buf = { }; + int ret; + + scoped_guard(mutex, &data->lock) { + ret = adp810_measure(data, &buf); + if (ret) { + dev_err(dev, "Failed to read from device\n"); + return ret; + } + } + + switch (mask) { + case IIO_CHAN_INFO_RAW: + switch (chan->type) { + case IIO_PRESSURE: + *val = get_unaligned_be16(&buf.dp); + return IIO_VAL_INT; + case IIO_TEMP: + *val = get_unaligned_be16(&buf.tmp); + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_PRESSURE: + *val = get_unaligned_be16(&buf.sf); + return IIO_VAL_INT; + case IIO_TEMP: + *val = 200; + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static const struct iio_info adp810_info = { + .read_raw = adp810_read_raw, +}; + +static const struct iio_chan_spec adp810_channels[] = { + { + .type = IIO_PRESSURE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + }, + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + }, +}; + +static int adp810_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct iio_dev *indio_dev; + struct adp810_data *data; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + data->client = client; + + ret = devm_mutex_init(dev, &data->lock); + if (ret) + return ret; + + indio_dev->name = "adp810"; + indio_dev->channels = adp810_channels; + indio_dev->num_channels = ARRAY_SIZE(adp810_channels); + indio_dev->info = &adp810_info; + indio_dev->modes = INDIO_DIRECT_MODE; + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to register IIO device\n"); + + return 0; +} + +static const struct i2c_device_id adp810_id_table[] = { + { "adp810" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, adp810_id_table); + +static const struct of_device_id adp810_of_table[] = { + { .compatible = "aosong,adp810" }, + { } +}; +MODULE_DEVICE_TABLE(of, adp810_of_table); + +static struct i2c_driver adp810_driver = { + .driver = { + .name = "adp810", + .of_match_table = adp810_of_table, + }, + .probe = adp810_probe, + .id_table = adp810_id_table, +}; +module_i2c_driver(adp810_driver); + +MODULE_AUTHOR("Akhilesh Patil "); +MODULE_DESCRIPTION("Driver for Aosong ADP810 sensor"); +MODULE_LICENSE("GPL"); From 1d165919c8261b927f8dc8cfe61eb04342bedb7e Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 25 Oct 2025 19:47:59 -0700 Subject: [PATCH 180/304] iio: imu: adis: fix all kernel-doc warnings in header file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct and add to adis.h to resolve all kernel-doc warnings: - add a missing struct member description - change one non-kernel-doc comment to use /* instead of /** - correct function parameter @value to @val (7 locations) - add function return value comments (13 locations) Warning: include/linux/iio/imu/adis.h:97 struct member 'has_fifo' not described in 'adis_data' Warning: include/linux/iio/imu/adis.h:139 Incorrect use of kernel-doc format: * The state_lock is meant to be used during operations that require Warning: include/linux/iio/imu/adis.h:158 struct member '"__adis_"' not described in 'adis' Warning: include/linux/iio/imu/adis.h:264 function parameter 'val' not described in 'adis_write_reg' Warning: include/linux/iio/imu/adis.h:371 No description found for return value of 'adis_update_bits_base' Signed-off-by: Randy Dunlap Reviewed-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- include/linux/iio/imu/adis.h | 45 ++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/include/linux/iio/imu/adis.h b/include/linux/iio/imu/adis.h index aa160511e265..bfb6df68e6c9 100644 --- a/include/linux/iio/imu/adis.h +++ b/include/linux/iio/imu/adis.h @@ -57,6 +57,7 @@ struct adis_timeout { * @enable_irq: Hook for ADIS devices that have a special IRQ enable/disable * @unmasked_drdy: True for devices that cannot mask/unmask the data ready pin * @has_paging: True if ADIS device has paged registers + * @has_fifo: True if ADIS device has a hardware FIFO * @burst_reg_cmd: Register command that triggers burst * @burst_len: Burst size in the SPI RX buffer. If @burst_max_len is defined, * this should be the minimum size supported by the device. @@ -136,7 +137,7 @@ struct adis { const struct adis_data *data; unsigned int burst_extra_len; const struct adis_ops *ops; - /** + /* * The state_lock is meant to be used during operations that require * a sequence of SPI R/W in order to protect the SPI transfer * information (fields 'xfer', 'msg' & 'current_page') between @@ -166,7 +167,7 @@ int __adis_reset(struct adis *adis); * adis_reset() - Reset the device * @adis: The adis device * - * Returns 0 on success, a negative error code otherwise + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_reset(struct adis *adis) { @@ -183,7 +184,9 @@ int __adis_read_reg(struct adis *adis, unsigned int reg, * __adis_write_reg_8() - Write single byte to a register (unlocked) * @adis: The adis device * @reg: The address of the register to be written - * @value: The value to write + * @val: The value to write + * + * Returns: %0 on success, a negative error code otherwise */ static inline int __adis_write_reg_8(struct adis *adis, unsigned int reg, u8 val) @@ -195,7 +198,9 @@ static inline int __adis_write_reg_8(struct adis *adis, unsigned int reg, * __adis_write_reg_16() - Write 2 bytes to a pair of registers (unlocked) * @adis: The adis device * @reg: The address of the lower of the two registers - * @value: Value to be written + * @val: Value to be written + * + * Returns: %0 on success, a negative error code otherwise */ static inline int __adis_write_reg_16(struct adis *adis, unsigned int reg, u16 val) @@ -207,7 +212,9 @@ static inline int __adis_write_reg_16(struct adis *adis, unsigned int reg, * __adis_write_reg_32() - write 4 bytes to four registers (unlocked) * @adis: The adis device * @reg: The address of the lower of the four register - * @value: Value to be written + * @val: Value to be written + * + * Returns: %0 on success, a negative error code otherwise */ static inline int __adis_write_reg_32(struct adis *adis, unsigned int reg, u32 val) @@ -220,6 +227,8 @@ static inline int __adis_write_reg_32(struct adis *adis, unsigned int reg, * @adis: The adis device * @reg: The address of the lower of the two registers * @val: The value read back from the device + * + * Returns: %0 on success, a negative error code otherwise */ static inline int __adis_read_reg_16(struct adis *adis, unsigned int reg, u16 *val) @@ -239,6 +248,8 @@ static inline int __adis_read_reg_16(struct adis *adis, unsigned int reg, * @adis: The adis device * @reg: The address of the lower of the two registers * @val: The value read back from the device + * + * Returns: %0 on success, a negative error code otherwise */ static inline int __adis_read_reg_32(struct adis *adis, unsigned int reg, u32 *val) @@ -257,8 +268,10 @@ static inline int __adis_read_reg_32(struct adis *adis, unsigned int reg, * adis_write_reg() - write N bytes to register * @adis: The adis device * @reg: The address of the lower of the two registers - * @value: The value to write to device (up to 4 bytes) + * @val: The value to write to device (up to 4 bytes) * @size: The size of the @value (in bytes) + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_write_reg(struct adis *adis, unsigned int reg, unsigned int val, unsigned int size) @@ -273,6 +286,8 @@ static inline int adis_write_reg(struct adis *adis, unsigned int reg, * @reg: The address of the lower of the two registers * @val: The value read back from the device * @size: The size of the @val buffer + * + * Returns: %0 on success, a negative error code otherwise */ static int adis_read_reg(struct adis *adis, unsigned int reg, unsigned int *val, unsigned int size) @@ -285,7 +300,9 @@ static int adis_read_reg(struct adis *adis, unsigned int reg, * adis_write_reg_8() - Write single byte to a register * @adis: The adis device * @reg: The address of the register to be written - * @value: The value to write + * @val: The value to write + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_write_reg_8(struct adis *adis, unsigned int reg, u8 val) @@ -297,7 +314,9 @@ static inline int adis_write_reg_8(struct adis *adis, unsigned int reg, * adis_write_reg_16() - Write 2 bytes to a pair of registers * @adis: The adis device * @reg: The address of the lower of the two registers - * @value: Value to be written + * @val: Value to be written + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_write_reg_16(struct adis *adis, unsigned int reg, u16 val) @@ -309,7 +328,9 @@ static inline int adis_write_reg_16(struct adis *adis, unsigned int reg, * adis_write_reg_32() - write 4 bytes to four registers * @adis: The adis device * @reg: The address of the lower of the four register - * @value: Value to be written + * @val: Value to be written + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_write_reg_32(struct adis *adis, unsigned int reg, u32 val) @@ -322,6 +343,8 @@ static inline int adis_write_reg_32(struct adis *adis, unsigned int reg, * @adis: The adis device * @reg: The address of the lower of the two registers * @val: The value read back from the device + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_read_reg_16(struct adis *adis, unsigned int reg, u16 *val) @@ -341,6 +364,8 @@ static inline int adis_read_reg_16(struct adis *adis, unsigned int reg, * @adis: The adis device * @reg: The address of the lower of the two registers * @val: The value read back from the device + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_read_reg_32(struct adis *adis, unsigned int reg, u32 *val) @@ -366,6 +391,8 @@ int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask, * @size: Size of the register to update * * Updates the desired bits of @reg in accordance with @mask and @val. + * + * Returns: %0 on success, a negative error code otherwise */ static inline int adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask, const u32 val, u8 size) From d2e805319bf092ea748cbfe84b775e1f398ed9b3 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 27 Oct 2025 14:50:30 +0200 Subject: [PATCH 181/304] iio: adc: rohm-bd79112: Use regmap_reg_range() Initializing the regmap_ranges using direct assignment to the range_min and range_max members is slightly verbose. We can make it a tad cleaner when using the regmap_reg_range() macro. Clean up the code using regmap_reg_range() when initializing the regmap_range structure. Signed-off-by: Matti Vaittinen Signed-off-by: Jonathan Cameron --- drivers/iio/adc/rohm-bd79112.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/rohm-bd79112.c b/drivers/iio/adc/rohm-bd79112.c index d15e06c8b94d..7420aa6627d5 100644 --- a/drivers/iio/adc/rohm-bd79112.c +++ b/drivers/iio/adc/rohm-bd79112.c @@ -168,15 +168,10 @@ static int _get_gpio_reg(unsigned int offset, unsigned int base) #define GET_GPI_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_VALUE_A0_A7) static const struct regmap_range bd71815_volatile_ro_ranges[] = { - { - /* Read ADC data */ - .range_min = BD79112_REG_AGIO0A, - .range_max = BD79112_REG_AGIO15B, - }, { - /* GPI state */ - .range_min = BD79112_REG_GPI_VALUE_B8_15, - .range_max = BD79112_REG_GPI_VALUE_A0_A7, - }, + /* Read ADC data */ + regmap_reg_range(BD79112_REG_AGIO0A, BD79112_REG_AGIO15B), + /* GPI state */ + regmap_reg_range(BD79112_REG_GPI_VALUE_B8_15, BD79112_REG_GPI_VALUE_A0_A7), }; static const struct regmap_access_table bd79112_volatile_regs = { From a337775ed8e7f9a8cf273cd61a3920f73aa9b422 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 27 Oct 2025 14:50:51 +0200 Subject: [PATCH 182/304] iio: adc: rohm-bd79124: Use regmap_reg_range() Initializing the regmap_ranges using direct assignment to the range_min and range_max members is slightly verbose. We can make it a tad cleaner when using the regmap_reg_range() macro. Clean up the code using regmap_reg_range() when initializing the regmap_range structure. Signed-off-by: Matti Vaittinen Signed-off-by: Jonathan Cameron --- drivers/iio/adc/rohm-bd79124.c | 39 ++++++++-------------------------- 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/iio/adc/rohm-bd79124.c b/drivers/iio/adc/rohm-bd79124.c index 06c55c8da93f..fc0452749b79 100644 --- a/drivers/iio/adc/rohm-bd79124.c +++ b/drivers/iio/adc/rohm-bd79124.c @@ -126,13 +126,8 @@ struct bd79124_data { }; static const struct regmap_range bd79124_ro_ranges[] = { - { - .range_min = BD79124_REG_EVENT_FLAG, - .range_max = BD79124_REG_EVENT_FLAG, - }, { - .range_min = BD79124_REG_RECENT_CH0_LSB, - .range_max = BD79124_REG_RECENT_CH7_MSB, - }, + regmap_reg_range(BD79124_REG_EVENT_FLAG, BD79124_REG_EVENT_FLAG), + regmap_reg_range(BD79124_REG_RECENT_CH0_LSB, BD79124_REG_RECENT_CH7_MSB), }; static const struct regmap_access_table bd79124_ro_regs = { @@ -141,22 +136,11 @@ static const struct regmap_access_table bd79124_ro_regs = { }; static const struct regmap_range bd79124_volatile_ranges[] = { - { - .range_min = BD79124_REG_RECENT_CH0_LSB, - .range_max = BD79124_REG_RECENT_CH7_MSB, - }, { - .range_min = BD79124_REG_EVENT_FLAG, - .range_max = BD79124_REG_EVENT_FLAG, - }, { - .range_min = BD79124_REG_EVENT_FLAG_HI, - .range_max = BD79124_REG_EVENT_FLAG_HI, - }, { - .range_min = BD79124_REG_EVENT_FLAG_LO, - .range_max = BD79124_REG_EVENT_FLAG_LO, - }, { - .range_min = BD79124_REG_SYSTEM_STATUS, - .range_max = BD79124_REG_SYSTEM_STATUS, - }, + regmap_reg_range(BD79124_REG_RECENT_CH0_LSB, BD79124_REG_RECENT_CH7_MSB), + regmap_reg_range(BD79124_REG_EVENT_FLAG, BD79124_REG_EVENT_FLAG), + regmap_reg_range(BD79124_REG_EVENT_FLAG_HI, BD79124_REG_EVENT_FLAG_HI), + regmap_reg_range(BD79124_REG_EVENT_FLAG_LO, BD79124_REG_EVENT_FLAG_LO), + regmap_reg_range(BD79124_REG_SYSTEM_STATUS, BD79124_REG_SYSTEM_STATUS), }; static const struct regmap_access_table bd79124_volatile_regs = { @@ -165,13 +149,8 @@ static const struct regmap_access_table bd79124_volatile_regs = { }; static const struct regmap_range bd79124_precious_ranges[] = { - { - .range_min = BD79124_REG_EVENT_FLAG_HI, - .range_max = BD79124_REG_EVENT_FLAG_HI, - }, { - .range_min = BD79124_REG_EVENT_FLAG_LO, - .range_max = BD79124_REG_EVENT_FLAG_LO, - }, + regmap_reg_range(BD79124_REG_EVENT_FLAG_HI, BD79124_REG_EVENT_FLAG_HI), + regmap_reg_range(BD79124_REG_EVENT_FLAG_LO, BD79124_REG_EVENT_FLAG_LO), }; static const struct regmap_access_table bd79124_precious_regs = { From 759cafdd8b4997b4f266b67ea5684373722742f2 Mon Sep 17 00:00:00 2001 From: Jack Hsu Date: Thu, 30 Oct 2025 21:44:34 +0800 Subject: [PATCH 183/304] dt-bindings: iio: adc: Support MediaTek MT8189 evb board auxadc add compatible string for mt8189 evb board dts node of auxadc Signed-off-by: Jack Hsu Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 14363389f30a..d9e825e5054f 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -42,6 +42,7 @@ properties: - mediatek,mt8183-auxadc - mediatek,mt8186-auxadc - mediatek,mt8188-auxadc + - mediatek,mt8189-auxadc - mediatek,mt8195-auxadc - mediatek,mt8516-auxadc - const: mediatek,mt8173-auxadc From 59f40887509d258d1ac40300f6b224cac853a6d1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 29 Oct 2025 15:27:18 -0400 Subject: [PATCH 184/304] dt-bindings: iio: imu: mpu6050: remove interrupts from required list Irq is optional signal to make sensor work. Not all boards connect this signals, so remove it from required list. Signed-off-by: Frank Li Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/imu/invensense,mpu6050.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml index 0bce71529e34..1af0855c33e6 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml @@ -86,7 +86,6 @@ unevaluatedProperties: false required: - compatible - reg - - interrupts examples: - | From 49708f45be675d726b6c39a0eee260c0df1f77bc Mon Sep 17 00:00:00 2001 From: Kriish Sharma Date: Tue, 28 Oct 2025 09:33:26 +0000 Subject: [PATCH 185/304] iio: backend: fix kernel-doc to avoid warnings and ensure consistency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix multiple kernel-doc warnings and make the documentation style consistent in drivers/iio/industrialio-backend.c. Changes include: - Add missing @chan parameter description in iio_backend_oversampling_ratio_set(). - Add missing RETURNS section in iio_backend_get_priv(). - Replace Return: with “RETURNS:” across the file for consistency. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202506292344.HLJbrrgR-lkp@intel.com Suggested-by: Andy Shevchenko Suggested-by: David Lechner Signed-off-by: Kriish Sharma Reviewed-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-backend.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-backend.c index 23760652a046..447b694d6d5f 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -702,7 +702,7 @@ EXPORT_SYMBOL_NS_GPL(iio_backend_interface_type_get, "IIO_BACKEND"); * interface/data bus. Hence, the backend device needs to be aware of it so * data can be correctly transferred. * - * Return: + * RETURNS: * 0 on success, negative error number on failure. */ int iio_backend_data_size_set(struct iio_backend *back, unsigned int size) @@ -717,9 +717,10 @@ EXPORT_SYMBOL_NS_GPL(iio_backend_data_size_set, "IIO_BACKEND"); /** * iio_backend_oversampling_ratio_set - set the oversampling ratio * @back: Backend device + * @chan: Channel number * @ratio: The oversampling ratio - value 1 corresponds to no oversampling. * - * Return: + * RETURNS: * 0 on success, negative error number on failure. */ int iio_backend_oversampling_ratio_set(struct iio_backend *back, @@ -1064,6 +1065,9 @@ EXPORT_SYMBOL_NS_GPL(__devm_iio_backend_get_from_fwnode_lookup, "IIO_BACKEND"); /** * iio_backend_get_priv - Get driver private data * @back: Backend device + * + * RETURNS: + * Pointer to the driver private data associated with the backend. */ void *iio_backend_get_priv(const struct iio_backend *back) { From e5191f62a67aada464ff2c4ab6d96a657b1486aa Mon Sep 17 00:00:00 2001 From: Chu Guangqing Date: Fri, 24 Oct 2025 15:38:20 +0800 Subject: [PATCH 186/304] iio: adc: ade9000: convert to use maple tree register cache The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Chu Guangqing Signed-off-by: Jonathan Cameron --- drivers/iio/adc/ade9000.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ade9000.c b/drivers/iio/adc/ade9000.c index 94e05e11abd9..2de8a718d62a 100644 --- a/drivers/iio/adc/ade9000.c +++ b/drivers/iio/adc/ade9000.c @@ -1629,7 +1629,7 @@ static const struct regmap_config ade9000_regmap_config = { .val_bits = 32, .max_register = 0x6bc, .zero_flag_mask = true, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, .reg_read = ade9000_spi_read_reg, .reg_write = ade9000_spi_write_reg, .volatile_reg = ade9000_is_volatile_reg, From 00d3bd9e3f7166220838d7065e52bffc85b871df Mon Sep 17 00:00:00 2001 From: Chu Guangqing Date: Fri, 24 Oct 2025 15:38:21 +0800 Subject: [PATCH 187/304] iio: light: veml3235: convert to use maple tree register cache The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Chu Guangqing Signed-off-by: Jonathan Cameron --- drivers/iio/light/veml3235.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/light/veml3235.c b/drivers/iio/light/veml3235.c index 77c9ae17ed47..9309ad83ca9e 100644 --- a/drivers/iio/light/veml3235.c +++ b/drivers/iio/light/veml3235.c @@ -154,7 +154,7 @@ static const struct regmap_config veml3235_regmap_config = { .rd_table = &veml3235_readable_table, .wr_table = &veml3235_writable_table, .volatile_table = &veml3235_volatile_table, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; static int veml3235_get_it(struct veml3235_data *data, int *val, int *val2) From 52d182b2ff99d5e50e763ad5a5a874da3b49434f Mon Sep 17 00:00:00 2001 From: Chu Guangqing Date: Fri, 24 Oct 2025 15:38:22 +0800 Subject: [PATCH 188/304] iio: light: apds9306: convert to use maple tree register cache The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Chu Guangqing Acked-by: Subhajit Ghosh Signed-off-by: Jonathan Cameron --- drivers/iio/light/apds9306.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/light/apds9306.c b/drivers/iio/light/apds9306.c index 389125675caa..7e68cca0edfa 100644 --- a/drivers/iio/light/apds9306.c +++ b/drivers/iio/light/apds9306.c @@ -350,7 +350,7 @@ static const struct regmap_config apds9306_regmap = { .volatile_table = &apds9306_volatile_table, .precious_table = &apds9306_precious_table, .max_register = APDS9306_ALS_THRES_VAR_REG, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; static const struct reg_field apds9306_rf_sw_reset = From 698dcf54282a221588281b2e1e6107707cc61f37 Mon Sep 17 00:00:00 2001 From: Chu Guangqing Date: Fri, 24 Oct 2025 15:38:23 +0800 Subject: [PATCH 189/304] iio: light: apds9960: convert to use maple tree register cache The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Chu Guangqing Signed-off-by: Jonathan Cameron --- drivers/iio/light/apds9960.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/light/apds9960.c b/drivers/iio/light/apds9960.c index 79b202c59a0f..785c5dbe2d08 100644 --- a/drivers/iio/light/apds9960.c +++ b/drivers/iio/light/apds9960.c @@ -234,7 +234,7 @@ static const struct regmap_config apds9960_regmap_config = { .reg_defaults = apds9960_reg_defaults, .num_reg_defaults = ARRAY_SIZE(apds9960_reg_defaults), .max_register = APDS9960_REG_GFIFO_DIR(RIGHT), - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; static const struct iio_event_spec apds9960_pxs_event_spec[] = { From 02f86101e430cce9a99a044b483c4ed5b91bb3b8 Mon Sep 17 00:00:00 2001 From: Rodrigo Gobbi Date: Sun, 2 Nov 2025 19:30:18 -0300 Subject: [PATCH 190/304] iio: imu: bmi270: fix dev_err_probe error msg The bmi270 can be connected to I2C or a SPI interface. If it is a SPI, during probe, if devm_regmap_init() fails, it should print the "spi" term rather "i2c". Fixes: 92cc50a00574 ("iio: imu: bmi270: Add spi driver for bmi270 imu") Signed-off-by: Rodrigo Gobbi Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/imu/bmi270/bmi270_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/imu/bmi270/bmi270_spi.c b/drivers/iio/imu/bmi270/bmi270_spi.c index 19dd7734f9d0..80c9fa1d685a 100644 --- a/drivers/iio/imu/bmi270/bmi270_spi.c +++ b/drivers/iio/imu/bmi270/bmi270_spi.c @@ -60,7 +60,7 @@ static int bmi270_spi_probe(struct spi_device *spi) &bmi270_spi_regmap_config); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), - "Failed to init i2c regmap"); + "Failed to init spi regmap\n"); return bmi270_core_probe(dev, regmap, chip_info); } From 69f5dcaa990e3f43c89fc5cec4ae92ececdb12f3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 3 Nov 2025 09:29:11 +0100 Subject: [PATCH 191/304] iio: common: scmi_sensors: Get rid of const_ilog2() Fisrt of all, const_ilog2() was a workaround of some sparse issue, which was never appeared in the C functions. Second, the calls here are done against constants and work with a bit of luck. Replace this altogether by a pre-calculated simple integer constant. Amend a comment to give a hint where it comes from. Signed-off-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/common/scmi_sensors/scmi_iio.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iio/common/scmi_sensors/scmi_iio.c b/drivers/iio/common/scmi_sensors/scmi_iio.c index 39c61c47022a..5136ad9ada04 100644 --- a/drivers/iio/common/scmi_sensors/scmi_iio.c +++ b/drivers/iio/common/scmi_sensors/scmi_iio.c @@ -66,10 +66,9 @@ static int scmi_iio_sensor_update_cb(struct notifier_block *nb, /* * Timestamp returned by SCMI is in seconds and is equal to * time * power-of-10 multiplier(tstamp_scale) seconds. - * Converting the timestamp to nanoseconds below. + * Converting the timestamp to nanoseconds (10⁹) below. */ - tstamp_scale = sensor->sensor_info->tstamp_scale + - const_ilog2(NSEC_PER_SEC) / const_ilog2(10); + tstamp_scale = sensor->sensor_info->tstamp_scale + 9; if (tstamp_scale < 0) { do_div(time, int_pow(10, abs(tstamp_scale))); time_ns = time; From 436cd7712598e9ca07c76f14d1531a1f6c3c502f Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Mon, 3 Nov 2025 18:52:16 +0800 Subject: [PATCH 192/304] dt-bindings: iio: adc: Add AST2700 ADC compatible strings Add the compatible strings "aspeed,ast2700-adc0" and "aspeed,ast2700-adc1" to the binding for the Aspeed ADC. These new compatibles represent the ADC instances found on the AST2700 SoC, which are similar to the AST2600 but have their trimming data located at different SCU offset. Signed-off-by: Billy Tsai Acked-by: Krzysztof Kozlowski Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml b/Documentation/devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml index 5c08d8b6e995..509bfb1007c4 100644 --- a/Documentation/devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml @@ -29,6 +29,8 @@ properties: enum: - aspeed,ast2600-adc0 - aspeed,ast2600-adc1 + - aspeed,ast2700-adc0 + - aspeed,ast2700-adc1 description: Their trimming data, which is used to calibrate internal reference volage, locates in different address of OTP. From 9d8b88ffb773470ea3a324b67e77e64c0fa8400d Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Mon, 3 Nov 2025 18:52:17 +0800 Subject: [PATCH 193/304] iio: adc: aspeed: Add AST2700 ADC support This patch adds support for the ADCs found on the Aspeed AST2700 SoC, which includes two instances: "ast2700-adc0" and "ast2700-adc1". While they are functionally similar to those on AST2600, the OTP trimming data is located at the same offset (0x820), but uses different bitfields. Signed-off-by: Billy Tsai Reviewed-by: David Lechner Signed-off-by: Jonathan Cameron --- drivers/iio/adc/aspeed_adc.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 1d5fd5f534b8..bf2bfd6bdc41 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -645,6 +645,16 @@ static const struct aspeed_adc_trim_locate ast2600_adc1_trim = { .field = GENMASK(7, 4), }; +static const struct aspeed_adc_trim_locate ast2700_adc0_trim = { + .offset = 0x820, + .field = GENMASK(3, 0), +}; + +static const struct aspeed_adc_trim_locate ast2700_adc1_trim = { + .offset = 0x820, + .field = GENMASK(7, 4), +}; + static const struct aspeed_adc_model_data ast2400_model_data = { .model_name = "ast2400-adc", .vref_fixed_mv = 2500, @@ -689,11 +699,35 @@ static const struct aspeed_adc_model_data ast2600_adc1_model_data = { .trim_locate = &ast2600_adc1_trim, }; +static const struct aspeed_adc_model_data ast2700_adc0_model_data = { + .model_name = "ast2700-adc0", + .min_sampling_rate = 10000, + .max_sampling_rate = 500000, + .wait_init_sequence = true, + .bat_sense_sup = true, + .scaler_bit_width = 16, + .num_channels = 8, + .trim_locate = &ast2700_adc0_trim, +}; + +static const struct aspeed_adc_model_data ast2700_adc1_model_data = { + .model_name = "ast2700-adc1", + .min_sampling_rate = 10000, + .max_sampling_rate = 500000, + .wait_init_sequence = true, + .bat_sense_sup = true, + .scaler_bit_width = 16, + .num_channels = 8, + .trim_locate = &ast2700_adc1_trim, +}; + static const struct of_device_id aspeed_adc_matches[] = { { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data }, { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data }, + { .compatible = "aspeed,ast2700-adc0", .data = &ast2700_adc0_model_data }, + { .compatible = "aspeed,ast2700-adc1", .data = &ast2700_adc1_model_data }, { } }; MODULE_DEVICE_TABLE(of, aspeed_adc_matches); From 77538d110933de556c8a2dae7c04fd459db58d8b Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Mon, 3 Nov 2025 15:18:31 +0100 Subject: [PATCH 194/304] dt-bindings: iio: adc: Add the Renesas RZ/N1 ADC The Renesas RZ/N1 ADC controller is the ADC controller available in the Renesas RZ/N1 SoCs family. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Rob Herring (Arm) Signed-off-by: Jonathan Cameron --- .../bindings/iio/adc/renesas,rzn1-adc.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml new file mode 100644 index 000000000000..1a40352165fb --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,rzn1-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Analog to Digital Converter (ADC) + +maintainers: + - Herve Codina + +description: + The Renesas RZ/N1 ADC controller available in the Renesas RZ/N1 SoCs family + can use up to two internal ADC cores (ADC1 and ADC2) those internal cores are + handled through ADC controller virtual channels. + +properties: + compatible: + items: + - const: renesas,r9a06g032-adc # RZ/N1D + - const: renesas,rzn1-adc + + reg: + maxItems: 1 + + clocks: + items: + - description: APB internal bus clock + - description: ADC clock + + clock-names: + items: + - const: pclk + - const: adc + + power-domains: + maxItems: 1 + + adc1-avdd-supply: + description: + ADC1 analog power supply. + + adc1-vref-supply: + description: + ADC1 reference voltage supply. + + adc2-avdd-supply: + description: + ADC2 analog power supply. + + adc2-vref-supply: + description: + ADC2 reference voltage supply. + + '#io-channel-cells': + const: 1 + description: | + Channels numbers available: + if ADC1 is used (i.e. adc1-{avdd,vref}-supply present): + - 0: ADC1 IN0 + - 1: ADC1 IN1 + - 2: ADC1 IN2 + - 3: ADC1 IN3 + - 4: ADC1 IN4 + - 5: ADC1 IN6 + - 6: ADC1 IN7 + - 7: ADC1 IN8 + if ADC2 is used (i.e. adc2-{avdd,vref}-supply present): + - 8: ADC2 IN0 + - 9: ADC2 IN1 + - 10: ADC2 IN2 + - 11: ADC2 IN3 + - 12: ADC2 IN4 + - 13: ADC2 IN6 + - 14: ADC2 IN7 + - 15: ADC2 IN8 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#io-channel-cells' + +# At least one of avvd/vref supplies +anyOf: + - required: + - adc1-vref-supply + - adc1-avdd-supply + - required: + - adc2-vref-supply + - adc2-avdd-supply + +additionalProperties: false + +examples: + - | + #include + + adc: adc@40065000 { + compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg = <0x40065000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; + clock-names = "pclk", "adc"; + power-domains = <&sysctrl>; + adc1-avdd-supply = <&adc1_avdd>; + adc1-vref-supply = <&adc1_vref>; + #io-channel-cells = <1>; + }; +... From 2387a7d6e5ab81cded0310f2d7544f4470666a6c Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Mon, 3 Nov 2025 15:18:32 +0100 Subject: [PATCH 195/304] iio: adc: Add support for the Renesas RZ/N1 ADC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Renesas RZ/N1 ADC controller is the ADC controller available in the Renesas RZ/N1 SoCs family. It can use up to two internal ADC cores (ADC1 and ADC2) those internal cores are not directly accessed but are handled through ADC controller virtual channels. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzn1-adc.c | 490 +++++++++++++++++++++++++++++++++++++ 3 files changed, 501 insertions(+) create mode 100644 drivers/iio/adc/rzn1-adc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 31335af6b2f1..58da8255525e 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1413,6 +1413,16 @@ config RZG2L_ADC To compile this driver as a module, choose M here: the module will be called rzg2l_adc. +config RZN1_ADC + tristate "Renesas RZ/N1 ADC driver" + depends on ARCH_RZN1 || COMPILE_TEST + help + Say yes here to build support for the ADC found in Renesas + RZ/N1 family. + + To compile this driver as a module, choose M here: the + module will be called rzn1-adc. + config RZT2H_ADC tristate "Renesas RZ/T2H / RZ/N2H ADC driver" depends on ARCH_RENESAS || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index e5349b01e4d9..7cc8f9a12f76 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -124,6 +124,7 @@ obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o +obj-$(CONFIG_RZN1_ADC) += rzn1-adc.o obj-$(CONFIG_RZT2H_ADC) += rzt2h_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o diff --git a/drivers/iio/adc/rzn1-adc.c b/drivers/iio/adc/rzn1-adc.c new file mode 100644 index 000000000000..93b0feef8ea0 --- /dev/null +++ b/drivers/iio/adc/rzn1-adc.c @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/N1 ADC driver + * + * Copyright (C) 2025 Schneider-Electric + * + * Author: Herve Codina + * + * The RZ/N1 ADC controller can handle channels from its internal ADC1 and/or + * ADC2 cores. The driver use ADC1 and/or ADC2 cores depending on the presence + * of the related power supplies (AVDD and VREF) description in the device-tree. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZN1_ADC_CONTROL_REG 0x02c +#define RZN1_ADC_CONTROL_ADC_BUSY BIT(6) + +#define RZN1_ADC_FORCE_REG 0x030 +#define RZN1_ADC_SET_FORCE_REG 0x034 +#define RZN1_ADC_CLEAR_FORCE_REG 0x038 +#define RZN1_ADC_FORCE_VC(_n) BIT(_n) + +#define RZN1_ADC_CONFIG_REG 0x040 +#define RZN1_ADC_CONFIG_ADC_POWER_DOWN BIT(3) + +#define RZN1_ADC_VC_REG(_n) (0x0c0 + 4 * (_n)) +#define RZN1_ADC_VC_ADC2_ENABLE BIT(16) +#define RZN1_ADC_VC_ADC1_ENABLE BIT(15) +#define RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK GENMASK(5, 3) +#define RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK GENMASK(2, 0) + +#define RZN1_ADC_ADC1_DATA_REG(_n) (0x100 + 4 * (_n)) +#define RZN1_ADC_ADC2_DATA_REG(_n) (0x140 + 4 * (_n)) +#define RZN1_ADC_ADCX_DATA_DATA_MASK GENMASK(11, 0) + +#define RZN1_ADC_NO_CHANNEL -1 + +#define RZN1_ADC_CHANNEL_SHARED_SCALE(_ch, _ds_name) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = (_ch), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .datasheet_name = (_ds_name), \ +} + +#define RZN1_ADC_CHANNEL_SEPARATED_SCALE(_ch, _ds_name) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = (_ch), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .datasheet_name = (_ds_name), \ +} + +/* + * 8 ADC1_IN signals existed numbered 0..4, 6..8 + * ADCx_IN5 doesn't exist in RZ/N1 datasheet + */ +static struct iio_chan_spec rzn1_adc1_channels[] = { + RZN1_ADC_CHANNEL_SHARED_SCALE(0, "ADC1_IN0"), + RZN1_ADC_CHANNEL_SHARED_SCALE(1, "ADC1_IN1"), + RZN1_ADC_CHANNEL_SHARED_SCALE(2, "ADC1_IN2"), + RZN1_ADC_CHANNEL_SHARED_SCALE(3, "ADC1_IN3"), + RZN1_ADC_CHANNEL_SHARED_SCALE(4, "ADC1_IN4"), + RZN1_ADC_CHANNEL_SHARED_SCALE(5, "ADC1_IN6"), + RZN1_ADC_CHANNEL_SHARED_SCALE(6, "ADC1_IN7"), + RZN1_ADC_CHANNEL_SHARED_SCALE(7, "ADC1_IN8"), +}; + +static struct iio_chan_spec rzn1_adc2_channels[] = { + RZN1_ADC_CHANNEL_SHARED_SCALE(8, "ADC2_IN0"), + RZN1_ADC_CHANNEL_SHARED_SCALE(9, "ADC2_IN1"), + RZN1_ADC_CHANNEL_SHARED_SCALE(10, "ADC2_IN2"), + RZN1_ADC_CHANNEL_SHARED_SCALE(11, "ADC2_IN3"), + RZN1_ADC_CHANNEL_SHARED_SCALE(12, "ADC2_IN4"), + RZN1_ADC_CHANNEL_SHARED_SCALE(13, "ADC2_IN6"), + RZN1_ADC_CHANNEL_SHARED_SCALE(14, "ADC2_IN7"), + RZN1_ADC_CHANNEL_SHARED_SCALE(15, "ADC2_IN8"), +}; + +/* + * If both ADCs core are used, scale cannot be common. Indeed, scale is + * based on Vref connected on each ADC core. + */ +static struct iio_chan_spec rzn1_adc1_adc2_channels[] = { + RZN1_ADC_CHANNEL_SEPARATED_SCALE(0, "ADC1_IN0"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(1, "ADC1_IN1"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(2, "ADC1_IN2"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(3, "ADC1_IN3"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(4, "ADC1_IN4"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(5, "ADC1_IN6"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(6, "ADC1_IN7"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(7, "ADC1_IN8"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(8, "ADC2_IN0"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(9, "ADC2_IN1"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(10, "ADC2_IN2"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(11, "ADC2_IN3"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(12, "ADC2_IN4"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(13, "ADC2_IN6"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(14, "ADC2_IN7"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(15, "ADC2_IN8"), +}; + +struct rzn1_adc { + struct device *dev; + void __iomem *regs; + struct mutex lock; /* ADC lock */ + int adc1_vref_mV; /* ADC1 Vref in mV. Negative if ADC1 is not used */ + int adc2_vref_mV; /* ADC2 Vref in mV. Negative if ADC2 is not used */ +}; + +static int rzn1_adc_power(struct rzn1_adc *rzn1_adc, bool power) +{ + u32 v; + + writel(power ? 0 : RZN1_ADC_CONFIG_ADC_POWER_DOWN, + rzn1_adc->regs + RZN1_ADC_CONFIG_REG); + + /* Wait for the ADC_BUSY to clear */ + return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG, + v, !(v & RZN1_ADC_CONTROL_ADC_BUSY), + 0, 500); +} + +static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch, + int adc1_ch, int adc2_ch) +{ + u32 vc = 0; + + if (adc1_ch != RZN1_ADC_NO_CHANNEL) + vc |= RZN1_ADC_VC_ADC1_ENABLE | + FIELD_PREP(RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK, adc1_ch); + + if (adc2_ch != RZN1_ADC_NO_CHANNEL) + vc |= RZN1_ADC_VC_ADC2_ENABLE | + FIELD_PREP(RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK, adc2_ch); + + writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch)); +} + +static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch) +{ + u32 val; + + val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG); + if (val & RZN1_ADC_FORCE_VC(ch)) + return -EBUSY; + + writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG); + + return 0; +} + +static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch) +{ + writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG); +} + +static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch, + u32 *adc1_data, u32 *adc2_data) +{ + u32 data_reg; + int ret; + u32 v; + + /* + * When a VC is selected, it needs 20 ADC clocks to perform the + * conversion. + * + * The worst case is when the 16 VCs need to perform a conversion and + * our VC is the lowest in term of priority. + * + * In that case, the conversion is performed in 16 * 20 ADC clocks. + * + * The ADC clock can be set from 4MHz to 20MHz. This leads to a worst + * case of 16 * 20 * 1/4Mhz = 80us. + * + * Round it up to 100us. + */ + + /* Wait for the ADC_FORCE_VC(n) to clear */ + ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG, + v, !(v & RZN1_ADC_FORCE_VC(ch)), + 0, 100); + if (ret) + return ret; + + if (adc1_data) { + data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch)); + *adc1_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg); + } + + if (adc2_data) { + data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch)); + *adc2_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg); + } + + return 0; +} + +static int rzn1_adc_read_raw_ch(struct rzn1_adc *rzn1_adc, unsigned int chan, int *val) +{ + u32 *adc1_data, *adc2_data; + int adc1_ch, adc2_ch; + u32 adc_data; + int ret; + + /* + * IIO chan are decoupled from chans used in rzn1_adc_vc_*() functions. + * The RZ/N1 ADC VC controller can handle on a single VC chan one + * channel from the ADC1 core and one channel from the ADC2 core. + * + * Even if IIO chans are mapped 1:1 to ADC core chans and so uses only + * a chan from ADC1 or a chan from ADC2, future improvements can define + * an IIO chan that uses one chan from ADC1 and one chan from ADC2. + */ + + if (chan < 8) { + /* chan 0..7 used to get ADC1 ch 0..7 */ + adc1_ch = chan; + adc1_data = &adc_data; + adc2_ch = RZN1_ADC_NO_CHANNEL; + adc2_data = NULL; + } else if (chan < 16) { + /* chan 8..15 used to get ADC2 ch 0..7 */ + adc1_ch = RZN1_ADC_NO_CHANNEL; + adc1_data = NULL; + adc2_ch = chan - 8; + adc2_data = &adc_data; + } else { + return -EINVAL; + } + + ACQUIRE(pm_runtime_active_auto_try_enabled, pm)(rzn1_adc->dev); + ret = ACQUIRE_ERR(pm_runtime_active_auto_try_enabled, &pm); + if (ret < 0) + return ret; + + scoped_guard(mutex, &rzn1_adc->lock) { + rzn1_adc_vc_setup_conversion(rzn1_adc, chan, adc1_ch, adc2_ch); + + ret = rzn1_adc_vc_start_conversion(rzn1_adc, chan); + if (ret) + return ret; + + ret = rzn1_adc_vc_wait_conversion(rzn1_adc, chan, adc1_data, adc2_data); + if (ret) { + rzn1_adc_vc_stop_conversion(rzn1_adc, chan); + return ret; + } + } + + *val = adc_data; + ret = IIO_VAL_INT; + + return 0; +} + +static int rzn1_adc_get_vref_mV(struct rzn1_adc *rzn1_adc, unsigned int chan) +{ + /* chan 0..7 use ADC1 ch 0..7. Vref related to ADC1 core */ + if (chan < 8) + return rzn1_adc->adc1_vref_mV; + + /* chan 8..15 use ADC2 ch 0..7. Vref related to ADC2 core */ + if (chan < 16) + return rzn1_adc->adc2_vref_mV; + + return -EINVAL; +} + +static int rzn1_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct rzn1_adc *rzn1_adc = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val); + if (ret) + return ret; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + ret = rzn1_adc_get_vref_mV(rzn1_adc, chan->channel); + if (ret < 0) + return ret; + *val = ret; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + + default: + return -EINVAL; + } +} + +static const struct iio_info rzn1_adc_info = { + .read_raw = &rzn1_adc_read_raw, +}; + +static int rzn1_adc_set_iio_dev_channels(struct rzn1_adc *rzn1_adc, + struct iio_dev *indio_dev) +{ + /* + * When an ADC core is not used, its related vref_mV is set to a + * negative error code. Use the correct IIO channels table based on + * those vref_mV values. + */ + if (rzn1_adc->adc1_vref_mV >= 0) { + if (rzn1_adc->adc2_vref_mV >= 0) { + indio_dev->channels = rzn1_adc1_adc2_channels; + indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_adc2_channels); + } else { + indio_dev->channels = rzn1_adc1_channels; + indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_channels); + } + return 0; + } + + if (rzn1_adc->adc2_vref_mV >= 0) { + indio_dev->channels = rzn1_adc2_channels; + indio_dev->num_channels = ARRAY_SIZE(rzn1_adc2_channels); + return 0; + } + + return dev_err_probe(rzn1_adc->dev, -ENODEV, + "Failed to set IIO channels, no ADC core used\n"); +} + +static int rzn1_adc_core_get_regulators(struct rzn1_adc *rzn1_adc, + int *adc_vref_mV, + const char *avdd_name, const char *vref_name) +{ + struct device *dev = rzn1_adc->dev; + int ret; + + /* + * For a given ADC core (ADC1 or ADC2), both regulators (AVDD and VREF) + * must be available in order to have the ADC core used. + * + * We use the regulators presence to check the usage of the related + * ADC core. If both regulators are available, the ADC core is used. + * Otherwise, the ADC core is not used. + * + * The adc_vref_mV value is set to a negative error code (-ENODEV) when + * the ADC core is not used. Otherwise it is set to the VRef mV value. + */ + + *adc_vref_mV = -ENODEV; + + ret = devm_regulator_get_enable_optional(dev, avdd_name); + if (ret == -ENODEV) + return 0; + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n", + avdd_name); + + ret = devm_regulator_get_enable_read_voltage(dev, vref_name); + if (ret == -ENODEV) + return 0; + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n", + vref_name); + + /* + * Both regulators are available. + * Set adc_vref_mV to the Vref value in mV. This, as the value set is + * positive, also signals that the ADC is used. + */ + *adc_vref_mV = ret / 1000; + + return 0; +} + +static int rzn1_adc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rzn1_adc *rzn1_adc; + struct clk *clk; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*rzn1_adc)); + if (!indio_dev) + return -ENOMEM; + + rzn1_adc = iio_priv(indio_dev); + rzn1_adc->dev = dev; + + ret = devm_mutex_init(dev, &rzn1_adc->lock); + if (ret) + return ret; + + rzn1_adc->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rzn1_adc->regs)) + return PTR_ERR(rzn1_adc->regs); + + clk = devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get pclk\n"); + + clk = devm_clk_get_enabled(dev, "adc"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get adc clk\n"); + + ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc1_vref_mV, + "adc1-avdd", "adc1-vref"); + if (ret) + return ret; + + ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc2_vref_mV, + "adc2-avdd", "adc2-vref"); + if (ret) + return ret; + + platform_set_drvdata(pdev, rzn1_adc); + + indio_dev->name = "rzn1-adc"; + indio_dev->info = &rzn1_adc_info; + indio_dev->modes = INDIO_DIRECT_MODE; + ret = rzn1_adc_set_iio_dev_channels(rzn1_adc, indio_dev); + if (ret) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 500); + pm_runtime_use_autosuspend(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static int rzn1_adc_pm_runtime_suspend(struct device *dev) +{ + struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev); + + return rzn1_adc_power(rzn1_adc, false); +} + +static int rzn1_adc_pm_runtime_resume(struct device *dev) +{ + struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev); + + return rzn1_adc_power(rzn1_adc, true); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(rzn1_adc_pm_ops, + rzn1_adc_pm_runtime_suspend, + rzn1_adc_pm_runtime_resume, + NULL); + +static const struct of_device_id rzn1_adc_of_match[] = { + { .compatible = "renesas,rzn1-adc" }, + { } +}; +MODULE_DEVICE_TABLE(of, rzn1_adc_of_match); + +static struct platform_driver rzn1_adc_driver = { + .probe = rzn1_adc_probe, + .driver = { + .name = "rzn1-adc", + .of_match_table = rzn1_adc_of_match, + .pm = pm_ptr(&rzn1_adc_pm_ops), + }, +}; +module_platform_driver(rzn1_adc_driver); + +MODULE_AUTHOR("Herve Codina "); +MODULE_DESCRIPTION("Renesas RZ/N1 ADC Driver"); +MODULE_LICENSE("GPL"); From 5478fd5a599463970378c874dcc4ccb9e1113c63 Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Mon, 3 Nov 2025 15:18:34 +0100 Subject: [PATCH 196/304] MAINTAINERS: Add the Renesas RZ/N1 ADC driver entry After contributing the driver, add myself as the maintainer for the Renesas RZ/N1 ADC driver. Signed-off-by: Herve Codina (Schneider Electric) Signed-off-by: Jonathan Cameron --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9f3413e05c83..647ba29ede5c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21914,6 +21914,13 @@ F: include/dt-bindings/net/pcs-rzn1-miic.h F: include/linux/pcs-rzn1-miic.h F: net/dsa/tag_rzn1_a5psw.c +RENESAS RZ/N1 ADC DRIVER +M: Herve Codina +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml +F: drivers/iio/adc/rzn1-adc.c + RENESAS RZ/N1 DWMAC GLUE LAYER M: Romain Gantois S: Maintained From 2e5f09334719bb9bd319c97c067dac9a9aa82df5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:06 +0000 Subject: [PATCH 197/304] dt-bindings: iio: dac: Document AD5446 and similar devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device tree binding documentation for the Analog Devices AD5446 family of Digital-to-Analog Converters and derivative devices from Texas Instruments. There's both SPI and I2C interfaces and feature resolutions ranging from 8-bit to 16-bit. The binding covers 29 derivatives devices including the AD5446 series, AD5600 series, AD5620/5640/5660 variants with different voltage ranges, and TI DAC081s101/DAC101s101/DAC121s101 devices. Signed-off-by: Nuno Sá Acked-by: Conor Dooley Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- .../bindings/iio/dac/adi,ad5446.yaml | 138 ++++++++++++++++++ MAINTAINERS | 8 + 2 files changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ad5446.yaml diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5446.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5446.yaml new file mode 100644 index 000000000000..2669d2c4948b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5446.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5446.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5446 and similar DACs + +maintainers: + - Michael Hennerich + - Nuno Sá + +description: + Digital to Analog Converter devices supporting both SPI and I2C interfaces. + These devices feature a range of resolutions from 8-bit to 16-bit. + +properties: + compatible: + oneOf: + - description: SPI DACs + enum: + - adi,ad5300 + - adi,ad5310 + - adi,ad5320 + - adi,ad5444 + - adi,ad5446 + - adi,ad5450 + - adi,ad5451 + - adi,ad5452 + - adi,ad5453 + - adi,ad5512a + - adi,ad5541a + - adi,ad5542 + - adi,ad5542a + - adi,ad5543 + - adi,ad5553 + - adi,ad5600 + - adi,ad5601 + - adi,ad5611 + - adi,ad5621 + - adi,ad5641 + - adi,ad5620-2500 + - adi,ad5620-1250 + - adi,ad5640-2500 + - adi,ad5640-1250 + - adi,ad5660-2500 + - adi,ad5660-1250 + - adi,ad5662 + - ti,dac081s101 + - ti,dac101s101 + - ti,dac121s101 + - description: I2C DACs + enum: + - adi,ad5301 + - adi,ad5311 + - adi,ad5321 + - adi,ad5602 + - adi,ad5612 + - adi,ad5622 + + reg: + maxItems: 1 + + vcc-supply: + description: + Reference voltage supply. If not supplied, devices with internal + voltage reference will use that. + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,ad5300 + - adi,ad5310 + - adi,ad5320 + - adi,ad5444 + - adi,ad5446 + - adi,ad5450 + - adi,ad5451 + - adi,ad5452 + - adi,ad5453 + - adi,ad5512a + - adi,ad5541a + - adi,ad5542 + - adi,ad5542a + - adi,ad5543 + - adi,ad5553 + - adi,ad5600 + - adi,ad5601 + - adi,ad5611 + - adi,ad5621 + - adi,ad5641 + - adi,ad5620-2500 + - adi,ad5620-1250 + - adi,ad5640-2500 + - adi,ad5640-1250 + - adi,ad5660-2500 + - adi,ad5660-1250 + - adi,ad5662 + - ti,dac081s101 + - ti,dac101s101 + - ti,dac121s101 + then: + allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "adi,ad5446"; + reg = <0>; + vcc-supply = <&dac_vref>; + }; + }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dac@42 { + compatible = "adi,ad5622"; + reg = <0x42>; + vcc-supply = <&dac_vref>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 647ba29ede5c..f4b661860127 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -440,6 +440,14 @@ W: http://wiki.analog.com/AD5398 W: https://ez.analog.com/linux-software-drivers F: drivers/regulator/ad5398.c +AD5446 ANALOG DEVICES INC AD5446 DAC DRIVER +M: Michael Hennerich +M: Nuno Sá +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/dac/adi,ad5446.yaml + AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A) M: Michael Hennerich S: Supported From 86c341d796b91f147d8995fe10ff92f8c9d57f41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:07 +0000 Subject: [PATCH 198/304] iio: dac: ad5446: Use DMA safe buffer for transfers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make sure to use DMA safe buffer. While for i2c we could be fine without them, we need it for spi anyways. As we now have DMA safe buffers, use i2c_master_send_dmasafe(). Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index ad304b0fec08..ce19e20dd38e 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -37,6 +37,8 @@ * @pwr_down_mode: power down mode (1k, 100k or tristate) * @pwr_down: true if the device is in power down * @lock: lock to protect the data buffer during write ops + * @d16: 16bit DMA safe buffer + * @d24: 24bit DMA safe buffer */ struct ad5446_state { @@ -47,6 +49,10 @@ struct ad5446_state { unsigned pwr_down_mode; unsigned pwr_down; struct mutex lock; + union { + __be16 d16; + u8 d24[3]; + } __aligned(IIO_DMA_MINALIGN); }; /** @@ -265,19 +271,18 @@ static int ad5446_probe(struct device *dev, const char *name, static int ad5446_write(struct ad5446_state *st, unsigned val) { struct spi_device *spi = to_spi_device(st->dev); - __be16 data = cpu_to_be16(val); + st->d16 = cpu_to_be16(val); - return spi_write(spi, &data, sizeof(data)); + return spi_write(spi, &st->d16, sizeof(st->d16)); } static int ad5660_write(struct ad5446_state *st, unsigned val) { struct spi_device *spi = to_spi_device(st->dev); - uint8_t data[3]; - put_unaligned_be24(val, &data[0]); + put_unaligned_be24(val, st->d24); - return spi_write(spi, data, sizeof(data)); + return spi_write(spi, st->d24, sizeof(st->d24)); } /* @@ -489,13 +494,13 @@ static inline void ad5446_spi_unregister_driver(void) { } static int ad5622_write(struct ad5446_state *st, unsigned val) { struct i2c_client *client = to_i2c_client(st->dev); - __be16 data = cpu_to_be16(val); + st->d16 = cpu_to_be16(val); int ret; - ret = i2c_master_send(client, (char *)&data, sizeof(data)); + ret = i2c_master_send_dmasafe(client, (char *)&st->d16, sizeof(st->d16)); if (ret < 0) return ret; - if (ret != sizeof(data)) + if (ret != sizeof(st->d16)) return -EIO; return 0; From 63232c9b5413bf398f62425266dfacaa321564c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:08 +0000 Subject: [PATCH 199/304] iio: dac: ad5446: Drop duplicated spi_id entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AD5600 and AD5541A are compatible so there's no need to have a dedicated entry for ID_AD5600. Suggested-by: Andy Shevchenko Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index ce19e20dd38e..4e4e080833d9 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -303,7 +303,6 @@ enum ad5446_supported_spi_device_ids { ID_AD5541A, ID_AD5512A, ID_AD5553, - ID_AD5600, ID_AD5601, ID_AD5611, ID_AD5621, @@ -358,10 +357,6 @@ static const struct ad5446_chip_info ad5446_spi_chip_info[] = { .channel = AD5446_CHANNEL(14, 16, 0), .write = ad5446_write, }, - [ID_AD5600] = { - .channel = AD5446_CHANNEL(16, 16, 0), - .write = ad5446_write, - }, [ID_AD5601] = { .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6), .write = ad5446_write, @@ -429,7 +424,7 @@ static const struct spi_device_id ad5446_spi_ids[] = { {"ad5542a", ID_AD5541A}, /* ad5541a and ad5542a are compatible */ {"ad5543", ID_AD5541A}, /* ad5541a and ad5543 are compatible */ {"ad5553", ID_AD5553}, - {"ad5600", ID_AD5600}, + {"ad5600", ID_AD5541A}, /* ad5541a and ad5600 are compatible */ {"ad5601", ID_AD5601}, {"ad5611", ID_AD5611}, {"ad5621", ID_AD5621}, From 14b72d8acea0a5c53dcffacafa43a9090fda3311 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:09 +0000 Subject: [PATCH 200/304] iio: dac: ad5446: Don't ignore missing regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the chip does not have an internal reference, do not ignore a missing regulator as we won't be able to actually provide a proper scale for the DAC. Since it's now seen as an error, flip the if() logic so errors are treated first (which is the typical pattern). Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index 4e4e080833d9..f7ec65249322 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -255,10 +255,11 @@ static int ad5446_probe(struct device *dev, const char *name, if (ret < 0 && ret != -ENODEV) return ret; if (ret == -ENODEV) { - if (chip_info->int_vref_mv) - st->vref_mv = chip_info->int_vref_mv; - else - dev_warn(dev, "reference voltage unspecified\n"); + if (!chip_info->int_vref_mv) + return dev_err_probe(dev, ret, + "reference voltage unspecified\n"); + + st->vref_mv = chip_info->int_vref_mv; } else { st->vref_mv = ret / 1000; } From 45d510a7203f63caa0298e40190b364d4646e2b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:10 +0000 Subject: [PATCH 201/304] iio: dac: ad5446: Move to single chip_info structures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not use an array with an enum id kind of thing. Use the more maintainable chip_info variable per chip. Adapt the probe functions to use the proper helpers (for SPI and I2c). Note that in a following patch we'll also add the chip_info variables to the of_device_id tables. Hence already use the helpers that internally use device_get_match_data(). Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 340 +++++++++++++++++++-------------------- 1 file changed, 170 insertions(+), 170 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index f7ec65249322..fa0c543cb9fb 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -293,154 +293,150 @@ static int ad5660_write(struct ad5446_state *st, unsigned val) * (and a bit cryptic), however this style is used to make clear which * parts are supported here. */ -enum ad5446_supported_spi_device_ids { - ID_AD5300, - ID_AD5310, - ID_AD5320, - ID_AD5444, - ID_AD5446, - ID_AD5450, - ID_AD5451, - ID_AD5541A, - ID_AD5512A, - ID_AD5553, - ID_AD5601, - ID_AD5611, - ID_AD5621, - ID_AD5641, - ID_AD5620_2500, - ID_AD5620_1250, - ID_AD5640_2500, - ID_AD5640_1250, - ID_AD5660_2500, - ID_AD5660_1250, - ID_AD5662, + +static const struct ad5446_chip_info ad5300_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), + .write = ad5446_write, }; -static const struct ad5446_chip_info ad5446_spi_chip_info[] = { - [ID_AD5300] = { - .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), - .write = ad5446_write, - }, - [ID_AD5310] = { - .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), - .write = ad5446_write, - }, - [ID_AD5320] = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), - .write = ad5446_write, - }, - [ID_AD5444] = { - .channel = AD5446_CHANNEL(12, 16, 2), - .write = ad5446_write, - }, - [ID_AD5446] = { - .channel = AD5446_CHANNEL(14, 16, 0), - .write = ad5446_write, - }, - [ID_AD5450] = { - .channel = AD5446_CHANNEL(8, 16, 6), - .write = ad5446_write, - }, - [ID_AD5451] = { - .channel = AD5446_CHANNEL(10, 16, 4), - .write = ad5446_write, - }, - [ID_AD5541A] = { - .channel = AD5446_CHANNEL(16, 16, 0), - .write = ad5446_write, - }, - [ID_AD5512A] = { - .channel = AD5446_CHANNEL(12, 16, 4), - .write = ad5446_write, - }, - [ID_AD5553] = { - .channel = AD5446_CHANNEL(14, 16, 0), - .write = ad5446_write, - }, - [ID_AD5601] = { - .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6), - .write = ad5446_write, - }, - [ID_AD5611] = { - .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 4), - .write = ad5446_write, - }, - [ID_AD5621] = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), - .write = ad5446_write, - }, - [ID_AD5641] = { - .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), - .write = ad5446_write, - }, - [ID_AD5620_2500] = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), - .int_vref_mv = 2500, - .write = ad5446_write, - }, - [ID_AD5620_1250] = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), - .int_vref_mv = 1250, - .write = ad5446_write, - }, - [ID_AD5640_2500] = { - .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), - .int_vref_mv = 2500, - .write = ad5446_write, - }, - [ID_AD5640_1250] = { - .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), - .int_vref_mv = 1250, - .write = ad5446_write, - }, - [ID_AD5660_2500] = { - .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), - .int_vref_mv = 2500, - .write = ad5660_write, - }, - [ID_AD5660_1250] = { - .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), - .int_vref_mv = 1250, - .write = ad5660_write, - }, - [ID_AD5662] = { - .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), - .write = ad5660_write, - }, +static const struct ad5446_chip_info ad5310_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5320_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5444_chip_info = { + .channel = AD5446_CHANNEL(12, 16, 2), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5446_chip_info = { + .channel = AD5446_CHANNEL(14, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5450_chip_info = { + .channel = AD5446_CHANNEL(8, 16, 6), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5451_chip_info = { + .channel = AD5446_CHANNEL(10, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5541a_chip_info = { + .channel = AD5446_CHANNEL(16, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5512a_chip_info = { + .channel = AD5446_CHANNEL(12, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5553_chip_info = { + .channel = AD5446_CHANNEL(14, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5601_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5611_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5621_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5641_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5620_2500_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), + .int_vref_mv = 2500, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5620_1250_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), + .int_vref_mv = 1250, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5640_2500_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), + .int_vref_mv = 2500, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5640_1250_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), + .int_vref_mv = 1250, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5660_2500_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), + .int_vref_mv = 2500, + .write = ad5660_write, +}; + +static const struct ad5446_chip_info ad5660_1250_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), + .int_vref_mv = 1250, + .write = ad5660_write, +}; + +static const struct ad5446_chip_info ad5662_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), + .write = ad5660_write, }; static const struct spi_device_id ad5446_spi_ids[] = { - {"ad5300", ID_AD5300}, - {"ad5310", ID_AD5310}, - {"ad5320", ID_AD5320}, - {"ad5444", ID_AD5444}, - {"ad5446", ID_AD5446}, - {"ad5450", ID_AD5450}, - {"ad5451", ID_AD5451}, - {"ad5452", ID_AD5444}, /* ad5452 is compatible to the ad5444 */ - {"ad5453", ID_AD5446}, /* ad5453 is compatible to the ad5446 */ - {"ad5512a", ID_AD5512A}, - {"ad5541a", ID_AD5541A}, - {"ad5542a", ID_AD5541A}, /* ad5541a and ad5542a are compatible */ - {"ad5543", ID_AD5541A}, /* ad5541a and ad5543 are compatible */ - {"ad5553", ID_AD5553}, - {"ad5600", ID_AD5541A}, /* ad5541a and ad5600 are compatible */ - {"ad5601", ID_AD5601}, - {"ad5611", ID_AD5611}, - {"ad5621", ID_AD5621}, - {"ad5641", ID_AD5641}, - {"ad5620-2500", ID_AD5620_2500}, /* AD5620/40/60: */ - {"ad5620-1250", ID_AD5620_1250}, /* part numbers may look differently */ - {"ad5640-2500", ID_AD5640_2500}, - {"ad5640-1250", ID_AD5640_1250}, - {"ad5660-2500", ID_AD5660_2500}, - {"ad5660-1250", ID_AD5660_1250}, - {"ad5662", ID_AD5662}, - {"dac081s101", ID_AD5300}, /* compatible Texas Instruments chips */ - {"dac101s101", ID_AD5310}, - {"dac121s101", ID_AD5320}, - {"dac7512", ID_AD5320}, + {"ad5300", (kernel_ulong_t)&ad5300_chip_info}, + {"ad5310", (kernel_ulong_t)&ad5310_chip_info}, + {"ad5320", (kernel_ulong_t)&ad5320_chip_info}, + {"ad5444", (kernel_ulong_t)&ad5444_chip_info}, + {"ad5446", (kernel_ulong_t)&ad5446_chip_info}, + {"ad5450", (kernel_ulong_t)&ad5450_chip_info}, + {"ad5451", (kernel_ulong_t)&ad5451_chip_info}, + {"ad5452", (kernel_ulong_t)&ad5444_chip_info}, /* ad5452 is compatible to the ad5444 */ + {"ad5453", (kernel_ulong_t)&ad5446_chip_info}, /* ad5453 is compatible to the ad5446 */ + {"ad5512a", (kernel_ulong_t)&ad5512a_chip_info}, + {"ad5541a", (kernel_ulong_t)&ad5541a_chip_info}, + {"ad5542a", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5542a are compatible */ + {"ad5543", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5543 are compatible */ + {"ad5553", (kernel_ulong_t)&ad5553_chip_info}, + {"ad5600", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5600 are compatible */ + {"ad5601", (kernel_ulong_t)&ad5601_chip_info}, + {"ad5611", (kernel_ulong_t)&ad5611_chip_info}, + {"ad5621", (kernel_ulong_t)&ad5621_chip_info}, + {"ad5641", (kernel_ulong_t)&ad5641_chip_info}, + {"ad5620-2500", (kernel_ulong_t)&ad5620_2500_chip_info}, /* AD5620/40/60: */ + /* part numbers may look differently */ + {"ad5620-1250", (kernel_ulong_t)&ad5620_1250_chip_info}, + {"ad5640-2500", (kernel_ulong_t)&ad5640_2500_chip_info}, + {"ad5640-1250", (kernel_ulong_t)&ad5640_1250_chip_info}, + {"ad5660-2500", (kernel_ulong_t)&ad5660_2500_chip_info}, + {"ad5660-1250", (kernel_ulong_t)&ad5660_1250_chip_info}, + {"ad5662", (kernel_ulong_t)&ad5662_chip_info}, + {"dac081s101", (kernel_ulong_t)&ad5300_chip_info}, /* compatible Texas Instruments chips */ + {"dac101s101", (kernel_ulong_t)&ad5310_chip_info}, + {"dac121s101", (kernel_ulong_t)&ad5320_chip_info}, + {"dac7512", (kernel_ulong_t)&ad5320_chip_info}, { } }; MODULE_DEVICE_TABLE(spi, ad5446_spi_ids); @@ -454,9 +450,13 @@ MODULE_DEVICE_TABLE(of, ad5446_of_ids); static int ad5446_spi_probe(struct spi_device *spi) { const struct spi_device_id *id = spi_get_device_id(spi); + const struct ad5446_chip_info *chip_info; - return ad5446_probe(&spi->dev, id->name, - &ad5446_spi_chip_info[id->driver_data]); + chip_info = spi_get_device_match_data(spi); + if (!chip_info) + return -ENODEV; + + return ad5446_probe(&spi->dev, id->name, chip_info); } static struct spi_driver ad5446_spi_driver = { @@ -509,41 +509,41 @@ static int ad5622_write(struct ad5446_state *st, unsigned val) * (and a bit cryptic), however this style is used to make clear which * parts are supported here. */ -enum ad5446_supported_i2c_device_ids { - ID_AD5602, - ID_AD5612, - ID_AD5622, + +static const struct ad5446_chip_info ad5602_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), + .write = ad5622_write, }; -static const struct ad5446_chip_info ad5446_i2c_chip_info[] = { - [ID_AD5602] = { - .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), - .write = ad5622_write, - }, - [ID_AD5612] = { - .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), - .write = ad5622_write, - }, - [ID_AD5622] = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), - .write = ad5622_write, - }, +static const struct ad5446_chip_info ad5612_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), + .write = ad5622_write, +}; + +static const struct ad5446_chip_info ad5622_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), + .write = ad5622_write, }; static int ad5446_i2c_probe(struct i2c_client *i2c) { const struct i2c_device_id *id = i2c_client_get_device_id(i2c); - return ad5446_probe(&i2c->dev, id->name, - &ad5446_i2c_chip_info[id->driver_data]); + const struct ad5446_chip_info *chip_info; + + chip_info = i2c_get_match_data(i2c); + if (!chip_info) + return -ENODEV; + + return ad5446_probe(&i2c->dev, id->name, chip_info); } static const struct i2c_device_id ad5446_i2c_ids[] = { - {"ad5301", ID_AD5602}, - {"ad5311", ID_AD5612}, - {"ad5321", ID_AD5622}, - {"ad5602", ID_AD5602}, - {"ad5612", ID_AD5612}, - {"ad5622", ID_AD5622}, + {"ad5301", (kernel_ulong_t)&ad5602_chip_info}, + {"ad5311", (kernel_ulong_t)&ad5612_chip_info}, + {"ad5321", (kernel_ulong_t)&ad5622_chip_info}, + {"ad5602", (kernel_ulong_t)&ad5602_chip_info}, + {"ad5612", (kernel_ulong_t)&ad5612_chip_info}, + {"ad5622", (kernel_ulong_t)&ad5622_chip_info}, { } }; MODULE_DEVICE_TABLE(i2c, ad5446_i2c_ids); From 5b622340bf19c2192ee5769f1b603ab5711949be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:11 +0000 Subject: [PATCH 202/304] iio: dac: ad5456: Add missing DT compatibles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing of_device_id compatibles for the i2c and spi drivers. Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index fa0c543cb9fb..37e17b7eb2fa 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -442,6 +442,35 @@ static const struct spi_device_id ad5446_spi_ids[] = { MODULE_DEVICE_TABLE(spi, ad5446_spi_ids); static const struct of_device_id ad5446_of_ids[] = { + { .compatible = "adi,ad5300", .data = &ad5300_chip_info }, + { .compatible = "adi,ad5310", .data = &ad5310_chip_info }, + { .compatible = "adi,ad5320", .data = &ad5320_chip_info }, + { .compatible = "adi,ad5444", .data = &ad5444_chip_info }, + { .compatible = "adi,ad5446", .data = &ad5446_chip_info }, + { .compatible = "adi,ad5450", .data = &ad5450_chip_info }, + { .compatible = "adi,ad5451", .data = &ad5451_chip_info }, + { .compatible = "adi,ad5452", .data = &ad5444_chip_info }, + { .compatible = "adi,ad5453", .data = &ad5446_chip_info }, + { .compatible = "adi,ad5512a", .data = &ad5512a_chip_info }, + { .compatible = "adi,ad5541a", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5542a", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5543", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5553", .data = &ad5553_chip_info }, + { .compatible = "adi,ad5600", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5601", .data = &ad5601_chip_info }, + { .compatible = "adi,ad5611", .data = &ad5611_chip_info }, + { .compatible = "adi,ad5621", .data = &ad5621_chip_info }, + { .compatible = "adi,ad5641", .data = &ad5641_chip_info }, + { .compatible = "adi,ad5620-2500", .data = &ad5620_2500_chip_info }, + { .compatible = "adi,ad5620-1250", .data = &ad5620_1250_chip_info }, + { .compatible = "adi,ad5640-2500", .data = &ad5640_2500_chip_info }, + { .compatible = "adi,ad5640-1250", .data = &ad5640_1250_chip_info }, + { .compatible = "adi,ad5660-2500", .data = &ad5660_2500_chip_info }, + { .compatible = "adi,ad5660-1250", .data = &ad5660_1250_chip_info }, + { .compatible = "adi,ad5662", .data = &ad5662_chip_info }, + { .compatible = "ti,dac081s101", .data = &ad5300_chip_info }, + { .compatible = "ti,dac101s101", .data = &ad5310_chip_info }, + { .compatible = "ti,dac121s101", .data = &ad5320_chip_info }, { .compatible = "ti,dac7512" }, { } }; @@ -548,9 +577,21 @@ static const struct i2c_device_id ad5446_i2c_ids[] = { }; MODULE_DEVICE_TABLE(i2c, ad5446_i2c_ids); +static const struct of_device_id ad5446_i2c_of_ids[] = { + { .compatible = "adi,ad5301", .data = &ad5602_chip_info }, + { .compatible = "adi,ad5311", .data = &ad5612_chip_info }, + { .compatible = "adi,ad5321", .data = &ad5622_chip_info }, + { .compatible = "adi,ad5602", .data = &ad5602_chip_info }, + { .compatible = "adi,ad5612", .data = &ad5612_chip_info }, + { .compatible = "adi,ad5622", .data = &ad5622_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad5446_i2c_of_ids); + static struct i2c_driver ad5446_i2c_driver = { .driver = { .name = "ad5446", + .of_match_table = ad5446_i2c_of_ids, }, .probe = ad5446_i2c_probe, .id_table = ad5446_i2c_ids, From 876d94024087b03494b206a5b5561fcd267824e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:12 +0000 Subject: [PATCH 203/304] iio: dac: ad5446: Separate I2C/SPI into different drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Properly separate the I2C and SPI drivers into two different drivers living in their own source file (as usual). So that no need for the hacky ifdefery. Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- MAINTAINERS | 4 + drivers/iio/dac/Kconfig | 31 ++- drivers/iio/dac/Makefile | 2 + drivers/iio/dac/ad5446-i2c.c | 102 ++++++++ drivers/iio/dac/ad5446-spi.c | 250 +++++++++++++++++++ drivers/iio/dac/ad5446.c | 452 +---------------------------------- drivers/iio/dac/ad5446.h | 76 ++++++ 7 files changed, 466 insertions(+), 451 deletions(-) create mode 100644 drivers/iio/dac/ad5446-i2c.c create mode 100644 drivers/iio/dac/ad5446-spi.c create mode 100644 drivers/iio/dac/ad5446.h diff --git a/MAINTAINERS b/MAINTAINERS index f4b661860127..31d98efb1ad1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -447,6 +447,10 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/dac/adi,ad5446.yaml +F: drivers/iio/dac/ad5446-i2c.c +F: drivers/iio/dac/ad5446-spi.c +F: drivers/iio/dac/ad5446.c +F: drivers/iio/dac/ad5446.h AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A) M: Michael Hennerich diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index e0996dc014a3..7cd3caec1262 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -97,17 +97,32 @@ config AD5421 ad5421. config AD5446 - tristate "Analog Devices AD5446 and similar single channel DACs driver" - depends on (SPI_MASTER && I2C!=m) || I2C + tristate + +config AD5446_SPI + tristate "Analog Devices AD5446 and similar single channel DACs driver (SPI)" + depends on SPI + select AD5446 help - Say yes here to build support for Analog Devices AD5300, AD5301, AD5310, - AD5311, AD5320, AD5321, AD5444, AD5446, AD5450, AD5451, AD5452, AD5453, - AD5512A, AD5541A, AD5542A, AD5543, AD5553, AD5600, AD5601, AD5602, AD5611, - AD5612, AD5620, AD5621, AD5622, AD5640, AD5641, AD5660, AD5662 DACs - as well as Texas Instruments DAC081S101, DAC101S101, DAC121S101. + Say yes here to build support for Analog Devices AD5300, AD5310, + AD5320, AD5444, AD5446, AD5450, AD5451, AD5452, AD5453, AD5512A, + AD5541A, AD5542A, AD5543, AD5553, AD5600, AD5601, AD5611, AD5620, + AD5621, AD5640, AD5641, AD5660, AD5662 DACs as well as + Texas Instruments DAC081S101, DAC101S101, DAC121S101. To compile this driver as a module, choose M here: the - module will be called ad5446. + module will be called ad5446-spi. + +config AD5446_I2C + tristate "Analog Devices AD5446 and similar single channel DACs driver (I2C)" + depends on I2C + select AD5446 + help + Say yes here to build support for Analog Devices AD5301, AD5311, AD5321, + AD5602, AD5612, AD5622 DACs. + + To compile this driver as a module, choose M here: the + module will be called ad5446-i2c. config AD5449 tristate "Analog Devices AD5449 and similar DACs driver" diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 3684cd52b7fa..e6ac4c67e337 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -15,6 +15,8 @@ obj-$(CONFIG_AD5624R_SPI) += ad5624r_spi.o obj-$(CONFIG_AD5064) += ad5064.o obj-$(CONFIG_AD5504) += ad5504.o obj-$(CONFIG_AD5446) += ad5446.o +obj-$(CONFIG_AD5446_SPI) += ad5446-spi.o +obj-$(CONFIG_AD5446_I2C) += ad5446-i2c.o obj-$(CONFIG_AD5449) += ad5449.o obj-$(CONFIG_AD5592R_BASE) += ad5592r-base.o obj-$(CONFIG_AD5592R) += ad5592r.o diff --git a/drivers/iio/dac/ad5446-i2c.c b/drivers/iio/dac/ad5446-i2c.c new file mode 100644 index 000000000000..40fe7e17fce4 --- /dev/null +++ b/drivers/iio/dac/ad5446-i2c.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD5446 SPI I2C driver + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include + +#include + +#include "ad5446.h" + +static int ad5622_write(struct ad5446_state *st, unsigned int val) +{ + struct i2c_client *client = to_i2c_client(st->dev); + int ret; + + st->d16 = cpu_to_be16(val); + + ret = i2c_master_send_dmasafe(client, (char *)&st->d16, sizeof(st->d16)); + if (ret < 0) + return ret; + if (ret != sizeof(st->d16)) + return -EIO; + + return 0; +} + +static int ad5446_i2c_probe(struct i2c_client *i2c) +{ + const struct i2c_device_id *id = i2c_client_get_device_id(i2c); + const struct ad5446_chip_info *chip_info; + + chip_info = i2c_get_match_data(i2c); + if (!chip_info) + return -ENODEV; + + return ad5446_probe(&i2c->dev, id->name, chip_info); +} + +/* + * ad5446_supported_i2c_device_ids: + * The AD5620/40/60 parts are available in different fixed internal reference + * voltage options. The actual part numbers may look differently + * (and a bit cryptic), however this style is used to make clear which + * parts are supported here. + */ + +static const struct ad5446_chip_info ad5602_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), + .write = ad5622_write, +}; + +static const struct ad5446_chip_info ad5612_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), + .write = ad5622_write, +}; + +static const struct ad5446_chip_info ad5622_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), + .write = ad5622_write, +}; + +static const struct i2c_device_id ad5446_i2c_ids[] = { + {"ad5301", (kernel_ulong_t)&ad5602_chip_info}, + {"ad5311", (kernel_ulong_t)&ad5612_chip_info}, + {"ad5321", (kernel_ulong_t)&ad5622_chip_info}, + {"ad5602", (kernel_ulong_t)&ad5602_chip_info}, + {"ad5612", (kernel_ulong_t)&ad5612_chip_info}, + {"ad5622", (kernel_ulong_t)&ad5622_chip_info}, + { } +}; +MODULE_DEVICE_TABLE(i2c, ad5446_i2c_ids); + +static const struct of_device_id ad5446_i2c_of_ids[] = { + { .compatible = "adi,ad5301", .data = &ad5602_chip_info }, + { .compatible = "adi,ad5311", .data = &ad5612_chip_info }, + { .compatible = "adi,ad5321", .data = &ad5622_chip_info }, + { .compatible = "adi,ad5602", .data = &ad5602_chip_info }, + { .compatible = "adi,ad5612", .data = &ad5612_chip_info }, + { .compatible = "adi,ad5622", .data = &ad5622_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(OF, ad5446_i2c_of_ids); + +static struct i2c_driver ad5446_i2c_driver = { + .driver = { + .name = "ad5446", + .of_match_table = ad5446_i2c_of_ids, + }, + .probe = ad5446_i2c_probe, + .id_table = ad5446_i2c_ids, +}; +module_i2c_driver(ad5446_i2c_driver); + +MODULE_AUTHOR("Nuno Sá "); +MODULE_DESCRIPTION("Analog Devices AD5622 and similar I2C DACs"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_AD5446"); diff --git a/drivers/iio/dac/ad5446-spi.c b/drivers/iio/dac/ad5446-spi.c new file mode 100644 index 000000000000..dfba1972d1e0 --- /dev/null +++ b/drivers/iio/dac/ad5446-spi.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD5446 SPI DAC driver + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include +#include + +#include + +#include "ad5446.h" + +static int ad5446_write(struct ad5446_state *st, unsigned int val) +{ + struct spi_device *spi = to_spi_device(st->dev); + + st->d16 = cpu_to_be16(val); + + return spi_write(spi, &st->d16, sizeof(st->d16)); +} + +static int ad5660_write(struct ad5446_state *st, unsigned int val) +{ + struct spi_device *spi = to_spi_device(st->dev); + + put_unaligned_be24(val, st->d24); + + return spi_write(spi, st->d24, sizeof(st->d24)); +} + +static int ad5446_spi_probe(struct spi_device *spi) +{ + const struct spi_device_id *id = spi_get_device_id(spi); + const struct ad5446_chip_info *chip_info; + + chip_info = spi_get_device_match_data(spi); + if (!chip_info) + return -ENODEV; + + return ad5446_probe(&spi->dev, id->name, chip_info); +} + +/* + * ad5446_supported_spi_device_ids: + * The AD5620/40/60 parts are available in different fixed internal reference + * voltage options. The actual part numbers may look differently + * (and a bit cryptic), however this style is used to make clear which + * parts are supported here. + */ + +static const struct ad5446_chip_info ad5300_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5310_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5320_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5444_chip_info = { + .channel = AD5446_CHANNEL(12, 16, 2), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5446_chip_info = { + .channel = AD5446_CHANNEL(14, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5450_chip_info = { + .channel = AD5446_CHANNEL(8, 16, 6), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5451_chip_info = { + .channel = AD5446_CHANNEL(10, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5541a_chip_info = { + .channel = AD5446_CHANNEL(16, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5512a_chip_info = { + .channel = AD5446_CHANNEL(12, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5553_chip_info = { + .channel = AD5446_CHANNEL(14, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5601_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5611_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 4), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5621_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5641_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5620_2500_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), + .int_vref_mv = 2500, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5620_1250_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), + .int_vref_mv = 1250, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5640_2500_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), + .int_vref_mv = 2500, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5640_1250_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), + .int_vref_mv = 1250, + .write = ad5446_write, +}; + +static const struct ad5446_chip_info ad5660_2500_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), + .int_vref_mv = 2500, + .write = ad5660_write, +}; + +static const struct ad5446_chip_info ad5660_1250_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), + .int_vref_mv = 1250, + .write = ad5660_write, +}; + +static const struct ad5446_chip_info ad5662_chip_info = { + .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), + .write = ad5660_write, +}; + +static const struct spi_device_id ad5446_spi_ids[] = { + {"ad5300", (kernel_ulong_t)&ad5300_chip_info}, + {"ad5310", (kernel_ulong_t)&ad5310_chip_info}, + {"ad5320", (kernel_ulong_t)&ad5320_chip_info}, + {"ad5444", (kernel_ulong_t)&ad5444_chip_info}, + {"ad5446", (kernel_ulong_t)&ad5446_chip_info}, + {"ad5450", (kernel_ulong_t)&ad5450_chip_info}, + {"ad5451", (kernel_ulong_t)&ad5451_chip_info}, + {"ad5452", (kernel_ulong_t)&ad5444_chip_info}, /* ad5452 is compatible to the ad5444 */ + {"ad5453", (kernel_ulong_t)&ad5446_chip_info}, /* ad5453 is compatible to the ad5446 */ + {"ad5512a", (kernel_ulong_t)&ad5512a_chip_info}, + {"ad5541a", (kernel_ulong_t)&ad5541a_chip_info}, + {"ad5542a", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5542a are compatible */ + {"ad5543", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5543 are compatible */ + {"ad5553", (kernel_ulong_t)&ad5553_chip_info}, + {"ad5600", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5600 are compatible */ + {"ad5601", (kernel_ulong_t)&ad5601_chip_info}, + {"ad5611", (kernel_ulong_t)&ad5611_chip_info}, + {"ad5621", (kernel_ulong_t)&ad5621_chip_info}, + {"ad5641", (kernel_ulong_t)&ad5641_chip_info}, + {"ad5620-2500", (kernel_ulong_t)&ad5620_2500_chip_info}, /* AD5620/40/60: */ + /* part numbers may look differently */ + {"ad5620-1250", (kernel_ulong_t)&ad5620_1250_chip_info}, + {"ad5640-2500", (kernel_ulong_t)&ad5640_2500_chip_info}, + {"ad5640-1250", (kernel_ulong_t)&ad5640_1250_chip_info}, + {"ad5660-2500", (kernel_ulong_t)&ad5660_2500_chip_info}, + {"ad5660-1250", (kernel_ulong_t)&ad5660_1250_chip_info}, + {"ad5662", (kernel_ulong_t)&ad5662_chip_info}, + {"dac081s101", (kernel_ulong_t)&ad5300_chip_info}, /* compatible Texas Instruments chips */ + {"dac101s101", (kernel_ulong_t)&ad5310_chip_info}, + {"dac121s101", (kernel_ulong_t)&ad5320_chip_info}, + {"dac7512", (kernel_ulong_t)&ad5320_chip_info}, + { } +}; +MODULE_DEVICE_TABLE(spi, ad5446_spi_ids); + +static const struct of_device_id ad5446_of_ids[] = { + { .compatible = "adi,ad5300", .data = &ad5300_chip_info }, + { .compatible = "adi,ad5310", .data = &ad5310_chip_info }, + { .compatible = "adi,ad5320", .data = &ad5320_chip_info }, + { .compatible = "adi,ad5444", .data = &ad5444_chip_info }, + { .compatible = "adi,ad5446", .data = &ad5446_chip_info }, + { .compatible = "adi,ad5450", .data = &ad5450_chip_info }, + { .compatible = "adi,ad5451", .data = &ad5451_chip_info }, + { .compatible = "adi,ad5452", .data = &ad5444_chip_info }, + { .compatible = "adi,ad5453", .data = &ad5446_chip_info }, + { .compatible = "adi,ad5512a", .data = &ad5512a_chip_info }, + { .compatible = "adi,ad5541a", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5542a", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5543", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5553", .data = &ad5553_chip_info }, + { .compatible = "adi,ad5600", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5601", .data = &ad5601_chip_info }, + { .compatible = "adi,ad5611", .data = &ad5611_chip_info }, + { .compatible = "adi,ad5621", .data = &ad5621_chip_info }, + { .compatible = "adi,ad5641", .data = &ad5641_chip_info }, + { .compatible = "adi,ad5620-2500", .data = &ad5620_2500_chip_info }, + { .compatible = "adi,ad5620-1250", .data = &ad5620_1250_chip_info }, + { .compatible = "adi,ad5640-2500", .data = &ad5640_2500_chip_info }, + { .compatible = "adi,ad5640-1250", .data = &ad5640_1250_chip_info }, + { .compatible = "adi,ad5660-2500", .data = &ad5660_2500_chip_info }, + { .compatible = "adi,ad5660-1250", .data = &ad5660_1250_chip_info }, + { .compatible = "adi,ad5662", .data = &ad5662_chip_info }, + { .compatible = "ti,dac081s101", .data = &ad5300_chip_info }, + { .compatible = "ti,dac101s101", .data = &ad5310_chip_info }, + { .compatible = "ti,dac121s101", .data = &ad5320_chip_info }, + { .compatible = "ti,dac7512", .data = &ad5320_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad5446_of_ids); + +static struct spi_driver ad5446_spi_driver = { + .driver = { + .name = "ad5446", + .of_match_table = ad5446_of_ids, + }, + .probe = ad5446_spi_probe, + .id_table = ad5446_spi_ids, +}; +module_spi_driver(ad5446_spi_driver); + +MODULE_AUTHOR("Nuno Sá "); +MODULE_DESCRIPTION("Analog Devices AD5446 and similar SPI DACs"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_AD5446"); diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index 37e17b7eb2fa..c7876217c7ec 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -1,10 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * AD5446 SPI DAC driver + * AD5446 CORE DAC driver * * Copyright 2010 Analog Devices Inc. */ +#include #include #include #include @@ -12,62 +13,19 @@ #include #include #include -#include -#include #include #include #include -#include #include #include -#include +#include "ad5446.h" #define MODE_PWRDWN_1k 0x1 #define MODE_PWRDWN_100k 0x2 #define MODE_PWRDWN_TRISTATE 0x3 -/** - * struct ad5446_state - driver instance specific data - * @dev: this device - * @chip_info: chip model specific constants, available modes etc - * @vref_mv: actual reference voltage used - * @cached_val: store/retrieve values during power down - * @pwr_down_mode: power down mode (1k, 100k or tristate) - * @pwr_down: true if the device is in power down - * @lock: lock to protect the data buffer during write ops - * @d16: 16bit DMA safe buffer - * @d24: 24bit DMA safe buffer - */ - -struct ad5446_state { - struct device *dev; - const struct ad5446_chip_info *chip_info; - unsigned short vref_mv; - unsigned cached_val; - unsigned pwr_down_mode; - unsigned pwr_down; - struct mutex lock; - union { - __be16 d16; - u8 d24[3]; - } __aligned(IIO_DMA_MINALIGN); -}; - -/** - * struct ad5446_chip_info - chip specific information - * @channel: channel spec for the DAC - * @int_vref_mv: AD5620/40/60: the internal reference voltage - * @write: chip specific helper function to write to the register - */ - -struct ad5446_chip_info { - struct iio_chan_spec channel; - u16 int_vref_mv; - int (*write)(struct ad5446_state *st, unsigned val); -}; - static const char * const ad5446_powerdown_modes[] = { "1kohm_to_gnd", "100kohm_to_gnd", "three_state" }; @@ -138,7 +96,7 @@ static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev, return ret ? ret : len; } -static const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[] = { +const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[] = { { .name = "powerdown", .read = ad5446_read_dac_powerdown, @@ -149,28 +107,7 @@ static const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[] = { IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5446_powerdown_mode_enum), { } }; - -#define _AD5446_CHANNEL(bits, storage, _shift, ext) { \ - .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .output = 1, \ - .channel = 0, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ - .scan_type = { \ - .sign = 'u', \ - .realbits = (bits), \ - .storagebits = (storage), \ - .shift = (_shift), \ - }, \ - .ext_info = (ext), \ -} - -#define AD5446_CHANNEL(bits, storage, shift) \ - _AD5446_CHANNEL(bits, storage, shift, NULL) - -#define AD5446_CHANNEL_POWERDOWN(bits, storage, shift) \ - _AD5446_CHANNEL(bits, storage, shift, ad5446_ext_info_powerdown) +EXPORT_SYMBOL_NS_GPL(ad5446_ext_info_powerdown, "IIO_AD5446"); static int ad5446_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, @@ -225,8 +162,8 @@ static const struct iio_info ad5446_info = { .write_raw = ad5446_write_raw, }; -static int ad5446_probe(struct device *dev, const char *name, - const struct ad5446_chip_info *chip_info) +int ad5446_probe(struct device *dev, const char *name, + const struct ad5446_chip_info *chip_info) { struct ad5446_state *st; struct iio_dev *indio_dev; @@ -266,379 +203,8 @@ static int ad5446_probe(struct device *dev, const char *name, return devm_iio_device_register(dev, indio_dev); } - -#if IS_ENABLED(CONFIG_SPI_MASTER) - -static int ad5446_write(struct ad5446_state *st, unsigned val) -{ - struct spi_device *spi = to_spi_device(st->dev); - st->d16 = cpu_to_be16(val); - - return spi_write(spi, &st->d16, sizeof(st->d16)); -} - -static int ad5660_write(struct ad5446_state *st, unsigned val) -{ - struct spi_device *spi = to_spi_device(st->dev); - - put_unaligned_be24(val, st->d24); - - return spi_write(spi, st->d24, sizeof(st->d24)); -} - -/* - * ad5446_supported_spi_device_ids: - * The AD5620/40/60 parts are available in different fixed internal reference - * voltage options. The actual part numbers may look differently - * (and a bit cryptic), however this style is used to make clear which - * parts are supported here. - */ - -static const struct ad5446_chip_info ad5300_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5310_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5320_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5444_chip_info = { - .channel = AD5446_CHANNEL(12, 16, 2), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5446_chip_info = { - .channel = AD5446_CHANNEL(14, 16, 0), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5450_chip_info = { - .channel = AD5446_CHANNEL(8, 16, 6), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5451_chip_info = { - .channel = AD5446_CHANNEL(10, 16, 4), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5541a_chip_info = { - .channel = AD5446_CHANNEL(16, 16, 0), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5512a_chip_info = { - .channel = AD5446_CHANNEL(12, 16, 4), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5553_chip_info = { - .channel = AD5446_CHANNEL(14, 16, 0), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5601_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5611_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 4), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5621_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5641_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5620_2500_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), - .int_vref_mv = 2500, - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5620_1250_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2), - .int_vref_mv = 1250, - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5640_2500_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), - .int_vref_mv = 2500, - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5640_1250_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0), - .int_vref_mv = 1250, - .write = ad5446_write, -}; - -static const struct ad5446_chip_info ad5660_2500_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), - .int_vref_mv = 2500, - .write = ad5660_write, -}; - -static const struct ad5446_chip_info ad5660_1250_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), - .int_vref_mv = 1250, - .write = ad5660_write, -}; - -static const struct ad5446_chip_info ad5662_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0), - .write = ad5660_write, -}; - -static const struct spi_device_id ad5446_spi_ids[] = { - {"ad5300", (kernel_ulong_t)&ad5300_chip_info}, - {"ad5310", (kernel_ulong_t)&ad5310_chip_info}, - {"ad5320", (kernel_ulong_t)&ad5320_chip_info}, - {"ad5444", (kernel_ulong_t)&ad5444_chip_info}, - {"ad5446", (kernel_ulong_t)&ad5446_chip_info}, - {"ad5450", (kernel_ulong_t)&ad5450_chip_info}, - {"ad5451", (kernel_ulong_t)&ad5451_chip_info}, - {"ad5452", (kernel_ulong_t)&ad5444_chip_info}, /* ad5452 is compatible to the ad5444 */ - {"ad5453", (kernel_ulong_t)&ad5446_chip_info}, /* ad5453 is compatible to the ad5446 */ - {"ad5512a", (kernel_ulong_t)&ad5512a_chip_info}, - {"ad5541a", (kernel_ulong_t)&ad5541a_chip_info}, - {"ad5542a", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5542a are compatible */ - {"ad5543", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5543 are compatible */ - {"ad5553", (kernel_ulong_t)&ad5553_chip_info}, - {"ad5600", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5600 are compatible */ - {"ad5601", (kernel_ulong_t)&ad5601_chip_info}, - {"ad5611", (kernel_ulong_t)&ad5611_chip_info}, - {"ad5621", (kernel_ulong_t)&ad5621_chip_info}, - {"ad5641", (kernel_ulong_t)&ad5641_chip_info}, - {"ad5620-2500", (kernel_ulong_t)&ad5620_2500_chip_info}, /* AD5620/40/60: */ - /* part numbers may look differently */ - {"ad5620-1250", (kernel_ulong_t)&ad5620_1250_chip_info}, - {"ad5640-2500", (kernel_ulong_t)&ad5640_2500_chip_info}, - {"ad5640-1250", (kernel_ulong_t)&ad5640_1250_chip_info}, - {"ad5660-2500", (kernel_ulong_t)&ad5660_2500_chip_info}, - {"ad5660-1250", (kernel_ulong_t)&ad5660_1250_chip_info}, - {"ad5662", (kernel_ulong_t)&ad5662_chip_info}, - {"dac081s101", (kernel_ulong_t)&ad5300_chip_info}, /* compatible Texas Instruments chips */ - {"dac101s101", (kernel_ulong_t)&ad5310_chip_info}, - {"dac121s101", (kernel_ulong_t)&ad5320_chip_info}, - {"dac7512", (kernel_ulong_t)&ad5320_chip_info}, - { } -}; -MODULE_DEVICE_TABLE(spi, ad5446_spi_ids); - -static const struct of_device_id ad5446_of_ids[] = { - { .compatible = "adi,ad5300", .data = &ad5300_chip_info }, - { .compatible = "adi,ad5310", .data = &ad5310_chip_info }, - { .compatible = "adi,ad5320", .data = &ad5320_chip_info }, - { .compatible = "adi,ad5444", .data = &ad5444_chip_info }, - { .compatible = "adi,ad5446", .data = &ad5446_chip_info }, - { .compatible = "adi,ad5450", .data = &ad5450_chip_info }, - { .compatible = "adi,ad5451", .data = &ad5451_chip_info }, - { .compatible = "adi,ad5452", .data = &ad5444_chip_info }, - { .compatible = "adi,ad5453", .data = &ad5446_chip_info }, - { .compatible = "adi,ad5512a", .data = &ad5512a_chip_info }, - { .compatible = "adi,ad5541a", .data = &ad5541a_chip_info }, - { .compatible = "adi,ad5542a", .data = &ad5541a_chip_info }, - { .compatible = "adi,ad5543", .data = &ad5541a_chip_info }, - { .compatible = "adi,ad5553", .data = &ad5553_chip_info }, - { .compatible = "adi,ad5600", .data = &ad5541a_chip_info }, - { .compatible = "adi,ad5601", .data = &ad5601_chip_info }, - { .compatible = "adi,ad5611", .data = &ad5611_chip_info }, - { .compatible = "adi,ad5621", .data = &ad5621_chip_info }, - { .compatible = "adi,ad5641", .data = &ad5641_chip_info }, - { .compatible = "adi,ad5620-2500", .data = &ad5620_2500_chip_info }, - { .compatible = "adi,ad5620-1250", .data = &ad5620_1250_chip_info }, - { .compatible = "adi,ad5640-2500", .data = &ad5640_2500_chip_info }, - { .compatible = "adi,ad5640-1250", .data = &ad5640_1250_chip_info }, - { .compatible = "adi,ad5660-2500", .data = &ad5660_2500_chip_info }, - { .compatible = "adi,ad5660-1250", .data = &ad5660_1250_chip_info }, - { .compatible = "adi,ad5662", .data = &ad5662_chip_info }, - { .compatible = "ti,dac081s101", .data = &ad5300_chip_info }, - { .compatible = "ti,dac101s101", .data = &ad5310_chip_info }, - { .compatible = "ti,dac121s101", .data = &ad5320_chip_info }, - { .compatible = "ti,dac7512" }, - { } -}; -MODULE_DEVICE_TABLE(of, ad5446_of_ids); - -static int ad5446_spi_probe(struct spi_device *spi) -{ - const struct spi_device_id *id = spi_get_device_id(spi); - const struct ad5446_chip_info *chip_info; - - chip_info = spi_get_device_match_data(spi); - if (!chip_info) - return -ENODEV; - - return ad5446_probe(&spi->dev, id->name, chip_info); -} - -static struct spi_driver ad5446_spi_driver = { - .driver = { - .name = "ad5446", - .of_match_table = ad5446_of_ids, - }, - .probe = ad5446_spi_probe, - .id_table = ad5446_spi_ids, -}; - -static int __init ad5446_spi_register_driver(void) -{ - return spi_register_driver(&ad5446_spi_driver); -} - -static void ad5446_spi_unregister_driver(void) -{ - spi_unregister_driver(&ad5446_spi_driver); -} - -#else - -static inline int ad5446_spi_register_driver(void) { return 0; } -static inline void ad5446_spi_unregister_driver(void) { } - -#endif - -#if IS_ENABLED(CONFIG_I2C) - -static int ad5622_write(struct ad5446_state *st, unsigned val) -{ - struct i2c_client *client = to_i2c_client(st->dev); - st->d16 = cpu_to_be16(val); - int ret; - - ret = i2c_master_send_dmasafe(client, (char *)&st->d16, sizeof(st->d16)); - if (ret < 0) - return ret; - if (ret != sizeof(st->d16)) - return -EIO; - - return 0; -} - -/* - * ad5446_supported_i2c_device_ids: - * The AD5620/40/60 parts are available in different fixed internal reference - * voltage options. The actual part numbers may look differently - * (and a bit cryptic), however this style is used to make clear which - * parts are supported here. - */ - -static const struct ad5446_chip_info ad5602_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4), - .write = ad5622_write, -}; - -static const struct ad5446_chip_info ad5612_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2), - .write = ad5622_write, -}; - -static const struct ad5446_chip_info ad5622_chip_info = { - .channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0), - .write = ad5622_write, -}; - -static int ad5446_i2c_probe(struct i2c_client *i2c) -{ - const struct i2c_device_id *id = i2c_client_get_device_id(i2c); - const struct ad5446_chip_info *chip_info; - - chip_info = i2c_get_match_data(i2c); - if (!chip_info) - return -ENODEV; - - return ad5446_probe(&i2c->dev, id->name, chip_info); -} - -static const struct i2c_device_id ad5446_i2c_ids[] = { - {"ad5301", (kernel_ulong_t)&ad5602_chip_info}, - {"ad5311", (kernel_ulong_t)&ad5612_chip_info}, - {"ad5321", (kernel_ulong_t)&ad5622_chip_info}, - {"ad5602", (kernel_ulong_t)&ad5602_chip_info}, - {"ad5612", (kernel_ulong_t)&ad5612_chip_info}, - {"ad5622", (kernel_ulong_t)&ad5622_chip_info}, - { } -}; -MODULE_DEVICE_TABLE(i2c, ad5446_i2c_ids); - -static const struct of_device_id ad5446_i2c_of_ids[] = { - { .compatible = "adi,ad5301", .data = &ad5602_chip_info }, - { .compatible = "adi,ad5311", .data = &ad5612_chip_info }, - { .compatible = "adi,ad5321", .data = &ad5622_chip_info }, - { .compatible = "adi,ad5602", .data = &ad5602_chip_info }, - { .compatible = "adi,ad5612", .data = &ad5612_chip_info }, - { .compatible = "adi,ad5622", .data = &ad5622_chip_info }, - { } -}; -MODULE_DEVICE_TABLE(of, ad5446_i2c_of_ids); - -static struct i2c_driver ad5446_i2c_driver = { - .driver = { - .name = "ad5446", - .of_match_table = ad5446_i2c_of_ids, - }, - .probe = ad5446_i2c_probe, - .id_table = ad5446_i2c_ids, -}; - -static int __init ad5446_i2c_register_driver(void) -{ - return i2c_add_driver(&ad5446_i2c_driver); -} - -static void __exit ad5446_i2c_unregister_driver(void) -{ - i2c_del_driver(&ad5446_i2c_driver); -} - -#else - -static inline int ad5446_i2c_register_driver(void) { return 0; } -static inline void ad5446_i2c_unregister_driver(void) { } - -#endif - -static int __init ad5446_init(void) -{ - int ret; - - ret = ad5446_spi_register_driver(); - if (ret) - return ret; - - ret = ad5446_i2c_register_driver(); - if (ret) { - ad5446_spi_unregister_driver(); - return ret; - } - - return 0; -} -module_init(ad5446_init); - -static void __exit ad5446_exit(void) -{ - ad5446_i2c_unregister_driver(); - ad5446_spi_unregister_driver(); -} -module_exit(ad5446_exit); +EXPORT_SYMBOL_NS_GPL(ad5446_probe, "IIO_AD5446"); MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("Analog Devices AD5444/AD5446 DAC"); +MODULE_DESCRIPTION("Analog Devices CORE AD5446 DAC and similar devices"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/dac/ad5446.h b/drivers/iio/dac/ad5446.h new file mode 100644 index 000000000000..ee3d2c7d1764 --- /dev/null +++ b/drivers/iio/dac/ad5446.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_AD5446_H +#define _LINUX_AD5446_H + +#include +#include +#include +#include + +struct device; + +extern const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[]; + +#define _AD5446_CHANNEL(bits, storage, _shift, ext) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .output = 1, \ + .channel = 0, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = (bits), \ + .storagebits = (storage), \ + .shift = (_shift), \ + }, \ + .ext_info = (ext), \ +} + +#define AD5446_CHANNEL(bits, storage, shift) \ + _AD5446_CHANNEL(bits, storage, shift, NULL) + +#define AD5446_CHANNEL_POWERDOWN(bits, storage, shift) \ + _AD5446_CHANNEL(bits, storage, shift, ad5446_ext_info_powerdown) + +/** + * struct ad5446_state - driver instance specific data + * @dev: this device + * @chip_info: chip model specific constants, available modes etc + * @vref_mv: actual reference voltage used + * @cached_val: store/retrieve values during power down + * @pwr_down_mode: power down mode (1k, 100k or tristate) + * @pwr_down: true if the device is in power down + * @lock: lock to protect the data buffer during write ops + */ +struct ad5446_state { + struct device *dev; + const struct ad5446_chip_info *chip_info; + unsigned short vref_mv; + unsigned int cached_val; + unsigned int pwr_down_mode; + unsigned int pwr_down; + /* mutex to protect device shared data */ + struct mutex lock; + union { + __be16 d16; + u8 d24[3]; + } __aligned(IIO_DMA_MINALIGN); +}; + +/** + * struct ad5446_chip_info - chip specific information + * @channel: channel spec for the DAC + * @int_vref_mv: AD5620/40/60: the internal reference voltage + * @write: chip specific helper function to write to the register + */ +struct ad5446_chip_info { + struct iio_chan_spec channel; + u16 int_vref_mv; + int (*write)(struct ad5446_state *st, unsigned int val); +}; + +int ad5446_probe(struct device *dev, const char *name, + const struct ad5446_chip_info *chip_info); + +#endif From 6e43c10675d876a5fb71e57a9bcca9533fccccd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:13 +0000 Subject: [PATCH 204/304] iio: dac: ad5446: Make use of devm_mutex_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use devm_mutex_init() which is helpful with CONFIG_DEBUG_MUTEXES. Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index c7876217c7ec..59e1f67ef334 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -184,7 +184,9 @@ int ad5446_probe(struct device *dev, const char *name, indio_dev->channels = &st->chip_info->channel; indio_dev->num_channels = 1; - mutex_init(&st->lock); + ret = devm_mutex_init(dev, &st->lock); + if (ret) + return ret; st->pwr_down_mode = MODE_PWRDWN_1k; From 308d4474cfa298dbf4a7e4f18314a86c38a51da1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:14 +0000 Subject: [PATCH 205/304] iio: dac: ad5446: Make use of the cleanup helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the auto unlocking helpers from cleanup.h. Allows for some code simplification. While at it, don't use the ternary operator in ad5446_write_dac_powerdown() and add an helper function to write the DAC code. The reason for the function was purely to avoid having to use unreachable(). Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 45 +++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index 59e1f67ef334..1943e8014990 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -5,6 +5,7 @@ * Copyright 2010 Analog Devices Inc. */ +#include #include #include #include @@ -80,7 +81,7 @@ static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev, if (ret) return ret; - mutex_lock(&st->lock); + guard(mutex)(&st->lock); st->pwr_down = powerdown; if (st->pwr_down) { @@ -91,9 +92,10 @@ static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev, } ret = st->chip_info->write(st, val); - mutex_unlock(&st->lock); + if (ret) + return ret; - return ret ? ret : len; + return len; } const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[] = { @@ -129,32 +131,37 @@ static int ad5446_read_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int ad5446_write_dac_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int val) +{ + struct ad5446_state *st = iio_priv(indio_dev); + + if (val >= (1 << chan->scan_type.realbits) || val < 0) + return -EINVAL; + + val <<= chan->scan_type.shift; + guard(mutex)(&st->lock); + + st->cached_val = val; + if (st->pwr_down) + return 0; + + return st->chip_info->write(st, val); +} + static int ad5446_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { - struct ad5446_state *st = iio_priv(indio_dev); - int ret = 0; - switch (mask) { case IIO_CHAN_INFO_RAW: - if (val >= (1 << chan->scan_type.realbits) || val < 0) - return -EINVAL; - - val <<= chan->scan_type.shift; - mutex_lock(&st->lock); - st->cached_val = val; - if (!st->pwr_down) - ret = st->chip_info->write(st, val); - mutex_unlock(&st->lock); - break; + return ad5446_write_dac_raw(indio_dev, chan, val); default: - ret = -EINVAL; + return -EINVAL; } - - return ret; } static const struct iio_info ad5446_info = { From bb5565a98660035370d8492085ed442151014954 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:15 +0000 Subject: [PATCH 206/304] iio: dac: ad5446: Refactor header inclusion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make sure include files are given in alphabetical order and that we include the ones that were missing and remove the ones we don't really use. Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 18 +++++++----------- drivers/iio/dac/ad5446.h | 1 + 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index 1943e8014990..0556ce78c2f6 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -5,21 +5,17 @@ * Copyright 2010 Analog Devices Inc. */ +#include #include -#include -#include -#include #include -#include -#include -#include -#include -#include #include -#include - +#include #include -#include +#include +#include +#include +#include +#include #include "ad5446.h" diff --git a/drivers/iio/dac/ad5446.h b/drivers/iio/dac/ad5446.h index ee3d2c7d1764..6ba31d98f415 100644 --- a/drivers/iio/dac/ad5446.h +++ b/drivers/iio/dac/ad5446.h @@ -3,6 +3,7 @@ #define _LINUX_AD5446_H #include +#include #include #include #include From 8265cc284dc619aefb49fb07dde436bb3e8b52e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Tue, 4 Nov 2025 15:35:16 +0000 Subject: [PATCH 207/304] iio: dac: ad5446: Fix coding style issues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix style issues as reported by checkpatch. Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/iio/dac/ad5446.c b/drivers/iio/dac/ad5446.c index 0556ce78c2f6..46a2eadb1d9b 100644 --- a/drivers/iio/dac/ad5446.c +++ b/drivers/iio/dac/ad5446.c @@ -28,7 +28,8 @@ static const char * const ad5446_powerdown_modes[] = { }; static int ad5446_set_powerdown_mode(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan, unsigned int mode) + const struct iio_chan_spec *chan, + unsigned int mode) { struct ad5446_state *st = iio_priv(indio_dev); @@ -38,7 +39,7 @@ static int ad5446_set_powerdown_mode(struct iio_dev *indio_dev, } static int ad5446_get_powerdown_mode(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan) + const struct iio_chan_spec *chan) { struct ad5446_state *st = iio_priv(indio_dev); @@ -53,9 +54,9 @@ static const struct iio_enum ad5446_powerdown_mode_enum = { }; static ssize_t ad5446_read_dac_powerdown(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - char *buf) + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) { struct ad5446_state *st = iio_priv(indio_dev); @@ -63,9 +64,9 @@ static ssize_t ad5446_read_dac_powerdown(struct iio_dev *indio_dev, } static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - const char *buf, size_t len) + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) { struct ad5446_state *st = iio_priv(indio_dev); unsigned int shift; @@ -147,10 +148,8 @@ static int ad5446_write_dac_raw(struct iio_dev *indio_dev, } static int ad5446_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, - int val2, - long mask) + struct iio_chan_spec const *chan, int val, + int val2, long mask) { switch (mask) { case IIO_CHAN_INFO_RAW: From 826ccaecbe06b9626bbc1863f892485e62af5813 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 4 Nov 2025 15:35:17 +0000 Subject: [PATCH 208/304] iio: dac: ad5446: Add AD5542 to the spi id table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds support for the AD5542 single channel Current Source and Voltage Output DACs. It is similar to the AD5542A model so just use the same id. Signed-off-by: Michael Hennerich Co-developed-by: Nuno Sá Signed-off-by: Nuno Sá Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5446-spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iio/dac/ad5446-spi.c b/drivers/iio/dac/ad5446-spi.c index dfba1972d1e0..e29d77f21482 100644 --- a/drivers/iio/dac/ad5446-spi.c +++ b/drivers/iio/dac/ad5446-spi.c @@ -175,6 +175,7 @@ static const struct spi_device_id ad5446_spi_ids[] = { {"ad5453", (kernel_ulong_t)&ad5446_chip_info}, /* ad5453 is compatible to the ad5446 */ {"ad5512a", (kernel_ulong_t)&ad5512a_chip_info}, {"ad5541a", (kernel_ulong_t)&ad5541a_chip_info}, + {"ad5542", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5542 are compatible */ {"ad5542a", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5542a are compatible */ {"ad5543", (kernel_ulong_t)&ad5541a_chip_info}, /* ad5541a and ad5543 are compatible */ {"ad5553", (kernel_ulong_t)&ad5553_chip_info}, @@ -211,6 +212,7 @@ static const struct of_device_id ad5446_of_ids[] = { { .compatible = "adi,ad5453", .data = &ad5446_chip_info }, { .compatible = "adi,ad5512a", .data = &ad5512a_chip_info }, { .compatible = "adi,ad5541a", .data = &ad5541a_chip_info }, + { .compatible = "adi,ad5542", .data = &ad5541a_chip_info }, { .compatible = "adi,ad5542a", .data = &ad5541a_chip_info }, { .compatible = "adi,ad5543", .data = &ad5541a_chip_info }, { .compatible = "adi,ad5553", .data = &ad5553_chip_info }, From 9eb98a05f050be20e60852f8f0ddf34c7e49740d Mon Sep 17 00:00:00 2001 From: Marco Crivellari Date: Wed, 5 Nov 2025 11:43:30 +0100 Subject: [PATCH 209/304] iio: adc: pac1934: replace use of system_wq with system_percpu_wq Currently if a user enqueues a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistency cannot be addressed without refactoring the API. This patch continues the effort to refactor worqueue APIs, which has begun with the change introducing new workqueues and a new alloc_workqueue flag: commit 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") commit 930c2ea566af ("workqueue: Add new WQ_PERCPU flag") system_percpu_wq replaced system_wq, so change the wq in iio/adc/pac1934. The old wq (system_wq) will be kept for a few release cycles. Suggested-by: Tejun Heo Signed-off-by: Marco Crivellari Signed-off-by: Jonathan Cameron --- drivers/iio/adc/pac1934.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/pac1934.c b/drivers/iio/adc/pac1934.c index 48df16509260..ec96bb0f2ed6 100644 --- a/drivers/iio/adc/pac1934.c +++ b/drivers/iio/adc/pac1934.c @@ -768,7 +768,7 @@ static int pac1934_retrieve_data(struct pac1934_chip_info *info, * Re-schedule the work for the read registers on timeout * (to prevent chip registers saturation) */ - mod_delayed_work(system_wq, &info->work_chip_rfsh, + mod_delayed_work(system_percpu_wq, &info->work_chip_rfsh, msecs_to_jiffies(PAC1934_MAX_RFSH_LIMIT_MS)); } From d16d1c2553248f9b859b86c94344d8b81f0297cd Mon Sep 17 00:00:00 2001 From: Remi Buisson Date: Thu, 6 Nov 2025 15:31:07 +0000 Subject: [PATCH 210/304] iio: imu: inv_icm45600: Initializes inv_icm45600_buffer_postdisable() sleep The sleep variable in inv_icm45600_buffer_postdisable() could be used without being assigned in case of error. It must be initialized to 0 by default. Fixes: 06674a72cf7a ("iio: imu: inv_icm45600: add buffer support in iio devices") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/linux-iio/aPi6Xw-ZoUkW76zR@stanley.mountain/ Signed-off-by: Remi Buisson Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c index 2efcc177f9d6..2b9ea317385c 100644 --- a/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c +++ b/drivers/iio/imu/inv_icm45600/inv_icm45600_buffer.c @@ -370,6 +370,7 @@ static int inv_icm45600_buffer_postdisable(struct iio_dev *indio_dev) return -EINVAL; } + sleep = 0; scoped_guard(mutex, &st->lock) ret = _inv_icm45600_buffer_postdisable(st, sensor, watermark, &sleep); From 85faa6495f34129778db61d8cd5a80db8ab19261 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 26 Oct 2025 08:02:37 -0300 Subject: [PATCH 211/304] fpga: xilinx-spi: Add missing spi_device_id table The "xlnx,fpga-slave-serial" devicetree compatible string currently misses its SPI device ID entry. Without an spi_device_id table, the driver still works with device tree, but triggers the following runtime warning when registered via SPI core: SPI driver xlnx-slave-spi has no spi_device_id for xlnx,fpga-slave-serial Fix it by adding a corresponding spi_device_id table entry. Signed-off-by: Fabio Estevam Link: https://lore.kernel.org/r/20251026110237.986279-1-festevam@gmail.com [ Yilun: Remove extra whitespaces ] Reviewed-by: Xu Yilun Signed-off-by: Xu Yilun --- drivers/fpga/xilinx-spi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c index 8756504340de..e294e3a6cc03 100644 --- a/drivers/fpga/xilinx-spi.c +++ b/drivers/fpga/xilinx-spi.c @@ -57,6 +57,12 @@ static int xilinx_spi_probe(struct spi_device *spi) return xilinx_core_probe(core); } +static const struct spi_device_id xilinx_spi_ids[] = { + { "fpga-slave-serial" }, + { }, +}; +MODULE_DEVICE_TABLE(spi, xilinx_spi_ids); + #ifdef CONFIG_OF static const struct of_device_id xlnx_spi_of_match[] = { { @@ -73,6 +79,7 @@ static struct spi_driver xilinx_slave_spi_driver = { .of_match_table = of_match_ptr(xlnx_spi_of_match), }, .probe = xilinx_spi_probe, + .id_table = xilinx_spi_ids, }; module_spi_driver(xilinx_slave_spi_driver) From 2cf07ffeba5eb893c9f3637cbdbc5dcf95d7eaac Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 1 Nov 2025 14:08:48 -0500 Subject: [PATCH 212/304] dt-bindings: fpga: update link for Altera's and AMD partial recon The link is giving the 404 error, so use the correct link for the documents Signed-off-by: Dinh Nguyen Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251101190848.24271-1-dinguyen@kernel.org Reviewed-by: Xu Yilun Signed-off-by: Xu Yilun --- Documentation/devicetree/bindings/fpga/fpga-region.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.yaml b/Documentation/devicetree/bindings/fpga/fpga-region.yaml index 7d2d3b7aa4b7..98e7c311c0c8 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.yaml +++ b/Documentation/devicetree/bindings/fpga/fpga-region.yaml @@ -215,9 +215,9 @@ description: | FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. -- - [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [1] https://www.intel.com/programmable/technical-pdfs/683404.pdf [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf - [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + [3] https://docs.amd.com/v/u/en-US/ug702 properties: $nodename: From c9243d6df0d617535e842aa4c3d1d7dfdb91d07b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Sun, 9 Nov 2025 21:16:37 +0100 Subject: [PATCH 213/304] fpga: altera-cvp: Use pci_find_vsec_capability() when probing FPGA device Currently altera_cvp_probe() open-codes pci_find_vsec_capability(). Refactor the former to use the latter. With that done: - use the VSEC ID as per datasheet [1] - update the error message accordingly Link: https://www.intel.com/content/www/us/en/docs/programmable/683763/23-1/vendor-specific-header-register.html [1] Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20251109201729.3220460-1-andriy.shevchenko@linux.intel.com Reviewed-by: Xu Yilun Signed-off-by: Xu Yilun --- drivers/fpga/altera-cvp.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 5af0bd33890c..44badfd11e1b 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/altera-cvp.c @@ -22,9 +22,6 @@ #define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */ /* Vendor Specific Extended Capability Registers */ -#define VSE_PCIE_EXT_CAP_ID 0x0 -#define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */ - #define VSE_CVP_STATUS 0x1c /* 32bit */ #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */ #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */ @@ -577,25 +574,18 @@ static int altera_cvp_probe(struct pci_dev *pdev, { struct altera_cvp_conf *conf; struct fpga_manager *mgr; - int ret, offset; - u16 cmd, val; + u16 cmd, offset; u32 regval; - - /* Discover the Vendor Specific Offset for this device */ - offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR); - if (!offset) { - dev_err(&pdev->dev, "No Vendor Specific Offset.\n"); - return -ENODEV; - } + int ret; /* * First check if this is the expected FPGA device. PCI config * space access works without enabling the PCI device, memory * space access is enabled further down. */ - pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val); - if (val != VSE_PCIE_EXT_CAP_ID_VAL) { - dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val); + offset = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALTERA, 0x1172); + if (!offset) { + dev_err(&pdev->dev, "Wrong VSEC ID value\n"); return -ENODEV; } From 9e24bdfecdb071a3a42fb74be1ab503c958e2740 Mon Sep 17 00:00:00 2001 From: Marco Crivellari Date: Thu, 6 Nov 2025 17:24:30 +0100 Subject: [PATCH 214/304] bus: mhi: ep: add WQ_PERCPU to alloc_workqueue users MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently if a user enqueue a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistency cannot be addressed without refactoring the API. alloc_workqueue() treats all queues as per-CPU by default, while unbound workqueues must opt-in via WQ_UNBOUND. This default is suboptimal: most workloads benefit from unbound queues, allowing the scheduler to place worker threads where they’re needed and reducing noise when CPUs are isolated. This continues the effort to refactor workqueue APIs, which began with the introduction of new workqueues and a new alloc_workqueue flag in: commit 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") commit 930c2ea566af ("workqueue: Add new WQ_PERCPU flag") This change adds a new WQ_PERCPU flag to explicitly request alloc_workqueue() to be per-cpu when WQ_UNBOUND has not been specified. With the introduction of the WQ_PERCPU flag (equivalent to !WQ_UNBOUND), any alloc_workqueue() caller that doesn’t explicitly specify WQ_UNBOUND must now use WQ_PERCPU. Once migration is complete, WQ_UNBOUND can be removed and unbound will become the implicit default. Suggested-by: Tejun Heo Signed-off-by: Marco Crivellari Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251106162430.328701-1-marco.crivellari@suse.com --- drivers/bus/mhi/ep/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 86e003bc44e0..3c208b5c8446 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -1494,7 +1494,7 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl, INIT_WORK(&mhi_cntrl->cmd_ring_work, mhi_ep_cmd_ring_worker); INIT_WORK(&mhi_cntrl->ch_ring_work, mhi_ep_ch_ring_worker); - mhi_cntrl->wq = alloc_workqueue("mhi_ep_wq", 0, 0); + mhi_cntrl->wq = alloc_workqueue("mhi_ep_wq", WQ_PERCPU, 0); if (!mhi_cntrl->wq) { ret = -ENOMEM; goto err_destroy_ring_item_cache; From aaa5abcc9d44d2c8484f779ab46d242d774cabcb Mon Sep 17 00:00:00 2001 From: Carl Worth Date: Thu, 25 Sep 2025 18:42:31 +0800 Subject: [PATCH 215/304] coresight: tmc: add the handle of the event to the path The handle is essential for retrieving the AUX_EVENT of each CPU and is required in perf mode. It has been added to the coresight_path so that dependent devices can access it from the path when needed. The existing bug can be reproduced with: perf record -e cs_etm//k -C 0-9 dd if=/dev/zero of=/dev/null Showing an oops as follows: Unable to handle kernel paging request at virtual address 000f6e84934ed19e Call trace: tmc_etr_get_buffer+0x30/0x80 [coresight_tmc] (P) catu_enable_hw+0xbc/0x3d0 [coresight_catu] catu_enable+0x70/0xe0 [coresight_catu] coresight_enable_path+0xb0/0x258 [coresight] Fixes: 080ee83cc361 ("Coresight: Change functions to accept the coresight_path") Signed-off-by: Carl Worth Reviewed-by: Leo Yan Co-developed-by: Jie Gan Signed-off-by: Jie Gan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250925-fix_helper_data-v2-1-edd8a07c1646@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-etm-perf.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 3 ++- include/linux/coresight.h | 10 ++++++---- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index f677c08233ba..5c256af6e54a 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -520,6 +520,7 @@ static void etm_event_start(struct perf_event *event, int flags) goto out; path = etm_event_cpu_path(event_data, cpu); + path->handle = handle; /* We need a sink, no need to continue without one */ sink = coresight_get_sink(path); if (WARN_ON_ONCE(!sink)) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 800be06598c1..60b0e0a6da05 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1334,7 +1334,8 @@ out: struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data) { - struct perf_output_handle *handle = data; + struct coresight_path *path = data; + struct perf_output_handle *handle = path->handle; struct etr_perf_buffer *etr_perf; switch (mode) { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6de59ce8ef8c..2626105e3719 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -332,12 +332,14 @@ static struct coresight_dev_list (var) = { \ /** * struct coresight_path - data needed by enable/disable path - * @path_list: path from source to sink. - * @trace_id: trace_id of the whole path. + * @path_list: path from source to sink. + * @trace_id: trace_id of the whole path. + * @handle: handle of the aux_event. */ struct coresight_path { - struct list_head path_list; - u8 trace_id; + struct list_head path_list; + u8 trace_id; + struct perf_output_handle *handle; }; enum cs_mode { From 94baedb51dea4b0c97e3c9acd90953bec98d03e7 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 25 Sep 2025 18:42:32 +0800 Subject: [PATCH 216/304] coresight: change helper_ops to accept coresight_path Update the helper_enable and helper_disable functions to accept coresight_path instead of a generic void *data, as coresight_path encapsulates all the necessary data required by devices along the path. Tested-by: Carl Worth Reviewed-by: Carl Worth Reviewed-by: Leo Yan Signed-off-by: Jie Gan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250925-fix_helper_data-v2-2-edd8a07c1646@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-catu.c | 10 +++++----- drivers/hwtracing/coresight/coresight-core.c | 20 +++++++++++-------- .../hwtracing/coresight/coresight-ctcu-core.c | 9 +++------ .../hwtracing/coresight/coresight-cti-core.c | 5 +++-- drivers/hwtracing/coresight/coresight-cti.h | 5 +++-- .../hwtracing/coresight/coresight-tmc-etr.c | 4 ++-- drivers/hwtracing/coresight/coresight-tmc.h | 3 ++- include/linux/coresight.h | 5 +++-- 8 files changed, 33 insertions(+), 28 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index a3ccb7034ae1..69b36bae97ab 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -397,7 +397,7 @@ static int catu_wait_for_ready(struct catu_drvdata *drvdata) } static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mode, - void *data) + struct coresight_path *path) { int rc; u32 control, mode; @@ -425,7 +425,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mode, etrdev = coresight_find_input_type( csdev->pdata, CORESIGHT_DEV_TYPE_SINK, etr_subtype); if (etrdev) { - etr_buf = tmc_etr_get_buffer(etrdev, cs_mode, data); + etr_buf = tmc_etr_get_buffer(etrdev, cs_mode, path); if (IS_ERR(etr_buf)) return PTR_ERR(etr_buf); } @@ -455,7 +455,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mode, } static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { int rc = 0; struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); @@ -463,7 +463,7 @@ static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock); if (csdev->refcnt == 0) { CS_UNLOCK(catu_drvdata->base); - rc = catu_enable_hw(catu_drvdata, mode, data); + rc = catu_enable_hw(catu_drvdata, mode, path); CS_LOCK(catu_drvdata->base); } if (!rc) @@ -488,7 +488,7 @@ static int catu_disable_hw(struct catu_drvdata *drvdata) return rc; } -static int catu_disable(struct coresight_device *csdev, void *__unused) +static int catu_disable(struct coresight_device *csdev, struct coresight_path *path) { int rc = 0; struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 3267192f0c1c..f44ec9e5b692 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -355,17 +355,20 @@ static bool coresight_is_helper(struct coresight_device *csdev) } static int coresight_enable_helper(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { - return helper_ops(csdev)->enable(csdev, mode, data); + return helper_ops(csdev)->enable(csdev, mode, path); } -static void coresight_disable_helper(struct coresight_device *csdev, void *data) +static void coresight_disable_helper(struct coresight_device *csdev, + struct coresight_path *path) { - helper_ops(csdev)->disable(csdev, data); + helper_ops(csdev)->disable(csdev, path); } -static void coresight_disable_helpers(struct coresight_device *csdev, void *data) +static void coresight_disable_helpers(struct coresight_device *csdev, + struct coresight_path *path) { int i; struct coresight_device *helper; @@ -373,7 +376,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev, void *data for (i = 0; i < csdev->pdata->nr_outconns; ++i) { helper = csdev->pdata->out_conns[i]->dest_dev; if (helper && coresight_is_helper(helper)) - coresight_disable_helper(helper, data); + coresight_disable_helper(helper, path); } } @@ -479,7 +482,8 @@ void coresight_disable_path(struct coresight_path *path) EXPORT_SYMBOL_GPL(coresight_disable_path); static int coresight_enable_helpers(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { int i, ret = 0; struct coresight_device *helper; @@ -489,7 +493,7 @@ static int coresight_enable_helpers(struct coresight_device *csdev, if (!helper || !coresight_is_helper(helper)) continue; - ret = coresight_enable_helper(helper, mode, data); + ret = coresight_enable_helper(helper, mode, path); if (ret) return ret; } diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c index c586495e9a08..abed15eb72b4 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -156,17 +156,14 @@ static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable); } -static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, void *data) +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_path *path) { - struct coresight_path *path = (struct coresight_path *)data; - return ctcu_set_etr_traceid(csdev, path, true); } -static int ctcu_disable(struct coresight_device *csdev, void *data) +static int ctcu_disable(struct coresight_device *csdev, struct coresight_path *path) { - struct coresight_path *path = (struct coresight_path *)data; - return ctcu_set_etr_traceid(csdev, path, false); } diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 8fb30dd73fd2..bfbc365bb2ef 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -799,14 +799,15 @@ static void cti_pm_release(struct cti_drvdata *drvdata) } /** cti ect operations **/ -int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *data) +int cti_enable(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_path *path) { struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev); return cti_enable_hw(drvdata); } -int cti_disable(struct coresight_device *csdev, void *data) +int cti_disable(struct coresight_device *csdev, struct coresight_path *path) { struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev); diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 8362a47c939c..4f89091ee93f 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -216,8 +216,9 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata, const char *assoc_dev_name); struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, int out_sigs); -int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *data); -int cti_disable(struct coresight_device *csdev, void *data); +int cti_enable(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_path *path); +int cti_disable(struct coresight_device *csdev, struct coresight_path *path); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 60b0e0a6da05..51c6f73dd15c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1332,9 +1332,9 @@ out: } struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { - struct coresight_path *path = data; struct perf_output_handle *handle = path->handle; struct etr_perf_buffer *etr_perf; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index cbb4ba439158..95473d131032 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -442,7 +442,8 @@ struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); void tmc_etr_remove_catu_ops(void); struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, - enum cs_mode mode, void *data); + enum cs_mode mode, + struct coresight_path *path); extern const struct attribute_group coresight_etr_group; #endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 2626105e3719..2bee2e3bb1c6 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -424,8 +424,9 @@ struct coresight_ops_source { */ struct coresight_ops_helper { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, - void *data); - int (*disable)(struct coresight_device *csdev, void *data); + struct coresight_path *path); + int (*disable)(struct coresight_device *csdev, + struct coresight_path *path); }; From b139702a889692ec30702534ebb1ae2b11ed1cbf Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 25 Sep 2025 18:42:33 +0800 Subject: [PATCH 217/304] coresight: change the sink_ops to accept coresight_path Update the sink_enable functions to accept coresight_path instead of a generic void *data, as coresight_path encapsulates all the necessary data required by devices along the path. Tested-by: Carl Worth Reviewed-by: Carl Worth Reviewed-by: Leo Yan Signed-off-by: Jie Gan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250925-fix_helper_data-v2-3-edd8a07c1646@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-core.c | 10 +++++----- drivers/hwtracing/coresight/coresight-dummy.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 8 ++++---- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 +-- drivers/hwtracing/coresight/coresight-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++---- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++---- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 4 ++-- drivers/hwtracing/coresight/ultrasoc-smb.c | 9 +++++---- include/linux/coresight.h | 2 +- 12 files changed, 34 insertions(+), 30 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f44ec9e5b692..c660cf8adb1c 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -300,9 +300,10 @@ unlock: EXPORT_SYMBOL_GPL(coresight_add_helper); static int coresight_enable_sink(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { - return sink_ops(csdev)->enable(csdev, mode, data); + return sink_ops(csdev)->enable(csdev, mode, path); } static void coresight_disable_sink(struct coresight_device *csdev) @@ -501,8 +502,7 @@ static int coresight_enable_helpers(struct coresight_device *csdev, return 0; } -int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, - void *sink_data) +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode) { int ret = 0; u32 type; @@ -532,7 +532,7 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, switch (type) { case CORESIGHT_DEV_TYPE_SINK: - ret = coresight_enable_sink(csdev, mode, sink_data); + ret = coresight_enable_sink(csdev, mode, path); /* * Sink is the first component turned on. If we * failed to enable the sink, there are no components diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c index aaa92b5081e3..14322c99e29d 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -52,7 +52,7 @@ static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused } static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { dev_dbg(csdev->dev.parent, "Dummy sink enabled\n"); diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 35db1b6093d1..6657602d8f2e 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -167,13 +167,13 @@ out: return ret; } -static int etb_enable_perf(struct coresight_device *csdev, void *data) +static int etb_enable_perf(struct coresight_device *csdev, struct coresight_path *path) { int ret = 0; pid_t pid; unsigned long flags; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct perf_output_handle *handle = path->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); raw_spin_lock_irqsave(&drvdata->spinlock, flags); @@ -224,7 +224,7 @@ out: } static int etb_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { int ret; @@ -233,7 +233,7 @@ static int etb_enable(struct coresight_device *csdev, enum cs_mode mode, ret = etb_enable_sysfs(csdev); break; case CS_MODE_PERF: - ret = etb_enable_perf(csdev, data); + ret = etb_enable_perf(csdev, path); break; default: ret = -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 5c256af6e54a..17afa0f4cdee 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -527,7 +527,7 @@ static void etm_event_start(struct perf_event *event, int flags) goto fail_end_stop; /* Nothing will happen without a path */ - if (coresight_enable_path(path, CS_MODE_PERF, handle)) + if (coresight_enable_path(path, CS_MODE_PERF)) goto fail_end_stop; /* Finally enable the tracer */ diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 33e22b1ba043..fd896ac07942 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -135,8 +135,7 @@ static inline void CS_UNLOCK(void __iomem *addr) } void coresight_disable_path(struct coresight_path *path); -int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, - void *sink_data); +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode); struct coresight_device *coresight_get_sink(struct coresight_path *path); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 5e52324aa9ac..d2a6ed8bcc74 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -215,7 +215,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev) if (!IS_VALID_CS_TRACE_ID(path->trace_id)) goto err_path; - ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL); + ret = coresight_enable_path(path, CS_MODE_SYSFS); if (ret) goto err_path; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 0f45ab5e5249..8882b1c4cdc0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -246,13 +246,14 @@ out: return ret; } -static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, + struct coresight_path *path) { int ret = 0; pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct perf_output_handle *handle = path->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); raw_spin_lock_irqsave(&drvdata->spinlock, flags); @@ -304,7 +305,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) } static int tmc_enable_etf_sink(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { int ret; @@ -313,7 +315,7 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, ret = tmc_enable_etf_sink_sysfs(csdev); break; case CS_MODE_PERF: - ret = tmc_enable_etf_sink_perf(csdev, data); + ret = tmc_enable_etf_sink_perf(csdev, path); break; /* We shouldn't be here */ default: diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 51c6f73dd15c..e0d83ee01b77 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1733,13 +1733,14 @@ out: return size; } -static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, + struct coresight_path *path) { int rc = 0; pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct perf_output_handle *handle = path->handle; struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); raw_spin_lock_irqsave(&drvdata->spinlock, flags); @@ -1787,13 +1788,14 @@ unlock_out: } static int tmc_enable_etr_sink(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { switch (mode) { case CS_MODE_SYSFS: return tmc_enable_etr_sink_sysfs(csdev); case CS_MODE_PERF: - return tmc_enable_etr_sink_perf(csdev, data); + return tmc_enable_etr_sink_perf(csdev, path); default: return -EINVAL; } diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 9463afdbda8a..aaa44bc521c3 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -75,7 +75,7 @@ static void tpiu_enable_hw(struct csdev_access *csa) } static int tpiu_enable(struct coresight_device *csdev, enum cs_mode mode, - void *__unused) + struct coresight_path *path) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 43643d2c5bdd..293715b4ff0e 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1013,11 +1013,11 @@ err: } static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); - struct perf_output_handle *handle = data; + struct perf_output_handle *handle = path->handle; struct trbe_buf *buf = etm_perf_sink_config(handle); WARN_ON(cpudata->cpu != smp_processor_id()); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c index 26cfc939e5bd..8f7922a5e534 100644 --- a/drivers/hwtracing/coresight/ultrasoc-smb.c +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -213,10 +213,11 @@ static void smb_enable_sysfs(struct coresight_device *csdev) coresight_set_mode(csdev, CS_MODE_SYSFS); } -static int smb_enable_perf(struct coresight_device *csdev, void *data) +static int smb_enable_perf(struct coresight_device *csdev, + struct coresight_path *path) { struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct perf_output_handle *handle = path->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); pid_t pid; @@ -240,7 +241,7 @@ static int smb_enable_perf(struct coresight_device *csdev, void *data) } static int smb_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); int ret = 0; @@ -261,7 +262,7 @@ static int smb_enable(struct coresight_device *csdev, enum cs_mode mode, smb_enable_sysfs(csdev); break; case CS_MODE_PERF: - ret = smb_enable_perf(csdev, data); + ret = smb_enable_perf(csdev, path); break; default: ret = -EINVAL; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 2bee2e3bb1c6..56d0108658db 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -367,7 +367,7 @@ enum cs_mode { */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, - void *data); + struct coresight_path *path); int (*disable)(struct coresight_device *csdev); void *(*alloc_buffer)(struct coresight_device *csdev, struct perf_event *event, void **pages, From a5d908e0ec05bd4f5dd818160f0252861879a5a2 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 11 Nov 2025 11:43:02 +0200 Subject: [PATCH 218/304] w1: omap-hdq: Remove redundant pm_runtime_mark_last_busy() calls pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus Link: https://patch.msgid.link/20251111094302.95003-1-sakari.ailus@linux.intel.com Signed-off-by: Krzysztof Kozlowski --- drivers/w1/masters/omap_hdq.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index 69b1d145657a..d13db3396570 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c @@ -445,7 +445,6 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) out: mutex_unlock(&hdq_data->hdq_mutex); rtn: - pm_runtime_mark_last_busy(hdq_data->dev); pm_runtime_put_autosuspend(hdq_data->dev); return ret; @@ -466,7 +465,6 @@ static u8 omap_w1_reset_bus(void *_hdq) omap_hdq_break(hdq_data); - pm_runtime_mark_last_busy(hdq_data->dev); pm_runtime_put_autosuspend(hdq_data->dev); return 0; @@ -490,7 +488,6 @@ static u8 omap_w1_read_byte(void *_hdq) if (ret) val = -1; - pm_runtime_mark_last_busy(hdq_data->dev); pm_runtime_put_autosuspend(hdq_data->dev); return val; @@ -525,7 +522,6 @@ static void omap_w1_write_byte(void *_hdq, u8 byte) } out_err: - pm_runtime_mark_last_busy(hdq_data->dev); pm_runtime_put_autosuspend(hdq_data->dev); } @@ -625,7 +621,6 @@ static int omap_hdq_probe(struct platform_device *pdev) omap_hdq_break(hdq_data); - pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); omap_w1_master.data = hdq_data; From 693d1eaca940f277af24c74873ef2313816ff444 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:35 +0000 Subject: [PATCH 219/304] coresight: Change device mode to atomic type The device mode is defined as local type. This type cannot promise SMP-safe access. Change to atomic type and impose relax ordering, which ensures the SMP-safe synchronisation and the ordering between the mode setting and relevant operations. Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enable()") Reviewed-by: Mike Leach Tested-by: James Clark Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-1-f55553b6c8b3@arm.com --- include/linux/coresight.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 56d0108658db..2b48be97fcd0 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -251,15 +251,11 @@ struct coresight_trace_id_map { * by @coresight_ops. * @access: Device i/o access abstraction for this device. * @dev: The device entity associated to this component. - * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is - * actually an 'enum cs_mode', but is stored in an atomic type. - * This is always accessed through local_read() and local_set(), - * but wherever it's done from within the Coresight device's lock, - * a non-atomic read would also work. This is the main point of - * synchronisation between code happening inside the sysfs mode's - * coresight_mutex and outside when running in Perf mode. A compare - * and exchange swap is done to atomically claim one mode or the - * other. + * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually + * an 'enum cs_mode' but stored in an atomic type. Access is always + * through atomic APIs, ensuring SMP-safe synchronisation between + * racing from sysFS and Perf mode. A compare-and-exchange + * operation is done to atomically claim one mode or the other. * @refcnt: keep track of what is in use. Only access this outside of the * device's spinlock when the coresight_mutex held and mode == * CS_MODE_SYSFS. Otherwise it must be accessed from inside the @@ -288,7 +284,7 @@ struct coresight_device { const struct coresight_ops *ops; struct csdev_access access; struct device dev; - local_t mode; + atomic_t mode; int refcnt; bool orphan; /* sink specific fields */ @@ -624,13 +620,14 @@ static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) static inline bool coresight_take_mode(struct coresight_device *csdev, enum cs_mode new_mode) { - return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == - CS_MODE_DISABLED; + int curr = CS_MODE_DISABLED; + + return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode); } static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) { - return local_read(&csdev->mode); + return atomic_read_acquire(&csdev->mode); } static inline void coresight_set_mode(struct coresight_device *csdev, @@ -646,7 +643,7 @@ static inline void coresight_set_mode(struct coresight_device *csdev, WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && current_mode != new_mode, "Device already in use\n"); - local_set(&csdev->mode, new_mode); + atomic_set_release(&csdev->mode, new_mode); } struct coresight_device *coresight_register(struct coresight_desc *desc); From 28eee2158575aea8fee7807adb9248ceaf9196f1 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:36 +0000 Subject: [PATCH 220/304] coresight: etm4x: Always set tracer's device mode on target CPU When enabling a tracer via SysFS interface, the device mode may be set by any CPU - not necessarily the target CPU. This can lead to race condition in SMP, and may result in incorrect mode values being read. Consider the following example, where CPU0 attempts to enable the tracer on CPU1 (the target CPU): CPU0 CPU1 etm4_enable() ` coresight_take_mode(SYSFS) ` etm4_enable_sysfs() ` smp_call_function_single() ----> etm4_enable_hw_smp_call() / / CPU idle: / etm4_cpu_save() / ` coresight_get_mode() Failed to enable h/w / ^^^ ` coresight_set_mode(DISABLED) <-' Read the intermediate SYSFS mode In this case, CPU0 initiates the operation by taking the SYSFS mode to avoid conflicts with the Perf mode. It then sends an IPI to CPU1 to configure the tracer registers. If any error occurs during this process, CPU0 rolls back by setting the mode to DISABLED. However, if CPU1 enters an idle state during this time, it might read the intermediate SYSFS mode. As a result, the CPU PM flow could wrongly save and restore tracer context that is actually disabled. To resolve the issue, this commit moves the device mode setting logic on the target CPU. This ensures that the device mode is only modified by the target CPU, eliminating race condition between mode writes and reads across CPUs. An additional change introduces the etm4_disable_sysfs_smp_call() function for SMP calls, which disables the tracer and explicitly set the mode to DISABLED during SysFS operations. Rename etm4_disable_hw_smp_call() to etm4_disable_sysfs_smp_call() for naming consistency. The flow is updated with this change: CPU0 CPU1 etm4_enable() ` etm4_enable_sysfs() ` smp_call_function_single() ----> etm4_enable_hw_smp_call() ` coresight_take_mode(SYSFS) Failed, set back to DISABLED ` coresight_set_mode(DISABLED) CPU idle: etm4_cpu_save() ` coresight_get_mode() ^^^ Read out the DISABLED mode Fixes: c38a9ec2b2c1 ("coresight: etm4x: moving etm_drvdata::enable to atomic field") Reviewed-by: Yeoreum Yun Reviewed-by: mike Leach Tested-by: James Clark Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-2-f55553b6c8b3@arm.com --- .../coresight/coresight-etm4x-core.c | 60 ++++++++++++------- 1 file changed, 38 insertions(+), 22 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 020f070bf17d..1324b40d5421 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -589,13 +589,26 @@ done: return rc; } -static void etm4_enable_hw_smp_call(void *info) +static void etm4_enable_sysfs_smp_call(void *info) { struct etm4_enable_arg *arg = info; + struct coresight_device *csdev; if (WARN_ON(!arg)) return; + + csdev = arg->drvdata->csdev; + if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { + /* Someone is already using the tracer */ + arg->rc = -EBUSY; + return; + } + arg->rc = etm4_enable_hw(arg->drvdata); + + /* The tracer didn't start */ + if (arg->rc) + coresight_set_mode(csdev, CS_MODE_DISABLED); } /* @@ -808,13 +821,14 @@ static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event, struct coresight_path *path) { - int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; - if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { - ret = -EINVAL; - goto out; - } + if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) + return -EINVAL; + + if (!coresight_take_mode(csdev, CS_MODE_PERF)) + return -EBUSY; /* Configure the tracer based on the session's specifics */ ret = etm4_parse_event_config(csdev, event); @@ -830,6 +844,9 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_enable_hw(drvdata); out: + /* Failed to start tracer; roll back to DISABLED mode */ + if (ret) + coresight_set_mode(csdev, CS_MODE_DISABLED); return ret; } @@ -861,7 +878,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa */ arg.drvdata = drvdata; ret = smp_call_function_single(drvdata->cpu, - etm4_enable_hw_smp_call, &arg, 1); + etm4_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc; if (!ret) @@ -882,11 +899,6 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, { int ret; - if (!coresight_take_mode(csdev, mode)) { - /* Someone is already using the tracer */ - return -EBUSY; - } - switch (mode) { case CS_MODE_SYSFS: ret = etm4_enable_sysfs(csdev, path); @@ -898,10 +910,6 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, ret = -EINVAL; } - /* The tracer didn't start */ - if (ret) - coresight_set_mode(csdev, CS_MODE_DISABLED); - return ret; } @@ -953,10 +961,9 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) isb(); } -static void etm4_disable_hw(void *info) +static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control; - struct etmv4_drvdata *drvdata = info; struct etmv4_config *config = &drvdata->config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; @@ -993,6 +1000,15 @@ static void etm4_disable_hw(void *info) "cpu: %d disable smp call done\n", drvdata->cpu); } +static void etm4_disable_sysfs_smp_call(void *info) +{ + struct etmv4_drvdata *drvdata = info; + + etm4_disable_hw(drvdata); + + coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); +} + static int etm4_disable_perf(struct coresight_device *csdev, struct perf_event *event) { @@ -1022,6 +1038,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9)); + coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); + /* * perf will release trace ids when _free_aux() is * called at the end of the session. @@ -1047,7 +1065,8 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) * Executing etm4_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. */ - smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); + smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call, + drvdata, 1); raw_spin_unlock(&drvdata->spinlock); @@ -1087,9 +1106,6 @@ static void etm4_disable(struct coresight_device *csdev, etm4_disable_perf(csdev, event); break; } - - if (mode) - coresight_set_mode(csdev, CS_MODE_DISABLED); } static int etm4_resume_perf(struct coresight_device *csdev) From ab3fde32afe6a77e5cc60f868e44e6e09424752b Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:37 +0000 Subject: [PATCH 221/304] coresight: etm3x: Always set tracer's device mode on target CPU The ETMv3 driver shares the same issue as ETMv4 regarding race conditions when accessing the device mode. This commit applies the same fix: ensuring that the device mode is modified only by the target CPU to eliminate race conditions across CPUs. Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enable()") Reviewed-by: Mike Leach Tested-by: James Clark Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-3-f55553b6c8b3@arm.com --- .../coresight/coresight-etm3x-core.c | 59 +++++++++++++------ 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 45630a1cd32f..a5e809589d3e 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -439,13 +439,26 @@ struct etm_enable_arg { int rc; }; -static void etm_enable_hw_smp_call(void *info) +static void etm_enable_sysfs_smp_call(void *info) { struct etm_enable_arg *arg = info; + struct coresight_device *csdev; if (WARN_ON(!arg)) return; + + csdev = arg->drvdata->csdev; + if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { + /* Someone is already using the tracer */ + arg->rc = -EBUSY; + return; + } + arg->rc = etm_enable_hw(arg->drvdata); + + /* The tracer didn't start */ + if (arg->rc) + coresight_set_mode(csdev, CS_MODE_DISABLED); } static int etm_cpu_id(struct coresight_device *csdev) @@ -465,16 +478,26 @@ static int etm_enable_perf(struct coresight_device *csdev, struct coresight_path *path) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; + if (!coresight_take_mode(csdev, CS_MODE_PERF)) + return -EBUSY; + /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); drvdata->traceid = path->trace_id; /* And enable it */ - return etm_enable_hw(drvdata); + ret = etm_enable_hw(drvdata); + + /* Failed to start tracer; roll back to DISABLED mode */ + if (ret) + coresight_set_mode(csdev, CS_MODE_DISABLED); + + return ret; } static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) @@ -494,7 +517,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat if (cpu_online(drvdata->cpu)) { arg.drvdata = drvdata; ret = smp_call_function_single(drvdata->cpu, - etm_enable_hw_smp_call, &arg, 1); + etm_enable_sysfs_smp_call, &arg, 1); if (!ret) ret = arg.rc; if (!ret) @@ -517,12 +540,6 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, enum cs_mode mode, struct coresight_path *path) { int ret; - struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - if (!coresight_take_mode(csdev, mode)) { - /* Someone is already using the tracer */ - return -EBUSY; - } switch (mode) { case CS_MODE_SYSFS: @@ -535,17 +552,12 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, ret = -EINVAL; } - /* The tracer didn't start */ - if (ret) - coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); - return ret; } -static void etm_disable_hw(void *info) +static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; - struct etm_drvdata *drvdata = info; struct etm_config *config = &drvdata->config; struct coresight_device *csdev = drvdata->csdev; @@ -567,6 +579,15 @@ static void etm_disable_hw(void *info) "cpu: %d disable smp call done\n", drvdata->cpu); } +static void etm_disable_sysfs_smp_call(void *info) +{ + struct etm_drvdata *drvdata = info; + + etm_disable_hw(drvdata); + + coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); +} + static void etm_disable_perf(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -588,6 +609,8 @@ static void etm_disable_perf(struct coresight_device *csdev) CS_LOCK(drvdata->csa.base); + coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); + /* * perf will release trace ids when _free_aux() * is called at the end of the session @@ -612,7 +635,8 @@ static void etm_disable_sysfs(struct coresight_device *csdev) * Executing etm_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. */ - smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1); + smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call, + drvdata, 1); spin_unlock(&drvdata->spinlock); cpus_read_unlock(); @@ -652,9 +676,6 @@ static void etm_disable(struct coresight_device *csdev, WARN_ON_ONCE(mode); return; } - - if (mode) - coresight_set_mode(csdev, CS_MODE_DISABLED); } static const struct coresight_ops_source etm_source_ops = { From 4dc4e22f9536341255f5de6047977a80ff47eaef Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:38 +0000 Subject: [PATCH 222/304] coresight: etm4x: Correct polling IDLE bit Since commit 4ff6039ffb79 ("coresight-etm4x: add isb() before reading the TRCSTATR"), the code has incorrectly been polling the PMSTABLE bit instead of the IDLE bit. This commit corrects the typo. Fixes: 4ff6039ffb79 ("coresight-etm4x: add isb() before reading the TRCSTATR") Reviewed-by: Yeoreum Yun Reviewed-by: Mike Leach Tested-by: James Clark Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-4-f55553b6c8b3@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1324b40d5421..c562f8298519 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1924,7 +1924,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcpdcr = etm4x_read32(csa, TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ - if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) { + if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) { dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); etm4_os_unlock(drvdata); From 64eb04ae545294e105ad91714dc3167a0b660731 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:39 +0000 Subject: [PATCH 223/304] coresight: etm4x: Add context synchronization before enabling trace According to the software usage PKLXF in Arm ARM (ARM DDI 0487 L.a), a Context synchronization event is required before enabling the trace unit. An ISB is added to meet this requirement, particularly for guarding the operations in the flow: etm4x_allow_trace() `> kvm_tracing_set_el1_configuration() `> write_sysreg_s(trfcr_while_in_guest, SYS_TRFCR_EL12) Improved the barrier comments to provide more accurate information. Fixes: 1ab3bb9df5e3 ("coresight: etm4x: Add necessary synchronization for sysreg access") Reviewed-by: Mike Leach Reviewed-by: Yeoreun Yun Tested-by: James Clark Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-5-f55553b6c8b3@arm.com --- .../coresight/coresight-etm4x-core.c | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c562f8298519..5e707d082537 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -446,10 +446,24 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); etm4x_allow_trace(drvdata); + + /* + * According to software usage PKLXF in Arm ARM (ARM DDI 0487 L.a), + * execute a Context synchronization event to guarantee the trace unit + * will observe the new values of the System registers. + */ + if (!csa->io_mem) + isb(); + /* Enable the trace unit */ etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); - /* Synchronize the register updates for sysreg access */ + /* + * As recommended by section 4.3.7 ("Synchronization when using system + * instructions to progrom the trace unit") of ARM IHI 0064H.b, the + * self-hosted trace analyzer must perform a Context synchronization + * event between writing to the TRCPRGCTLR and reading the TRCSTATR. + */ if (!csa->io_mem) isb(); @@ -931,11 +945,16 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) */ etm4x_prohibit_trace(drvdata); /* - * Make sure everything completes before disabling, as recommended - * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, - * SSTATUS") of ARM IHI 0064D + * Prevent being speculative at the point of disabling the trace unit, + * as recommended by section 7.3.77 ("TRCVICTLR, ViewInst Main Control + * Register, SSTATUS") of ARM IHI 0064D */ dsb(sy); + /* + * According to software usage VKHHY in Arm ARM (ARM DDI 0487 L.a), + * execute a Context synchronization event to guarantee no new + * program-flow trace is generated. + */ isb(); /* Trace synchronization barrier, is a nop if not supported */ tsb_csync(); From 1fdc2cd347a7bc58acacb6144404ee892cea6c2e Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:40 +0000 Subject: [PATCH 224/304] coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF If a CPU supports FEAT_TRF, as described in the section K5.5 "Context switching", Arm ARM (ARM DDI 0487 L.a), it defines a flow to prohibit program-flow trace, execute a TSB CSYNC instruction for flushing, followed by clearing TRCPRGCTLR.EN bit. To restore the state, the reverse sequence is required. This differs from the procedure described in the section 3.4.1 "The procedure when powering down the PE" of ARM IHI0064H.b, which involves the OS Lock to prevent external debugger accesses and implicitly disables trace. To be compatible with different ETM versions, explicitly control trace unit using etm4_disable_trace_unit() and etm4_enable_trace_unit() during CPU idle to comply with FEAT_TRF. As a result, the save states for TRFCR_ELx and trcprgctlr are redundant, remove them. Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Reviewed-by: Mike Leach Tested-by: James Clark Reviewed-by: Yeoreum Yun Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-6-f55553b6c8b3@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 +++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 --- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 5e707d082537..fdda924a2c71 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1858,9 +1858,11 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) goto out; } + if (!drvdata->paused) + etm4_disable_trace_unit(drvdata); + state = drvdata->save_state; - state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR); if (drvdata->nr_pe) state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); @@ -1970,9 +1972,6 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) { int ret = 0; - /* Save the TRFCR irrespective of whether the ETM is ON */ - if (drvdata->trfcr) - drvdata->save_trfcr = read_trfcr(); /* * Save and restore the ETM Trace registers only if * the ETM is active. @@ -1994,7 +1993,6 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); - etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); if (drvdata->nr_pe) etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); @@ -2079,13 +2077,15 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); + + if (!drvdata->paused) + etm4_enable_trace_unit(drvdata); + etm4_cs_lock(drvdata, csa); } static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) { - if (drvdata->trfcr) - write_trfcr(drvdata->save_trfcr); if (drvdata->state_needs_restore) __etm4_cpu_restore(drvdata); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 13ec9ecef46f..b8796b427102 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -866,7 +866,6 @@ struct etmv4_config { * struct etm4_save_state - state to be preserved when ETM is without power */ struct etmv4_save_state { - u32 trcprgctlr; u32 trcprocselr; u32 trcconfigr; u32 trcauxctlr; @@ -980,7 +979,6 @@ struct etmv4_save_state { * at runtime, due to the additional setting of TRFCR_CX when * in EL2. Otherwise, 0. * @config: structure holding configuration parameters. - * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event. * @save_state: State to be preserved across power loss * @state_needs_restore: True when there is context to restore after PM exit * @skip_power_up: Indicates if an implementation can skip powering up @@ -1037,7 +1035,6 @@ struct etmv4_drvdata { bool lpoverride; u64 trfcr; struct etmv4_config config; - u64 save_trfcr; struct etmv4_save_state *save_state; bool state_needs_restore; bool skip_power_up; From a5e6f584dab0c450e27616433d41cc38fc062ecd Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:41 +0000 Subject: [PATCH 225/304] coresight: etm4x: Remove the redundant DSB As recommended in section 4.3.7 "Synchronization when using the memory-mapped interface" of ARM IHI0064H.b: When using the memory-mapped interface to program the trace unit, the trace analyzer must ensure that writes have completed, to ensure that the trace unit is fully programmed and either enabled or disabled. To ensure writes have completed, the trace analyzer can do ... If the memory marked is as Device-nGnRE or stronger, read back the value of any register in the trace unit. This relies on peripheral coherence order defined in the Arm architecture. Polling TRCSTATR ensures the previous write has completed. Therefore, removes the redundant DSB barrier in the enabling flow. Update the comment in the disable flow for consistency. Reviewed-by: Yeoreum Yun Signed-off-by: Leo Yan Reviewed-by: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-7-f55553b6c8b3@arm.com --- .../coresight/coresight-etm4x-core.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index fdda924a2c71..bdf5ab85b221 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -475,10 +475,16 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) } /* - * As recommended by section 4.3.7 ("Synchronization when using the - * memory-mapped interface") of ARM IHI 0064D + * As recommended in section 4.3.7 (Synchronization of register updates) + * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an + * ISB instruction after programming the trace unit registers. + * + * For the memory-mapped interface, the registers are mapped as Device + * type (Device-nGnRE). Reading back the value of any register in the + * trace unit ensures that all writes have completed. Therefore, polling + * on TRCSTATR guarantees that the writing TRCPRGCTLR is complete, and + * no explicit dsb() is required at here. */ - dsb(sy); isb(); return 0; @@ -974,8 +980,15 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) dev_err(etm_dev, "timeout while waiting for PM stable Trace Status\n"); /* - * As recommended by section 4.3.7 (Synchronization of register updates) - * of ARM IHI 0064H.b. + * As recommended in section 4.3.7 (Synchronization of register updates) + * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an + * ISB instruction after programming the trace unit registers. + * + * For the memory-mapped interface, the registers are mapped as Device + * type (Device-nGnRE). Reading back the value of any register in the + * trace unit ensures that all writes have completed. Therefore, polling + * on TRCSTATR guarantees that the writing TRCPRGCTLR is complete, and + * no explicit dsb() is required at here. */ isb(); } From 9e9182cab5ebc3ee7544e60ef08ba19fdf216920 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 11 Nov 2025 18:58:42 +0000 Subject: [PATCH 226/304] coresight: etm4x: Remove the state_needs_restore flag When the restore flow is invoked, it means no error occurred during the save phase. Otherwise, if any errors happened while saving the context, the function would return an error and abort the suspend sequence. Therefore, the state_needs_restore flag is unnecessary. The save and restore functions are changed to check two conditions: 1) The global flag pm_save_enable is SELF_HOSTED mode; 2) The device is in active mode (non DISABLED). Reviewed-by: Yeoreum Yun Reviewed-by: Mike Leach Tested-by: James Clark Signed-off-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-8-f55553b6c8b3@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 ++++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 2 -- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bdf5ab85b221..560975b70474 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1966,8 +1966,6 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) goto out; } - drvdata->state_needs_restore = true; - /* * Power can be removed from the trace unit now. We do this to * potentially save power on systems that respect the TRCPDCR_PU @@ -1985,11 +1983,14 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) { int ret = 0; + if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED) + return 0; + /* * Save and restore the ETM Trace registers only if * the ETM is active. */ - if (coresight_get_mode(drvdata->csdev) && drvdata->save_state) + if (coresight_get_mode(drvdata->csdev)) ret = __etm4_cpu_save(drvdata); return ret; } @@ -2079,8 +2080,6 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) if (!drvdata->skip_power_up) etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); - drvdata->state_needs_restore = false; - /* * As recommended by section 4.3.7 ("Synchronization when using the * memory-mapped interface") of ARM IHI 0064D @@ -2099,7 +2098,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) { - if (drvdata->state_needs_restore) + if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED) + return; + + if (coresight_get_mode(drvdata->csdev)) __etm4_cpu_restore(drvdata); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b8796b427102..012c52fd1933 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -980,7 +980,6 @@ struct etmv4_save_state { * in EL2. Otherwise, 0. * @config: structure holding configuration parameters. * @save_state: State to be preserved across power loss - * @state_needs_restore: True when there is context to restore after PM exit * @skip_power_up: Indicates if an implementation can skip powering up * the trace unit. * @paused: Indicates if the trace unit is paused. @@ -1036,7 +1035,6 @@ struct etmv4_drvdata { u64 trfcr; struct etmv4_config config; struct etmv4_save_state *save_state; - bool state_needs_restore; bool skip_power_up; bool paused; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); From 4f49088c162579a4ed049c555fe0cd188fd928c4 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Wed, 8 Oct 2025 17:09:05 +0800 Subject: [PATCH 227/304] firmware: stratix10-svc: Add definition for voltage and temperature sensor Add entry in Stratix 10 Service Layer to support temperature and voltage sensor. Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen --- drivers/firmware/stratix10-svc.c | 21 ++++++++++-- include/linux/firmware/intel/stratix10-smc.h | 34 +++++++++++++++++++ .../firmware/intel/stratix10-svc-client.h | 8 ++++- 3 files changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index e3f990d888d7..5a32c1054bee 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -34,7 +34,7 @@ * timeout is set to 30 seconds (30 * 1000) at Intel Stratix10 SoC. */ #define SVC_NUM_DATA_IN_FIFO 32 -#define SVC_NUM_CHANNEL 3 +#define SVC_NUM_CHANNEL 4 #define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS 200 #define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30 #define BYTE_TO_WORD_SIZE 4 @@ -341,6 +341,8 @@ static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data, case COMMAND_RSU_MAX_RETRY: case COMMAND_RSU_DCMF_STATUS: case COMMAND_FIRMWARE_VERSION: + case COMMAND_HWMON_READTEMP: + case COMMAND_HWMON_READVOLT: cb_data->status = BIT(SVC_STATUS_OK); cb_data->kaddr1 = &res.a1; break; @@ -525,7 +527,17 @@ static int svc_normal_to_secure_thread(void *data) a1 = (unsigned long)pdata->paddr; a2 = 0; break; - + /* for HWMON */ + case COMMAND_HWMON_READTEMP: + a0 = INTEL_SIP_SMC_HWMON_READTEMP; + a1 = pdata->arg[0]; + a2 = 0; + break; + case COMMAND_HWMON_READVOLT: + a0 = INTEL_SIP_SMC_HWMON_READVOLT; + a1 = pdata->arg[0]; + a2 = 0; + break; /* for polling */ case COMMAND_POLL_SERVICE_STATUS: a0 = INTEL_SIP_SMC_SERVICE_COMPLETED; @@ -1197,6 +1209,11 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) chans[2].name = SVC_CLIENT_FCS; spin_lock_init(&chans[2].lock); + chans[3].scl = NULL; + chans[3].ctrl = controller; + chans[3].name = SVC_CLIENT_HWMON; + spin_lock_init(&chans[3].lock); + list_add_tail(&controller->node, &svc_ctrl); platform_set_drvdata(pdev, controller); diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h index ee80ca4bb0d0..7306dd243b2a 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -620,4 +620,38 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FCS_GET_PROVISION_DATA) +/** + * Request INTEL_SIP_SMC_HWMON_READTEMP + * Sync call to request temperature + * + * Call register usage: + * a0 Temperature Channel + * a1-a7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 Temperature Value + * a2-a3 not used + */ +#define INTEL_SIP_SMC_FUNCID_HWMON_READTEMP 32 +#define INTEL_SIP_SMC_HWMON_READTEMP \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HWMON_READTEMP) + +/** + * Request INTEL_SIP_SMC_HWMON_READVOLT + * Sync call to request voltage + * + * Call register usage: + * a0 Voltage Channel + * a1-a7 not used + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1 Voltage Value + * a2-a3 not used + */ +#define INTEL_SIP_SMC_FUNCID_HWMON_READVOLT 33 +#define INTEL_SIP_SMC_HWMON_READVOLT \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HWMON_READVOLT) + #endif diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 60ed82112680..520004a5f15d 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -11,12 +11,14 @@ * * fpga: for FPGA configuration * rsu: for remote status update + * hwmon: for hardware monitoring (voltage and temperature) */ #define SVC_CLIENT_FPGA "fpga" #define SVC_CLIENT_RSU "rsu" #define SVC_CLIENT_FCS "fcs" +#define SVC_CLIENT_HWMON "hwmon" -/* +/** * Status of the sent command, in bit number * * SVC_STATUS_OK: @@ -70,6 +72,7 @@ #define SVC_RSU_REQUEST_TIMEOUT_MS 300 #define SVC_FCS_REQUEST_TIMEOUT_MS 2000 #define SVC_COMPLETED_TIMEOUT_MS 30000 +#define SVC_HWMON_REQUEST_TIMEOUT_MS 300 struct stratix10_svc_chan; @@ -171,6 +174,9 @@ enum stratix10_svc_command_code { COMMAND_MBOX_SEND_CMD = 100, /* Non-mailbox SMC Call */ COMMAND_SMC_SVC_VERSION = 200, + /* for HWMON */ + COMMAND_HWMON_READTEMP, + COMMAND_HWMON_READVOLT }; /** From 85f96cbbbc67b59652b2c1ec394b8ddc0ddf1b0b Mon Sep 17 00:00:00 2001 From: Mahesh Rao Date: Mon, 27 Oct 2025 22:54:40 +0800 Subject: [PATCH 228/304] firmware: stratix10-svc: Add mutex in stratix10 memory management Add mutex lock to stratix10_svc_allocate_memory and stratix10_svc_free_memory for thread safety. This prevents race conditions and ensures proper synchronization during memory operations. This is required for parallel communication with the Stratix10 service channel. Fixes: 7ca5ce896524f ("firmware: add Intel Stratix10 service layer driver") Cc: stable@vger.kernel.org Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- drivers/firmware/stratix10-svc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 5a32c1054bee..9372a17d89b7 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025, Altera Corporation */ #include @@ -172,6 +173,12 @@ struct stratix10_svc_chan { static LIST_HEAD(svc_ctrl); static LIST_HEAD(svc_data_mem); +/** + * svc_mem_lock protects access to the svc_data_mem list for + * concurrent multi-client operations + */ +static DEFINE_MUTEX(svc_mem_lock); + /** * svc_pa_to_va() - translate physical address to virtual address * @addr: to be translated physical address @@ -184,6 +191,7 @@ static void *svc_pa_to_va(unsigned long addr) struct stratix10_svc_data_mem *pmem; pr_debug("claim back P-addr=0x%016x\n", (unsigned int)addr); + guard(mutex)(&svc_mem_lock); list_for_each_entry(pmem, &svc_data_mem, node) if (pmem->paddr == addr) return pmem->vaddr; @@ -1002,6 +1010,7 @@ int stratix10_svc_send(struct stratix10_svc_chan *chan, void *msg) p_data->flag = ct->flags; } } else { + guard(mutex)(&svc_mem_lock); list_for_each_entry(p_mem, &svc_data_mem, node) if (p_mem->vaddr == p_msg->payload) { p_data->paddr = p_mem->paddr; @@ -1084,6 +1093,7 @@ void *stratix10_svc_allocate_memory(struct stratix10_svc_chan *chan, if (!pmem) return ERR_PTR(-ENOMEM); + guard(mutex)(&svc_mem_lock); va = gen_pool_alloc(genpool, s); if (!va) return ERR_PTR(-ENOMEM); @@ -1112,6 +1122,7 @@ EXPORT_SYMBOL_GPL(stratix10_svc_allocate_memory); void stratix10_svc_free_memory(struct stratix10_svc_chan *chan, void *kaddr) { struct stratix10_svc_data_mem *pmem; + guard(mutex)(&svc_mem_lock); list_for_each_entry(pmem, &svc_data_mem, node) if (pmem->vaddr == kaddr) { From bcb9f4f0706147afc62c48533276a18fe7b8f354 Mon Sep 17 00:00:00 2001 From: Mahesh Rao Date: Mon, 27 Oct 2025 22:54:41 +0800 Subject: [PATCH 229/304] firmware: stratix10-svc: Add support for async communication Introduce support for asynchronous communication with the Stratix10 service channel. Define new structures to enable asynchronous messaging with the Secure Device Manager (SDM). Add and remove asynchronous support for existing channels. Implement initialization and cleanup routines for the asynchronous framework. Enable sending and polling of messages to the SDM asynchronously. The new public functions added are: - stratix10_svc_add_async_client: Adds a client to the service channel. - stratix10_svc_remove_async_client: Removes an asynchronous client from the service channel. - stratix10_svc_async_send: Sends an asynchronous message to the SDM mailbox in EL3 secure firmware. - stratix10_svc_async_poll: Polls the status of an asynchronous service request in EL3 secure firmware. - stratix10_svc_async_done: Marks an asynchronous transaction as complete and frees up the resources. These changes enhance the functionality of the Stratix10 service channel by allowing for more efficient and flexible communication with the firmware. Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- drivers/firmware/stratix10-svc.c | 656 +++++++++++++++++- include/linux/firmware/intel/stratix10-smc.h | 25 + .../firmware/intel/stratix10-svc-client.h | 88 +++ 3 files changed, 765 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 9372a17d89b7..14bfa36a58ed 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -4,9 +4,12 @@ * Copyright (C) 2025, Altera Corporation */ +#include #include #include #include +#include +#include #include #include #include @@ -44,6 +47,49 @@ #define STRATIX10_RSU "stratix10-rsu" #define INTEL_FCS "intel-fcs" +/* Maximum number of SDM client IDs. */ +#define MAX_SDM_CLIENT_IDS 16 +/* Client ID for SIP Service Version 1. */ +#define SIP_SVC_V1_CLIENT_ID 0x1 +/* Maximum number of SDM job IDs. */ +#define MAX_SDM_JOB_IDS 16 +/* Number of bits used for asynchronous transaction hashing. */ +#define ASYNC_TRX_HASH_BITS 3 +/** + * Total number of transaction IDs, which is a combination of + * client ID and job ID. + */ +#define TOTAL_TRANSACTION_IDS \ + (MAX_SDM_CLIENT_IDS * MAX_SDM_JOB_IDS) + +/* Minimum major version of the ATF for Asynchronous transactions. */ +#define ASYNC_ATF_MINIMUM_MAJOR_VERSION 0x3 +/* Minimum minor version of the ATF for Asynchronous transactions.*/ +#define ASYNC_ATF_MINIMUM_MINOR_VERSION 0x0 + +/* Job ID field in the transaction ID */ +#define STRATIX10_JOB_FIELD GENMASK(3, 0) +/* Client ID field in the transaction ID */ +#define STRATIX10_CLIENT_FIELD GENMASK(7, 4) +/* Transaction ID mask for Stratix10 service layer */ +#define STRATIX10_TRANS_ID_FIELD GENMASK(7, 0) + +/* Macro to extract the job ID from a transaction ID. */ +#define STRATIX10_GET_JOBID(transaction_id) \ + (FIELD_GET(STRATIX10_JOB_FIELD, transaction_id)) +/* Macro to set the job ID in a transaction ID. */ +#define STRATIX10_SET_JOBID(jobid) \ + (FIELD_PREP(STRATIX10_JOB_FIELD, jobid)) +/* Macro to set the client ID in a transaction ID. */ +#define STRATIX10_SET_CLIENTID(clientid) \ + (FIELD_PREP(STRATIX10_CLIENT_FIELD, clientid)) +/* Macro to set a transaction ID using a client ID and a job ID. */ +#define STRATIX10_SET_TRANSACTIONID(clientid, jobid) \ + (STRATIX10_SET_CLIENTID(clientid) | STRATIX10_SET_JOBID(jobid)) +/* Macro to set a transaction ID for SIP SMC Async transactions */ +#define STRATIX10_SIP_SMC_SET_TRANSACTIONID_X1(transaction_id) \ + (FIELD_PREP(STRATIX10_TRANS_ID_FIELD, transaction_id)) + typedef void (svc_invoke_fn)(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, @@ -64,7 +110,7 @@ struct stratix10_svc { * @sync_complete: state for a completion * @addr: physical address of shared memory block * @size: size of shared memory block - * @invoke_fn: function to issue secure monitor or hypervisor call + * @invoke_fn: service clients to handle secure monitor or hypervisor calls * * This struct is used to save physical address and size of shared memory * block. The shared memory blocked is allocated by secure monitor software @@ -122,6 +168,74 @@ struct stratix10_svc_data { u64 arg[3]; }; +/** + * struct stratix10_svc_async_handler - Asynchronous handler for Stratix10 + * service layer + * @transaction_id: Unique identifier for the transaction + * @achan: Pointer to the asynchronous channel structure + * @cb_arg: Argument to be passed to the callback function + * @cb: Callback function to be called upon completion + * @msg: Pointer to the client message structure + * @next: Node in the hash list + * @res: Response structure to store result from the secure firmware + * + * This structure is used to handle asynchronous transactions in the + * Stratix10 service layer. It maintains the necessary information + * for processing and completing asynchronous requests. + */ + +struct stratix10_svc_async_handler { + u8 transaction_id; + struct stratix10_async_chan *achan; + void *cb_arg; + async_callback_t cb; + struct stratix10_svc_client_msg *msg; + struct hlist_node next; + struct arm_smccc_1_2_regs res; +}; + +/** + * struct stratix10_async_chan - Structure representing an asynchronous channel + * @async_client_id: Unique client identifier for the asynchronous operation + * @job_id_pool: Pointer to the job ID pool associated with this channel + */ + +struct stratix10_async_chan { + unsigned long async_client_id; + struct ida job_id_pool; +}; + +/** + * struct stratix10_async_ctrl - Control structure for Stratix10 + * asynchronous operations + * @initialized: Flag indicating whether the control structure has + * been initialized + * @invoke_fn: Function pointer for invoking Stratix10 service calls + * to EL3 secure firmware + * @async_id_pool: Pointer to the ID pool used for asynchronous + * operations + * @common_achan_refcount: Atomic reference count for the common + * asynchronous channel usage + * @common_async_chan: Pointer to the common asynchronous channel + * structure + * @trx_list_lock: Spinlock for protecting the transaction list + * operations + * @trx_list: Hash table for managing asynchronous transactions + */ + +struct stratix10_async_ctrl { + bool initialized; + void (*invoke_fn)(struct stratix10_async_ctrl *actrl, + const struct arm_smccc_1_2_regs *args, + struct arm_smccc_1_2_regs *res); + struct ida async_id_pool; + atomic_t common_achan_refcount; + struct stratix10_async_chan *common_async_chan; + /* spinlock to protect trx_list hash table */ + spinlock_t trx_list_lock; + DECLARE_HASHTABLE(trx_list, ASYNC_TRX_HASH_BITS); +}; + /** * struct stratix10_svc_controller - service controller * @dev: device @@ -135,6 +249,7 @@ struct stratix10_svc_data { * @complete_status: state for completion * @svc_fifo_lock: protect access to service message data queue * @invoke_fn: function to issue secure monitor call or hypervisor call + * @actrl: async control structure * * This struct is used to create communication channels for service clients, to * handle secure monitor or hypervisor call. @@ -151,6 +266,7 @@ struct stratix10_svc_controller { struct completion complete_status; spinlock_t svc_fifo_lock; svc_invoke_fn *invoke_fn; + struct stratix10_async_ctrl actrl; }; /** @@ -159,15 +275,17 @@ struct stratix10_svc_controller { * @scl: pointer to service client which owns the channel * @name: service client name associated with the channel * @lock: protect access to the channel + * @async_chan: reference to asynchronous channel object for this channel * - * This struct is used by service client to communicate with service layer, each - * service client has its own channel created by service controller. + * This struct is used by service client to communicate with service layer. + * Each service client has its own channel created by service controller. */ struct stratix10_svc_chan { struct stratix10_svc_controller *ctrl; struct stratix10_svc_client *scl; char *name; spinlock_t lock; + struct stratix10_async_chan *async_chan; }; static LIST_HEAD(svc_ctrl); @@ -942,6 +1060,525 @@ struct stratix10_svc_chan *stratix10_svc_request_channel_byname( } EXPORT_SYMBOL_GPL(stratix10_svc_request_channel_byname); +/** + * stratix10_svc_add_async_client - Add an asynchronous client to the + * Stratix10 service channel. + * @chan: Pointer to the Stratix10 service channel structure. + * @use_unique_clientid: Boolean flag indicating whether to use a + * unique client ID. + * + * This function adds an asynchronous client to the specified + * Stratix10 service channel. If the `use_unique_clientid` flag is + * set to true, a unique client ID is allocated for the asynchronous + * channel. Otherwise, a common asynchronous channel is used. + * + * Return: 0 on success, or a negative error code on failure: + * -EINVAL if the channel is NULL or the async controller is + * not initialized. + * -EALREADY if the async channel is already allocated. + * -ENOMEM if memory allocation fails. + * Other negative values if ID allocation fails. + */ +int stratix10_svc_add_async_client(struct stratix10_svc_chan *chan, + bool use_unique_clientid) +{ + struct stratix10_svc_controller *ctrl; + struct stratix10_async_ctrl *actrl; + struct stratix10_async_chan *achan; + int ret = 0; + + if (!chan) + return -EINVAL; + + ctrl = chan->ctrl; + actrl = &ctrl->actrl; + + if (!actrl->initialized) { + dev_err(ctrl->dev, "Async controller not initialized\n"); + return -EINVAL; + } + + if (chan->async_chan) { + dev_err(ctrl->dev, "async channel already allocated\n"); + return -EALREADY; + } + + if (use_unique_clientid && + atomic_read(&actrl->common_achan_refcount) > 0) { + chan->async_chan = actrl->common_async_chan; + atomic_inc(&actrl->common_achan_refcount); + return 0; + } + + achan = kzalloc(sizeof(*achan), GFP_KERNEL); + if (!achan) + return -ENOMEM; + + ida_init(&achan->job_id_pool); + + ret = ida_alloc_max(&actrl->async_id_pool, MAX_SDM_CLIENT_IDS, + GFP_KERNEL); + if (ret < 0) { + dev_err(ctrl->dev, + "Failed to allocate async client id\n"); + ida_destroy(&achan->job_id_pool); + kfree(achan); + return ret; + } + + achan->async_client_id = ret; + chan->async_chan = achan; + + if (use_unique_clientid && + atomic_read(&actrl->common_achan_refcount) == 0) { + actrl->common_async_chan = achan; + atomic_inc(&actrl->common_achan_refcount); + } + + return 0; +} +EXPORT_SYMBOL_GPL(stratix10_svc_add_async_client); + +/** + * stratix10_svc_remove_async_client - Remove an asynchronous client + * from the Stratix10 service + * channel. + * @chan: Pointer to the Stratix10 service channel structure. + * + * This function removes an asynchronous client associated with the + * given service channel. It checks if the channel and the + * asynchronous channel are valid, and then proceeds to decrement + * the reference count for the common asynchronous channel if + * applicable. If the reference count reaches zero, it destroys the + * job ID pool and deallocates the asynchronous client ID. For + * non-common asynchronous channels, it directly destroys the job ID + * pool, deallocates the asynchronous client ID, and frees the + * memory allocated for the asynchronous channel. + * + * Return: 0 on success, -EINVAL if the channel or asynchronous + * channel is invalid. + */ +int stratix10_svc_remove_async_client(struct stratix10_svc_chan *chan) +{ + struct stratix10_svc_controller *ctrl; + struct stratix10_async_ctrl *actrl; + struct stratix10_async_chan *achan; + + if (!chan) + return -EINVAL; + + ctrl = chan->ctrl; + actrl = &ctrl->actrl; + achan = chan->async_chan; + + if (!achan) { + dev_err(ctrl->dev, "async channel not allocated\n"); + return -EINVAL; + } + + if (achan == actrl->common_async_chan) { + atomic_dec(&actrl->common_achan_refcount); + if (atomic_read(&actrl->common_achan_refcount) == 0) { + ida_destroy(&achan->job_id_pool); + ida_free(&actrl->async_id_pool, + achan->async_client_id); + kfree(achan); + actrl->common_async_chan = NULL; + } + } else { + ida_destroy(&achan->job_id_pool); + ida_free(&actrl->async_id_pool, achan->async_client_id); + kfree(achan); + } + chan->async_chan = NULL; + + return 0; +} +EXPORT_SYMBOL_GPL(stratix10_svc_remove_async_client); + +/** + * stratix10_svc_async_send - Send an asynchronous message to the + * Stratix10 service + * @chan: Pointer to the service channel structure + * @msg: Pointer to the message to be sent + * @handler: Pointer to the handler for the asynchronous message + * used by caller for later reference. + * @cb: Callback function to be called upon completion + * @cb_arg: Argument to be passed to the callback function + * + * This function sends an asynchronous message to the SDM mailbox in + * EL3 secure firmware. It performs various checks and setups, + * including allocating a job ID, setting up the transaction ID and + * packaging it to El3 firmware. The function handles different + * commands by setting up the appropriate arguments for the SMC call. + * If the SMC call is successful, the handler is set up and the + * function returns 0. If the SMC call fails, appropriate error + * handling is performed along with cleanup of resources. + * + * Return: 0 on success, -EINVAL for invalid argument, -ENOMEM if + * memory is not available, -EAGAIN if EL3 firmware is busy, -EBADF + * if the message is rejected by EL3 firmware and -EIO on other + * errors from EL3 firmware. + */ +int stratix10_svc_async_send(struct stratix10_svc_chan *chan, void *msg, + void **handler, async_callback_t cb, void *cb_arg) +{ + struct arm_smccc_1_2_regs args = { 0 }, res = { 0 }; + struct stratix10_svc_async_handler *handle = NULL; + struct stratix10_svc_client_msg *p_msg = + (struct stratix10_svc_client_msg *)msg; + struct stratix10_svc_controller *ctrl; + struct stratix10_async_ctrl *actrl; + struct stratix10_async_chan *achan; + int ret = 0; + + if (!chan || !msg || !handler) + return -EINVAL; + + achan = chan->async_chan; + ctrl = chan->ctrl; + actrl = &ctrl->actrl; + + if (!actrl->initialized) { + dev_err(ctrl->dev, "Async controller not initialized\n"); + return -EINVAL; + } + + if (!achan) { + dev_err(ctrl->dev, "Async channel not allocated\n"); + return -EINVAL; + } + + handle = kzalloc(sizeof(*handle), GFP_KERNEL); + if (!handle) + return -ENOMEM; + + ret = ida_alloc_max(&achan->job_id_pool, MAX_SDM_JOB_IDS, + GFP_KERNEL); + if (ret < 0) { + dev_err(ctrl->dev, "Failed to allocate job id\n"); + kfree(handle); + return -ENOMEM; + } + + handle->transaction_id = + STRATIX10_SET_TRANSACTIONID(achan->async_client_id, ret); + handle->cb = cb; + handle->msg = p_msg; + handle->cb_arg = cb_arg; + handle->achan = achan; + + /*set the transaction jobid in args.a1*/ + args.a1 = + STRATIX10_SIP_SMC_SET_TRANSACTIONID_X1(handle->transaction_id); + + switch (p_msg->command) { + default: + dev_err(ctrl->dev, "Invalid command ,%d\n", p_msg->command); + ret = -EINVAL; + goto deallocate_id; + } + + /** + * There is a chance that during the execution of async_send() + * in one core, an interrupt might be received in another core; + * to mitigate this we are adding the handle to the DB and then + * send the smc call. If the smc call is rejected or busy then + * we will deallocate the handle for the client to retry again. + */ + scoped_guard(spinlock_bh, &actrl->trx_list_lock) { + hash_add(actrl->trx_list, &handle->next, + handle->transaction_id); + } + + actrl->invoke_fn(actrl, &args, &res); + + switch (res.a0) { + case INTEL_SIP_SMC_STATUS_OK: + dev_dbg(ctrl->dev, + "Async message sent with transaction_id 0x%02x\n", + handle->transaction_id); + *handler = handle; + return 0; + case INTEL_SIP_SMC_STATUS_BUSY: + dev_warn(ctrl->dev, "Mailbox is busy, try after some time\n"); + ret = -EAGAIN; + break; + case INTEL_SIP_SMC_STATUS_REJECTED: + dev_err(ctrl->dev, "Async message rejected\n"); + ret = -EBADF; + break; + default: + dev_err(ctrl->dev, + "Failed to send async message ,got status as %ld\n", + res.a0); + ret = -EIO; + } + + scoped_guard(spinlock_bh, &actrl->trx_list_lock) { + hash_del(&handle->next); + } + +deallocate_id: + ida_free(&achan->job_id_pool, + STRATIX10_GET_JOBID(handle->transaction_id)); + kfree(handle); + return ret; +} +EXPORT_SYMBOL_GPL(stratix10_svc_async_send); +/** + * stratix10_svc_async_poll - Polls the status of an asynchronous + * transaction. + * @chan: Pointer to the service channel structure. + * @tx_handle: Handle to the transaction being polled. + * @data: Pointer to the callback data structure. + * + * This function polls the status of an asynchronous transaction + * identified by the given transaction handle. It ensures that the + * necessary structures are initialized and valid before proceeding + * with the poll operation. The function sets up the necessary + * arguments for the SMC call, invokes the call, and prepares the + * response data if the call is successful. If the call fails, the + * function returns the error mapped to the SVC status error. + * + * Return: 0 on success, -EINVAL if any input parameter is invalid, + * -EAGAIN if the transaction is still in progress, + * -EPERM if the command is invalid, or other negative + * error codes on failure. + */ +int stratix10_svc_async_poll(struct stratix10_svc_chan *chan, + void *tx_handle, + struct stratix10_svc_cb_data *data) +{ + struct stratix10_svc_async_handler *handle; + struct arm_smccc_1_2_regs args = { 0 }; + struct stratix10_svc_controller *ctrl; + struct stratix10_async_ctrl *actrl; + struct stratix10_async_chan *achan; + + if (!chan || !tx_handle || !data) + return -EINVAL; + + ctrl = chan->ctrl; + actrl = &ctrl->actrl; + achan = chan->async_chan; + + if (!achan) { + dev_err(ctrl->dev, "Async channel not allocated\n"); + return -EINVAL; + } + + handle = (struct stratix10_svc_async_handler *)tx_handle; + scoped_guard(spinlock_bh, &actrl->trx_list_lock) { + if (!hash_hashed(&handle->next)) { + dev_err(ctrl->dev, "Invalid transaction handler"); + return -EINVAL; + } + } + + args.a0 = INTEL_SIP_SMC_ASYNC_POLL; + args.a1 = + STRATIX10_SIP_SMC_SET_TRANSACTIONID_X1(handle->transaction_id); + + actrl->invoke_fn(actrl, &args, &handle->res); + + /*clear data for response*/ + memset(data, 0, sizeof(*data)); + + if (handle->res.a0 == INTEL_SIP_SMC_STATUS_OK) { + return 0; + } else if (handle->res.a0 == INTEL_SIP_SMC_STATUS_BUSY) { + dev_dbg(ctrl->dev, "async message is still in progress\n"); + return -EAGAIN; + } + + dev_err(ctrl->dev, + "Failed to poll async message ,got status as %ld\n", + handle->res.a0); + return -EINVAL; +} +EXPORT_SYMBOL_GPL(stratix10_svc_async_poll); + +/** + * stratix10_svc_async_done - Completes an asynchronous transaction. + * @chan: Pointer to the service channel structure. + * @tx_handle: Handle to the transaction being completed. + * + * This function completes an asynchronous transaction identified by + * the given transaction handle. It ensures that the necessary + * structures are initialized and valid before proceeding with the + * completion operation. The function deallocates the transaction ID, + * frees the memory allocated for the handler, and removes the handler + * from the transaction list. + * + * Return: 0 on success, -EINVAL if any input parameter is invalid, + * or other negative error codes on failure. + */ +int stratix10_svc_async_done(struct stratix10_svc_chan *chan, void *tx_handle) +{ + struct stratix10_svc_async_handler *handle; + struct stratix10_svc_controller *ctrl; + struct stratix10_async_chan *achan; + struct stratix10_async_ctrl *actrl; + + if (!chan || !tx_handle) + return -EINVAL; + + ctrl = chan->ctrl; + achan = chan->async_chan; + actrl = &ctrl->actrl; + + if (!achan) { + dev_err(ctrl->dev, "async channel not allocated\n"); + return -EINVAL; + } + + handle = (struct stratix10_svc_async_handler *)tx_handle; + scoped_guard(spinlock_bh, &actrl->trx_list_lock) { + if (!hash_hashed(&handle->next)) { + dev_err(ctrl->dev, "Invalid transaction handle"); + return -EINVAL; + } + hash_del(&handle->next); + } + ida_free(&achan->job_id_pool, + STRATIX10_GET_JOBID(handle->transaction_id)); + kfree(handle); + return 0; +} +EXPORT_SYMBOL_GPL(stratix10_svc_async_done); + +static inline void stratix10_smc_1_2(struct stratix10_async_ctrl *actrl, + const struct arm_smccc_1_2_regs *args, + struct arm_smccc_1_2_regs *res) +{ + arm_smccc_1_2_smc(args, res); +} + +/** + * stratix10_svc_async_init - Initialize the Stratix10 service + * controller for asynchronous operations. + * @controller: Pointer to the Stratix10 service controller structure. + * + * This function initializes the asynchronous service controller by + * setting up the necessary data structures and initializing the + * transaction list. + * + * Return: 0 on success, -EINVAL if the controller is NULL or already + * initialized, -ENOMEM if memory allocation fails, + * -EADDRINUSE if the client ID is already reserved, or other + * negative error codes on failure. + */ +static int stratix10_svc_async_init(struct stratix10_svc_controller *controller) +{ + struct stratix10_async_ctrl *actrl; + struct arm_smccc_res res; + struct device *dev; + int ret; + + if (!controller) + return -EINVAL; + + actrl = &controller->actrl; + + if (actrl->initialized) + return -EINVAL; + + dev = controller->dev; + + controller->invoke_fn(INTEL_SIP_SMC_SVC_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != INTEL_SIP_SMC_STATUS_OK || + !(res.a1 > ASYNC_ATF_MINIMUM_MAJOR_VERSION || + (res.a1 == ASYNC_ATF_MINIMUM_MAJOR_VERSION && + res.a2 >= ASYNC_ATF_MINIMUM_MINOR_VERSION))) { + dev_err(dev, + "Intel Service Layer Driver: ATF version is not compatible for async operation\n"); + return -EINVAL; + } + + actrl->invoke_fn = stratix10_smc_1_2; + + ida_init(&actrl->async_id_pool); + + /** + * SIP_SVC_V1_CLIENT_ID is used by V1/stratix10_svc_send() clients + * for communicating with SDM synchronously. We need to restrict + * this in V3/stratix10_svc_async_send() usage to distinguish + * between V1 and V3 messages in El3 firmware. + */ + ret = ida_alloc_range(&actrl->async_id_pool, SIP_SVC_V1_CLIENT_ID, + SIP_SVC_V1_CLIENT_ID, GFP_KERNEL); + if (ret < 0) { + dev_err(dev, + "Intel Service Layer Driver: Error on reserving SIP_SVC_V1_CLIENT_ID\n"); + ida_destroy(&actrl->async_id_pool); + actrl->invoke_fn = NULL; + return -EADDRINUSE; + } + + spin_lock_init(&actrl->trx_list_lock); + hash_init(actrl->trx_list); + atomic_set(&actrl->common_achan_refcount, 0); + + actrl->initialized = true; + return 0; +} + +/** + * stratix10_svc_async_exit - Clean up and exit the asynchronous + * service controller + * @ctrl: Pointer to the stratix10_svc_controller structure + * + * This function performs the necessary cleanup for the asynchronous + * service controller. It checks if the controller is valid and if it + * has been initialized. It then locks the transaction list and safely + * removes and deallocates each handler in the list. The function also + * removes any asynchronous clients associated with the controller's + * channels and destroys the asynchronous ID pool. Finally, it resets + * the asynchronous ID pool and invoke function pointers to NULL. + * + * Return: 0 on success, -EINVAL if the controller is invalid or not + * initialized. + */ +static int stratix10_svc_async_exit(struct stratix10_svc_controller *ctrl) +{ + struct stratix10_svc_async_handler *handler; + struct stratix10_async_ctrl *actrl; + struct hlist_node *tmp; + int i; + + if (!ctrl) + return -EINVAL; + + actrl = &ctrl->actrl; + + if (!actrl->initialized) + return -EINVAL; + + actrl->initialized = false; + + scoped_guard(spinlock_bh, &actrl->trx_list_lock) { + hash_for_each_safe(actrl->trx_list, i, tmp, handler, next) { + ida_free(&handler->achan->job_id_pool, + STRATIX10_GET_JOBID(handler->transaction_id)); + hash_del(&handler->next); + kfree(handler); + } + } + + for (i = 0; i < SVC_NUM_CHANNEL; i++) { + if (ctrl->chans[i].async_chan) { + stratix10_svc_remove_async_client(&ctrl->chans[i]); + ctrl->chans[i].async_chan = NULL; + } + } + + ida_destroy(&actrl->async_id_pool); + actrl->invoke_fn = NULL; + + return 0; +} + /** * stratix10_svc_free_channel() - free service channel * @chan: service channel to be freed @@ -1197,11 +1834,18 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) controller->invoke_fn = invoke_fn; init_completion(&controller->complete_status); + ret = stratix10_svc_async_init(controller); + if (ret) { + dev_dbg(dev, "Intel Service Layer Driver: Error on stratix10_svc_async_init %d\n", + ret); + goto err_destroy_pool; + } + fifo_size = sizeof(struct stratix10_svc_data) * SVC_NUM_DATA_IN_FIFO; ret = kfifo_alloc(&controller->svc_fifo, fifo_size, GFP_KERNEL); if (ret) { dev_err(dev, "failed to allocate FIFO\n"); - goto err_destroy_pool; + goto err_async_exit; } spin_lock_init(&controller->svc_fifo_lock); @@ -1277,6 +1921,8 @@ err_unregister_rsu_dev: platform_device_unregister(svc->stratix10_svc_rsu); err_free_kfifo: kfifo_free(&controller->svc_fifo); +err_async_exit: + stratix10_svc_async_exit(controller); err_destroy_pool: gen_pool_destroy(genpool); return ret; @@ -1287,6 +1933,8 @@ static void stratix10_svc_drv_remove(struct platform_device *pdev) struct stratix10_svc *svc = dev_get_drvdata(&pdev->dev); struct stratix10_svc_controller *ctrl = platform_get_drvdata(pdev); + stratix10_svc_async_exit(ctrl); + of_platform_depopulate(ctrl->dev); platform_device_unregister(svc->intel_svc_fcs); diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h index 7306dd243b2a..3995d5d70cce 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025, Altera Corporation */ #ifndef __STRATIX10_SMC_H @@ -47,6 +48,10 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ ARM_SMCCC_OWNER_SIP, (func_num)) +#define INTEL_SIP_SMC_ASYNC_VAL(func_name) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_name)) + /** * Return values in INTEL_SIP_SMC_* call * @@ -654,4 +659,24 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_HWMON_READVOLT \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HWMON_READVOLT) +/** + * Request INTEL_SIP_SMC_ASYNC_POLL + * Async call used by service driver at EL1 to query mailbox response from SDM. + * + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_POLL + * a1 transaction job id + * a2-17 will be used to return the response data + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1-17 will contain the response values from mailbox for the previous send + * transaction + * Or + * a0 INTEL_SIP_SMC_STATUS_NO_RESPONSE + * a1-17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL (0xC8) +#define INTEL_SIP_SMC_ASYNC_POLL \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL) #endif diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 520004a5f15d..532dd4bd76dd 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025, Altera Corporation */ #ifndef __STRATIX10_SVC_CLIENT_H @@ -290,5 +291,92 @@ int stratix10_svc_send(struct stratix10_svc_chan *chan, void *msg); * request process. */ void stratix10_svc_done(struct stratix10_svc_chan *chan); + +/** + * typedef async_callback_t - A type definition for an asynchronous callback function. + * + * This type defines a function pointer for an asynchronous callback. + * The callback function takes a single argument, which is a pointer to + * user-defined data. + * + * @param cb_arg A pointer to user-defined data passed to the callback function. + */ +typedef void (*async_callback_t)(void *cb_arg); + +/** + * stratix10_svc_add_async_client - Add an asynchronous client to a Stratix 10 + * service channel. + * @chan: Pointer to the Stratix 10 service channel structure. + * @use_unique_clientid: Boolean flag indicating whether to use a unique client ID. + * + * This function registers an asynchronous client with the specified Stratix 10 + * service channel. If the use_unique_clientid flag is set to true, a unique client + * ID will be assigned to the client. + * + * Return: 0 on success, or a negative error code on failure: + * -EINVAL if the channel is NULL or the async controller is not initialized. + * -EALREADY if the async channel is already allocated. + * -ENOMEM if memory allocation fails. + * Other negative values if ID allocation fails + */ +int stratix10_svc_add_async_client(struct stratix10_svc_chan *chan, bool use_unique_clientid); + +/** + * stratix10_svc_remove_async_client - Remove an asynchronous client from the Stratix 10 + * service channel. + * @chan: Pointer to the Stratix 10 service channel structure. + * + * This function removes an asynchronous client from the specified Stratix 10 service channel. + * It is typically used to clean up and release resources associated with the client. + * + * Return: 0 on success, -EINVAL if the channel or asynchronous channel is invalid. + */ +int stratix10_svc_remove_async_client(struct stratix10_svc_chan *chan); + +/** + * stratix10_svc_async_send - Send an asynchronous message to the SDM mailbox + * in EL3 secure firmware. + * @chan: Pointer to the service channel structure. + * @msg: Pointer to the message to be sent. + * @handler: Pointer to the handler object used by caller to track the transaction. + * @cb: Callback function to be called upon completion. + * @cb_arg: Argument to be passed to the callback function. + * + * This function sends a message asynchronously to the SDM mailbox in EL3 secure firmware. + * and registers a callback function to be invoked when the operation completes. + * + * Return: 0 on success,and negative error codes on failure. + */ +int stratix10_svc_async_send(struct stratix10_svc_chan *chan, void *msg, void **handler, + async_callback_t cb, void *cb_arg); + +/** + * stratix10_svc_async_poll - Polls the status of an asynchronous service request. + * @chan: Pointer to the service channel structure. + * @tx_handle: Handle to the transaction being polled. + * @data: Pointer to the callback data structure to be filled with the result. + * + * This function checks the status of an asynchronous service request + * and fills the provided callback data structure with the result. + * + * Return: 0 on success, -EINVAL if any input parameter is invalid or if the + * async controller is not initialized, -EAGAIN if the transaction is + * still in progress, or other negative error codes on failure. + */ +int stratix10_svc_async_poll(struct stratix10_svc_chan *chan, void *tx_handle, + struct stratix10_svc_cb_data *data); + +/** + * stratix10_svc_async_done - Complete an asynchronous transaction + * @chan: Pointer to the service channel structure + * @tx_handle: Pointer to the transaction handle + * + * This function completes an asynchronous transaction by removing the + * transaction from the hash table and deallocating the associated resources. + * + * Return: 0 on success, -EINVAL on invalid input or errors. + */ +int stratix10_svc_async_done(struct stratix10_svc_chan *chan, void *tx_handle); + #endif From ec52379341a1209826c3e0ae53674393724d2071 Mon Sep 17 00:00:00 2001 From: Mahesh Rao Date: Mon, 27 Oct 2025 22:54:42 +0800 Subject: [PATCH 230/304] firmware: stratix10-svc: Add support for RSU commands in asynchronous framework Integrate Remote System Update(RSU) service commands into the asynchronous framework for communicating with SDM. This allows the RSU commands to be processed asynchronously, improving the responsiveness of the Stratix10 service channel. The asynchronous framework now supports the following RSU commands: * COMMAND_RSU_GET_SPT_TABLE * COMMAND_RSU_STATUS * COMMAND_RSU_NOTIFY Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- drivers/firmware/stratix10-svc.c | 72 +++++++++++++++++++ include/linux/firmware/intel/stratix10-smc.h | 52 ++++++++++++++ .../firmware/intel/stratix10-svc-client.h | 4 ++ 3 files changed, 128 insertions(+) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 14bfa36a58ed..3acfa067c5dd 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -90,6 +90,12 @@ #define STRATIX10_SIP_SMC_SET_TRANSACTIONID_X1(transaction_id) \ (FIELD_PREP(STRATIX10_TRANS_ID_FIELD, transaction_id)) +/* 10-bit mask for extracting the SDM status code */ +#define STRATIX10_SDM_STATUS_MASK GENMASK(9, 0) +/* Macro to get the SDM mailbox error status */ +#define STRATIX10_GET_SDM_STATUS_CODE(status) \ + (FIELD_GET(STRATIX10_SDM_STATUS_MASK, status)) + typedef void (svc_invoke_fn)(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, @@ -1273,6 +1279,16 @@ int stratix10_svc_async_send(struct stratix10_svc_chan *chan, void *msg, STRATIX10_SIP_SMC_SET_TRANSACTIONID_X1(handle->transaction_id); switch (p_msg->command) { + case COMMAND_RSU_GET_SPT_TABLE: + args.a0 = INTEL_SIP_SMC_ASYNC_RSU_GET_SPT; + break; + case COMMAND_RSU_STATUS: + args.a0 = INTEL_SIP_SMC_ASYNC_RSU_GET_ERROR_STATUS; + break; + case COMMAND_RSU_NOTIFY: + args.a0 = INTEL_SIP_SMC_ASYNC_RSU_NOTIFY; + args.a2 = p_msg->arg[0]; + break; default: dev_err(ctrl->dev, "Invalid command ,%d\n", p_msg->command); ret = -EINVAL; @@ -1326,6 +1342,56 @@ deallocate_id: return ret; } EXPORT_SYMBOL_GPL(stratix10_svc_async_send); + +/** + * stratix10_svc_async_prepare_response - Prepare the response data for + * an asynchronous transaction. + * @chan: Pointer to the service channel structure. + * @handle: Pointer to the asynchronous handler structure. + * @data: Pointer to the callback data structure. + * + * This function prepares the response data for an asynchronous transaction. It + * extracts the response data from the SMC response structure and stores it in + * the callback data structure. The function also logs the completion of the + * asynchronous transaction. + * + * Return: 0 on success, -ENOENT if the command is invalid + */ +static int stratix10_svc_async_prepare_response(struct stratix10_svc_chan *chan, + struct stratix10_svc_async_handler *handle, + struct stratix10_svc_cb_data *data) +{ + struct stratix10_svc_client_msg *p_msg = + (struct stratix10_svc_client_msg *)handle->msg; + struct stratix10_svc_controller *ctrl = chan->ctrl; + + data->status = STRATIX10_GET_SDM_STATUS_CODE(handle->res.a1); + + switch (p_msg->command) { + case COMMAND_RSU_NOTIFY: + break; + case COMMAND_RSU_GET_SPT_TABLE: + data->kaddr1 = (void *)&handle->res.a2; + data->kaddr2 = (void *)&handle->res.a3; + break; + case COMMAND_RSU_STATUS: + /* COMMAND_RSU_STATUS has more elements than the cb_data + * can acomodate, so passing the response structure to the + * response function to be handled before done command is + * executed by the client. + */ + data->kaddr1 = (void *)&handle->res; + break; + + default: + dev_alert(ctrl->dev, "Invalid command\n ,%d", p_msg->command); + return -ENOENT; + } + dev_dbg(ctrl->dev, "Async message completed transaction_id 0x%02x\n", + handle->transaction_id); + return 0; +} + /** * stratix10_svc_async_poll - Polls the status of an asynchronous * transaction. @@ -1355,6 +1421,7 @@ int stratix10_svc_async_poll(struct stratix10_svc_chan *chan, struct stratix10_svc_controller *ctrl; struct stratix10_async_ctrl *actrl; struct stratix10_async_chan *achan; + int ret; if (!chan || !tx_handle || !data) return -EINVAL; @@ -1386,6 +1453,11 @@ int stratix10_svc_async_poll(struct stratix10_svc_chan *chan, memset(data, 0, sizeof(*data)); if (handle->res.a0 == INTEL_SIP_SMC_STATUS_OK) { + ret = stratix10_svc_async_prepare_response(chan, handle, data); + if (ret) { + dev_err(ctrl->dev, "Error in preparation of response,%d\n", ret); + WARN_ON_ONCE(1); + } return 0; } else if (handle->res.a0 == INTEL_SIP_SMC_STATUS_BUSY) { dev_dbg(ctrl->dev, "async message is still in progress\n"); diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h index 3995d5d70cce..935dba3633b5 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -679,4 +679,56 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL (0xC8) #define INTEL_SIP_SMC_ASYNC_POLL \ INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL) + +/** + * Request INTEL_SIP_SMC_ASYNC_RSU_GET_SPT + * Async call to get RSU SPT from SDM. + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_RSU_GET_SPT + * a1 transaction job id + * a2-a17 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK ,INTEL_SIP_SMC_STATUS_REJECTED + * or INTEL_SIP_SMC_STATUS_BUSY + * a1-a17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_GET_SPT (0xEA) +#define INTEL_SIP_SMC_ASYNC_RSU_GET_SPT \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_GET_SPT) + +/** + * Request INTEL_SIP_SMC_ASYNC_RSU_GET_ERROR_STATUS + * Async call to get RSU error status from SDM. + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_RSU_GET_ERROR_STATUS + * a1 transaction job id + * a2-a17 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK ,INTEL_SIP_SMC_STATUS_REJECTED + * or INTEL_SIP_SMC_STATUS_BUSY + * a1-a17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_GET_ERROR_STATUS (0xEB) +#define INTEL_SIP_SMC_ASYNC_RSU_GET_ERROR_STATUS \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_GET_ERROR_STATUS) + +/** + * Request INTEL_SIP_SMC_ASYNC_RSU_NOTIFY + * Async call to send NOTIFY value to SDM. + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_RSU_NOTIFY + * a1 transaction job id + * a2 notify value + * a3-a17 not used + * + * Return status: + * a0 INTEL_SIP_SMC_STATUS_OK ,INTEL_SIP_SMC_STATUS_REJECTED + * or INTEL_SIP_SMC_STATUS_BUSY + * a1-a17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_NOTIFY (0xEC) +#define INTEL_SIP_SMC_ASYNC_RSU_NOTIFY \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_RSU_NOTIFY) #endif diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 532dd4bd76dd..1bcc56d14080 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -128,6 +128,9 @@ struct stratix10_svc_chan; * @COMMAND_RSU_DCMF_STATUS: query firmware for the DCMF status * return status is SVC_STATUS_OK or SVC_STATUS_ERROR * + * @COMMAND_RSU_GET_SPT_TABLE: query firmware for SPT table + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR + * * @COMMAND_FCS_REQUEST_SERVICE: request validation of image from firmware, * return status is SVC_STATUS_OK, SVC_STATUS_INVALID_PARAM * @@ -162,6 +165,7 @@ enum stratix10_svc_command_code { COMMAND_RSU_DCMF_VERSION, COMMAND_RSU_DCMF_STATUS, COMMAND_FIRMWARE_VERSION, + COMMAND_RSU_GET_SPT_TABLE, /* for FCS */ COMMAND_FCS_REQUEST_SERVICE = 20, COMMAND_FCS_SEND_CERTIFICATE, From 15847537b623f844d9a08da99ff4568315e1d4f8 Mon Sep 17 00:00:00 2001 From: Mahesh Rao Date: Mon, 27 Oct 2025 22:54:43 +0800 Subject: [PATCH 231/304] firmware: stratix10-rsu: Migrate RSU driver to use stratix10 asynchronous framework. * Add support for asynchronous communication to the RSU client channel. * Migrate functions that communicate with the SDM to use the asynchronous framework. Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- drivers/firmware/stratix10-rsu.c | 270 ++++++++++++++++--------------- 1 file changed, 141 insertions(+), 129 deletions(-) diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c index 1ea39a0a76c7..53b67b242cf0 100644 --- a/drivers/firmware/stratix10-rsu.c +++ b/drivers/firmware/stratix10-rsu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018-2019, Intel Corporation + * Copyright (C) 2025, Altera Corporation */ #include @@ -14,11 +15,9 @@ #include #include #include +#include -#define RSU_STATE_MASK GENMASK_ULL(31, 0) -#define RSU_VERSION_MASK GENMASK_ULL(63, 32) -#define RSU_ERROR_LOCATION_MASK GENMASK_ULL(31, 0) -#define RSU_ERROR_DETAIL_MASK GENMASK_ULL(63, 32) +#define RSU_ERASE_SIZE_MASK GENMASK_ULL(63, 32) #define RSU_DCMF0_MASK GENMASK_ULL(31, 0) #define RSU_DCMF1_MASK GENMASK_ULL(63, 32) #define RSU_DCMF2_MASK GENMASK_ULL(31, 0) @@ -35,7 +34,8 @@ #define INVALID_DCMF_STATUS 0xFFFFFFFF #define INVALID_SPT_ADDRESS 0x0 -#define RSU_GET_SPT_CMD 0x5A +#define RSU_RETRY_SLEEP_MS (1U) +#define RSU_ASYNC_MSG_RETRY (3U) #define RSU_GET_SPT_RESP_LEN (4 * sizeof(unsigned int)) typedef void (*rsu_callback)(struct stratix10_svc_client *client, @@ -64,7 +64,6 @@ typedef void (*rsu_callback)(struct stratix10_svc_client *client, * @max_retry: the preset max retry value * @spt0_address: address of spt0 * @spt1_address: address of spt1 - * @get_spt_response_buf: response from sdm for get_spt command */ struct stratix10_rsu_priv { struct stratix10_svc_chan *chan; @@ -99,47 +98,32 @@ struct stratix10_rsu_priv { unsigned long spt0_address; unsigned long spt1_address; - - unsigned int *get_spt_response_buf; }; +typedef void (*rsu_async_callback)(struct device *dev, + struct stratix10_rsu_priv *priv, struct stratix10_svc_cb_data *data); + /** - * rsu_status_callback() - Status callback from Intel Service Layer - * @client: pointer to service client + * rsu_async_status_callback() - Status callback from rsu_async_send() + * @dev: pointer to device object + * @priv: pointer to priv object * @data: pointer to callback data structure * - * Callback from Intel service layer for RSU status request. Status is - * only updated after a system reboot, so a get updated status call is - * made during driver probe. + * Callback from rsu_async_send() to get the system rsu error status. */ -static void rsu_status_callback(struct stratix10_svc_client *client, - struct stratix10_svc_cb_data *data) +static void rsu_async_status_callback(struct device *dev, + struct stratix10_rsu_priv *priv, + struct stratix10_svc_cb_data *data) { - struct stratix10_rsu_priv *priv = client->priv; - struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1; + struct arm_smccc_1_2_regs *res = (struct arm_smccc_1_2_regs *)data->kaddr1; - if (data->status == BIT(SVC_STATUS_OK)) { - priv->status.version = FIELD_GET(RSU_VERSION_MASK, - res->a2); - priv->status.state = FIELD_GET(RSU_STATE_MASK, res->a2); - priv->status.fail_image = res->a1; - priv->status.current_image = res->a0; - priv->status.error_location = - FIELD_GET(RSU_ERROR_LOCATION_MASK, res->a3); - priv->status.error_details = - FIELD_GET(RSU_ERROR_DETAIL_MASK, res->a3); - } else { - dev_err(client->dev, "COMMAND_RSU_STATUS returned 0x%lX\n", - res->a0); - priv->status.version = 0; - priv->status.state = 0; - priv->status.fail_image = 0; - priv->status.current_image = 0; - priv->status.error_location = 0; - priv->status.error_details = 0; - } - - complete(&priv->completion); + priv->status.current_image = res->a2; + priv->status.fail_image = res->a3; + priv->status.state = res->a4; + priv->status.version = res->a5; + priv->status.error_location = res->a7; + priv->status.error_details = res->a8; + priv->retry_counter = res->a9; } /** @@ -163,32 +147,6 @@ static void rsu_command_callback(struct stratix10_svc_client *client, complete(&priv->completion); } -/** - * rsu_retry_callback() - Callback from Intel service layer for getting - * the current image's retry counter from the firmware - * @client: pointer to client - * @data: pointer to callback data structure - * - * Callback from Intel service layer for retry counter, which is used by - * user to know how many times the images is still allowed to reload - * itself before giving up and starting RSU fail-over flow. - */ -static void rsu_retry_callback(struct stratix10_svc_client *client, - struct stratix10_svc_cb_data *data) -{ - struct stratix10_rsu_priv *priv = client->priv; - unsigned int *counter = (unsigned int *)data->kaddr1; - - if (data->status == BIT(SVC_STATUS_OK)) - priv->retry_counter = *counter; - else if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) - dev_warn(client->dev, "Secure FW doesn't support retry\n"); - else - dev_err(client->dev, "Failed to get retry counter %lu\n", - BIT(data->status)); - - complete(&priv->completion); -} /** * rsu_max_retry_callback() - Callback from Intel service layer for getting @@ -270,34 +228,19 @@ static void rsu_dcmf_status_callback(struct stratix10_svc_client *client, complete(&priv->completion); } -static void rsu_get_spt_callback(struct stratix10_svc_client *client, - struct stratix10_svc_cb_data *data) +/** + * rsu_async_get_spt_table_callback() - Callback to be used by the rsu_async_send() + * to retrieve the SPT table information. + * @dev: pointer to device object + * @priv: pointer to priv object + * @data: pointer to callback data structure + */ +static void rsu_async_get_spt_table_callback(struct device *dev, + struct stratix10_rsu_priv *priv, + struct stratix10_svc_cb_data *data) { - struct stratix10_rsu_priv *priv = client->priv; - unsigned long *mbox_err = (unsigned long *)data->kaddr1; - unsigned long *resp_len = (unsigned long *)data->kaddr2; - - if (data->status != BIT(SVC_STATUS_OK) || (*mbox_err) || - (*resp_len != RSU_GET_SPT_RESP_LEN)) - goto error; - - priv->spt0_address = priv->get_spt_response_buf[0]; - priv->spt0_address <<= 32; - priv->spt0_address |= priv->get_spt_response_buf[1]; - - priv->spt1_address = priv->get_spt_response_buf[2]; - priv->spt1_address <<= 32; - priv->spt1_address |= priv->get_spt_response_buf[3]; - - goto complete; - -error: - dev_err(client->dev, "failed to get SPTs\n"); - -complete: - stratix10_svc_free_memory(priv->chan, priv->get_spt_response_buf); - priv->get_spt_response_buf = NULL; - complete(&priv->completion); + priv->spt0_address = *((unsigned long *)data->kaddr1); + priv->spt1_address = *((unsigned long *)data->kaddr2); } /** @@ -329,14 +272,6 @@ static int rsu_send_msg(struct stratix10_rsu_priv *priv, if (arg) msg.arg[0] = arg; - if (command == COMMAND_MBOX_SEND_CMD) { - msg.arg[1] = 0; - msg.payload = NULL; - msg.payload_length = 0; - msg.payload_output = priv->get_spt_response_buf; - msg.payload_length_output = RSU_GET_SPT_RESP_LEN; - } - ret = stratix10_svc_send(priv->chan, &msg); if (ret < 0) goto status_done; @@ -362,6 +297,95 @@ status_done: return ret; } +/** + * soc64_async_callback() - Callback from Intel service layer for async requests + * @ptr: pointer to the completion object + */ +static void soc64_async_callback(void *ptr) +{ + if (ptr) + complete(ptr); +} + +/** + * rsu_send_async_msg() - send an async message to Intel service layer + * @dev: pointer to device object + * @priv: pointer to rsu private data + * @command: RSU status or update command + * @arg: the request argument, notify status + * @callback: function pointer for the callback (status or update) + */ +static int rsu_send_async_msg(struct device *dev, struct stratix10_rsu_priv *priv, + enum stratix10_svc_command_code command, + unsigned long arg, + rsu_async_callback callback) +{ + struct stratix10_svc_client_msg msg = {0}; + struct stratix10_svc_cb_data data = {0}; + struct completion completion; + int status, index, ret; + void *handle = NULL; + + msg.command = command; + msg.arg[0] = arg; + + init_completion(&completion); + + for (index = 0; index < RSU_ASYNC_MSG_RETRY; index++) { + status = stratix10_svc_async_send(priv->chan, &msg, + &handle, soc64_async_callback, + &completion); + if (status == 0) + break; + dev_warn(dev, "Failed to send async message\n"); + msleep(RSU_RETRY_SLEEP_MS); + } + + if (status && !handle) { + dev_err(dev, "Failed to send async message\n"); + return -ETIMEDOUT; + } + + ret = wait_for_completion_io_timeout(&completion, RSU_TIMEOUT); + if (ret > 0) + dev_dbg(dev, "Received async interrupt\n"); + else if (ret == 0) + dev_dbg(dev, "Timeout occurred. Trying to poll the response\n"); + + for (index = 0; index < RSU_ASYNC_MSG_RETRY; index++) { + status = stratix10_svc_async_poll(priv->chan, handle, &data); + if (status == -EAGAIN) { + dev_dbg(dev, "Async message is still in progress\n"); + } else if (status < 0) { + dev_alert(dev, "Failed to poll async message\n"); + ret = -ETIMEDOUT; + } else if (status == 0) { + ret = 0; + break; + } + msleep(RSU_RETRY_SLEEP_MS); + } + + if (ret) { + dev_err(dev, "Failed to get async response\n"); + goto status_done; + } + + if (data.status == 0) { + ret = 0; + if (callback) + callback(dev, priv, &data); + } else { + dev_err(dev, "%s returned 0x%x from SDM\n", __func__, + data.status); + ret = -EFAULT; + } + +status_done: + stratix10_svc_async_done(priv->chan, handle); + return ret; +} + /* * This driver exposes some optional features of the Intel Stratix 10 SoC FPGA. * The sysfs interfaces exposed here are FPGA Remote System Update (RSU) @@ -597,27 +621,20 @@ static ssize_t notify_store(struct device *dev, if (ret) return ret; - ret = rsu_send_msg(priv, COMMAND_RSU_NOTIFY, - status, rsu_command_callback); + ret = rsu_send_async_msg(dev, priv, COMMAND_RSU_NOTIFY, status, NULL); if (ret) { dev_err(dev, "Error, RSU notify returned %i\n", ret); return ret; } /* to get the updated state */ - ret = rsu_send_msg(priv, COMMAND_RSU_STATUS, - 0, rsu_status_callback); + ret = rsu_send_async_msg(dev, priv, COMMAND_RSU_STATUS, 0, + rsu_async_status_callback); if (ret) { dev_err(dev, "Error, getting RSU status %i\n", ret); return ret; } - ret = rsu_send_msg(priv, COMMAND_RSU_RETRY, 0, rsu_retry_callback); - if (ret) { - dev_err(dev, "Error, getting RSU retry %i\n", ret); - return ret; - } - return count; } @@ -737,12 +754,19 @@ static int stratix10_rsu_probe(struct platform_device *pdev) return PTR_ERR(priv->chan); } + ret = stratix10_svc_add_async_client(priv->chan, false); + if (ret) { + dev_err(dev, "failed to add async client\n"); + stratix10_svc_free_channel(priv->chan); + return ret; + } + init_completion(&priv->completion); platform_set_drvdata(pdev, priv); /* get the initial state from firmware */ - ret = rsu_send_msg(priv, COMMAND_RSU_STATUS, - 0, rsu_status_callback); + ret = rsu_send_async_msg(dev, priv, COMMAND_RSU_STATUS, 0, + rsu_async_status_callback); if (ret) { dev_err(dev, "Error, getting RSU status %i\n", ret); stratix10_svc_free_channel(priv->chan); @@ -763,12 +787,6 @@ static int stratix10_rsu_probe(struct platform_device *pdev) stratix10_svc_free_channel(priv->chan); } - ret = rsu_send_msg(priv, COMMAND_RSU_RETRY, 0, rsu_retry_callback); - if (ret) { - dev_err(dev, "Error, getting RSU retry %i\n", ret); - stratix10_svc_free_channel(priv->chan); - } - ret = rsu_send_msg(priv, COMMAND_RSU_MAX_RETRY, 0, rsu_max_retry_callback); if (ret) { @@ -776,18 +794,12 @@ static int stratix10_rsu_probe(struct platform_device *pdev) stratix10_svc_free_channel(priv->chan); } - priv->get_spt_response_buf = - stratix10_svc_allocate_memory(priv->chan, RSU_GET_SPT_RESP_LEN); - if (IS_ERR(priv->get_spt_response_buf)) { - dev_err(dev, "failed to allocate get spt buffer\n"); - } else { - ret = rsu_send_msg(priv, COMMAND_MBOX_SEND_CMD, - RSU_GET_SPT_CMD, rsu_get_spt_callback); - if (ret) { - dev_err(dev, "Error, getting SPT table %i\n", ret); - stratix10_svc_free_channel(priv->chan); - } + ret = rsu_send_async_msg(dev, priv, COMMAND_RSU_GET_SPT_TABLE, 0, + rsu_async_get_spt_table_callback); + if (ret) { + dev_err(dev, "Error, getting SPT table %i\n", ret); + stratix10_svc_free_channel(priv->chan); } return ret; From 4f7ffdfb9928a70debc6b019a68a6e068745e937 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Wed, 15 Oct 2025 15:11:17 +0530 Subject: [PATCH 232/304] firmware: stratix10-rsu: replace scnprintf() with sysfs_emit() in *_show() functions Replace scnprintf() with sysfs_emit() in sysfs *_show() functions in stratix10-rsu.c to follow the kernel's guidelines from Documentation/filesystems/sysfs.rst. This improves consistency, safety, and makes the code easier to maintain and update in the future. Signed-off-by: Rahul Kumar Signed-off-by: Dinh Nguyen --- drivers/firmware/stratix10-rsu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c index 53b67b242cf0..41da07c445a6 100644 --- a/drivers/firmware/stratix10-rsu.c +++ b/drivers/firmware/stratix10-rsu.c @@ -478,8 +478,7 @@ static ssize_t max_retry_show(struct device *dev, if (!priv) return -ENODEV; - return scnprintf(buf, sizeof(priv->max_retry), - "0x%08x\n", priv->max_retry); + return sysfs_emit(buf, "0x%08x\n", priv->max_retry); } static ssize_t dcmf0_show(struct device *dev, @@ -649,7 +648,7 @@ static ssize_t spt0_address_show(struct device *dev, if (priv->spt0_address == INVALID_SPT_ADDRESS) return -EIO; - return scnprintf(buf, PAGE_SIZE, "0x%08lx\n", priv->spt0_address); + return sysfs_emit(buf, "0x%08lx\n", priv->spt0_address); } static ssize_t spt1_address_show(struct device *dev, @@ -663,7 +662,7 @@ static ssize_t spt1_address_show(struct device *dev, if (priv->spt1_address == INVALID_SPT_ADDRESS) return -EIO; - return scnprintf(buf, PAGE_SIZE, "0x%08lx\n", priv->spt1_address); + return sysfs_emit(buf, "0x%08lx\n", priv->spt1_address); } static DEVICE_ATTR_RO(current_image); From 8775ebd25abcdedb6f3ddf1c3ad69277f9b76081 Mon Sep 17 00:00:00 2001 From: Jonathan Santos Date: Fri, 14 Nov 2025 19:13:55 -0300 Subject: [PATCH 233/304] dt-bindings: iio: accel: adxl380: add new supported parts Include ADXL318 and ADXL319 accelerometers to the documentation. The ADXL318 is based on the ADXL380, while the ADXL319 is based on the ADXL382. However, the ADXL318/319 do not support some built-in features like single tap, double tap and triple tap detection, and also activity and inactivity detection. Signed-off-by: Jonathan Santos Acked-by: Krzysztof Kozlowski Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/accel/adi,adxl380.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl380.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl380.yaml index f1ff5ff4f478..ab517720a6a7 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl380.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl380.yaml @@ -11,16 +11,19 @@ maintainers: - Antoniu Miclaus description: | - The ADXL380/ADXL382 is a low noise density, low power, 3-axis - accelerometer with selectable measurement ranges. The ADXL380 - supports the ±4 g, ±8 g, and ±16 g ranges, and the ADXL382 supports - ±15 g, ±30 g, and ±60 g ranges. + The ADXL380/ADXL382 and ADXL318/ADXL319 are low noise density, + low power, 3-axis accelerometers with selectable measurement ranges. + The ADXL380 and ADXL318 support the ±4 g, ±8 g, and ±16 g ranges, + while the ADXL382 and ADXL319 support ±15 g, ±30 g, and ±60 g ranges. + https://www.analog.com/en/products/adxl318.html https://www.analog.com/en/products/adxl380.html properties: compatible: enum: + - adi,adxl318 + - adi,adxl319 - adi,adxl380 - adi,adxl382 From 0ecad1964315bf171d4eb0874da65e3a7aeb1b3d Mon Sep 17 00:00:00 2001 From: Jonathan Santos Date: Fri, 14 Nov 2025 19:14:02 -0300 Subject: [PATCH 234/304] iio: accel: adxl380: add support for ADXL318 and ADXL319 The ADXL318 and ADXL319 are low noise density, low power, 3-axis accelerometers based on ADXL380 and ADXL382, respectively. The main difference between the new parts and the existing ones are the absence of interrupts and events like tap detection, activity/inactivity, and free-fall detection. Other differences in the new parts are fewer power modes, basically allowing only idle and measurement modes, and the removal of the 12-bit SAR ADC path for the 3-axis signals (known as lower signal chain), being excluisive for the temperature sensor in the ADXL318/319. Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Santos Signed-off-by: Jonathan Cameron --- drivers/iio/accel/adxl380.c | 134 ++++++++++++++++++++++---------- drivers/iio/accel/adxl380.h | 4 + drivers/iio/accel/adxl380_i2c.c | 4 + drivers/iio/accel/adxl380_spi.c | 4 + 4 files changed, 107 insertions(+), 39 deletions(-) diff --git a/drivers/iio/accel/adxl380.c b/drivers/iio/accel/adxl380.c index 0cf3c6815829..6d5f1a0d51e9 100644 --- a/drivers/iio/accel/adxl380.c +++ b/drivers/iio/accel/adxl380.c @@ -26,7 +26,9 @@ #include "adxl380.h" #define ADXL380_ID_VAL 380 +#define ADXL318_ID_VAL 380 #define ADXL382_ID_VAL 382 +#define ADXL319_ID_VAL 382 #define ADXL380_DEVID_AD_REG 0x00 #define ADLX380_PART_ID_REG 0x02 @@ -178,41 +180,6 @@ enum adxl380_tap_time_type { static const int adxl380_range_scale_factor_tbl[] = { 1, 2, 4 }; -const struct adxl380_chip_info adxl380_chip_info = { - .name = "adxl380", - .chip_id = ADXL380_ID_VAL, - .scale_tbl = { - [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 }, - [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 }, - [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 }, - }, - .samp_freq_tbl = { 8000, 16000, 32000 }, - /* - * The datasheet defines an intercept of 470 LSB at 25 degC - * and a sensitivity of 10.2 LSB/C. - */ - .temp_offset = 25 * 102 / 10 - 470, - -}; -EXPORT_SYMBOL_NS_GPL(adxl380_chip_info, "IIO_ADXL380"); - -const struct adxl380_chip_info adxl382_chip_info = { - .name = "adxl382", - .chip_id = ADXL382_ID_VAL, - .scale_tbl = { - [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 }, - [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 }, - [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 }, - }, - .samp_freq_tbl = { 16000, 32000, 64000 }, - /* - * The datasheet defines an intercept of 570 LSB at 25 degC - * and a sensitivity of 10.2 LSB/C. - */ - .temp_offset = 25 * 102 / 10 - 570, -}; -EXPORT_SYMBOL_NS_GPL(adxl382_chip_info, "IIO_ADXL380"); - static const unsigned int adxl380_th_reg_high_addr[2] = { [ADXL380_ACTIVITY] = ADXL380_THRESH_ACT_H_REG, [ADXL380_INACTIVITY] = ADXL380_THRESH_INACT_H_REG, @@ -276,9 +243,14 @@ static int adxl380_set_measure_en(struct adxl380_state *st, bool en) if (ret) return ret; - /* Activity/ Inactivity detection available only in VLP/ULP mode */ - if (FIELD_GET(ADXL380_ACT_EN_MSK, act_inact_ctl) || - FIELD_GET(ADXL380_INACT_EN_MSK, act_inact_ctl)) + /* + * Activity/Inactivity detection available only in VLP/ULP + * mode and for devices that support low power modes. Otherwise + * go straight to measure mode (same bits as ADXL380_OP_MODE_HP). + */ + if (st->chip_info->has_low_power && + (FIELD_GET(ADXL380_ACT_EN_MSK, act_inact_ctl) || + FIELD_GET(ADXL380_INACT_EN_MSK, act_inact_ctl))) op_mode = ADXL380_OP_MODE_VLP; else op_mode = ADXL380_OP_MODE_HP; @@ -1618,6 +1590,15 @@ static int adxl380_set_watermark(struct iio_dev *indio_dev, unsigned int val) return 0; } +static const struct iio_info adxl318_info = { + .read_raw = adxl380_read_raw, + .read_avail = &adxl380_read_avail, + .write_raw = adxl380_write_raw, + .write_raw_get_fmt = adxl380_write_raw_get_fmt, + .debugfs_reg_access = &adxl380_reg_access, + .hwfifo_set_watermark = adxl380_set_watermark, +}; + static const struct iio_info adxl380_info = { .read_raw = adxl380_read_raw, .read_avail = &adxl380_read_avail, @@ -1632,6 +1613,81 @@ static const struct iio_info adxl380_info = { .hwfifo_set_watermark = adxl380_set_watermark, }; +const struct adxl380_chip_info adxl318_chip_info = { + .name = "adxl318", + .chip_id = ADXL318_ID_VAL, + .scale_tbl = { + [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 }, + [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 }, + [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 }, + }, + .samp_freq_tbl = { 8000, 16000, 32000 }, + /* + * The datasheet defines an intercept of 550 LSB at 25 degC + * and a sensitivity of 10.2 LSB/C. + */ + .temp_offset = 25 * 102 / 10 - 550, + .info = &adxl318_info, +}; +EXPORT_SYMBOL_NS_GPL(adxl318_chip_info, "IIO_ADXL380"); + +const struct adxl380_chip_info adxl319_chip_info = { + .name = "adxl319", + .chip_id = ADXL319_ID_VAL, + .scale_tbl = { + [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 }, + [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 }, + [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 }, + }, + .samp_freq_tbl = { 16000, 32000, 64000 }, + /* + * The datasheet defines an intercept of 550 LSB at 25 degC + * and a sensitivity of 10.2 LSB/C. + */ + .temp_offset = 25 * 102 / 10 - 550, + .info = &adxl318_info, +}; +EXPORT_SYMBOL_NS_GPL(adxl319_chip_info, "IIO_ADXL380"); + +const struct adxl380_chip_info adxl380_chip_info = { + .name = "adxl380", + .chip_id = ADXL380_ID_VAL, + .scale_tbl = { + [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 }, + [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 }, + [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 }, + }, + .samp_freq_tbl = { 8000, 16000, 32000 }, + /* + * The datasheet defines an intercept of 470 LSB at 25 degC + * and a sensitivity of 10.2 LSB/C. + */ + .temp_offset = 25 * 102 / 10 - 470, + .has_low_power = true, + .info = &adxl380_info, + +}; +EXPORT_SYMBOL_NS_GPL(adxl380_chip_info, "IIO_ADXL380"); + +const struct adxl380_chip_info adxl382_chip_info = { + .name = "adxl382", + .chip_id = ADXL382_ID_VAL, + .scale_tbl = { + [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 }, + [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 }, + [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 }, + }, + .samp_freq_tbl = { 16000, 32000, 64000 }, + /* + * The datasheet defines an intercept of 570 LSB at 25 degC + * and a sensitivity of 10.2 LSB/C. + */ + .temp_offset = 25 * 102 / 10 - 570, + .has_low_power = true, + .info = &adxl380_info, +}; +EXPORT_SYMBOL_NS_GPL(adxl382_chip_info, "IIO_ADXL380"); + static const struct iio_event_spec adxl380_events[] = { { .type = IIO_EV_TYPE_THRESH, @@ -1866,7 +1922,7 @@ int adxl380_probe(struct device *dev, struct regmap *regmap, indio_dev->channels = adxl380_channels; indio_dev->num_channels = ARRAY_SIZE(adxl380_channels); indio_dev->name = chip_info->name; - indio_dev->info = &adxl380_info; + indio_dev->info = chip_info->info; indio_dev->modes = INDIO_DIRECT_MODE; ret = devm_regulator_get_enable(dev, "vddio"); diff --git a/drivers/iio/accel/adxl380.h b/drivers/iio/accel/adxl380.h index a683625d897a..e67c5aab8efc 100644 --- a/drivers/iio/accel/adxl380.h +++ b/drivers/iio/accel/adxl380.h @@ -12,10 +12,14 @@ struct adxl380_chip_info { const char *name; const int scale_tbl[3][2]; const int samp_freq_tbl[3]; + const struct iio_info *info; const int temp_offset; const u16 chip_id; + const bool has_low_power; }; +extern const struct adxl380_chip_info adxl318_chip_info; +extern const struct adxl380_chip_info adxl319_chip_info; extern const struct adxl380_chip_info adxl380_chip_info; extern const struct adxl380_chip_info adxl382_chip_info; diff --git a/drivers/iio/accel/adxl380_i2c.c b/drivers/iio/accel/adxl380_i2c.c index b4f86f972361..bd8782d08c7d 100644 --- a/drivers/iio/accel/adxl380_i2c.c +++ b/drivers/iio/accel/adxl380_i2c.c @@ -33,6 +33,8 @@ static int adxl380_i2c_probe(struct i2c_client *client) } static const struct i2c_device_id adxl380_i2c_id[] = { + { "adxl318", (kernel_ulong_t)&adxl318_chip_info }, + { "adxl319", (kernel_ulong_t)&adxl319_chip_info }, { "adxl380", (kernel_ulong_t)&adxl380_chip_info }, { "adxl382", (kernel_ulong_t)&adxl382_chip_info }, { } @@ -40,6 +42,8 @@ static const struct i2c_device_id adxl380_i2c_id[] = { MODULE_DEVICE_TABLE(i2c, adxl380_i2c_id); static const struct of_device_id adxl380_of_match[] = { + { .compatible = "adi,adxl318", .data = &adxl318_chip_info }, + { .compatible = "adi,adxl319", .data = &adxl319_chip_info }, { .compatible = "adi,adxl380", .data = &adxl380_chip_info }, { .compatible = "adi,adxl382", .data = &adxl382_chip_info }, { } diff --git a/drivers/iio/accel/adxl380_spi.c b/drivers/iio/accel/adxl380_spi.c index 6edd0d211ffa..4ead949b24f1 100644 --- a/drivers/iio/accel/adxl380_spi.c +++ b/drivers/iio/accel/adxl380_spi.c @@ -35,6 +35,8 @@ static int adxl380_spi_probe(struct spi_device *spi) } static const struct spi_device_id adxl380_spi_id[] = { + { "adxl318", (kernel_ulong_t)&adxl318_chip_info }, + { "adxl319", (kernel_ulong_t)&adxl319_chip_info }, { "adxl380", (kernel_ulong_t)&adxl380_chip_info }, { "adxl382", (kernel_ulong_t)&adxl382_chip_info }, { } @@ -42,6 +44,8 @@ static const struct spi_device_id adxl380_spi_id[] = { MODULE_DEVICE_TABLE(spi, adxl380_spi_id); static const struct of_device_id adxl380_of_match[] = { + { .compatible = "adi,adxl318", .data = &adxl318_chip_info }, + { .compatible = "adi,adxl319", .data = &adxl319_chip_info }, { .compatible = "adi,adxl380", .data = &adxl380_chip_info }, { .compatible = "adi,adxl382", .data = &adxl382_chip_info }, { } From f5d203467a31798191365efeb16cd619d2c8f23a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 12 Nov 2025 15:55:08 +0100 Subject: [PATCH 235/304] iio: core: add missing mutex_destroy in iio_dev_release() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing mutex_destroy() call in iio_dev_release() to properly clean up the mutex initialized in iio_device_alloc(). Ensure proper resource cleanup and follows kernel practices. Found by code review. While at it, create a lockdep key before mutex initialisation. This will help with converting it to the better API in the future. Fixes: 847ec80bbaa7 ("Staging: IIO: core support for device registration and management") Fixes: ac917a81117c ("staging:iio:core set the iio_dev.info pointer to null on unregister under lock.") Signed-off-by: Andy Shevchenko Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 88c3d585a1bd..93d6e5b101cf 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1654,6 +1654,9 @@ static void iio_dev_release(struct device *device) iio_device_detach_buffers(indio_dev); + mutex_destroy(&iio_dev_opaque->info_exist_lock); + mutex_destroy(&iio_dev_opaque->mlock); + lockdep_unregister_key(&iio_dev_opaque->mlock_key); ida_free(&iio_ida, iio_dev_opaque->id); @@ -1698,8 +1701,7 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) indio_dev->dev.type = &iio_device_type; indio_dev->dev.bus = &iio_bus_type; device_initialize(&indio_dev->dev); - mutex_init(&iio_dev_opaque->mlock); - mutex_init(&iio_dev_opaque->info_exist_lock); + INIT_LIST_HEAD(&iio_dev_opaque->channel_attr_list); iio_dev_opaque->id = ida_alloc(&iio_ida, GFP_KERNEL); @@ -1722,6 +1724,9 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) lockdep_register_key(&iio_dev_opaque->mlock_key); lockdep_set_class(&iio_dev_opaque->mlock, &iio_dev_opaque->mlock_key); + mutex_init(&iio_dev_opaque->mlock); + mutex_init(&iio_dev_opaque->info_exist_lock); + return indio_dev; } EXPORT_SYMBOL(iio_device_alloc); From b0e6871415b25f5e84a79621834e3d0c9d4627a6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 12 Nov 2025 15:55:09 +0100 Subject: [PATCH 236/304] iio: core: Clean up device correctly on iio_device_alloc() failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Once we called device_initialize() we have to call put_device() on it. Refactor the code to make it in the right order. Fixes: fe6f45f6ba22 ("iio: core: check return value when calling dev_set_name()") Fixes: 847ec80bbaa7 ("Staging: IIO: core support for device registration and management") Signed-off-by: Andy Shevchenko Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 93d6e5b101cf..5d2f35cf18bc 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1697,11 +1697,6 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) ACCESS_PRIVATE(indio_dev, priv) = (char *)iio_dev_opaque + ALIGN(sizeof(*iio_dev_opaque), IIO_DMA_MINALIGN); - indio_dev->dev.parent = parent; - indio_dev->dev.type = &iio_device_type; - indio_dev->dev.bus = &iio_bus_type; - device_initialize(&indio_dev->dev); - INIT_LIST_HEAD(&iio_dev_opaque->channel_attr_list); iio_dev_opaque->id = ida_alloc(&iio_ida, GFP_KERNEL); @@ -1727,6 +1722,11 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) mutex_init(&iio_dev_opaque->mlock); mutex_init(&iio_dev_opaque->info_exist_lock); + indio_dev->dev.parent = parent; + indio_dev->dev.type = &iio_device_type; + indio_dev->dev.bus = &iio_bus_type; + device_initialize(&indio_dev->dev); + return indio_dev; } EXPORT_SYMBOL(iio_device_alloc); From c76ba4b2644424b8dbacee80bb40991eac29d39e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 12 Nov 2025 15:55:10 +0100 Subject: [PATCH 237/304] iio: core: Replace lockdep_set_class() + mutex_init() by combined call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace lockdep_set_class() + mutex_init() by combined call mutex_init_with_key(). Signed-off-by: Andy Shevchenko Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 5d2f35cf18bc..f69deefcfb6f 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1717,9 +1717,8 @@ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) INIT_LIST_HEAD(&iio_dev_opaque->ioctl_handlers); lockdep_register_key(&iio_dev_opaque->mlock_key); - lockdep_set_class(&iio_dev_opaque->mlock, &iio_dev_opaque->mlock_key); - mutex_init(&iio_dev_opaque->mlock); + mutex_init_with_key(&iio_dev_opaque->mlock, &iio_dev_opaque->mlock_key); mutex_init(&iio_dev_opaque->info_exist_lock); indio_dev->dev.parent = parent; From 0de73abe5f5c2b58d66d6dcb7d44df05b0f73684 Mon Sep 17 00:00:00 2001 From: Liang Jie Date: Fri, 14 Nov 2025 16:47:25 +0800 Subject: [PATCH 238/304] iio: buffer: use dma_buf_unmap_attachment_unlocked() helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace open-coded dma_resv_lock()/dma_resv_unlock() around dma_buf_unmap_attachment() in iio_buffer_dmabuf_release() with the dma_buf_unmap_attachment_unlocked() helper. This aligns with the standard DMA-BUF API, avoids duplicating locking logic and eases future maintenance. No functional change. Reviewed-by: fanggeng Signed-off-by: Liang Jie Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-buffer.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index f1448ae1b843..b9ebb6f43404 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -1563,9 +1563,7 @@ static void iio_buffer_dmabuf_release(struct kref *ref) struct iio_buffer *buffer = priv->buffer; struct dma_buf *dmabuf = attach->dmabuf; - dma_resv_lock(dmabuf->resv, NULL); - dma_buf_unmap_attachment(attach, priv->sgt, priv->dir); - dma_resv_unlock(dmabuf->resv); + dma_buf_unmap_attachment_unlocked(attach, priv->sgt, priv->dir); buffer->access->detach_dmabuf(buffer, priv->block); From 47e4b1ca441cc4f1d9db13ff5e9b89e53aae0198 Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Wed, 12 Nov 2025 23:56:59 +0100 Subject: [PATCH 239/304] iio: mpl3115: use get_unaligned_be24() to retrieve pressure data The pressure measurement result is arranged as 20-bit unsigned value residing in three 8-bit registers. Hence, it can be retrieved using get_unaligned_be24() and by applying 4-bit shift. Reviewed-by: Marcelo Schmitt Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/mpl3115.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index c212dfdf59ff..5594256fffbd 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -125,7 +126,7 @@ static int mpl3115_read_info_raw(struct mpl3115_data *data, switch (chan->type) { case IIO_PRESSURE: { /* in 0.25 pascal / LSB */ - __be32 tmp = 0; + u8 press_be24[3]; guard(mutex)(&data->lock); ret = mpl3115_request(data); @@ -134,11 +135,17 @@ static int mpl3115_read_info_raw(struct mpl3115_data *data, ret = i2c_smbus_read_i2c_block_data(data->client, MPL3115_OUT_PRESS, - 3, (u8 *) &tmp); + sizeof(press_be24), + press_be24); if (ret < 0) return ret; - *val = be32_to_cpu(tmp) >> chan->scan_type.shift; + /* + * The pressure channel shift is applied in the case where the + * data (24-bit big endian) is read into a 32-bit buffer. Here + * the data is stored in a 24-bit buffer, so the shift is 4. + */ + *val = get_unaligned_be24(press_be24) >> 4; return IIO_VAL_INT; } case IIO_TEMP: { /* in 0.0625 celsius / LSB */ From 6062cd20cbea6006d30af50e6f7d2a8722baa81b Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Wed, 12 Nov 2025 23:57:00 +0100 Subject: [PATCH 240/304] iio: mpl3115: add threshold events support Add support for pressure and temperature rising threshold events. For both channels *_en and *_value (in raw units) attributes are exposed. Since in write_event_config() the ctrl_reg1.active and ctrl_reg4 are modified, accessing the data->ctrl_reg{1,4} in set_trigger_state() and write_event_config() needs to be now guarded by data->lock. Otherwise, it would be possible that 2 concurrent threads executing these functions would access the data->ctrl_reg{1,4} at the same time and then one would overwrite the other's result. Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/mpl3115.c | 223 +++++++++++++++++++++++++++++++-- 1 file changed, 212 insertions(+), 11 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index 5594256fffbd..aeac1586f12e 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -14,11 +14,13 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -31,6 +33,8 @@ #define MPL3115_WHO_AM_I 0x0c #define MPL3115_INT_SOURCE 0x12 #define MPL3115_PT_DATA_CFG 0x13 +#define MPL3115_PRESS_TGT 0x16 /* MSB first, 16 bit */ +#define MPL3115_TEMP_TGT 0x18 #define MPL3115_CTRL_REG1 0x26 #define MPL3115_CTRL_REG2 0x27 #define MPL3115_CTRL_REG3 0x28 @@ -43,6 +47,8 @@ #define MPL3115_STATUS_TEMP_RDY BIT(1) #define MPL3115_INT_SRC_DRDY BIT(7) +#define MPL3115_INT_SRC_PTH BIT(3) +#define MPL3115_INT_SRC_TTH BIT(2) #define MPL3115_PT_DATA_EVENT_ALL GENMASK(2, 0) @@ -57,6 +63,8 @@ #define MPL3115_CTRL3_IPOL2 BIT(1) #define MPL3115_CTRL4_INT_EN_DRDY BIT(7) +#define MPL3115_CTRL4_INT_EN_PTH BIT(3) +#define MPL3115_CTRL4_INT_EN_TTH BIT(2) #define MPL3115_CTRL5_INT_CFG_DRDY BIT(7) @@ -84,6 +92,7 @@ struct mpl3115_data { struct iio_trigger *drdy_trig; struct mutex lock; u8 ctrl_reg1; + u8 ctrl_reg4; }; enum mpl3115_irq_pin { @@ -313,6 +322,15 @@ done: return IRQ_HANDLED; } +static const struct iio_event_spec mpl3115_temp_press_event[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_ENABLE) | + BIT(IIO_EV_INFO_VALUE), + }, +}; + static const struct iio_chan_spec mpl3115_channels[] = { { .type = IIO_PRESSURE, @@ -328,7 +346,9 @@ static const struct iio_chan_spec mpl3115_channels[] = { .storagebits = 32, .shift = 12, .endianness = IIO_BE, - } + }, + .event_spec = mpl3115_temp_press_event, + .num_event_specs = ARRAY_SIZE(mpl3115_temp_press_event), }, { .type = IIO_TEMP, @@ -344,7 +364,9 @@ static const struct iio_chan_spec mpl3115_channels[] = { .storagebits = 16, .shift = 4, .endianness = IIO_BE, - } + }, + .event_spec = mpl3115_temp_press_event, + .num_event_specs = ARRAY_SIZE(mpl3115_temp_press_event), }, IIO_CHAN_SOFT_TIMESTAMP(2), }; @@ -354,15 +376,46 @@ static irqreturn_t mpl3115_interrupt_handler(int irq, void *private) struct iio_dev *indio_dev = private; struct mpl3115_data *data = iio_priv(indio_dev); int ret; + u8 val_press[3]; + __be16 val_temp; ret = i2c_smbus_read_byte_data(data->client, MPL3115_INT_SOURCE); if (ret < 0) return IRQ_HANDLED; - if (!(ret & MPL3115_INT_SRC_DRDY)) + if (!(ret & (MPL3115_INT_SRC_TTH | MPL3115_INT_SRC_PTH | + MPL3115_INT_SRC_DRDY))) return IRQ_NONE; - iio_trigger_poll_nested(data->drdy_trig); + if (ret & MPL3115_INT_SRC_DRDY) + iio_trigger_poll_nested(data->drdy_trig); + + if (ret & MPL3115_INT_SRC_PTH) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_PRESSURE, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + + /* Reset the SRC_PTH bit in INT_SOURCE */ + i2c_smbus_read_i2c_block_data(data->client, + MPL3115_OUT_PRESS, + sizeof(val_press), val_press); + } + + if (ret & MPL3115_INT_SRC_TTH) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + + /* Reset the SRC_TTH bit in INT_SOURCE */ + i2c_smbus_read_i2c_block_data(data->client, + MPL3115_OUT_TEMP, + sizeof(val_temp), + (u8 *)&val_temp); + } return IRQ_HANDLED; } @@ -383,6 +436,7 @@ static int mpl3115_config_interrupt(struct mpl3115_data *data, goto reg1_cleanup; data->ctrl_reg1 = ctrl_reg1; + data->ctrl_reg4 = ctrl_reg4; return 0; @@ -396,16 +450,23 @@ static int mpl3115_set_trigger_state(struct iio_trigger *trig, bool state) { struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); struct mpl3115_data *data = iio_priv(indio_dev); - u8 ctrl_reg1 = data->ctrl_reg1; - u8 ctrl_reg4 = state ? MPL3115_CTRL4_INT_EN_DRDY : 0; - - if (state) - ctrl_reg1 |= MPL3115_CTRL1_ACTIVE; - else - ctrl_reg1 &= ~MPL3115_CTRL1_ACTIVE; + u8 ctrl_reg1, ctrl_reg4; guard(mutex)(&data->lock); + ctrl_reg1 = data->ctrl_reg1; + ctrl_reg4 = data->ctrl_reg4; + + if (state) { + ctrl_reg1 |= MPL3115_CTRL1_ACTIVE; + ctrl_reg4 |= MPL3115_CTRL4_INT_EN_DRDY; + } else { + ctrl_reg4 &= ~MPL3115_CTRL4_INT_EN_DRDY; + + if (!ctrl_reg4) + ctrl_reg1 &= ~MPL3115_CTRL1_ACTIVE; + } + return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4); } @@ -413,10 +474,150 @@ static const struct iio_trigger_ops mpl3115_trigger_ops = { .set_trigger_state = mpl3115_set_trigger_state, }; +static int mpl3115_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct mpl3115_data *data = iio_priv(indio_dev); + + if (chan->type == IIO_PRESSURE) + return !!(data->ctrl_reg4 & MPL3115_CTRL4_INT_EN_PTH); + + if (chan->type == IIO_TEMP) + return !!(data->ctrl_reg4 & MPL3115_CTRL4_INT_EN_TTH); + + return -EINVAL; +} + +static int mpl3115_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct mpl3115_data *data = iio_priv(indio_dev); + u8 int_en_mask; + u8 ctrl_reg1, ctrl_reg4; + + switch (chan->type) { + case IIO_PRESSURE: + int_en_mask = MPL3115_CTRL4_INT_EN_PTH; + break; + case IIO_TEMP: + int_en_mask = MPL3115_CTRL4_INT_EN_TTH; + break; + default: + return -EINVAL; + } + + guard(mutex)(&data->lock); + + ctrl_reg1 = data->ctrl_reg1; + ctrl_reg4 = data->ctrl_reg4; + + if (state) { + ctrl_reg1 |= MPL3115_CTRL1_ACTIVE; + ctrl_reg4 |= int_en_mask; + } else { + ctrl_reg4 &= ~int_en_mask; + + if (!ctrl_reg4) + ctrl_reg1 &= ~MPL3115_CTRL1_ACTIVE; + } + + return mpl3115_config_interrupt(data, ctrl_reg1, ctrl_reg4); +} + +static int mpl3115_read_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + struct mpl3115_data *data = iio_priv(indio_dev); + int ret; + __be16 press_tgt; + + if (info != IIO_EV_INFO_VALUE) + return -EINVAL; + + switch (chan->type) { + case IIO_PRESSURE: + ret = i2c_smbus_read_i2c_block_data(data->client, + MPL3115_PRESS_TGT, + sizeof(press_tgt), + (u8 *)&press_tgt); + if (ret < 0) + return ret; + + /* + * Target value for the pressure is 16-bit unsigned value, + * expressed in 2 Pa units + */ + *val = be16_to_cpu(press_tgt) << 1; + + return IIO_VAL_INT; + case IIO_TEMP: + ret = i2c_smbus_read_byte_data(data->client, MPL3115_TEMP_TGT); + if (ret < 0) + return ret; + + /* Target value for the temperature is 8-bit 2's complement */ + *val = sign_extend32(ret, 7); + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int mpl3115_write_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct mpl3115_data *data = iio_priv(indio_dev); + __be16 press_tgt; + + if (info != IIO_EV_INFO_VALUE) + return -EINVAL; + + switch (chan->type) { + case IIO_PRESSURE: + val >>= 1; + + if (val < 0 || val > U16_MAX) + return -EINVAL; + + press_tgt = cpu_to_be16(val); + + return i2c_smbus_write_i2c_block_data(data->client, + MPL3115_PRESS_TGT, + sizeof(press_tgt), + (u8 *)&press_tgt); + case IIO_TEMP: + if (val < S8_MIN || val > S8_MAX) + return -EINVAL; + + return i2c_smbus_write_byte_data(data->client, + MPL3115_TEMP_TGT, val); + default: + return -EINVAL; + } +} + static const struct iio_info mpl3115_info = { .read_raw = &mpl3115_read_raw, .read_avail = &mpl3115_read_avail, .write_raw = &mpl3115_write_raw, + .read_event_config = mpl3115_read_event_config, + .write_event_config = mpl3115_write_event_config, + .read_event_value = mpl3115_read_thresh, + .write_event_value = mpl3115_write_thresh, }; static int mpl3115_trigger_probe(struct mpl3115_data *data, From 28b53b35c037c05bfedd28ef027e80a1b505f4aa Mon Sep 17 00:00:00 2001 From: Antoni Pokusinski Date: Wed, 12 Nov 2025 23:57:01 +0100 Subject: [PATCH 241/304] iio: ABI: document pressure event attributes Add sysfs pressure event attributes exposed by the mpl3115 driver. These allow controlling the threshold value and the enable state. Reviewed-by: Marcelo Schmitt Signed-off-by: Antoni Pokusinski Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 352ab7b8476c..5f87dcee78f7 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -898,6 +898,7 @@ What: /sys/.../iio:deviceX/events/in_tempY_thresh_rising_en What: /sys/.../iio:deviceX/events/in_tempY_thresh_falling_en What: /sys/.../iio:deviceX/events/in_capacitanceY_thresh_rising_en What: /sys/.../iio:deviceX/events/in_capacitanceY_thresh_falling_en +What: /sys/.../iio:deviceX/events/in_pressure_thresh_rising_en KernelVersion: 2.6.37 Contact: linux-iio@vger.kernel.org Description: @@ -1047,6 +1048,7 @@ What: /sys/.../events/in_capacitanceY_thresh_rising_value What: /sys/.../events/in_capacitanceY_thresh_falling_value What: /sys/.../events/in_capacitanceY_thresh_adaptive_rising_value What: /sys/.../events/in_capacitanceY_thresh_falling_rising_value +What: /sys/.../events/in_pressure_thresh_rising_value KernelVersion: 2.6.37 Contact: linux-iio@vger.kernel.org Description: From 02d44a1b64f11cdbcd5349063f149309c42a9fa5 Mon Sep 17 00:00:00 2001 From: Akhilesh Patil Date: Sun, 16 Nov 2025 11:48:49 +0530 Subject: [PATCH 242/304] iio: pressure: Arrange Makefile alphabetically Fix hp206c and st_pressure_* entries in pressure Makefiles to follow alphabetical order as per guideline mentioned in iio/pressure/Makefile. Signed-off-by: Akhilesh Patil Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/Makefile | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/iio/pressure/Makefile b/drivers/iio/pressure/Makefile index 47bf7656f975..a21443e992b9 100644 --- a/drivers/iio/pressure/Makefile +++ b/drivers/iio/pressure/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DPS310) += dps310.o obj-$(CONFIG_IIO_CROS_EC_BARO) += cros_ec_baro.o obj-$(CONFIG_HID_SENSOR_PRESS) += hid-sensor-press.o obj-$(CONFIG_HP03) += hp03.o +obj-$(CONFIG_HP206C) += hp206c.o obj-$(CONFIG_HSC030PA) += hsc030pa.o obj-$(CONFIG_HSC030PA_I2C) += hsc030pa_i2c.o obj-$(CONFIG_HSC030PA_SPI) += hsc030pa_spi.o @@ -35,11 +36,9 @@ obj-$(CONFIG_SDP500) += sdp500.o obj-$(CONFIG_IIO_ST_PRESS) += st_pressure.o st_pressure-y := st_pressure_core.o st_pressure-$(CONFIG_IIO_BUFFER) += st_pressure_buffer.o +obj-$(CONFIG_IIO_ST_PRESS_I2C) += st_pressure_i2c.o +obj-$(CONFIG_IIO_ST_PRESS_SPI) += st_pressure_spi.o obj-$(CONFIG_T5403) += t5403.o -obj-$(CONFIG_HP206C) += hp206c.o obj-$(CONFIG_ZPA2326) += zpa2326.o obj-$(CONFIG_ZPA2326_I2C) += zpa2326_i2c.o obj-$(CONFIG_ZPA2326_SPI) += zpa2326_spi.o - -obj-$(CONFIG_IIO_ST_PRESS_I2C) += st_pressure_i2c.o -obj-$(CONFIG_IIO_ST_PRESS_SPI) += st_pressure_spi.o From f9e05791642810a0cf6237d39fafd6fec5e0b4bb Mon Sep 17 00:00:00 2001 From: Shi Hao Date: Sun, 16 Nov 2025 15:46:20 +0530 Subject: [PATCH 243/304] staging: iio: adt7316: replace sprintf() with sysfs_emit() Convert several sprintf() calls to sysfs_emit() in the sysfs show functions, as it is the preferred helper and prevents potential buffer overruns. No functional changes intended. Signed-off-by: Shi Hao Reviewed-by: Andy Shevchenko Signed-off-by: Jonathan Cameron --- drivers/staging/iio/addac/adt7316.c | 102 ++++++++++++++-------------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/drivers/staging/iio/addac/adt7316.c b/drivers/staging/iio/addac/adt7316.c index 16f30c4f1aa0..8a9a8262c2be 100644 --- a/drivers/staging/iio/addac/adt7316.c +++ b/drivers/staging/iio/addac/adt7316.c @@ -216,7 +216,7 @@ static ssize_t adt7316_show_enabled(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", !!(chip->config1 & ADT7316_EN)); + return sysfs_emit(buf, "%d\n", !!(chip->config1 & ADT7316_EN)); } static ssize_t _adt7316_store_enabled(struct adt7316_chip_info *chip, @@ -274,7 +274,7 @@ static ssize_t adt7316_show_select_ex_temp(struct device *dev, if ((chip->id & ID_FAMILY_MASK) != ID_ADT75XX) return -EPERM; - return sprintf(buf, "%d\n", !!(chip->config1 & ADT7516_SEL_EX_TEMP)); + return sysfs_emit(buf, "%d\n", !!(chip->config1 & ADT7516_SEL_EX_TEMP)); } static ssize_t adt7316_store_select_ex_temp(struct device *dev, @@ -316,9 +316,9 @@ static ssize_t adt7316_show_mode(struct device *dev, struct adt7316_chip_info *chip = iio_priv(dev_info); if (chip->config2 & ADT7316_AD_SINGLE_CH_MODE) - return sprintf(buf, "single_channel\n"); + return sysfs_emit(buf, "single_channel\n"); - return sprintf(buf, "round_robin\n"); + return sysfs_emit(buf, "round_robin\n"); } static ssize_t adt7316_store_mode(struct device *dev, @@ -353,7 +353,7 @@ static ssize_t adt7316_show_all_modes(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "single_channel\nround_robin\n"); + return sysfs_emit(buf, "single_channel\nround_robin\n"); } static IIO_DEVICE_ATTR(all_modes, 0444, adt7316_show_all_modes, NULL, 0); @@ -370,29 +370,29 @@ static ssize_t adt7316_show_ad_channel(struct device *dev, switch (chip->config2 & ADT7516_AD_SINGLE_CH_MASK) { case ADT7316_AD_SINGLE_CH_VDD: - return sprintf(buf, "0 - VDD\n"); + return sysfs_emit(buf, "0 - VDD\n"); case ADT7316_AD_SINGLE_CH_IN: - return sprintf(buf, "1 - Internal Temperature\n"); + return sysfs_emit(buf, "1 - Internal Temperature\n"); case ADT7316_AD_SINGLE_CH_EX: if (((chip->id & ID_FAMILY_MASK) == ID_ADT75XX) && (chip->config1 & ADT7516_SEL_AIN1_2_EX_TEMP_MASK) == 0) - return sprintf(buf, "2 - AIN1\n"); + return sysfs_emit(buf, "2 - AIN1\n"); - return sprintf(buf, "2 - External Temperature\n"); + return sysfs_emit(buf, "2 - External Temperature\n"); case ADT7516_AD_SINGLE_CH_AIN2: if ((chip->config1 & ADT7516_SEL_AIN1_2_EX_TEMP_MASK) == 0) - return sprintf(buf, "3 - AIN2\n"); + return sysfs_emit(buf, "3 - AIN2\n"); - return sprintf(buf, "N/A\n"); + return sysfs_emit(buf, "N/A\n"); case ADT7516_AD_SINGLE_CH_AIN3: if (chip->config1 & ADT7516_SEL_AIN3) - return sprintf(buf, "4 - AIN3\n"); + return sysfs_emit(buf, "4 - AIN3\n"); - return sprintf(buf, "N/A\n"); + return sysfs_emit(buf, "N/A\n"); case ADT7516_AD_SINGLE_CH_AIN4: - return sprintf(buf, "5 - AIN4\n"); + return sysfs_emit(buf, "5 - AIN4\n"); default: - return sprintf(buf, "N/A\n"); + return sysfs_emit(buf, "N/A\n"); } } @@ -453,10 +453,10 @@ static ssize_t adt7316_show_all_ad_channels(struct device *dev, return -EPERM; if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX) - return sprintf(buf, "0 - VDD\n1 - Internal Temperature\n" + return sysfs_emit(buf, "0 - VDD\n1 - Internal Temperature\n" "2 - External Temperature or AIN1\n" "3 - AIN2\n4 - AIN3\n5 - AIN4\n"); - return sprintf(buf, "0 - VDD\n1 - Internal Temperature\n" + return sysfs_emit(buf, "0 - VDD\n1 - Internal Temperature\n" "2 - External Temperature\n"); } @@ -470,7 +470,7 @@ static ssize_t adt7316_show_disable_averaging(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->config2 & ADT7316_DISABLE_AVERAGING)); } @@ -509,7 +509,7 @@ static ssize_t adt7316_show_enable_smbus_timeout(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->config2 & ADT7316_EN_SMBUS_TIMEOUT)); } @@ -548,7 +548,7 @@ static ssize_t adt7316_show_powerdown(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", !!(chip->config1 & ADT7316_PD)); + return sysfs_emit(buf, "%d\n", !!(chip->config1 & ADT7316_PD)); } static ssize_t adt7316_store_powerdown(struct device *dev, @@ -586,7 +586,7 @@ static ssize_t adt7316_show_fast_ad_clock(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", !!(chip->config3 & ADT7316_ADCLK_22_5)); + return sysfs_emit(buf, "%d\n", !!(chip->config3 & ADT7316_ADCLK_22_5)); } static ssize_t adt7316_store_fast_ad_clock(struct device *dev, @@ -626,10 +626,10 @@ static ssize_t adt7316_show_da_high_resolution(struct device *dev, if (chip->config3 & ADT7316_DA_HIGH_RESOLUTION) { if (chip->id != ID_ADT7318 && chip->id != ID_ADT7519) - return sprintf(buf, "1 (10 bits)\n"); + return sysfs_emit(buf, "1 (10 bits)\n"); } - return sprintf(buf, "0 (8 bits)\n"); + return sysfs_emit(buf, "0 (8 bits)\n"); } static ssize_t adt7316_store_da_high_resolution(struct device *dev, @@ -673,7 +673,7 @@ static ssize_t adt7316_show_AIN_internal_Vref(struct device *dev, if ((chip->id & ID_FAMILY_MASK) != ID_ADT75XX) return -EPERM; - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->config3 & ADT7516_AIN_IN_VREF)); } @@ -716,7 +716,7 @@ static ssize_t adt7316_show_enable_prop_DACA(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->config3 & ADT7316_EN_IN_TEMP_PROP_DACA)); } @@ -755,7 +755,7 @@ static ssize_t adt7316_show_enable_prop_DACB(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->config3 & ADT7316_EN_EX_TEMP_PROP_DACB)); } @@ -794,7 +794,7 @@ static ssize_t adt7316_show_DAC_2Vref_ch_mask(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "0x%x\n", + return sysfs_emit(buf, "0x%x\n", chip->dac_config & ADT7316_DA_2VREF_CH_MASK); } @@ -838,20 +838,20 @@ static ssize_t adt7316_show_DAC_update_mode(struct device *dev, struct adt7316_chip_info *chip = iio_priv(dev_info); if (!(chip->config3 & ADT7316_DA_EN_VIA_DAC_LDAC)) - return sprintf(buf, "manual\n"); + return sysfs_emit(buf, "manual\n"); switch (chip->dac_config & ADT7316_DA_EN_MODE_MASK) { case ADT7316_DA_EN_MODE_SINGLE: - return sprintf(buf, + return sysfs_emit(buf, "0 - auto at any MSB DAC writing\n"); case ADT7316_DA_EN_MODE_AB_CD: - return sprintf(buf, + return sysfs_emit(buf, "1 - auto at MSB DAC AB and CD writing\n"); case ADT7316_DA_EN_MODE_ABCD: - return sprintf(buf, + return sysfs_emit(buf, "2 - auto at MSB DAC ABCD writing\n"); default: /* ADT7316_DA_EN_MODE_LDAC */ - return sprintf(buf, "3 - manual\n"); + return sysfs_emit(buf, "3 - manual\n"); } } @@ -898,11 +898,11 @@ static ssize_t adt7316_show_all_DAC_update_modes(struct device *dev, struct adt7316_chip_info *chip = iio_priv(dev_info); if (chip->config3 & ADT7316_DA_EN_VIA_DAC_LDAC) - return sprintf(buf, "0 - auto at any MSB DAC writing\n" + return sysfs_emit(buf, "0 - auto at any MSB DAC writing\n" "1 - auto at MSB DAC AB and CD writing\n" "2 - auto at MSB DAC ABCD writing\n" "3 - manual\n"); - return sprintf(buf, "manual\n"); + return sysfs_emit(buf, "manual\n"); } static IIO_DEVICE_ATTR(all_DAC_update_modes, 0444, @@ -955,7 +955,7 @@ static ssize_t adt7316_show_DA_AB_Vref_bypass(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->dac_config & ADT7316_VREF_BYPASS_DAC_AB)); } @@ -994,7 +994,7 @@ static ssize_t adt7316_show_DA_CD_Vref_bypass(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->dac_config & ADT7316_VREF_BYPASS_DAC_CD)); } @@ -1034,10 +1034,10 @@ static ssize_t adt7316_show_DAC_internal_Vref(struct device *dev, struct adt7316_chip_info *chip = iio_priv(dev_info); if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX) - return sprintf(buf, "0x%x\n", + return sysfs_emit(buf, "0x%x\n", (chip->ldac_config & ADT7516_DAC_IN_VREF_MASK) >> ADT7516_DAC_IN_VREF_OFFSET); - return sprintf(buf, "%d\n", + return sysfs_emit(buf, "%d\n", !!(chip->ldac_config & ADT7316_DAC_IN_VREF)); } @@ -1128,7 +1128,7 @@ static ssize_t adt7316_show_ad(struct adt7316_chip_info *chip, data = msb << ADT7316_T_VALUE_FLOAT_OFFSET; data |= (lsb & ADT7316_LSB_VDD_MASK) >> ADT7316_LSB_VDD_OFFSET; - return sprintf(buf, "%d\n", data); + return sysfs_emit(buf, "%d\n", data); default: /* ex_temp and ain */ ret = chip->bus.read(chip->bus.client, ADT7316_LSB_EX_TEMP_AIN, &lsb); @@ -1146,7 +1146,7 @@ static ssize_t adt7316_show_ad(struct adt7316_chip_info *chip, (ADT7316_MSB_EX_TEMP - ADT7316_AD_MSB_DATA_BASE)))); if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX) - return sprintf(buf, "%d\n", data); + return sysfs_emit(buf, "%d\n", data); break; } @@ -1157,7 +1157,7 @@ static ssize_t adt7316_show_ad(struct adt7316_chip_info *chip, sign = '-'; } - return sprintf(buf, "%c%d.%.2d\n", sign, + return sysfs_emit(buf, "%c%d.%.2d\n", sign, (data >> ADT7316_T_VALUE_FLOAT_OFFSET), (data & ADT7316_T_VALUE_FLOAT_MASK) * 25); } @@ -1247,7 +1247,7 @@ static ssize_t adt7316_show_temp_offset(struct adt7316_chip_info *chip, if (val & 0x80) data -= 256; - return sprintf(buf, "%d\n", data); + return sysfs_emit(buf, "%d\n", data); } static ssize_t adt7316_store_temp_offset(struct adt7316_chip_info *chip, @@ -1415,7 +1415,7 @@ static ssize_t adt7316_show_DAC(struct adt7316_chip_info *chip, data = lsb >> ADT7316_DA_10_BIT_LSB_SHIFT; data |= msb << offset; - return sprintf(buf, "%d\n", data); + return sysfs_emit(buf, "%d\n", data); } static ssize_t adt7316_store_DAC(struct adt7316_chip_info *chip, @@ -1568,7 +1568,7 @@ static ssize_t adt7316_show_device_id(struct device *dev, if (ret) return -EIO; - return sprintf(buf, "%d\n", id); + return sysfs_emit(buf, "%d\n", id); } static IIO_DEVICE_ATTR(device_id, 0444, adt7316_show_device_id, NULL, 0); @@ -1586,7 +1586,7 @@ static ssize_t adt7316_show_manufactorer_id(struct device *dev, if (ret) return -EIO; - return sprintf(buf, "%d\n", id); + return sysfs_emit(buf, "%d\n", id); } static IIO_DEVICE_ATTR(manufactorer_id, 0444, @@ -1605,7 +1605,7 @@ static ssize_t adt7316_show_device_rev(struct device *dev, if (ret) return -EIO; - return sprintf(buf, "%d\n", rev); + return sysfs_emit(buf, "%d\n", rev); } static IIO_DEVICE_ATTR(device_rev, 0444, adt7316_show_device_rev, NULL, 0); @@ -1624,9 +1624,9 @@ static ssize_t adt7316_show_bus_type(struct device *dev, return -EIO; if (stat) - return sprintf(buf, "spi\n"); + return sysfs_emit(buf, "spi\n"); - return sprintf(buf, "i2c\n"); + return sysfs_emit(buf, "i2c\n"); } static IIO_DEVICE_ATTR(bus_type, 0444, adt7316_show_bus_type, NULL, 0); @@ -1836,7 +1836,7 @@ static ssize_t adt7316_show_int_mask(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "0x%x\n", chip->int_mask); + return sysfs_emit(buf, "0x%x\n", chip->int_mask); } /* @@ -1910,7 +1910,7 @@ static inline ssize_t adt7316_show_ad_bound(struct device *dev, data -= 256; } - return sprintf(buf, "%d\n", data); + return sysfs_emit(buf, "%d\n", data); } static inline ssize_t adt7316_set_ad_bound(struct device *dev, @@ -1961,7 +1961,7 @@ static ssize_t adt7316_show_int_enabled(struct device *dev, struct iio_dev *dev_info = dev_to_iio_dev(dev); struct adt7316_chip_info *chip = iio_priv(dev_info); - return sprintf(buf, "%d\n", !!(chip->config1 & ADT7316_INT_EN)); + return sysfs_emit(buf, "%d\n", !!(chip->config1 & ADT7316_INT_EN)); } static ssize_t adt7316_set_int_enabled(struct device *dev, From 6e38a225fc347d05156e3ae9fa0bda6355aa29c8 Mon Sep 17 00:00:00 2001 From: Amir Vajid Date: Fri, 14 Nov 2025 01:22:03 +0200 Subject: [PATCH 244/304] dt-bindings: interconnect: qcom-bwmon: Document Kaanapali BWMONs Document the Kaanapali BWMONs, which have one instance per cluster of BWMONv4. Signed-off-by: Amir Vajid Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250924-knp-bwmon-v1-1-56a9cdda7d72@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 256de140c03d..0d1a268db921 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -25,6 +25,7 @@ properties: - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: + - qcom,kaanapali-cpu-bwmon - qcom,qcm2290-cpu-bwmon - qcom,qcs615-cpu-bwmon - qcom,qcs8300-cpu-bwmon From dfb1717308ff4940b5252857f76bccbfb25ae69c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:09 +0100 Subject: [PATCH 245/304] dt-bindings: interconnect: qcom,sm6350-rpmh: Add clocks for QoS Add the clocks for some interconnects to the bindings that are required to set up the QoS correctly. Update one of the examples to aggre2_noc to have an example with clocks. Also while we're at it, remove #interconnect-cells: true as that's already provided from qcom,rpmh-common.yaml. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-1-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- .../interconnect/qcom,sm6350-rpmh.yaml | 65 +++++++++++++++---- 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml index 49eb156b08e0..2dc16e4293a9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml @@ -12,9 +12,6 @@ maintainers: description: Qualcomm RPMh-based interconnect provider on SM6350. -allOf: - - $ref: qcom,rpmh-common.yaml# - properties: compatible: enum: @@ -30,7 +27,9 @@ properties: reg: maxItems: 1 - '#interconnect-cells': true + clocks: + minItems: 1 + maxItems: 2 patternProperties: '^interconnect-[a-z0-9\-]+$': @@ -46,8 +45,6 @@ patternProperties: - qcom,sm6350-clk-virt - qcom,sm6350-compute-noc - '#interconnect-cells': true - required: - compatible @@ -57,10 +54,54 @@ required: - compatible - reg +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre1-noc + - qcom,sm6350-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false examples: - | + #include + #include + config_noc: interconnect@1500000 { compatible = "qcom,sm6350-config-noc"; reg = <0x01500000 0x28000>; @@ -68,14 +109,16 @@ examples: qcom,bcm-voters = <&apps_bcm_voter>; }; - system_noc: interconnect@1620000 { - compatible = "qcom,sm6350-system-noc"; - reg = <0x01620000 0x17080>; + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm6350-aggre2-noc"; + reg = <0x01700000 0x1f880>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; - clk_virt: interconnect-clk-virt { - compatible = "qcom,sm6350-clk-virt"; + compute_noc: interconnect-compute-noc { + compatible = "qcom,sm6350-compute-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; From b56fb8aa66fc18cf4d44a95c4edb97ffcc3d63ef Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:10 +0100 Subject: [PATCH 246/304] interconnect: qcom: icc-rpmh: Get parent's regmap for nested NoCs Since commit 57eb14779dfd ("interconnect: qcom: icc-rpmh: Support child NoC device probe") the icc-rpmh driver supports initializing child NoCs, but those child NoCs also need to be able to get the parent's regmap in order to enable QoS. Change the driver to support that and support programming QoS register. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-2-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpmh.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index f90c29111f48..3b445acefece 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -308,14 +308,19 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) - goto skip_qos_config; + /* Try parent's regmap first */ + qp->regmap = dev_get_regmap(dev->parent, NULL); + if (!qp->regmap) { + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + goto skip_qos_config; - qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); - if (IS_ERR(qp->regmap)) { - dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap)); - goto skip_qos_config; + qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); + if (IS_ERR(qp->regmap)) { + dev_info(dev, "Skipping QoS, regmap failed; %ld\n", + PTR_ERR(qp->regmap)); + goto skip_qos_config; + } } qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks); From ccd789e53a5c72bb90be85a5b2ebfbb26b9c03ea Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:11 +0100 Subject: [PATCH 247/304] interconnect: qcom: sm6350: Remove empty BCM arrays Clean up the code by removing empty BCM arrays to save some lines. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-3-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm6350.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 99c435a5968f..246549cb761e 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1526,9 +1526,6 @@ static const struct qcom_icc_desc sm6350_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm * const dc_noc_bcms[] = { -}; - static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, @@ -1538,8 +1535,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { static const struct qcom_icc_desc sm6350_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), - .bcms = dc_noc_bcms, - .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; static struct qcom_icc_bcm * const gem_noc_bcms[] = { @@ -1600,9 +1595,6 @@ static const struct qcom_icc_desc sm6350_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm * const npu_noc_bcms[] = { -}; - static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, @@ -1620,8 +1612,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { static const struct qcom_icc_desc sm6350_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), - .bcms = npu_noc_bcms, - .num_bcms = ARRAY_SIZE(npu_noc_bcms), }; static struct qcom_icc_bcm * const system_noc_bcms[] = { From ee7184813059388c86d73819d9c1c166aa3aab21 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:12 +0100 Subject: [PATCH 248/304] interconnect: qcom: sm6350: enable QoS configuration Enable QoS configuration for master ports with predefined values for priority and urgency forwarding. While this does require some "clocks" to be specified in devicetree to work correctly, thanks to ".qos_requires_clocks = true," this is backwards compatible with old DT as QoS programming will be skipped for aggre1_noc and aggre2_noc when clocks are not provided. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-4-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm6350.c | 288 +++++++++++++++++++++++++++++ 1 file changed, 288 insertions(+) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 246549cb761e..d96bec1cbb26 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -150,26 +150,50 @@ static struct qcom_icc_node qhm_a1noc_cfg = { .link_nodes = { &srvc_aggre1_noc }, }; +static struct qcom_icc_qosbox qhm_qup_0_qos = { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qup_0 = { .name = "qhm_qup_0", .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup_0_qos, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; +static struct qcom_icc_qosbox xm_emmc_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", .channels = 1, .buswidth = 8, + .qosbox = &xm_emmc_qos, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .num_ports = 1, + .port_offsets = { 0x8000 }, + .prio = 4, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .channels = 1, .buswidth = 8, + .qosbox = &xm_ufs_mem_qos, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -182,58 +206,113 @@ static struct qcom_icc_node qhm_a2noc_cfg = { .link_nodes = { &srvc_aggre2_noc }, }; +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .channels = 1, .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qhm_qup_1_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 2, + .urg_fwd = 0, +}; static struct qcom_icc_node qhm_qup_1 = { .name = "qhm_qup_1", .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup_1_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x6000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .channels = 1, .buswidth = 8, + .qosbox = &qxm_crypto_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qxm_ipa_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .channels = 1, .buswidth = 8, + .qosbox = &qxm_ipa_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox xm_qdss_etr_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", .channels = 1, .buswidth = 8, + .qosbox = &xm_qdss_etr_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox xm_sdc2_qos = { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc2_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .channels = 1, .buswidth = 8, + .qosbox = &xm_usb3_0_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -278,18 +357,34 @@ static struct qcom_icc_node qup1_core_master = { .link_nodes = { &qup1_core_slave }, }; +static struct qcom_icc_qosbox qnm_npu_qos = { + .num_ports = 2, + .port_offsets = { 0xf000, 0x11000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", .channels = 2, .buswidth = 32, + .qosbox = &qnm_npu_qos, .num_links = 1, .link_nodes = { &qns_cdsp_gemnoc }, }; +static struct qcom_icc_qosbox qxm_npu_dsp_qos = { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_npu_dsp = { .name = "qxm_npu_dsp", .channels = 1, .buswidth = 8, + .qosbox = &qxm_npu_dsp_qos, .num_links = 1, .link_nodes = { &qns_cdsp_gemnoc }, }; @@ -401,19 +496,35 @@ static struct qcom_icc_node qhm_cnoc_dc_noc = { &qhs_gemnoc }, }; +static struct qcom_icc_qosbox acm_apps_qos = { + .num_ports = 2, + .port_offsets = { 0x2f100, 0x2f000 }, + .prio = 0, + .urg_fwd = 0, +}; + static struct qcom_icc_node acm_apps = { .name = "acm_apps", .channels = 1, .buswidth = 16, + .qosbox = &acm_apps_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox acm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 6, + .urg_fwd = 0, +}; + static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", .channels = 1, .buswidth = 8, + .qosbox = &acm_sys_tcu_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, @@ -429,53 +540,101 @@ static struct qcom_icc_node qhm_gemnoc_cfg = { &qhs_mdsp_ms_mpu_cfg }, }; +static struct qcom_icc_qosbox qnm_cmpnoc_qos = { + .num_ports = 1, + .port_offsets = { 0x2e000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", .channels = 1, .buswidth = 32, + .qosbox = &qnm_cmpnoc_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 1, + .port_offsets = { 0x30000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x34000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .num_ports = 1, + .port_offsets = { 0x32000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .channels = 1, .buswidth = 8, + .qosbox = &qnm_snoc_gc_qos, .num_links = 1, .link_nodes = { &qns_llcc }, }; +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x31000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .channels = 1, .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, .num_links = 1, .link_nodes = { &qns_llcc }, }; +static struct qcom_icc_qosbox qxm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0x33000, 0x33080 }, + .prio = 0, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", .channels = 2, .buswidth = 32, + .qosbox = &qxm_gpu_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, @@ -497,50 +656,98 @@ static struct qcom_icc_node qhm_mnoc_cfg = { .link_nodes = { &srvc_mnoc }, }; +static struct qcom_icc_qosbox qnm_video0_qos = { + .num_ports = 1, + .port_offsets = { 0xf000 }, + .prio = 2, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", .channels = 1, .buswidth = 32, + .qosbox = &qnm_video0_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qnm_video_cvp_qos = { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 5, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", .channels = 1, .buswidth = 8, + .qosbox = &qnm_video_cvp_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qxm_camnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0xa000, 0xb000 }, + .prio = 3, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", .channels = 2, .buswidth = 32, + .qosbox = &qxm_camnoc_hf_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; +static struct qcom_icc_qosbox qxm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 5, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", .channels = 1, .buswidth = 8, + .qosbox = &qxm_camnoc_icp_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 3, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", .channels = 1, .buswidth = 32, + .qosbox = &qxm_camnoc_sf_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qxm_mdp0_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 3, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", .channels = 1, .buswidth = 32, + .qosbox = &qxm_mdp0_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; @@ -616,19 +823,35 @@ static struct qcom_icc_node qnm_gemnoc = { &xs_qdss_stm }, }; +static struct qcom_icc_qosbox qxm_pimem_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", .channels = 1, .buswidth = 8, + .qosbox = &qxm_pimem_qos, .num_links = 2, .link_nodes = { &qns_gemnoc_gc, &qxs_imem }, }; +static struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 3, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_gic = { .name = "xm_gic", .channels = 1, .buswidth = 8, + .qosbox = &xm_gic_qos, .num_links = 1, .link_nodes = { &qns_gemnoc_gc }, }; @@ -1388,11 +1611,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; +static const struct regmap_config sm6350_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15080, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_aggre1_noc = { + .config = &sm6350_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1413,11 +1646,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; +static const struct regmap_config sm6350_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f880, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_aggre2_noc = { + .config = &sm6350_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1459,7 +1702,16 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, }; +static const struct regmap_config sm6350_compute_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f880, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_compute_noc = { + .config = &sm6350_compute_noc_regmap_config, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1532,7 +1784,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { [SLAVE_LLCC_CFG] = &qhs_llcc, }; +static const struct regmap_config sm6350_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3200, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_dc_noc = { + .config = &sm6350_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1561,7 +1822,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; +static const struct regmap_config sm6350_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3e200, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_gem_noc = { + .config = &sm6350_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1588,7 +1858,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; +static const struct regmap_config sm6350_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c100, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_mmss_noc = { + .config = &sm6350_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1643,7 +1922,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config sm6350_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17080, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_system_noc = { + .config = &sm6350_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, From ac35e04f8000aaaf98635792464647e7a6f3422e Mon Sep 17 00:00:00 2001 From: Slark Xiao Date: Wed, 19 Nov 2025 18:56:14 +0800 Subject: [PATCH 249/304] bus: mhi: host: pci_generic: Add Foxconn T99W760 modem T99W760 modem is based on Qualcomm SDX35 chipset. It uses the same channel configurations of Foxconn SDX61 modem. Hence, add support for it by reusing the 'modem_foxconn_sdx61_config' config structure. The EDL firmware for this modem has been pushed to linux-firmware. Signed-off-by: Slark Xiao [mani: reworded description] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119105615.48295-2-slark_xiao@163.com --- drivers/bus/mhi/host/pci_generic.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 3d8c9729fcfc..e3bc737313a2 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -663,6 +663,17 @@ static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = { .sideband_wake = false, }; +static const struct mhi_pci_dev_info mhi_foxconn_t99w760_info = { + .name = "foxconn-t99w760", + .edl = "qcom/sdx35/foxconn/xbl_s_devprg_ns.melf", + .edl_trigger = true, + .config = &modem_foxconn_sdx61_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .mru_default = 32768, + .sideband_wake = false, +}; + static const struct mhi_channel_config mhi_mv3x_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), @@ -1010,6 +1021,8 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* DW5934e(sdx72), Non-eSIM */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe123), + .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w760_info }, /* MV31-W (Cinterion) */ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), .driver_data = (kernel_ulong_t) &mhi_mv31_info }, From 36b1cb4f33e77eae456e33c72534b9c7917c4a07 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 14 Nov 2025 12:58:14 -0600 Subject: [PATCH 250/304] firmware: stratix-svc: fix make htmldocs warning Stephen Rothwell reports htmldocs warnings when merging char-misc tree: WARNING: drivers/firmware/stratix10-svc.c:58 This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Total number of transaction IDs, which is a combination of WARNING: drivers/firmware/stratix10-svc.c:302 This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * svc_mem_lock protects access to the svc_data_mem list for Fixes: bcb9f4f07061 ("firmware: stratix10-svc: Add support for async communication") Reported-by: Stephen Rothwell Closes: https://lore.kernel.org/linux-next/20251114153347.16001109@canb.auug.org.au/ Signed-off-by: Dinh Nguyen Link: https://patch.msgid.link/20251114185815.358423-2-dinguyen@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/stratix10-svc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 3acfa067c5dd..08ed1b40bcfc 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -55,7 +55,7 @@ #define MAX_SDM_JOB_IDS 16 /* Number of bits used for asynchronous transaction hashing. */ #define ASYNC_TRX_HASH_BITS 3 -/** +/* * Total number of transaction IDs, which is a combination of * client ID and job ID. */ @@ -297,7 +297,7 @@ struct stratix10_svc_chan { static LIST_HEAD(svc_ctrl); static LIST_HEAD(svc_data_mem); -/** +/* * svc_mem_lock protects access to the svc_data_mem list for * concurrent multi-client operations */ From 935419b9fb74ab2643583fce750cb774c9b5faa6 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 14 Nov 2025 12:58:15 -0600 Subject: [PATCH 251/304] firmware: stratix10-svc: fix make htmldocs warning Stephen Rothwell reports htmldocs warnings when merging char-misc tree: WARNING: include/linux/firmware/intel/stratix10-svc-client.h:22 This comment starts with '/**', but isn't a kernel-doc comment. WARNING: include/linux/firmware/intel/stratix10-svc-client.h:184 Enum value 'COMMAND_HWMON_READTEMP' not described in enum 'stratix10_svc_command_code' WARNING: include/linux/firmware/intel/stratix10-svc-client.h:184 Enum value 'COMMAND_HWMON_READVOLT' not described in enum 'stratix10_svc_command_code' WARNING: include/linux/firmware/intel/stratix10-svc-client.h:307 function parameter 'cb_arg' not described in 'async_callback_t' Fixes: 4f49088c1625 ("firmware: stratix10-svc: Add definition for voltage and temperature sensor") Reported-by: Stephen Rothwell Closes: https://lore.kernel.org/linux-next/20251114153920.1c5df700@canb.auug.org.au/ Signed-off-by: Dinh Nguyen Link: https://patch.msgid.link/20251114185815.358423-3-dinguyen@kernel.org Signed-off-by: Greg Kroah-Hartman --- include/linux/firmware/intel/stratix10-svc-client.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 1bcc56d14080..d290060f4c73 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -19,7 +19,7 @@ #define SVC_CLIENT_FCS "fcs" #define SVC_CLIENT_HWMON "hwmon" -/** +/* * Status of the sent command, in bit number * * SVC_STATUS_OK: @@ -148,6 +148,12 @@ struct stratix10_svc_chan; * * @COMMAND_FCS_RANDOM_NUMBER_GEN: generate a random number, return status * is SVC_STATUS_OK, SVC_STATUS_ERROR + * + * @COMMAND_HWMON_READTEMP: query the temperature from the hardware monitor, + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR + * + * @COMMAND_HWMON_READVOLT: query the voltage from the hardware monitor, + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR */ enum stratix10_svc_command_code { /* for FPGA */ @@ -303,7 +309,7 @@ void stratix10_svc_done(struct stratix10_svc_chan *chan); * The callback function takes a single argument, which is a pointer to * user-defined data. * - * @param cb_arg A pointer to user-defined data passed to the callback function. + * @cb_arg: Argument to be passed to the callback function. */ typedef void (*async_callback_t)(void *cb_arg); From 377441d53a2df61b105e823b335010cd4f1a6e56 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 14 Nov 2025 12:58:13 -0600 Subject: [PATCH 252/304] firmware: stratix10-svc: fix make htmldocs warning for stratix10_svc Fix this warning that was generated from "make htmldocs": WARNING: drivers/firmware/stratix10-svc.c:58 struct member 'intel_svc_fcs' not described in 'stratix10_svc' Fixes: e6281c26674e ("firmware: stratix10-svc: Add support for FCS") Reported-by: Stephen Rothwell Closes: https://lore.kernel.org/linux-next/20251106145941.37920e97@canb.auug.org.au/ Signed-off-by: Dinh Nguyen Link: https://patch.msgid.link/20251114185815.358423-1-dinguyen@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/stratix10-svc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 08ed1b40bcfc..e909ec6f8d45 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -105,6 +105,7 @@ struct stratix10_svc_chan; /** * struct stratix10_svc - svc private data * @stratix10_svc_rsu: pointer to stratix10 RSU device + * @intel_svc_fcs: pointer to the FCS device */ struct stratix10_svc { struct platform_device *stratix10_svc_rsu; From e7ac47e20fd5dfaa3bf13029266c1af0316a4f6b Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Fri, 14 Nov 2025 11:06:29 +0000 Subject: [PATCH 253/304] dt-bindings: nvmem: qfprom: Add sa8775p compatible Document compatible string for the QFPROM on Lemans platform. Acked-by: Krzysztof Kozlowski Acked-by: Srinivas Kandagatla Signed-off-by: Akhil P Oommen Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 3f6dc6a3a9f1..7d1612acca48 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -39,6 +39,7 @@ properties: - qcom,qcs404-qfprom - qcom,qcs615-qfprom - qcom,qcs8300-qfprom + - qcom,sa8775p-qfprom - qcom,sar2130p-qfprom - qcom,sc7180-qfprom - qcom,sc7280-qfprom From 47b7ea6528d51acc5e39dede6d28dac7fa38ea47 Mon Sep 17 00:00:00 2001 From: Jack Hsu Date: Fri, 14 Nov 2025 11:06:30 +0000 Subject: [PATCH 254/304] dt-bindings: nvmem: Support MediaTek MT8189 evb board efuse add compatible string for mt8189 evb board dts node of efuse Signed-off-by: Jack Hsu Acked-by: Conor Dooley Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-3-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 4dc0d42df3e6..9d52caaf3e5c 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -48,6 +48,7 @@ properties: - mediatek,mt7988-efuse - mediatek,mt8173-efuse - mediatek,mt8183-efuse + - mediatek,mt8189-efuse - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse From 2f9fae509895fc8198f521f4ace1fb4dda42c9a6 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Nov 2025 11:06:31 +0000 Subject: [PATCH 255/304] nvmem: Add driver for the eeprom in qnap-mcu controllers The qnap-mcu also has an eeprom connected to it, that contains some specific product-information like the mac addresses for the network interfaces. Add a nvmem driver for it. Signed-off-by: Heiko Stuebner Acked-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-4-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/Kconfig | 9 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/qnap-mcu-eeprom.c | 111 ++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 drivers/nvmem/qnap-mcu-eeprom.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index e0d88d3199c1..bf47a982cf62 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -285,6 +285,15 @@ config NVMEM_QCOM_SEC_QFPROM This driver can also be built as a module. If so, the module will be called nvmem_sec_qfprom. +config NVMEM_QNAP_MCU_EEPROM + tristate "QNAP MCU EEPROM Support" + depends on MFD_QNAP_MCU + help + Say y here to enable support for accessing the EEPROM attached to + QNAP MCU devices. This EEPROM contains additional runtime device + information, like MAC addresses for ethernet devices that do not + contain their own mac storage. + config NVMEM_RAVE_SP_EEPROM tristate "Rave SP EEPROM Support" depends on RAVE_SP_CORE diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 70a4464dcb1e..7252b8ec88d4 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -56,6 +56,8 @@ obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o nvmem_qfprom-y := qfprom.o obj-$(CONFIG_NVMEM_QCOM_SEC_QFPROM) += nvmem_sec_qfprom.o nvmem_sec_qfprom-y := sec-qfprom.o +obj-$(CONFIG_NVMEM_QNAP_MCU_EEPROM) += nvmem-qnap-mcu-eeprom.o +nvmem-qnap-mcu-eeprom-y := qnap-mcu-eeprom.o obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o obj-$(CONFIG_NVMEM_RCAR_EFUSE) += nvmem-rcar-efuse.o diff --git a/drivers/nvmem/qnap-mcu-eeprom.c b/drivers/nvmem/qnap-mcu-eeprom.c new file mode 100644 index 000000000000..0b919895b3b2 --- /dev/null +++ b/drivers/nvmem/qnap-mcu-eeprom.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ee1004 - driver for DDR4 SPD EEPROMs + * + * Copyright (C) 2017-2019 Jean Delvare + * + * Based on the at24 driver: + * Copyright (C) 2005-2007 David Brownell + * Copyright (C) 2008 Wolfram Sang, Pengutronix + */ + +#include +#include +#include +#include +#include + +/* Determined by trial and error until read anomalies appeared */ +#define QNAP_MCU_EEPROM_SIZE 256 +#define QNAP_MCU_EEPROM_BLOCK_SIZE 32 + +static int qnap_mcu_eeprom_read_block(struct qnap_mcu *mcu, unsigned int offset, + void *val, size_t bytes) +{ + const u8 cmd[] = { 0xf7, 0xa1, offset, bytes }; + u8 *reply; + int ret = 0; + + reply = kzalloc(bytes + sizeof(cmd), GFP_KERNEL); + if (!reply) + return -ENOMEM; + + ret = qnap_mcu_exec(mcu, cmd, sizeof(cmd), reply, bytes + sizeof(cmd)); + if (ret) + goto out; + + /* First bytes must mirror the sent command */ + if (memcmp(cmd, reply, sizeof(cmd))) { + ret = -EIO; + goto out; + } + + memcpy(val, reply + sizeof(cmd), bytes); + +out: + kfree(reply); + return ret; +} + +static int qnap_mcu_eeprom_read(void *priv, unsigned int offset, void *val, size_t bytes) +{ + struct qnap_mcu *mcu = priv; + int pos = 0, ret; + u8 *buf = val; + + if (unlikely(!bytes)) + return 0; + + while (bytes > 0) { + size_t to_read = (bytes > QNAP_MCU_EEPROM_BLOCK_SIZE) ? + QNAP_MCU_EEPROM_BLOCK_SIZE : bytes; + + ret = qnap_mcu_eeprom_read_block(mcu, offset + pos, &buf[pos], to_read); + if (ret < 0) + return ret; + + pos += to_read; + bytes -= to_read; + } + + return 0; +} + +static int qnap_mcu_eeprom_probe(struct platform_device *pdev) +{ + struct qnap_mcu *mcu = dev_get_drvdata(pdev->dev.parent); + struct nvmem_config nvcfg = {}; + struct nvmem_device *ndev; + + nvcfg.dev = &pdev->dev; + nvcfg.of_node = pdev->dev.parent->of_node; + nvcfg.name = dev_name(&pdev->dev); + nvcfg.id = NVMEM_DEVID_NONE; + nvcfg.owner = THIS_MODULE; + nvcfg.type = NVMEM_TYPE_EEPROM; + nvcfg.read_only = true; + nvcfg.root_only = false; + nvcfg.reg_read = qnap_mcu_eeprom_read; + nvcfg.size = QNAP_MCU_EEPROM_SIZE, + nvcfg.word_size = 1, + nvcfg.stride = 1, + nvcfg.priv = mcu, + + ndev = devm_nvmem_register(&pdev->dev, &nvcfg); + if (IS_ERR(ndev)) + return PTR_ERR(ndev); + + return 0; +} + +static struct platform_driver qnap_mcu_eeprom_driver = { + .probe = qnap_mcu_eeprom_probe, + .driver = { + .name = "qnap-mcu-eeprom", + }, +}; +module_platform_driver(qnap_mcu_eeprom_driver); + +MODULE_AUTHOR("Heiko Stuebner "); +MODULE_DESCRIPTION("QNAP MCU EEPROM driver"); +MODULE_LICENSE("GPL"); From 5b2f8c133d987ddc4a0e0ba7c58afb587ffeb96f Mon Sep 17 00:00:00 2001 From: Jascha Sundaresan Date: Fri, 14 Nov 2025 11:06:32 +0000 Subject: [PATCH 256/304] nvmem: layouts: u-boot-env: add optional "env-size" property Some devices reserve a larger NVMEM region for the U-Boot environment than the actual environment data length used by U-Boot itself. The CRC32 in the U-Boot header is calculated over the smaller data length, causing CRC validation to fail when Linux reads the full partition. Allow an optional device tree property "env-size" to specify the environment data size to use for CRC computation. v2: add missing $ref line to DT binding Signed-off-by: Jascha Sundaresan Reviewed-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-5-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/layouts/u-boot,env.yaml | 7 +++++++ drivers/nvmem/layouts/u-boot-env.c | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml b/Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml index 56a8f55d4a09..e9e75c38bd11 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml @@ -46,6 +46,12 @@ properties: type: object description: Command to use for automatic booting + env-size: + description: + Size in bytes of the environment data used by U-Boot for CRC + calculation. If omitted, the full NVMEM region size is used. + $ref: /schemas/types.yaml#/definitions/uint32 + ethaddr: type: object description: Ethernet interfaces base MAC address. @@ -104,6 +110,7 @@ examples: partition-u-boot-env { compatible = "brcm,env"; + env-size = <0x20000>; ethaddr { }; diff --git a/drivers/nvmem/layouts/u-boot-env.c b/drivers/nvmem/layouts/u-boot-env.c index a27eeb08146f..ab32bf1291af 100644 --- a/drivers/nvmem/layouts/u-boot-env.c +++ b/drivers/nvmem/layouts/u-boot-env.c @@ -99,10 +99,12 @@ int u_boot_env_parse(struct device *dev, struct nvmem_device *nvmem, uint32_t crc32; uint32_t calc; uint8_t *buf; + u32 env_size; int bytes; int err; - dev_size = nvmem_dev_size(nvmem); + dev_size = device_property_read_u32(dev, "env-size", &env_size) ? + nvmem_dev_size(nvmem) : (size_t)env_size; buf = kzalloc(dev_size, GFP_KERNEL); if (!buf) { From 7dc63a2a8d965d4adb2e31fc30944474a069cf96 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Fri, 14 Nov 2025 11:06:33 +0000 Subject: [PATCH 257/304] dt-bindings: nvmem: mediatek: efuse: Add compatible for MT8189 SoC Add compatible string for the eFuse layout on MT8189 SoC, that is compatible with MT8186. Signed-off-by: Louis-Alexis Eyraud Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-6-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 9d52caaf3e5c..c9bf34ee0efb 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -25,7 +25,9 @@ properties: compatible: oneOf: - items: - - const: mediatek,mt8188-efuse + - enum: + - mediatek,mt8188-efuse + - mediatek,mt8189-efuse - const: mediatek,mt8186-efuse - const: mediatek,mt8186-efuse From ee5c565163fddc570b52c8ee8b4683046e5295f0 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 14 Nov 2025 11:06:34 +0000 Subject: [PATCH 258/304] dt-bindings: nvmem: don't check node names Node names are already and properly checked by the core schema. No need to do it again. Signed-off-by: Wolfram Sang Acked-by: Conor Dooley Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-7-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml index 3b2aa605a551..ab4cdc4e3614 100644 --- a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml @@ -31,7 +31,7 @@ properties: maxItems: 1 patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": type: object $ref: layouts/fixed-cell.yaml unevaluatedProperties: false From c7ea8eadd5d35311a2529f9f15095ac37dd9e2e3 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Fri, 14 Nov 2025 11:06:35 +0000 Subject: [PATCH 259/304] dt-bindings: nvmem: imx-ocotp: Add support for i.MX94 Add the compatible string "fsl,imx94-ocotp" to the imx-ocotp device tree binding documentation to support the i.MX94. Signed-off-by: Alice Guo Acked-by: Conor Dooley Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-8-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml index b2cb76cf9053..a8076d0e2737 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml @@ -14,7 +14,8 @@ maintainers: description: | This binding represents the on-chip eFuse OTP controller found on i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, - i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP and i.MX93/5 SoCs. + i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP, i.MX93, i.MX94, + and i.MX95. allOf: - $ref: nvmem.yaml# @@ -36,6 +37,7 @@ properties: - fsl,imx8mq-ocotp - fsl,imx8mm-ocotp - fsl,imx93-ocotp + - fsl,imx94-ocotp - fsl,imx95-ocotp - const: syscon - items: From d54d5e294c9febba9389b03a12fbae2fab9c8f6b Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Fri, 14 Nov 2025 11:06:36 +0000 Subject: [PATCH 260/304] nvmem: imx-ocotp-ele: Add i.MX94 OCOTP support Add OCOTP device type for i.MX94, including register offset, total size, and fuse layout. This enables NVMEM access to the eFuse of i.MX94. Signed-off-by: Alice Guo Reviewed-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110636.143268-9-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/imx-ocotp-ele.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/nvmem/imx-ocotp-ele.c b/drivers/nvmem/imx-ocotp-ele.c index 7807ec0e2d18..7cf7e809a8f5 100644 --- a/drivers/nvmem/imx-ocotp-ele.c +++ b/drivers/nvmem/imx-ocotp-ele.c @@ -186,6 +186,25 @@ static const struct ocotp_devtype_data imx93_ocotp_data = { }, }; +static const struct ocotp_devtype_data imx94_ocotp_data = { + .reg_off = 0x8000, + .reg_read = imx_ocotp_reg_read, + .size = 3296, /* 103 Banks */ + .num_entry = 10, + .entry = { + { 0, 1, FUSE_FSB | FUSE_ECC }, + { 7, 1, FUSE_FSB | FUSE_ECC }, + { 9, 3, FUSE_FSB | FUSE_ECC }, + { 12, 24, FUSE_FSB }, + { 36, 2, FUSE_FSB | FUSE_ECC }, + { 38, 14, FUSE_FSB }, + { 59, 1, FUSE_ELE }, + { 525, 2, FUSE_FSB | FUSE_ECC }, + { 528, 7, FUSE_FSB }, + { 536, 280, FUSE_FSB }, + }, +}; + static const struct ocotp_devtype_data imx95_ocotp_data = { .reg_off = 0x8000, .reg_read = imx_ocotp_reg_read, @@ -209,6 +228,7 @@ static const struct ocotp_devtype_data imx95_ocotp_data = { static const struct of_device_id imx_ele_ocotp_dt_ids[] = { { .compatible = "fsl,imx93-ocotp", .data = &imx93_ocotp_data, }, + { .compatible = "fsl,imx94-ocotp", .data = &imx94_ocotp_data, }, { .compatible = "fsl,imx95-ocotp", .data = &imx95_ocotp_data, }, {}, }; From a1fb84ab7b92e8e9df448a79e8c02b57c98b5141 Mon Sep 17 00:00:00 2001 From: Carlos Llamas Date: Fri, 24 Oct 2025 16:15:02 +0000 Subject: [PATCH 261/304] binder: mark binder_alloc_exhaustive_test as slow The binder_alloc_exhaustive_test kunit test takes over 30s to complete and the kunit framework reports: # binder_alloc_exhaustive_test: Test should be marked slow (runtime: 33.842881934s) Mark the test as suggested to silence the warning. Cc: Tiffany Yang Signed-off-by: Carlos Llamas Reviewed-by: Tiffany Yang Reviewed-by: Alice Ryhl Link: https://patch.msgid.link/20251024161525.1732874-1-cmllamas@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/tests/binder_alloc_kunit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/android/tests/binder_alloc_kunit.c b/drivers/android/tests/binder_alloc_kunit.c index 9b884d977f76..7f9cc003bbe3 100644 --- a/drivers/android/tests/binder_alloc_kunit.c +++ b/drivers/android/tests/binder_alloc_kunit.c @@ -554,7 +554,7 @@ static void binder_alloc_test_exit(struct kunit *test) static struct kunit_case binder_alloc_test_cases[] = { KUNIT_CASE(binder_alloc_test_init_freelist), KUNIT_CASE(binder_alloc_test_mmap), - KUNIT_CASE(binder_alloc_exhaustive_test), + KUNIT_CASE_SLOW(binder_alloc_exhaustive_test), {} }; From d4b83ba11cf227705986265fab0744060c02608b Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Fri, 31 Oct 2025 08:48:18 +0000 Subject: [PATCH 262/304] rust_binder: use compat_ptr_ioctl Binder always treats the ioctl argument as a pointer. In this scenario, the idiomatic way to implement compat_ioctl is to use compat_ptr_ioctl. Thus update Rust Binder to do that. Signed-off-by: Alice Ryhl Acked-by: Carlos Llamas Link: https://patch.msgid.link/20251031-binder-compatptrioctl-v2-1-3d05b5cc058e@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder/process.rs | 9 --------- drivers/android/binder/rust_binder_main.rs | 22 +++------------------- 2 files changed, 3 insertions(+), 28 deletions(-) diff --git a/drivers/android/binder/process.rs b/drivers/android/binder/process.rs index 7607353a5e92..27323070f30f 100644 --- a/drivers/android/binder/process.rs +++ b/drivers/android/binder/process.rs @@ -1623,15 +1623,6 @@ impl Process { } } - pub(crate) fn compat_ioctl( - this: ArcBorrow<'_, Process>, - file: &File, - cmd: u32, - arg: usize, - ) -> Result { - Self::ioctl(this, file, cmd, arg) - } - pub(crate) fn mmap( this: ArcBorrow<'_, Process>, _file: &File, diff --git a/drivers/android/binder/rust_binder_main.rs b/drivers/android/binder/rust_binder_main.rs index 6773b7c273ec..c79a9e742240 100644 --- a/drivers/android/binder/rust_binder_main.rs +++ b/drivers/android/binder/rust_binder_main.rs @@ -313,8 +313,8 @@ pub static rust_binder_fops: AssertSync = { let ops = kernel::bindings::file_operations { owner: THIS_MODULE.as_ptr(), poll: Some(rust_binder_poll), - unlocked_ioctl: Some(rust_binder_unlocked_ioctl), - compat_ioctl: Some(rust_binder_compat_ioctl), + unlocked_ioctl: Some(rust_binder_ioctl), + compat_ioctl: Some(bindings::compat_ptr_ioctl), mmap: Some(rust_binder_mmap), open: Some(rust_binder_open), release: Some(rust_binder_release), @@ -402,23 +402,7 @@ unsafe extern "C" fn rust_binder_release( /// # Safety /// Only called by binderfs. -unsafe extern "C" fn rust_binder_compat_ioctl( - file: *mut bindings::file, - cmd: kernel::ffi::c_uint, - arg: kernel::ffi::c_ulong, -) -> kernel::ffi::c_long { - // SAFETY: We previously set `private_data` in `rust_binder_open`. - let f = unsafe { Arc::::borrow((*file).private_data) }; - // SAFETY: The caller ensures that the file is valid. - match Process::compat_ioctl(f, unsafe { File::from_raw_file(file) }, cmd as _, arg as _) { - Ok(()) => 0, - Err(err) => err.to_errno() as isize, - } -} - -/// # Safety -/// Only called by binderfs. -unsafe extern "C" fn rust_binder_unlocked_ioctl( +unsafe extern "C" fn rust_binder_ioctl( file: *mut bindings::file, cmd: kernel::ffi::c_uint, arg: kernel::ffi::c_ulong, From c1437332e4d351e86049c275d879110f4dabe7b7 Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Wed, 29 Oct 2025 11:50:58 +0000 Subject: [PATCH 263/304] rust_binder: move BC_FREE_BUFFER drop inside if statement When looking at flamegraphs, there is a pretty large entry for the function call drop_in_place::> which in turn calls drop_in_place::. Combined with the looper_need_return condition, this means that the generated code looks like this: if let Some(buffer) = buffer { if buffer.looper_need_return_on_free() { self.inner.lock().looper_need_return = true; } } drop_in_place::>() { // not inlined if let Some(buffer) = buffer { drop_in_place::(buffer); } } This kind of situation where you check X and then check X again is normally optimized into a single condition, but in this case due to the non-inlined function call to drop_in_place::>, that optimization does not happen. Furthermore, the drop_in_place:: call is only two-thirds of the drop_in_place::> call in the flamegraph. This indicates that this double condition is not performing well. Also, last time I looked at Binder perf, I remember finding that the destructor of Allocation was involved with many branch mispredictions. Thus, change this code to look like this: if let Some(buffer) = buffer { if buffer.looper_need_return_on_free() { self.inner.lock().looper_need_return = true; } drop_in_place::(buffer); } by dropping the Allocation directly. Flamegraphs confirm that the drop_in_place::> call disappears from this change. Signed-off-by: Alice Ryhl Acked-by: Carlos Llamas Link: https://patch.msgid.link/20251029-binder-bcfreebuf-option-v1-1-4d282be0439f@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder/thread.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/android/binder/thread.rs b/drivers/android/binder/thread.rs index 7e34ccd394f8..1a8e6fdc0dc4 100644 --- a/drivers/android/binder/thread.rs +++ b/drivers/android/binder/thread.rs @@ -1323,12 +1323,12 @@ impl Thread { } BC_FREE_BUFFER => { let buffer = self.process.buffer_get(reader.read()?); - if let Some(buffer) = &buffer { + if let Some(buffer) = buffer { if buffer.looper_need_return_on_free() { self.inner.lock().looper_need_return = true; } + drop(buffer); } - drop(buffer); } BC_INCREFS => { self.process From c938fdd82fac65dfb64cf92e3825f125af7ab315 Mon Sep 17 00:00:00 2001 From: Carlos Llamas Date: Fri, 7 Nov 2025 22:48:22 +0000 Subject: [PATCH 264/304] MAINTAINERS: add Alice as a Binder maintainer Alice has been reviewing binder patches for years now and has a strong understanding of the driver, so this patch is well overdue. While here also clean up the list from folks who haven't been active for a while. Signed-off-by: Carlos Llamas Acked-by: Joel Fernandes Acked-by: Alice Ryhl Link: https://patch.msgid.link/20251107224824.644832-1-cmllamas@google.com Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index f909772e6315..194ee22e2026 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1819,11 +1819,9 @@ ANDROID DRIVERS M: Greg Kroah-Hartman M: Arve Hjønnevåg M: Todd Kjos -M: Martijn Coenen -M: Joel Fernandes M: Christian Brauner M: Carlos Llamas -M: Suren Baghdasaryan +M: Alice Ryhl L: linux-kernel@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git From 77198581e0d05aae08a06f471e21a19ab0edaea2 Mon Sep 17 00:00:00 2001 From: Sunday Adelodun Date: Fri, 21 Nov 2025 12:12:02 +0100 Subject: [PATCH 265/304] android: binderfs: add missing parameters in binder_ctl_ioctl()'s doc The kernel-doc comment for binder_ctl_ioctl() lacks descriptions for the @file, @cmd, and @arg parameters, which triggers warnings during documentation builds. Add the missing parameter descriptions to keep the kernel-doc consistent and free of warnings. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202511201725.ni2HZ2PP-lkp@intel.com/ Signed-off-by: Sunday Adelodun Link: https://patch.msgid.link/20251121111203.21800-1-adelodunolaoluwa@yahoo.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/binderfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index be8e64eb39ec..47f6d1e5971e 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -224,6 +224,9 @@ err: /** * binder_ctl_ioctl - handle binder device node allocation requests + * @file: The file pointer for the binder-control device node. + * @cmd: The ioctl command. + * @arg: The ioctl argument. * * The request handler for the binder-control device. All requests operate on * the binderfs mount the binder-control device resides in: From 1e9a37d35a0ea658df7b5d64889ec2bd529f46d6 Mon Sep 17 00:00:00 2001 From: Sunday Adelodun Date: Fri, 21 Nov 2025 12:12:03 +0100 Subject: [PATCH 266/304] android: binder: add missing return value documentation for binder_apply_fd_fixups() The kernel-doc for binder_apply_fd_fixups() was missing a description of its return value, which triggers a kernel-doc warning. Add the missing "Return:" entry to doc that the function returns 0 on success or a negative errno on failure. Signed-off-by: Sunday Adelodun Link: https://patch.msgid.link/20251121111203.21800-2-adelodunolaoluwa@yahoo.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/android/binder.c b/drivers/android/binder.c index a3a1b5c33ba3..535fc881c8da 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -4669,6 +4669,8 @@ static int binder_wait_for_work(struct binder_thread *thread, * * If we fail to allocate an fd, skip the install and release * any fds that have already been allocated. + * + * Return: 0 on success, a negative errno code on failure. */ static int binder_apply_fd_fixups(struct binder_proc *proc, struct binder_transaction *t) From 3e0ae02ba831da2b707905f4e602e43f8507b8cc Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Tue, 11 Nov 2025 14:23:32 +0000 Subject: [PATCH 267/304] rust_binder: fix race condition on death_list Rust Binder contains the following unsafe operation: // SAFETY: A `NodeDeath` is never inserted into the death list // of any node other than its owner, so it is either in this // death list or in no death list. unsafe { node_inner.death_list.remove(self) }; This operation is unsafe because when touching the prev/next pointers of a list element, we have to ensure that no other thread is also touching them in parallel. If the node is present in the list that `remove` is called on, then that is fine because we have exclusive access to that list. If the node is not in any list, then it's also ok. But if it's present in a different list that may be accessed in parallel, then that may be a data race on the prev/next pointers. And unfortunately that is exactly what is happening here. In Node::release, we: 1. Take the lock. 2. Move all items to a local list on the stack. 3. Drop the lock. 4. Iterate the local list on the stack. Combined with threads using the unsafe remove method on the original list, this leads to memory corruption of the prev/next pointers. This leads to crashes like this one: Unable to handle kernel paging request at virtual address 000bb9841bcac70e Mem abort info: ESR = 0x0000000096000044 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x04: level 0 translation fault Data abort info: ISV = 0, ISS = 0x00000044, ISS2 = 0x00000000 CM = 0, WnR = 1, TnD = 0, TagAccess = 0 GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [000bb9841bcac70e] address between user and kernel address ranges Internal error: Oops: 0000000096000044 [#1] PREEMPT SMP google-cdd 538c004.gcdd: context saved(CPU:1) item - log_kevents is disabled Modules linked in: ... rust_binder CPU: 1 UID: 0 PID: 2092 Comm: kworker/1:178 Tainted: G S W OE 6.12.52-android16-5-g98debd5df505-4k #1 f94a6367396c5488d635708e43ee0c888d230b0b Tainted: [S]=CPU_OUT_OF_SPEC, [W]=WARN, [O]=OOT_MODULE, [E]=UNSIGNED_MODULE Hardware name: MUSTANG PVT 1.0 based on LGA (DT) Workqueue: events _RNvXs6_NtCsdfZWD8DztAw_6kernel9workqueueINtNtNtB7_4sync3arc3ArcNtNtCs8QPsHWIn21X_16rust_binder_main7process7ProcessEINtB5_15WorkItemPointerKy0_E3runB13_ [rust_binder] pstate: 23400005 (nzCv daif +PAN -UAO +TCO +DIT -SSBS BTYPE=--) pc : _RNvXs3_NtCs8QPsHWIn21X_16rust_binder_main7processNtB5_7ProcessNtNtCsdfZWD8DztAw_6kernel9workqueue8WorkItem3run+0x450/0x11f8 [rust_binder] lr : _RNvXs3_NtCs8QPsHWIn21X_16rust_binder_main7processNtB5_7ProcessNtNtCsdfZWD8DztAw_6kernel9workqueue8WorkItem3run+0x464/0x11f8 [rust_binder] sp : ffffffc09b433ac0 x29: ffffffc09b433d30 x28: ffffff8821690000 x27: ffffffd40cbaa448 x26: ffffff8821690000 x25: 00000000ffffffff x24: ffffff88d0376578 x23: 0000000000000001 x22: ffffffc09b433c78 x21: ffffff88e8f9bf40 x20: ffffff88e8f9bf40 x19: ffffff882692b000 x18: ffffffd40f10bf00 x17: 00000000c006287d x16: 00000000c006287d x15: 00000000000003b0 x14: 0000000000000100 x13: 000000201cb79ae0 x12: fffffffffffffff0 x11: 0000000000000000 x10: 0000000000000001 x9 : 0000000000000000 x8 : b80bb9841bcac706 x7 : 0000000000000001 x6 : fffffffebee63f30 x5 : 0000000000000000 x4 : 0000000000000001 x3 : 0000000000000000 x2 : 0000000000004c31 x1 : ffffff88216900c0 x0 : ffffff88e8f9bf00 Call trace: _RNvXs3_NtCs8QPsHWIn21X_16rust_binder_main7processNtB5_7ProcessNtNtCsdfZWD8DztAw_6kernel9workqueue8WorkItem3run+0x450/0x11f8 [rust_binder bbc172b53665bbc815363b22e97e3f7e3fe971fc] process_scheduled_works+0x1c4/0x45c worker_thread+0x32c/0x3e8 kthread+0x11c/0x1c8 ret_from_fork+0x10/0x20 Code: 94218d85 b4000155 a94026a8 d10102a0 (f9000509) ---[ end trace 0000000000000000 ]--- Thus, modify Node::release to pop items directly off the original list. Cc: stable@vger.kernel.org Fixes: eafedbc7c050 ("rust_binder: add Rust Binder driver") Signed-off-by: Alice Ryhl Acked-by: Miguel Ojeda Link: https://patch.msgid.link/20251111-binder-fix-list-remove-v1-1-8ed14a0da63d@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder/node.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/android/binder/node.rs b/drivers/android/binder/node.rs index 08d362deaf61..c26d113ede96 100644 --- a/drivers/android/binder/node.rs +++ b/drivers/android/binder/node.rs @@ -541,10 +541,10 @@ impl Node { guard = self.owner.inner.lock(); } - let death_list = core::mem::take(&mut self.inner.access_mut(&mut guard).death_list); - drop(guard); - for death in death_list { + while let Some(death) = self.inner.access_mut(&mut guard).death_list.pop_front() { + drop(guard); death.into_arc().set_dead(); + guard = self.owner.inner.lock(); } } From 6c37bebd8c926ad01ef157c0d123633a203e5c0d Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Tue, 11 Nov 2025 14:23:33 +0000 Subject: [PATCH 268/304] rust_binder: avoid mem::take on delivered_deaths Similar to the previous commit, List::remove is used on delivered_deaths, so do not use mem::take on it as that may result in violations of the List::remove safety requirements. I don't think this particular case can be triggered because it requires fd close to run in parallel with an ioctl on the same fd. But let's not tempt fate. Cc: stable@vger.kernel.org Fixes: eafedbc7c050 ("rust_binder: add Rust Binder driver") Signed-off-by: Alice Ryhl Acked-by: Miguel Ojeda Link: https://patch.msgid.link/20251111-binder-fix-list-remove-v1-2-8ed14a0da63d@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder/process.rs | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/android/binder/process.rs b/drivers/android/binder/process.rs index 27323070f30f..fd5dcdc8788c 100644 --- a/drivers/android/binder/process.rs +++ b/drivers/android/binder/process.rs @@ -1362,8 +1362,12 @@ impl Process { work.into_arc().cancel(); } - let delivered_deaths = take(&mut self.inner.lock().delivered_deaths); - drop(delivered_deaths); + // Clear delivered_deaths list. + // + // Scope ensures that MutexGuard is dropped while executing the body. + while let Some(delivered_death) = { self.inner.lock().delivered_deaths.pop_front() } { + drop(delivered_death); + } // Free any resources kept alive by allocated buffers. let omapping = self.inner.lock().mapping.take(); From 2c8ad5cfc22dba7d0b3b3ddfec0a75d8ea4169c3 Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Tue, 11 Nov 2025 14:23:34 +0000 Subject: [PATCH 269/304] rust: list: add warning to List::remove docs about mem::take The previous patches in this series illustrate why the List::remove method is really dangerous. I think the real takeaway here is to replace the linked lists with a different data structure without this unsafe footgun, but for now we fix the bugs and add a warning to the docs. Signed-off-by: Alice Ryhl Acked-by: Miguel Ojeda Link: https://patch.msgid.link/20251111-binder-fix-list-remove-v1-3-8ed14a0da63d@google.com Signed-off-by: Greg Kroah-Hartman --- rust/kernel/list.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/rust/kernel/list.rs b/rust/kernel/list.rs index 7355bbac16a7..8349ff32fc37 100644 --- a/rust/kernel/list.rs +++ b/rust/kernel/list.rs @@ -576,6 +576,9 @@ impl, const ID: u64> List { /// This returns `None` if the item is not in the list. (Note that by the safety requirements, /// this means that the item is not in any list.) /// + /// When using this method, be careful with using `mem::take` on the same list as that may + /// result in violating the safety requirements of this method. + /// /// # Safety /// /// `item` must not be in a different linked list (with the same id). From 58796560642a6e3148661a4df9da342a9a301748 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 27 Oct 2025 13:41:18 +0200 Subject: [PATCH 270/304] mei: Remove redundant pm_runtime_mark_last_busy() calls pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus Acked-by: Alexander Usyskin Link: https://patch.msgid.link/20251027114118.390775-1-sakari.ailus@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/mei/client.c | 14 ++------------ drivers/misc/mei/interrupt.c | 2 -- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c index 159e8b841564..5dc665515263 100644 --- a/drivers/misc/mei/client.c +++ b/drivers/misc/mei/client.c @@ -709,7 +709,6 @@ void mei_host_client_init(struct mei_device *dev) schedule_work(&dev->bus_rescan_work); - pm_runtime_mark_last_busy(dev->parent); dev_dbg(&dev->dev, "rpm: autosuspend\n"); pm_request_autosuspend(dev->parent); } @@ -991,7 +990,6 @@ int mei_cl_disconnect(struct mei_cl *cl) rets = __mei_cl_disconnect(cl); cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); return rets; @@ -1167,7 +1165,6 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_client *me_cl, rets = cl->status; out: cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); mei_io_cb_free(cb); @@ -1554,7 +1551,6 @@ int mei_cl_notify_request(struct mei_cl *cl, out: cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); mei_io_cb_free(cb); @@ -1702,7 +1698,6 @@ int mei_cl_read_start(struct mei_cl *cl, size_t length, const struct file *fp) out: cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); nortpm: if (rets) @@ -2092,7 +2087,6 @@ out: rets = buf_len; err: cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); free: mei_io_cb_free(cb); @@ -2116,12 +2110,10 @@ void mei_cl_complete(struct mei_cl *cl, struct mei_cl_cb *cb) case MEI_FOP_WRITE: mei_tx_cb_dequeue(cb); cl->writing_state = MEI_WRITE_COMPLETE; - if (waitqueue_active(&cl->tx_wait)) { + if (waitqueue_active(&cl->tx_wait)) wake_up_interruptible(&cl->tx_wait); - } else { - pm_runtime_mark_last_busy(dev->parent); + else pm_request_autosuspend(dev->parent); - } break; case MEI_FOP_READ: @@ -2366,7 +2358,6 @@ out: mei_cl_dma_free(cl); cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); mei_io_cb_free(cb); @@ -2444,7 +2435,6 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct file *fp) mei_cl_dma_free(cl); out: cl_dbg(dev, cl, "rpm: autosuspend\n"); - pm_runtime_mark_last_busy(dev->parent); pm_runtime_put_autosuspend(dev->parent); mei_io_cb_free(cb); diff --git a/drivers/misc/mei/interrupt.c b/drivers/misc/mei/interrupt.c index 3aa66b6b0d36..3f210413fd32 100644 --- a/drivers/misc/mei/interrupt.c +++ b/drivers/misc/mei/interrupt.c @@ -229,7 +229,6 @@ static int mei_cl_irq_read_msg(struct mei_cl *cl, cl_dbg(dev, cl, "completed read length = %zu\n", cb->buf_idx); list_move_tail(&cb->list, cmpl_list); } else { - pm_runtime_mark_last_busy(dev->parent); pm_request_autosuspend(dev->parent); } @@ -310,7 +309,6 @@ static int mei_cl_irq_read(struct mei_cl *cl, struct mei_cl_cb *cb, return ret; } - pm_runtime_mark_last_busy(dev->parent); pm_request_autosuspend(dev->parent); list_move_tail(&cb->list, &cl->rd_pending); From 5d92c3b41f0bddfa416130c6e1b424414f3d2acf Mon Sep 17 00:00:00 2001 From: Junxiao Chang Date: Sun, 9 Nov 2025 17:35:33 +0200 Subject: [PATCH 271/304] mei: gsc: add dependency on Xe driver INTEL_MEI_GSC depends on either i915 or Xe and can be present when either of above is present. Cc: stable Fixes: 87a4c85d3a3e ("drm/xe/gsc: add gsc device support") Tested-by: Baoli Zhang Signed-off-by: Junxiao Chang Signed-off-by: Alexander Usyskin Link: https://patch.msgid.link/20251109153533.3179787-1-alexander.usyskin@intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/mei/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index f8b04e49e4ba..f4eb307cd35e 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -49,7 +49,7 @@ config INTEL_MEI_TXE config INTEL_MEI_GSC tristate "Intel MEI GSC embedded device" depends on INTEL_MEI_ME - depends on DRM_I915 + depends on DRM_I915 || DRM_XE help Intel auxiliary driver for GSC devices embedded in Intel graphics devices. From a6dab2f61d23c1eb32f1d08fa7b4919a2478950b Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Tue, 4 Nov 2025 10:01:33 +0800 Subject: [PATCH 272/304] mei: Fix error handling in mei_register mei_register() fails to release the device reference in error paths after device_initialize(). During normal device registration, the reference is properly handled through mei_deregister() which calls device_destroy(). However, in error handling paths (such as cdev_alloc failure, cdev_add failure, etc.), missing put_device() calls cause reference count leaks, preventing the device's release function (mei_device_release) from being called and resulting in memory leaks of mei_device. Found by code review. Cc: stable Fixes: 7704e6be4ed2 ("mei: hook mei_device on class device") Signed-off-by: Ma Ke Acked-by: Alexander Usyskin Link: https://patch.msgid.link/20251104020133.5017-1-make24@iscas.ac.cn Signed-off-by: Greg Kroah-Hartman --- drivers/misc/mei/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c index 86a73684a373..6f26d5160788 100644 --- a/drivers/misc/mei/main.c +++ b/drivers/misc/mei/main.c @@ -1307,6 +1307,7 @@ int mei_register(struct mei_device *dev, struct device *parent) err_del_cdev: cdev_del(dev->cdev); err: + put_device(&dev->dev); mei_minor_free(minor); return ret; } From f0a40fe2fc2c07827dfcee5ab070f3fe30413ed5 Mon Sep 17 00:00:00 2001 From: Andrew Donnellan Date: Thu, 20 Nov 2025 14:16:26 +1100 Subject: [PATCH 273/304] MAINTAINERS: Downgrade ocxl to Odd Fixes There hasn't been any substantive work on the ocxl driver since 2020, and all patches since then have been minor fixes or part of treewide or arch-wide changes. Frederic and I are no longer spending much time on this driver. Downgrade the status of the ocxl driver to Odd Fixes, to reflect the current reality. Signed-off-by: Andrew Donnellan Acked-by: Frederic Barrat Link: https://patch.msgid.link/20251120-ocxl-odd-fixes-v1-1-8b766f114621@linux.ibm.com Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 194ee22e2026..1fffce20d548 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18794,7 +18794,7 @@ OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER M: Frederic Barrat M: Andrew Donnellan L: linuxppc-dev@lists.ozlabs.org -S: Supported +S: Odd Fixes F: Documentation/userspace-api/accelerators/ocxl.rst F: arch/powerpc/include/asm/pnv-ocxl.h F: arch/powerpc/platforms/powernv/ocxl.c From 72262330f7b3ad2130e800cecf02adcce3c32c77 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Thu, 23 Oct 2025 13:31:41 +0100 Subject: [PATCH 274/304] comedi: c6xdigio: Fix invalid PNP driver unregistration The Comedi low-level driver "c6xdigio" seems to be for a parallel port connected device. When the Comedi core calls the driver's Comedi "attach" handler `c6xdigio_attach()` to configure a Comedi to use this driver, it tries to enable the parallel port PNP resources by registering a PNP driver with `pnp_register_driver()`, but ignores the return value. (The `struct pnp_driver` it uses has only the `name` and `id_table` members filled in.) The driver's Comedi "detach" handler `c6xdigio_detach()` unconditionally unregisters the PNP driver with `pnp_unregister_driver()`. It is possible for `c6xdigio_attach()` to return an error before it calls `pnp_register_driver()` and it is possible for the call to `pnp_register_driver()` to return an error (that is ignored). In both cases, the driver should not be calling `pnp_unregister_driver()` as it does in `c6xdigio_detach()`. (Note that `c6xdigio_detach()` will be called by the Comedi core if `c6xdigio_attach()` returns an error, or if the Comedi core decides to detach the Comedi device from the driver for some other reason.) The unconditional call to `pnp_unregister_driver()` without a previous successful call to `pnp_register_driver()` will cause `driver_unregister()` to issue a warning "Unexpected driver unregister!". This was detected by Syzbot [1]. Also, the PNP driver registration and unregistration should be done at module init and exit time, respectively, not when attaching or detaching Comedi devices to the driver. (There might be more than one Comedi device being attached to the driver, although that is unlikely.) Change the driver to do the PNP driver registration at module init time, and the unregistration at module exit time. Since `c6xdigio_detach()` now only calls `comedi_legacy_detach()`, remove the function and change the Comedi driver "detach" handler to `comedi_legacy_detach`. ------------------------------------------- [1] Syzbot sample crash report: Unexpected driver unregister! WARNING: CPU: 0 PID: 5970 at drivers/base/driver.c:273 driver_unregister drivers/base/driver.c:273 [inline] WARNING: CPU: 0 PID: 5970 at drivers/base/driver.c:273 driver_unregister+0x90/0xb0 drivers/base/driver.c:270 Modules linked in: CPU: 0 UID: 0 PID: 5970 Comm: syz.0.17 Not tainted syzkaller #0 PREEMPT(full) Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/02/2025 RIP: 0010:driver_unregister drivers/base/driver.c:273 [inline] RIP: 0010:driver_unregister+0x90/0xb0 drivers/base/driver.c:270 Code: 48 89 ef e8 c2 e6 82 fc 48 89 df e8 3a 93 ff ff 5b 5d e9 c3 6d d9 fb e8 be 6d d9 fb 90 48 c7 c7 e0 f8 1f 8c e8 51 a2 97 fb 90 <0f> 0b 90 90 5b 5d e9 a5 6d d9 fb e8 e0 f4 41 fc eb 94 e8 d9 f4 41 RSP: 0018:ffffc9000373f9a0 EFLAGS: 00010282 RAX: 0000000000000000 RBX: ffffffff8ff24720 RCX: ffffffff817b6ee8 RDX: ffff88807c932480 RSI: ffffffff817b6ef5 RDI: 0000000000000001 RBP: 0000000000000000 R08: 0000000000000001 R09: 0000000000000000 R10: 0000000000000001 R11: 0000000000000001 R12: ffffffff8ff24660 R13: dffffc0000000000 R14: 0000000000000000 R15: ffff88814cca0000 FS: 000055556dab1500(0000) GS:ffff8881249d9000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000055f77f285cd0 CR3: 000000007d871000 CR4: 00000000003526f0 Call Trace: comedi_device_detach_locked+0x12f/0xa50 drivers/comedi/drivers.c:207 comedi_device_detach+0x67/0xb0 drivers/comedi/drivers.c:215 comedi_device_attach+0x43d/0x900 drivers/comedi/drivers.c:1011 do_devconfig_ioctl+0x1b1/0x710 drivers/comedi/comedi_fops.c:872 comedi_unlocked_ioctl+0x165d/0x2f00 drivers/comedi/comedi_fops.c:2178 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:597 [inline] __se_sys_ioctl fs/ioctl.c:583 [inline] __x64_sys_ioctl+0x18e/0x210 fs/ioctl.c:583 do_syscall_x64 arch/x86/entry/syscall_64.c:63 [inline] do_syscall_64+0xcd/0xfa0 arch/x86/entry/syscall_64.c:94 entry_SYSCALL_64_after_hwframe+0x77/0x7f RIP: 0033:0x7fc05798eec9 Code: ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 a8 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007ffcf8184238 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00007fc057be5fa0 RCX: 00007fc05798eec9 RDX: 0000200000000080 RSI: 0000000040946400 RDI: 0000000000000003 RBP: 00007fc057a11f91 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 00007fc057be5fa0 R14: 00007fc057be5fa0 R15: 0000000000000003 ------------------------------------------- Reported-by: syzbot+6616bba359cec7a1def1@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=6616bba359cec7a1def1 Fixes: 2c89e159cd2f ("Staging: comedi: add c6xdigio driver") Cc: stable Signed-off-by: Ian Abbott Link: https://patch.msgid.link/20251023123141.6537-1-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/drivers/c6xdigio.c | 46 +++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/comedi/drivers/c6xdigio.c b/drivers/comedi/drivers/c6xdigio.c index 14b90d1c64dc..8a38d97d463b 100644 --- a/drivers/comedi/drivers/c6xdigio.c +++ b/drivers/comedi/drivers/c6xdigio.c @@ -249,9 +249,6 @@ static int c6xdigio_attach(struct comedi_device *dev, if (ret) return ret; - /* Make sure that PnP ports get activated */ - pnp_register_driver(&c6xdigio_pnp_driver); - s = &dev->subdevices[0]; /* pwm output subdevice */ s->type = COMEDI_SUBD_PWM; @@ -278,19 +275,46 @@ static int c6xdigio_attach(struct comedi_device *dev, return 0; } -static void c6xdigio_detach(struct comedi_device *dev) -{ - comedi_legacy_detach(dev); - pnp_unregister_driver(&c6xdigio_pnp_driver); -} - static struct comedi_driver c6xdigio_driver = { .driver_name = "c6xdigio", .module = THIS_MODULE, .attach = c6xdigio_attach, - .detach = c6xdigio_detach, + .detach = comedi_legacy_detach, }; -module_comedi_driver(c6xdigio_driver); + +static bool c6xdigio_pnp_registered = false; + +static int __init c6xdigio_module_init(void) +{ + int ret; + + ret = comedi_driver_register(&c6xdigio_driver); + if (ret) + return ret; + + if (IS_ENABLED(CONFIG_PNP)) { + /* Try to activate the PnP ports */ + ret = pnp_register_driver(&c6xdigio_pnp_driver); + if (ret) { + pr_warn("failed to register pnp driver - err %d\n", + ret); + ret = 0; /* ignore the error. */ + } else { + c6xdigio_pnp_registered = true; + } + } + + return 0; +} +module_init(c6xdigio_module_init); + +static void __exit c6xdigio_module_exit(void) +{ + if (c6xdigio_pnp_registered) + pnp_unregister_driver(&c6xdigio_pnp_driver); + comedi_driver_unregister(&c6xdigio_driver); +} +module_exit(c6xdigio_module_exit); MODULE_AUTHOR("Comedi https://www.comedi.org"); MODULE_DESCRIPTION("Comedi driver for the C6x_DIGIO DSP daughter card"); From 0de7d9cd07a2671fa6089173bccc0b2afe6b93ee Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Thu, 23 Oct 2025 16:22:32 +0300 Subject: [PATCH 275/304] comedi: check device's attached status in compat ioctls Syzbot identified an issue [1] that crashes kernel, seemingly due to unexistent callback dev->get_valid_routes(). By all means, this should not occur as said callback must always be set to get_zero_valid_routes() in __comedi_device_postconfig(). As the crash seems to appear exclusively in i386 kernels, at least, judging from [1] reports, the blame lies with compat versions of standard IOCTL handlers. Several of them are modified and do not use comedi_unlocked_ioctl(). While functionality of these ioctls essentially copy their original versions, they do not have required sanity check for device's attached status. This, in turn, leads to a possibility of calling select IOCTLs on a device that has not been properly setup, even via COMEDI_DEVCONFIG. Doing so on unconfigured devices means that several crucial steps are missed, for instance, specifying dev->get_valid_routes() callback. Fix this somewhat crudely by ensuring device's attached status before performing any ioctls, improving logic consistency between modern and compat functions. [1] Syzbot report: BUG: kernel NULL pointer dereference, address: 0000000000000000 ... CR2: ffffffffffffffd6 CR3: 000000006c717000 CR4: 0000000000352ef0 Call Trace: get_valid_routes drivers/comedi/comedi_fops.c:1322 [inline] parse_insn+0x78c/0x1970 drivers/comedi/comedi_fops.c:1401 do_insnlist_ioctl+0x272/0x700 drivers/comedi/comedi_fops.c:1594 compat_insnlist drivers/comedi/comedi_fops.c:3208 [inline] comedi_compat_ioctl+0x810/0x990 drivers/comedi/comedi_fops.c:3273 __do_compat_sys_ioctl fs/ioctl.c:695 [inline] __se_compat_sys_ioctl fs/ioctl.c:638 [inline] __ia32_compat_sys_ioctl+0x242/0x370 fs/ioctl.c:638 do_syscall_32_irqs_on arch/x86/entry/syscall_32.c:83 [inline] ... Reported-by: syzbot+ab8008c24e84adee93ff@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=ab8008c24e84adee93ff Fixes: 3fbfd2223a27 ("comedi: get rid of compat_alloc_user_space() mess in COMEDI_CHANINFO compat") Cc: stable Reviewed-by: Ian Abbott Signed-off-by: Nikita Zhandarovich Link: https://patch.msgid.link/20251023132234.395794-1-n.zhandarovich@fintech.ru Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/comedi_fops.c | 42 ++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c index dea698e509b1..40d8b29797ae 100644 --- a/drivers/comedi/comedi_fops.c +++ b/drivers/comedi/comedi_fops.c @@ -3018,7 +3018,12 @@ static int compat_chaninfo(struct file *file, unsigned long arg) chaninfo.rangelist = compat_ptr(chaninfo32.rangelist); mutex_lock(&dev->mutex); - err = do_chaninfo_ioctl(dev, &chaninfo); + if (!dev->attached) { + dev_dbg(dev->class_dev, "no driver attached\n"); + err = -ENODEV; + } else { + err = do_chaninfo_ioctl(dev, &chaninfo); + } mutex_unlock(&dev->mutex); return err; } @@ -3039,7 +3044,12 @@ static int compat_rangeinfo(struct file *file, unsigned long arg) rangeinfo.range_ptr = compat_ptr(rangeinfo32.range_ptr); mutex_lock(&dev->mutex); - err = do_rangeinfo_ioctl(dev, &rangeinfo); + if (!dev->attached) { + dev_dbg(dev->class_dev, "no driver attached\n"); + err = -ENODEV; + } else { + err = do_rangeinfo_ioctl(dev, &rangeinfo); + } mutex_unlock(&dev->mutex); return err; } @@ -3115,7 +3125,12 @@ static int compat_cmd(struct file *file, unsigned long arg) return rc; mutex_lock(&dev->mutex); - rc = do_cmd_ioctl(dev, &cmd, ©, file); + if (!dev->attached) { + dev_dbg(dev->class_dev, "no driver attached\n"); + rc = -ENODEV; + } else { + rc = do_cmd_ioctl(dev, &cmd, ©, file); + } mutex_unlock(&dev->mutex); if (copy) { /* Special case: copy cmd back to user. */ @@ -3140,7 +3155,12 @@ static int compat_cmdtest(struct file *file, unsigned long arg) return rc; mutex_lock(&dev->mutex); - rc = do_cmdtest_ioctl(dev, &cmd, ©, file); + if (!dev->attached) { + dev_dbg(dev->class_dev, "no driver attached\n"); + rc = -ENODEV; + } else { + rc = do_cmdtest_ioctl(dev, &cmd, ©, file); + } mutex_unlock(&dev->mutex); if (copy) { err = put_compat_cmd(compat_ptr(arg), &cmd); @@ -3200,7 +3220,12 @@ static int compat_insnlist(struct file *file, unsigned long arg) } mutex_lock(&dev->mutex); - rc = do_insnlist_ioctl(dev, insns, insnlist32.n_insns, file); + if (!dev->attached) { + dev_dbg(dev->class_dev, "no driver attached\n"); + rc = -ENODEV; + } else { + rc = do_insnlist_ioctl(dev, insns, insnlist32.n_insns, file); + } mutex_unlock(&dev->mutex); kfree(insns); return rc; @@ -3219,7 +3244,12 @@ static int compat_insn(struct file *file, unsigned long arg) return rc; mutex_lock(&dev->mutex); - rc = do_insn_ioctl(dev, &insn, file); + if (!dev->attached) { + dev_dbg(dev->class_dev, "no driver attached\n"); + rc = -ENODEV; + } else { + rc = do_insn_ioctl(dev, &insn, file); + } mutex_unlock(&dev->mutex); return rc; } From f24c6e3a39fa355dabfb684c9ca82db579534e72 Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Thu, 23 Oct 2025 16:22:04 +0300 Subject: [PATCH 276/304] comedi: multiq3: sanitize config options in multiq3_attach() Syzbot identified an issue [1] in multiq3_attach() that induces a task timeout due to open() or COMEDI_DEVCONFIG ioctl operations, specifically, in the case of multiq3 driver. This problem arose when syzkaller managed to craft weird configuration options used to specify the number of channels in encoder subdevice. If a particularly great number is passed to s->n_chan in multiq3_attach() via it->options[2], then multiple calls to multiq3_encoder_reset() at the end of driver-specific attach() method will be running for minutes, thus blocking tasks and affected devices as well. While this issue is most likely not too dangerous for real-life devices, it still makes sense to sanitize configuration inputs. Enable a sensible limit on the number of encoder chips (4 chips max, each with 2 channels) to stop this behaviour from manifesting. [1] Syzbot crash: INFO: task syz.2.19:6067 blocked for more than 143 seconds. ... Call Trace: context_switch kernel/sched/core.c:5254 [inline] __schedule+0x17c4/0x4d60 kernel/sched/core.c:6862 __schedule_loop kernel/sched/core.c:6944 [inline] schedule+0x165/0x360 kernel/sched/core.c:6959 schedule_preempt_disabled+0x13/0x30 kernel/sched/core.c:7016 __mutex_lock_common kernel/locking/mutex.c:676 [inline] __mutex_lock+0x7e6/0x1350 kernel/locking/mutex.c:760 comedi_open+0xc0/0x590 drivers/comedi/comedi_fops.c:2868 chrdev_open+0x4cc/0x5e0 fs/char_dev.c:414 do_dentry_open+0x953/0x13f0 fs/open.c:965 vfs_open+0x3b/0x340 fs/open.c:1097 ... Reported-by: syzbot+7811bb68a317954a0347@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=7811bb68a317954a0347 Fixes: 77e01cdbad51 ("Staging: comedi: add multiq3 driver") Cc: stable Signed-off-by: Nikita Zhandarovich Reviewed-by: Ian Abbott Link: https://patch.msgid.link/20251023132205.395753-1-n.zhandarovich@fintech.ru Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/drivers/multiq3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/comedi/drivers/multiq3.c b/drivers/comedi/drivers/multiq3.c index 07ff5383da99..ac369e9a262d 100644 --- a/drivers/comedi/drivers/multiq3.c +++ b/drivers/comedi/drivers/multiq3.c @@ -67,6 +67,11 @@ #define MULTIQ3_TRSFRCNTR_OL 0x10 /* xfer CNTR to OL (x and y) */ #define MULTIQ3_EFLAG_RESET 0x06 /* reset E bit of flag reg */ +/* + * Limit on the number of optional encoder channels + */ +#define MULTIQ3_MAX_ENC_CHANS 8 + static void multiq3_set_ctrl(struct comedi_device *dev, unsigned int bits) { /* @@ -312,6 +317,10 @@ static int multiq3_attach(struct comedi_device *dev, s->insn_read = multiq3_encoder_insn_read; s->insn_config = multiq3_encoder_insn_config; + /* sanity check for number of encoder channels */ + if (s->n_chan > MULTIQ3_MAX_ENC_CHANS) + s->n_chan = MULTIQ3_MAX_ENC_CHANS; + for (i = 0; i < s->n_chan; i++) multiq3_encoder_reset(dev, i); From a51f025b5038abd3d22eed2ede4cd46793d89565 Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Thu, 23 Oct 2025 17:14:56 +0300 Subject: [PATCH 277/304] comedi: pcl818: fix null-ptr-deref in pcl818_ai_cancel() Syzbot identified an issue [1] in pcl818_ai_cancel(), which stems from the fact that in case of early device detach via pcl818_detach(), subdevice dev->read_subdev may not have initialized its pointer to &struct comedi_async as intended. Thus, any such dereferencing of &s->async->cmd will lead to general protection fault and kernel crash. Mitigate this problem by removing a call to pcl818_ai_cancel() from pcl818_detach() altogether. This way, if the subdevice setups its support for async commands, everything async-related will be handled via subdevice's own ->cancel() function in comedi_device_detach_locked() even before pcl818_detach(). If no support for asynchronous commands is provided, there is no need to cancel anything either. [1] Syzbot crash: Oops: general protection fault, probably for non-canonical address 0xdffffc0000000005: 0000 [#1] SMP KASAN PTI KASAN: null-ptr-deref in range [0x0000000000000028-0x000000000000002f] CPU: 1 UID: 0 PID: 6050 Comm: syz.0.18 Not tainted syzkaller #0 PREEMPT(full) Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 08/18/2025 RIP: 0010:pcl818_ai_cancel+0x69/0x3f0 drivers/comedi/drivers/pcl818.c:762 ... Call Trace: pcl818_detach+0x66/0xd0 drivers/comedi/drivers/pcl818.c:1115 comedi_device_detach_locked+0x178/0x750 drivers/comedi/drivers.c:207 do_devconfig_ioctl drivers/comedi/comedi_fops.c:848 [inline] comedi_unlocked_ioctl+0xcde/0x1020 drivers/comedi/comedi_fops.c:2178 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:597 [inline] ... Reported-by: syzbot+fce5d9d5bd067d6fbe9b@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=fce5d9d5bd067d6fbe9b Fixes: 00aba6e7b565 ("staging: comedi: pcl818: remove 'neverending_ai' from private data") Cc: stable Signed-off-by: Nikita Zhandarovich Reviewed-by: Ian Abbott Link: https://patch.msgid.link/20251023141457.398685-1-n.zhandarovich@fintech.ru Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/drivers/pcl818.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/comedi/drivers/pcl818.c b/drivers/comedi/drivers/pcl818.c index 4127adcfb229..06fe06396f23 100644 --- a/drivers/comedi/drivers/pcl818.c +++ b/drivers/comedi/drivers/pcl818.c @@ -1111,10 +1111,9 @@ static void pcl818_detach(struct comedi_device *dev) { struct pcl818_private *devpriv = dev->private; - if (devpriv) { - pcl818_ai_cancel(dev, dev->read_subdev); + if (devpriv) pcl818_reset(dev); - } + pcl818_free_dma(dev); comedi_legacy_detach(dev); } From 4e1da516debbe6a573ffa0392e2809d180d0575c Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Thu, 23 Oct 2025 14:28:18 +0100 Subject: [PATCH 278/304] comedi: Add reference counting for Comedi command handling For interrupts from badly behaved hardware (as emulated by Syzbot), it is possible for the Comedi core functions that manage the progress of asynchronous data acquisition to be called from driver ISRs while no asynchronous command has been set up, which can cause problems such as invalid pointer dereferencing or dividing by zero. To help protect against that, introduce new functions to maintain a reference counter for asynchronous commands that are being set up. `comedi_get_is_subdevice_running(s)` will check if a command has been set up on a subdevice and is still marked as running, and if so will increment the reference counter and return `true`, otherwise it will return `false` without modifying the reference counter. `comedi_put_is_subdevice_running(s)` will decrement the reference counter and set a completion event when decremented to 0. Change the `do_cmd_ioctl()` function (responsible for setting up the asynchronous command) to reinitialize the completion event and set the reference counter to 1 before it marks the subdevice as running. Change the `do_become_nonbusy()` function (responsible for destroying a completed command) to call `comedi_put_is_subdevice_running(s)` and wait for the completion event after marking the subdevice as not running. Because the subdevice normally gets marked as not running before the call to `do_become_nonbusy()` (and may also be called when the Comedi device is being detached from the low-level driver), add a new flag `COMEDI_SRF_BUSY` to the set of subdevice run-flags that indicates that an asynchronous command was set up and will need to be destroyed. This flag is set by `do_cmd_ioctl()` and cleared and checked by `do_become_nonbusy()`. Subsequent patches will change the Comedi core functions that are called from low-level drivers for asynchrous command handling to make use of the `comedi_get_is_subdevice_running()` and `comedi_put_is_subdevice_running()` functions, and will modify the ISRs of some of these low-level drivers if they dereference the subdevice's `async` pointer directly. Signed-off-by: Ian Abbott Link: https://patch.msgid.link/20251023133001.8439-2-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/comedi_fops.c | 78 ++++++++++++++++++++++++++++---- drivers/comedi/drivers.c | 1 + include/linux/comedi/comedidev.h | 7 +++ 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c index 40d8b29797ae..8253e4e8232b 100644 --- a/drivers/comedi/comedi_fops.c +++ b/drivers/comedi/comedi_fops.c @@ -38,6 +38,7 @@ * COMEDI_SRF_ERROR: indicates an COMEDI_CB_ERROR event has occurred * since the last command was started * COMEDI_SRF_RUNNING: command is running + * COMEDI_SRF_BUSY: command was started and subdevice still busy * COMEDI_SRF_FREE_SPRIV: free s->private on detach * * COMEDI_SRF_BUSY_MASK: runflags that indicate the subdevice is "busy" @@ -45,9 +46,11 @@ #define COMEDI_SRF_RT BIT(1) #define COMEDI_SRF_ERROR BIT(2) #define COMEDI_SRF_RUNNING BIT(27) +#define COMEDI_SRF_BUSY BIT(28) #define COMEDI_SRF_FREE_SPRIV BIT(31) -#define COMEDI_SRF_BUSY_MASK (COMEDI_SRF_ERROR | COMEDI_SRF_RUNNING) +#define COMEDI_SRF_BUSY_MASK \ + (COMEDI_SRF_ERROR | COMEDI_SRF_RUNNING | COMEDI_SRF_BUSY) /** * struct comedi_file - Per-file private data for COMEDI device @@ -665,6 +668,11 @@ static bool comedi_is_runflags_in_error(unsigned int runflags) return runflags & COMEDI_SRF_ERROR; } +static bool comedi_is_runflags_busy(unsigned int runflags) +{ + return runflags & COMEDI_SRF_BUSY; +} + /** * comedi_is_subdevice_running() - Check if async command running on subdevice * @s: COMEDI subdevice. @@ -687,6 +695,46 @@ static bool __comedi_is_subdevice_running(struct comedi_subdevice *s) return comedi_is_runflags_running(runflags); } +/** + * comedi_get_is_subdevice_running() - Get if async command running on subdevice + * @s: COMEDI subdevice. + * + * If an asynchronous COMEDI command is running on the subdevice, increment + * a reference counter. If the function return value indicates that a + * command is running, then the details of the command will not be destroyed + * before a matching call to comedi_put_is_subdevice_running(). + * + * Return: %true if an asynchronous COMEDI command is active on the + * subdevice, else %false. + */ +bool comedi_get_is_subdevice_running(struct comedi_subdevice *s) +{ + unsigned long flags; + bool running; + + spin_lock_irqsave(&s->spin_lock, flags); + running = __comedi_is_subdevice_running(s); + if (running) + refcount_inc(&s->async->run_active); + spin_unlock_irqrestore(&s->spin_lock, flags); + return running; +} +EXPORT_SYMBOL_GPL(comedi_get_is_subdevice_running); + +/** + * comedi_put_is_subdevice_running() - Put if async command running on subdevice + * @s: COMEDI subdevice. + * + * Decrements the reference counter that was incremented when + * comedi_get_is_subdevice_running() returned %true. + */ +void comedi_put_is_subdevice_running(struct comedi_subdevice *s) +{ + if (refcount_dec_and_test(&s->async->run_active)) + complete_all(&s->async->run_complete); +} +EXPORT_SYMBOL_GPL(comedi_put_is_subdevice_running); + bool comedi_can_auto_free_spriv(struct comedi_subdevice *s) { unsigned int runflags = __comedi_get_subdevice_runflags(s); @@ -736,20 +784,28 @@ static void do_become_nonbusy(struct comedi_device *dev, struct comedi_subdevice *s) { struct comedi_async *async = s->async; + unsigned int runflags; + unsigned long flags; lockdep_assert_held(&dev->mutex); - comedi_update_subdevice_runflags(s, COMEDI_SRF_RUNNING, 0); - if (async) { + spin_lock_irqsave(&s->spin_lock, flags); + runflags = __comedi_get_subdevice_runflags(s); + __comedi_clear_subdevice_runflags(s, COMEDI_SRF_RUNNING | + COMEDI_SRF_BUSY); + spin_unlock_irqrestore(&s->spin_lock, flags); + if (comedi_is_runflags_busy(runflags)) { + /* + * "Run active" counter was set to 1 when setting up the + * command. Decrement it and wait for it to become 0. + */ + comedi_put_is_subdevice_running(s); + wait_for_completion(&async->run_complete); comedi_buf_reset(s); async->inttrig = NULL; kfree(async->cmd.chanlist); async->cmd.chanlist = NULL; s->busy = NULL; wake_up_interruptible_all(&async->wait_head); - } else { - dev_err(dev->class_dev, - "BUG: (?) %s called with async=NULL\n", __func__); - s->busy = NULL; } } @@ -1860,8 +1916,14 @@ static int do_cmd_ioctl(struct comedi_device *dev, if (async->cmd.flags & CMDF_WAKE_EOS) async->cb_mask |= COMEDI_CB_EOS; + /* + * Set the "run active" counter with an initial count of 1 that will + * complete the "safe to reset" event when it is decremented to 0. + */ + refcount_set(&s->async->run_active, 1); + reinit_completion(&s->async->run_complete); comedi_update_subdevice_runflags(s, COMEDI_SRF_BUSY_MASK, - COMEDI_SRF_RUNNING); + COMEDI_SRF_RUNNING | COMEDI_SRF_BUSY); /* * Set s->busy _after_ setting COMEDI_SRF_RUNNING flag to avoid diff --git a/drivers/comedi/drivers.c b/drivers/comedi/drivers.c index c9ebaadc5e82..fd6e6cbe47ad 100644 --- a/drivers/comedi/drivers.c +++ b/drivers/comedi/drivers.c @@ -677,6 +677,7 @@ static int __comedi_device_postconfig_async(struct comedi_device *dev, return -ENOMEM; init_waitqueue_head(&async->wait_head); + init_completion(&async->run_complete); s->async = async; async->max_bufsize = comedi_default_buf_maxsize_kb * 1024; diff --git a/include/linux/comedi/comedidev.h b/include/linux/comedi/comedidev.h index 4cb0400ad616..35fdc41845ce 100644 --- a/include/linux/comedi/comedidev.h +++ b/include/linux/comedi/comedidev.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #define COMEDI_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) @@ -272,6 +273,8 @@ struct comedi_buf_map { * @events: Bit-vector of events that have occurred. * @cmd: Details of comedi command in progress. * @wait_head: Task wait queue for file reader or writer. + * @run_complete: "run complete" completion event. + * @run_active: "run active" reference counter. * @cb_mask: Bit-vector of events that should wake waiting tasks. * @inttrig: Software trigger function for command, or NULL. * @@ -357,6 +360,8 @@ struct comedi_async { unsigned int events; struct comedi_cmd cmd; wait_queue_head_t wait_head; + struct completion run_complete; + refcount_t run_active; unsigned int cb_mask; int (*inttrig)(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int x); @@ -584,6 +589,8 @@ struct comedi_device *comedi_dev_get_from_minor(unsigned int minor); int comedi_dev_put(struct comedi_device *dev); bool comedi_is_subdevice_running(struct comedi_subdevice *s); +bool comedi_get_is_subdevice_running(struct comedi_subdevice *s); +void comedi_put_is_subdevice_running(struct comedi_subdevice *s); void *comedi_alloc_spriv(struct comedi_subdevice *s, size_t size); void comedi_set_spriv_auto_free(struct comedi_subdevice *s); From 51495254fda43cf1027fe052a77bea742ca23a05 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Thu, 23 Oct 2025 14:28:19 +0100 Subject: [PATCH 279/304] comedi: Use reference count for asynchronous command functions For interrupts from badly behaved hardware (as emulated by Syzbot), it is possible for the Comedi core functions that manage the progress of asynchronous data acquisition to be called from driver ISRs while no asynchronous command has been set up, which can cause problems such as invalid pointer dereferencing or dividing by zero. Change those functions in the Comedi core to use this pattern: if `comedi_get_is_subdevice_running(s)` returns `true` then call a safe version of the function with the same name prefixed with an underscore, followed by a call to `comedi_put_is_subdevice_running(s)`, otherwise take some default action. `comedi_get_is_subdevice_running(s)` returning `true` ensures that the details of the asynchronous command will not be destroyed before the matching call to `comedi_put_is_subdevice_running(s)`. Replace calls to those functions from elsewhere in the Comedi core with calls to the safe versions of the functions. The modified functions are: `comedi_buf_read_alloc()`, `comedi_buf_read_free()`, `comedi_buf_read_n_available()`, `comedi_buf_read_samples()`, `comedi_buf_write_alloc()`, `comedi_buf_write_free()`, `comedi_buf_write_samples()`, `comedi_bytes_per_scan()`, `comedi_event()`, `comedi_handle_events()`, `comedi_inc_scan_progress()`, `comedi_nsamples_left()`, `comedi_nscans_left()`. Signed-off-by: Ian Abbott Link: https://patch.msgid.link/20251023133001.8439-3-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/comedi_buf.c | 290 ++++++++++++++++++++----------- drivers/comedi/comedi_fops.c | 56 +++--- drivers/comedi/comedi_internal.h | 12 ++ drivers/comedi/drivers.c | 133 ++++++++++---- 4 files changed, 331 insertions(+), 160 deletions(-) diff --git a/drivers/comedi/comedi_buf.c b/drivers/comedi/comedi_buf.c index c7c262a2d8ca..785977b40a93 100644 --- a/drivers/comedi/comedi_buf.c +++ b/drivers/comedi/comedi_buf.c @@ -273,19 +273,8 @@ unsigned int comedi_buf_write_n_available(struct comedi_subdevice *s) return free_end - async->buf_write_count; } -/** - * comedi_buf_write_alloc() - Reserve buffer space for writing - * @s: COMEDI subdevice. - * @nbytes: Maximum space to reserve in bytes. - * - * Reserve up to @nbytes bytes of space to be written in the COMEDI acquisition - * data buffer associated with the subdevice. The amount reserved is limited - * by the space available. - * - * Return: The amount of space reserved in bytes. - */ -unsigned int comedi_buf_write_alloc(struct comedi_subdevice *s, - unsigned int nbytes) +unsigned int _comedi_buf_write_alloc(struct comedi_subdevice *s, + unsigned int nbytes) { struct comedi_async *async = s->async; unsigned int unalloc = comedi_buf_write_n_unalloc(s); @@ -303,6 +292,29 @@ unsigned int comedi_buf_write_alloc(struct comedi_subdevice *s, return nbytes; } + +/** + * comedi_buf_write_alloc() - Reserve buffer space for writing + * @s: COMEDI subdevice. + * @nbytes: Maximum space to reserve in bytes. + * + * Reserve up to @nbytes bytes of space to be written in the COMEDI acquisition + * data buffer associated with the subdevice. The amount reserved is limited + * by the space available. + * + * Return: The amount of space reserved in bytes. + */ +unsigned int comedi_buf_write_alloc(struct comedi_subdevice *s, + unsigned int nbytes) +{ + if (comedi_get_is_subdevice_running(s)) { + nbytes = _comedi_buf_write_alloc(s, nbytes); + comedi_put_is_subdevice_running(s); + } else { + nbytes = 0; + } + return nbytes; +} EXPORT_SYMBOL_GPL(comedi_buf_write_alloc); /* @@ -362,6 +374,24 @@ unsigned int comedi_buf_write_n_allocated(struct comedi_subdevice *s) return async->buf_write_alloc_count - async->buf_write_count; } +unsigned int _comedi_buf_write_free(struct comedi_subdevice *s, + unsigned int nbytes) +{ + struct comedi_async *async = s->async; + unsigned int allocated = comedi_buf_write_n_allocated(s); + + if (nbytes > allocated) + nbytes = allocated; + + async->buf_write_count += nbytes; + async->buf_write_ptr += nbytes; + comedi_buf_munge(s, async->buf_write_count - async->munge_count); + if (async->buf_write_ptr >= async->prealloc_bufsz) + async->buf_write_ptr %= async->prealloc_bufsz; + + return nbytes; +} + /** * comedi_buf_write_free() - Free buffer space after it is written * @s: COMEDI subdevice. @@ -380,34 +410,17 @@ unsigned int comedi_buf_write_n_allocated(struct comedi_subdevice *s) unsigned int comedi_buf_write_free(struct comedi_subdevice *s, unsigned int nbytes) { - struct comedi_async *async = s->async; - unsigned int allocated = comedi_buf_write_n_allocated(s); - - if (nbytes > allocated) - nbytes = allocated; - - async->buf_write_count += nbytes; - async->buf_write_ptr += nbytes; - comedi_buf_munge(s, async->buf_write_count - async->munge_count); - if (async->buf_write_ptr >= async->prealloc_bufsz) - async->buf_write_ptr %= async->prealloc_bufsz; - + if (comedi_get_is_subdevice_running(s)) { + nbytes = _comedi_buf_write_free(s, nbytes); + comedi_put_is_subdevice_running(s); + } else { + nbytes = 0; + } return nbytes; } EXPORT_SYMBOL_GPL(comedi_buf_write_free); -/** - * comedi_buf_read_n_available() - Determine amount of readable buffer space - * @s: COMEDI subdevice. - * - * Determine the amount of readable buffer space in the COMEDI acquisition data - * buffer associated with the subdevice. The readable buffer space is that - * which has been freed by the writer and "munged" to the sample data format - * expected by COMEDI if necessary. - * - * Return: The amount of readable buffer space. - */ -unsigned int comedi_buf_read_n_available(struct comedi_subdevice *s) +unsigned int _comedi_buf_read_n_available(struct comedi_subdevice *s) { struct comedi_async *async = s->async; unsigned int num_bytes; @@ -425,8 +438,53 @@ unsigned int comedi_buf_read_n_available(struct comedi_subdevice *s) return num_bytes; } + +/** + * comedi_buf_read_n_available() - Determine amount of readable buffer space + * @s: COMEDI subdevice. + * + * Determine the amount of readable buffer space in the COMEDI acquisition data + * buffer associated with the subdevice. The readable buffer space is that + * which has been freed by the writer and "munged" to the sample data format + * expected by COMEDI if necessary. + * + * Return: The amount of readable buffer space. + */ +unsigned int comedi_buf_read_n_available(struct comedi_subdevice *s) +{ + unsigned int num_bytes; + + if (comedi_get_is_subdevice_running(s)) { + num_bytes = _comedi_buf_read_n_available(s); + comedi_put_is_subdevice_running(s); + } else { + num_bytes = 0; + } + return num_bytes; +} EXPORT_SYMBOL_GPL(comedi_buf_read_n_available); +unsigned int _comedi_buf_read_alloc(struct comedi_subdevice *s, + unsigned int nbytes) +{ + struct comedi_async *async = s->async; + unsigned int available; + + available = async->munge_count - async->buf_read_alloc_count; + if (nbytes > available) + nbytes = available; + + async->buf_read_alloc_count += nbytes; + + /* + * ensure the async buffer 'counts' are read before we + * attempt to read data from the read-alloc'ed buffer space + */ + smp_rmb(); + + return nbytes; +} + /** * comedi_buf_read_alloc() - Reserve buffer space for reading * @s: COMEDI subdevice. @@ -445,21 +503,12 @@ EXPORT_SYMBOL_GPL(comedi_buf_read_n_available); unsigned int comedi_buf_read_alloc(struct comedi_subdevice *s, unsigned int nbytes) { - struct comedi_async *async = s->async; - unsigned int available; - - available = async->munge_count - async->buf_read_alloc_count; - if (nbytes > available) - nbytes = available; - - async->buf_read_alloc_count += nbytes; - - /* - * ensure the async buffer 'counts' are read before we - * attempt to read data from the read-alloc'ed buffer space - */ - smp_rmb(); - + if (comedi_get_is_subdevice_running(s)) { + nbytes = _comedi_buf_read_alloc(s, nbytes); + comedi_put_is_subdevice_running(s); + } else { + nbytes = 0; + } return nbytes; } EXPORT_SYMBOL_GPL(comedi_buf_read_alloc); @@ -469,6 +518,28 @@ static unsigned int comedi_buf_read_n_allocated(struct comedi_async *async) return async->buf_read_alloc_count - async->buf_read_count; } +unsigned int _comedi_buf_read_free(struct comedi_subdevice *s, + unsigned int nbytes) +{ + struct comedi_async *async = s->async; + unsigned int allocated; + + /* + * ensure data has been read out of buffer before + * the async read count is incremented + */ + smp_mb(); + + allocated = comedi_buf_read_n_allocated(async); + if (nbytes > allocated) + nbytes = allocated; + + async->buf_read_count += nbytes; + async->buf_read_ptr += nbytes; + async->buf_read_ptr %= async->prealloc_bufsz; + return nbytes; +} + /** * comedi_buf_read_free() - Free buffer space after it has been read * @s: COMEDI subdevice. @@ -485,22 +556,12 @@ static unsigned int comedi_buf_read_n_allocated(struct comedi_async *async) unsigned int comedi_buf_read_free(struct comedi_subdevice *s, unsigned int nbytes) { - struct comedi_async *async = s->async; - unsigned int allocated; - - /* - * ensure data has been read out of buffer before - * the async read count is incremented - */ - smp_mb(); - - allocated = comedi_buf_read_n_allocated(async); - if (nbytes > allocated) - nbytes = allocated; - - async->buf_read_count += nbytes; - async->buf_read_ptr += nbytes; - async->buf_read_ptr %= async->prealloc_bufsz; + if (comedi_get_is_subdevice_running(s)) { + nbytes = _comedi_buf_read_free(s, nbytes); + comedi_put_is_subdevice_running(s); + } else { + nbytes = 0; + } return nbytes; } EXPORT_SYMBOL_GPL(comedi_buf_read_free); @@ -558,6 +619,38 @@ static void comedi_buf_memcpy_from(struct comedi_subdevice *s, } } +static unsigned int _comedi_buf_write_samples(struct comedi_subdevice *s, + const void *data, + unsigned int nsamples) +{ + unsigned int max_samples; + unsigned int nbytes; + + /* + * Make sure there is enough room in the buffer for all the samples. + * If not, clamp the nsamples to the number that will fit, flag the + * buffer overrun and add the samples that fit. + */ + max_samples = comedi_bytes_to_samples(s, comedi_buf_write_n_unalloc(s)); + if (nsamples > max_samples) { + dev_warn(s->device->class_dev, "buffer overrun\n"); + s->async->events |= COMEDI_CB_OVERFLOW; + nsamples = max_samples; + } + + if (nsamples == 0) + return 0; + + nbytes = comedi_samples_to_bytes(s, nsamples); + nbytes = _comedi_buf_write_alloc(s, nbytes); + comedi_buf_memcpy_to(s, data, nbytes); + _comedi_buf_write_free(s, nbytes); + _comedi_inc_scan_progress(s, nbytes); + s->async->events |= COMEDI_CB_BLOCK; + + return nbytes; +} + /** * comedi_buf_write_samples() - Write sample data to COMEDI buffer * @s: COMEDI subdevice. @@ -577,35 +670,43 @@ static void comedi_buf_memcpy_from(struct comedi_subdevice *s, */ unsigned int comedi_buf_write_samples(struct comedi_subdevice *s, const void *data, unsigned int nsamples) +{ + unsigned int nbytes; + + if (comedi_get_is_subdevice_running(s)) { + nbytes = _comedi_buf_write_samples(s, data, nsamples); + comedi_put_is_subdevice_running(s); + } else { + nbytes = 0; + } + return nbytes; +} +EXPORT_SYMBOL_GPL(comedi_buf_write_samples); + +static unsigned int _comedi_buf_read_samples(struct comedi_subdevice *s, + void *data, unsigned int nsamples) { unsigned int max_samples; unsigned int nbytes; - /* - * Make sure there is enough room in the buffer for all the samples. - * If not, clamp the nsamples to the number that will fit, flag the - * buffer overrun and add the samples that fit. - */ - max_samples = comedi_bytes_to_samples(s, comedi_buf_write_n_unalloc(s)); - if (nsamples > max_samples) { - dev_warn(s->device->class_dev, "buffer overrun\n"); - s->async->events |= COMEDI_CB_OVERFLOW; + /* clamp nsamples to the number of full samples available */ + max_samples = comedi_bytes_to_samples(s, + _comedi_buf_read_n_available(s)); + if (nsamples > max_samples) nsamples = max_samples; - } if (nsamples == 0) return 0; - nbytes = comedi_buf_write_alloc(s, + nbytes = _comedi_buf_read_alloc(s, comedi_samples_to_bytes(s, nsamples)); - comedi_buf_memcpy_to(s, data, nbytes); - comedi_buf_write_free(s, nbytes); - comedi_inc_scan_progress(s, nbytes); + comedi_buf_memcpy_from(s, data, nbytes); + _comedi_buf_read_free(s, nbytes); + _comedi_inc_scan_progress(s, nbytes); s->async->events |= COMEDI_CB_BLOCK; return nbytes; } -EXPORT_SYMBOL_GPL(comedi_buf_write_samples); /** * comedi_buf_read_samples() - Read sample data from COMEDI buffer @@ -624,25 +725,14 @@ EXPORT_SYMBOL_GPL(comedi_buf_write_samples); unsigned int comedi_buf_read_samples(struct comedi_subdevice *s, void *data, unsigned int nsamples) { - unsigned int max_samples; unsigned int nbytes; - /* clamp nsamples to the number of full samples available */ - max_samples = comedi_bytes_to_samples(s, - comedi_buf_read_n_available(s)); - if (nsamples > max_samples) - nsamples = max_samples; - - if (nsamples == 0) - return 0; - - nbytes = comedi_buf_read_alloc(s, - comedi_samples_to_bytes(s, nsamples)); - comedi_buf_memcpy_from(s, data, nbytes); - comedi_buf_read_free(s, nbytes); - comedi_inc_scan_progress(s, nbytes); - s->async->events |= COMEDI_CB_BLOCK; - + if (comedi_get_is_subdevice_running(s)) { + nbytes = _comedi_buf_read_samples(s, data, nsamples); + comedi_put_is_subdevice_running(s); + } else { + nbytes = 0; + } return nbytes; } EXPORT_SYMBOL_GPL(comedi_buf_read_samples); diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c index 8253e4e8232b..657c98cd723e 100644 --- a/drivers/comedi/comedi_fops.c +++ b/drivers/comedi/comedi_fops.c @@ -1206,15 +1206,15 @@ static int do_bufinfo_ioctl(struct comedi_device *dev, if (!(async->cmd.flags & CMDF_WRITE)) { /* command was set up in "read" direction */ if (bi.bytes_read) { - comedi_buf_read_alloc(s, bi.bytes_read); - bi.bytes_read = comedi_buf_read_free(s, bi.bytes_read); + _comedi_buf_read_alloc(s, bi.bytes_read); + bi.bytes_read = _comedi_buf_read_free(s, bi.bytes_read); } /* * If nothing left to read, and command has stopped, and * {"read" position not updated or command stopped normally}, * then become non-busy. */ - if (comedi_buf_read_n_available(s) == 0 && + if (_comedi_buf_read_n_available(s) == 0 && !comedi_is_runflags_running(runflags) && (bi.bytes_read == 0 || !comedi_is_runflags_in_error(runflags))) { @@ -1231,9 +1231,9 @@ static int do_bufinfo_ioctl(struct comedi_device *dev, if (comedi_is_runflags_in_error(runflags)) retval = -EPIPE; } else if (bi.bytes_written) { - comedi_buf_write_alloc(s, bi.bytes_written); + _comedi_buf_write_alloc(s, bi.bytes_written); bi.bytes_written = - comedi_buf_write_free(s, bi.bytes_written); + _comedi_buf_write_free(s, bi.bytes_written); } bi.bytes_read = 0; } @@ -2569,7 +2569,7 @@ static __poll_t comedi_poll(struct file *file, poll_table *wait) poll_wait(file, &s->async->wait_head, wait); if (s->busy != file || !comedi_is_subdevice_running(s) || (s->async->cmd.flags & CMDF_WRITE) || - comedi_buf_read_n_available(s) > 0) + _comedi_buf_read_n_available(s) > 0) mask |= EPOLLIN | EPOLLRDNORM; } @@ -2702,7 +2702,7 @@ static ssize_t comedi_write(struct file *file, const char __user *buf, break; /* Allocate all free buffer space. */ - comedi_buf_write_alloc(s, async->prealloc_bufsz); + _comedi_buf_write_alloc(s, async->prealloc_bufsz); m = comedi_buf_write_n_allocated(s); n = min_t(size_t, m, nbytes); @@ -2730,7 +2730,7 @@ static ssize_t comedi_write(struct file *file, const char __user *buf, n -= m; retval = -EFAULT; } - comedi_buf_write_free(s, n); + _comedi_buf_write_free(s, n); count += n; nbytes -= n; @@ -2816,7 +2816,7 @@ static ssize_t comedi_read(struct file *file, char __user *buf, size_t nbytes, while (count == 0 && !retval) { set_current_state(TASK_INTERRUPTIBLE); - m = comedi_buf_read_n_available(s); + m = _comedi_buf_read_n_available(s); n = min_t(size_t, m, nbytes); if (n == 0) { @@ -2856,8 +2856,8 @@ static ssize_t comedi_read(struct file *file, char __user *buf, size_t nbytes, retval = -EFAULT; } - comedi_buf_read_alloc(s, n); - comedi_buf_read_free(s, n); + _comedi_buf_read_alloc(s, n); + _comedi_buf_read_free(s, n); count += n; nbytes -= n; @@ -2891,7 +2891,7 @@ static ssize_t comedi_read(struct file *file, char __user *buf, size_t nbytes, s == new_s && new_s->async == async && s->busy == file && !(async->cmd.flags & CMDF_WRITE) && !comedi_is_subdevice_running(s) && - comedi_buf_read_n_available(s) == 0) + _comedi_buf_read_n_available(s) == 0) do_become_nonbusy(dev, s); mutex_unlock(&dev->mutex); } @@ -3386,18 +3386,7 @@ static const struct file_operations comedi_fops = { .llseek = noop_llseek, }; -/** - * comedi_event() - Handle events for asynchronous COMEDI command - * @dev: COMEDI device. - * @s: COMEDI subdevice. - * Context: in_interrupt() (usually), @s->spin_lock spin-lock not held. - * - * If an asynchronous COMEDI command is active on the subdevice, process - * any %COMEDI_CB_... event flags that have been set, usually by an - * interrupt handler. These may change the run state of the asynchronous - * command, wake a task, and/or send a %SIGIO signal. - */ -void comedi_event(struct comedi_device *dev, struct comedi_subdevice *s) +void _comedi_event(struct comedi_device *dev, struct comedi_subdevice *s) { struct comedi_async *async = s->async; unsigned int events; @@ -3433,6 +3422,25 @@ void comedi_event(struct comedi_device *dev, struct comedi_subdevice *s) if (si_code) kill_fasync(&dev->async_queue, SIGIO, si_code); } + +/** + * comedi_event() - Handle events for asynchronous COMEDI command + * @dev: COMEDI device. + * @s: COMEDI subdevice. + * Context: in_interrupt() (usually), @s->spin_lock spin-lock not held. + * + * If an asynchronous COMEDI command is active on the subdevice, process + * any %COMEDI_CB_... event flags that have been set, usually by an + * interrupt handler. These may change the run state of the asynchronous + * command, wake a task, and/or send a %SIGIO signal. + */ +void comedi_event(struct comedi_device *dev, struct comedi_subdevice *s) +{ + if (comedi_get_is_subdevice_running(s)) { + comedi_event(dev, s); + comedi_put_is_subdevice_running(s); + } +} EXPORT_SYMBOL_GPL(comedi_event); /* Note: the ->mutex is pre-locked on successful return */ diff --git a/drivers/comedi/comedi_internal.h b/drivers/comedi/comedi_internal.h index cf10ba016ebc..41a3b09f8f05 100644 --- a/drivers/comedi/comedi_internal.h +++ b/drivers/comedi/comedi_internal.h @@ -36,6 +36,18 @@ struct comedi_buf_map * comedi_buf_map_from_subdev_get(struct comedi_subdevice *s); unsigned int comedi_buf_write_n_available(struct comedi_subdevice *s); unsigned int comedi_buf_write_n_allocated(struct comedi_subdevice *s); +unsigned int _comedi_buf_write_alloc(struct comedi_subdevice *s, + unsigned int nbytes); +unsigned int _comedi_buf_write_free(struct comedi_subdevice *s, + unsigned int nbytes); +unsigned int _comedi_buf_read_n_available(struct comedi_subdevice *s); +unsigned int _comedi_buf_read_alloc(struct comedi_subdevice *s, + unsigned int nbytes); +unsigned int _comedi_buf_read_free(struct comedi_subdevice *s, + unsigned int nbytes); +void _comedi_inc_scan_progress(struct comedi_subdevice *s, + unsigned int num_bytes); +void _comedi_event(struct comedi_device *dev, struct comedi_subdevice *s); void comedi_device_cancel_all(struct comedi_device *dev); bool comedi_can_auto_free_spriv(struct comedi_subdevice *s); diff --git a/drivers/comedi/drivers.c b/drivers/comedi/drivers.c index fd6e6cbe47ad..69cd2a253c66 100644 --- a/drivers/comedi/drivers.c +++ b/drivers/comedi/drivers.c @@ -441,6 +441,13 @@ unsigned int comedi_bytes_per_scan_cmd(struct comedi_subdevice *s, } EXPORT_SYMBOL_GPL(comedi_bytes_per_scan_cmd); +static unsigned int _comedi_bytes_per_scan(struct comedi_subdevice *s) +{ + struct comedi_cmd *cmd = &s->async->cmd; + + return comedi_bytes_per_scan_cmd(s, cmd); +} + /** * comedi_bytes_per_scan() - Get length of asynchronous command "scan" in bytes * @s: COMEDI subdevice. @@ -458,9 +465,16 @@ EXPORT_SYMBOL_GPL(comedi_bytes_per_scan_cmd); */ unsigned int comedi_bytes_per_scan(struct comedi_subdevice *s) { - struct comedi_cmd *cmd = &s->async->cmd; + unsigned int num_bytes; - return comedi_bytes_per_scan_cmd(s, cmd); + if (comedi_get_is_subdevice_running(s)) { + num_bytes = _comedi_bytes_per_scan(s); + comedi_put_is_subdevice_running(s); + } else { + /* Use nomimal, single sample scan length. */ + num_bytes = comedi_samples_to_bytes(s, 1); + } + return num_bytes; } EXPORT_SYMBOL_GPL(comedi_bytes_per_scan); @@ -482,6 +496,17 @@ static unsigned int __comedi_nscans_left(struct comedi_subdevice *s, return nscans; } +static unsigned int _comedi_nscans_left(struct comedi_subdevice *s, + unsigned int nscans) +{ + if (nscans == 0) { + unsigned int nbytes = _comedi_buf_read_n_available(s); + + nscans = nbytes / _comedi_bytes_per_scan(s); + } + return __comedi_nscans_left(s, nscans); +} + /** * comedi_nscans_left() - Return the number of scans left in the command * @s: COMEDI subdevice. @@ -499,25 +524,18 @@ static unsigned int __comedi_nscans_left(struct comedi_subdevice *s, unsigned int comedi_nscans_left(struct comedi_subdevice *s, unsigned int nscans) { - if (nscans == 0) { - unsigned int nbytes = comedi_buf_read_n_available(s); - - nscans = nbytes / comedi_bytes_per_scan(s); + if (comedi_get_is_subdevice_running(s)) { + nscans = _comedi_nscans_left(s, nscans); + comedi_put_is_subdevice_running(s); + } else { + nscans = 0; } - return __comedi_nscans_left(s, nscans); + return nscans; } EXPORT_SYMBOL_GPL(comedi_nscans_left); -/** - * comedi_nsamples_left() - Return the number of samples left in the command - * @s: COMEDI subdevice. - * @nsamples: The expected number of samples. - * - * Returns the number of samples remaining to complete the command, or the - * specified expected number of samples (@nsamples), whichever is fewer. - */ -unsigned int comedi_nsamples_left(struct comedi_subdevice *s, - unsigned int nsamples) +static unsigned int _comedi_nsamples_left(struct comedi_subdevice *s, + unsigned int nsamples) { struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; @@ -538,24 +556,34 @@ unsigned int comedi_nsamples_left(struct comedi_subdevice *s, return samples_left; return nsamples; } -EXPORT_SYMBOL_GPL(comedi_nsamples_left); /** - * comedi_inc_scan_progress() - Update scan progress in asynchronous command + * comedi_nsamples_left() - Return the number of samples left in the command * @s: COMEDI subdevice. - * @num_bytes: Amount of data in bytes to increment scan progress. + * @nsamples: The expected number of samples. * - * Increments the scan progress by the number of bytes specified by @num_bytes. - * If the scan progress reaches or exceeds the scan length in bytes, reduce - * it modulo the scan length in bytes and set the "end of scan" asynchronous - * event flag (%COMEDI_CB_EOS) to be processed later. + * Returns the number of samples remaining to complete the command, or the + * specified expected number of samples (@nsamples), whichever is fewer. */ -void comedi_inc_scan_progress(struct comedi_subdevice *s, - unsigned int num_bytes) +unsigned int comedi_nsamples_left(struct comedi_subdevice *s, + unsigned int nsamples) +{ + if (comedi_get_is_subdevice_running(s)) { + nsamples = _comedi_nsamples_left(s, nsamples); + comedi_put_is_subdevice_running(s); + } else { + nsamples = 0; + } + return nsamples; +} +EXPORT_SYMBOL_GPL(comedi_nsamples_left); + +void _comedi_inc_scan_progress(struct comedi_subdevice *s, + unsigned int num_bytes) { struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; - unsigned int scan_length = comedi_bytes_per_scan(s); + unsigned int scan_length = _comedi_bytes_per_scan(s); /* track the 'cur_chan' for non-SDF_PACKED subdevices */ if (!(s->subdev_flags & SDF_PACKED)) { @@ -576,8 +604,43 @@ void comedi_inc_scan_progress(struct comedi_subdevice *s, async->events |= COMEDI_CB_EOS; } } + +/** + * comedi_inc_scan_progress() - Update scan progress in asynchronous command + * @s: COMEDI subdevice. + * @num_bytes: Amount of data in bytes to increment scan progress. + * + * Increments the scan progress by the number of bytes specified by @num_bytes. + * If the scan progress reaches or exceeds the scan length in bytes, reduce + * it modulo the scan length in bytes and set the "end of scan" asynchronous + * event flag (%COMEDI_CB_EOS) to be processed later. + */ +void comedi_inc_scan_progress(struct comedi_subdevice *s, + unsigned int num_bytes) +{ + if (comedi_get_is_subdevice_running(s)) { + _comedi_inc_scan_progress(s, num_bytes); + comedi_put_is_subdevice_running(s); + } +} EXPORT_SYMBOL_GPL(comedi_inc_scan_progress); +static unsigned int _comedi_handle_events(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + unsigned int events = s->async->events; + + if (events == 0) + return events; + + if ((events & COMEDI_CB_CANCEL_MASK) && s->cancel) + s->cancel(dev, s); + + _comedi_event(dev, s); + + return events; +} + /** * comedi_handle_events() - Handle events and possibly stop acquisition * @dev: COMEDI device. @@ -597,16 +660,14 @@ EXPORT_SYMBOL_GPL(comedi_inc_scan_progress); unsigned int comedi_handle_events(struct comedi_device *dev, struct comedi_subdevice *s) { - unsigned int events = s->async->events; - - if (events == 0) - return events; - - if ((events & COMEDI_CB_CANCEL_MASK) && s->cancel) - s->cancel(dev, s); - - comedi_event(dev, s); + unsigned int events; + if (comedi_get_is_subdevice_running(s)) { + events = _comedi_handle_events(dev, s); + comedi_put_is_subdevice_running(s); + } else { + events = 0; + } return events; } EXPORT_SYMBOL_GPL(comedi_handle_events); From d1b3b9c70e11cb4f40b4e41a4dc1503b9a3c0109 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Mon, 27 Oct 2025 15:25:02 +0000 Subject: [PATCH 280/304] comedi: kcomedilib: Add loop checking variants of open and close Add `comedi_open_from(path, from)` and `comedi_close_from(dev, from)` as variants of the existing `comedi_from(path)` and `comedi_close(dev)`. The additional `from` parameter is a minor device number that tells the function that the COMEDI device is being opened or closed from another COMEDI device if the value is in the range [0, `COMEDI_NUM_BOARD_MINORS`-1]. In that case the function will refuse to open the device if it would lead to a chain of devices opening each other. (It will also impose a limit on the number of simultaneous opens from one device to another because we need to count those.) The new functions are intended to be used by the "comedi_bond" driver, which is the only driver that uses the existing `comedi_open()` and `comedi_close()` functions. The new functions will be used to avoid some possible deadlock situations. Replace the existing, exported `comedi_open()` and `comedi_close()` functions with inline wrapper functions that call the newly exported `comedi_open_from()` and `comedi_close_from()` functions. Signed-off-by: Ian Abbott Link: https://patch.msgid.link/20251027153748.4569-2-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/kcomedilib/kcomedilib_main.c | 120 +++++++++++++++++++- include/linux/comedi/comedilib.h | 34 +++++- 2 files changed, 147 insertions(+), 7 deletions(-) diff --git a/drivers/comedi/kcomedilib/kcomedilib_main.c b/drivers/comedi/kcomedilib/kcomedilib_main.c index 43fbe1a63b14..baa9eaaf97d4 100644 --- a/drivers/comedi/kcomedilib/kcomedilib_main.c +++ b/drivers/comedi/kcomedilib/kcomedilib_main.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -24,7 +25,104 @@ MODULE_AUTHOR("David Schleef "); MODULE_DESCRIPTION("Comedi kernel library"); MODULE_LICENSE("GPL"); -struct comedi_device *comedi_open(const char *filename) +static DEFINE_MUTEX(kcomedilib_to_from_lock); + +/* + * Row index is the "to" node, column index is the "from" node, element value + * is the number of links from the "from" node to the "to" node. + */ +static unsigned char + kcomedilib_to_from[COMEDI_NUM_BOARD_MINORS][COMEDI_NUM_BOARD_MINORS]; + +static bool kcomedilib_set_link_from_to(unsigned int from, unsigned int to) +{ + DECLARE_BITMAP(destinations[2], COMEDI_NUM_BOARD_MINORS); + unsigned int cur = 0; + bool okay = true; + + /* + * Allow "from" node to be out of range (no loop checking), + * but require "to" node to be in range. + */ + if (to >= COMEDI_NUM_BOARD_MINORS) + return false; + if (from >= COMEDI_NUM_BOARD_MINORS) + return true; + + /* + * Check that kcomedilib_to_from[to][from] can be made non-zero + * without creating a loop. + * + * Termination of the loop-testing code relies on the assumption that + * kcomedilib_to_from[][] does not contain any loops. + * + * Start with a set destinations set containing "from" as the only + * element and work backwards looking for loops. + */ + bitmap_zero(destinations[cur], COMEDI_NUM_BOARD_MINORS); + set_bit(from, destinations[cur]); + mutex_lock(&kcomedilib_to_from_lock); + do { + unsigned int next = 1 - cur; + unsigned int t = 0; + + if (test_bit(to, destinations[cur])) { + /* Loop detected. */ + okay = false; + break; + } + /* Create next set of destinations. */ + bitmap_zero(destinations[next], COMEDI_NUM_BOARD_MINORS); + while ((t = find_next_bit(destinations[cur], + COMEDI_NUM_BOARD_MINORS, + t)) < COMEDI_NUM_BOARD_MINORS) { + unsigned int f; + + for (f = 0; f < COMEDI_NUM_BOARD_MINORS; f++) { + if (kcomedilib_to_from[t][f]) + set_bit(f, destinations[next]); + } + t++; + } + cur = next; + } while (!bitmap_empty(destinations[cur], COMEDI_NUM_BOARD_MINORS)); + if (okay) { + /* Allow a maximum of 255 links from "from" to "to". */ + if (kcomedilib_to_from[to][from] < 255) + kcomedilib_to_from[to][from]++; + else + okay = false; + } + mutex_unlock(&kcomedilib_to_from_lock); + return okay; +} + +static void kcomedilib_clear_link_from_to(unsigned int from, unsigned int to) +{ + if (to < COMEDI_NUM_BOARD_MINORS && from < COMEDI_NUM_BOARD_MINORS) { + mutex_lock(&kcomedilib_to_from_lock); + if (kcomedilib_to_from[to][from]) + kcomedilib_to_from[to][from]--; + mutex_unlock(&kcomedilib_to_from_lock); + } +} + +/** + * comedi_open_from() - Open a COMEDI device from the kernel with loop checks + * @filename: Fake pathname of the form "/dev/comediN". + * @from: Device number it is being opened from (if in range). + * + * Converts @filename to a COMEDI device number and "opens" it if it exists + * and is attached to a low-level COMEDI driver. + * + * If @from is in range, refuse to open the device if doing so would form a + * loop of devices opening each other. There is also a limit of 255 on the + * number of concurrent opens from one device to another. + * + * Return: A pointer to the COMEDI device on success. + * Return %NULL on failure. + */ +struct comedi_device *comedi_open_from(const char *filename, int from) { struct comedi_device *dev, *retval = NULL; unsigned int minor; @@ -43,7 +141,7 @@ struct comedi_device *comedi_open(const char *filename) return NULL; down_read(&dev->attach_lock); - if (dev->attached) + if (dev->attached && kcomedilib_set_link_from_to(from, minor)) retval = dev; else retval = NULL; @@ -54,14 +152,26 @@ struct comedi_device *comedi_open(const char *filename) return retval; } -EXPORT_SYMBOL_GPL(comedi_open); +EXPORT_SYMBOL_GPL(comedi_open_from); -int comedi_close(struct comedi_device *dev) +/** + * comedi_close_from() - Close a COMEDI device from the kernel with loop checks + * @dev: COMEDI device. + * @from: Device number it was opened from (if in range). + * + * Closes a COMEDI device previously opened by comedi_open_from(). + * + * If @from is in range, it should be match the one used by comedi_open_from(). + * + * Returns: 0 + */ +int comedi_close_from(struct comedi_device *dev, int from) { + kcomedilib_clear_link_from_to(from, dev->minor); comedi_dev_put(dev); return 0; } -EXPORT_SYMBOL_GPL(comedi_close); +EXPORT_SYMBOL_GPL(comedi_close_from); static int comedi_do_insn(struct comedi_device *dev, struct comedi_insn *insn, diff --git a/include/linux/comedi/comedilib.h b/include/linux/comedi/comedilib.h index 0223c9cd9215..1f2b22b383cc 100644 --- a/include/linux/comedi/comedilib.h +++ b/include/linux/comedi/comedilib.h @@ -10,8 +10,38 @@ #ifndef _LINUX_COMEDILIB_H #define _LINUX_COMEDILIB_H -struct comedi_device *comedi_open(const char *path); -int comedi_close(struct comedi_device *dev); +struct comedi_device *comedi_open_from(const char *path, int from); + +/** + * comedi_open() - Open a COMEDI device from the kernel + * @filename: Fake pathname of the form "/dev/comediN". + * + * Converts @filename to a COMEDI device number and "opens" it if it exists + * and is attached to a low-level COMEDI driver. + * + * Return: A pointer to the COMEDI device on success. + * Return %NULL on failure. + */ +static inline struct comedi_device *comedi_open(const char *path) +{ + return comedi_open_from(path, -1); +} + +int comedi_close_from(struct comedi_device *dev, int from); + +/** + * comedi_close() - Close a COMEDI device from the kernel + * @dev: COMEDI device. + * + * Closes a COMEDI device previously opened by comedi_open(). + * + * Returns: 0 + */ +static inline int comedi_close(struct comedi_device *dev) +{ + return comedi_close_from(dev, -1); +} + int comedi_dio_get_config(struct comedi_device *dev, unsigned int subdev, unsigned int chan, unsigned int *io); int comedi_dio_config(struct comedi_device *dev, unsigned int subdev, From 2402f958cf3b2e96975ad5fd14784a108b7defe3 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Mon, 27 Oct 2025 15:25:03 +0000 Subject: [PATCH 281/304] comedi: comedi_bond: Check for loops when bonding devices The "comedi_bond" driver allows a composite COMEDI device to be built up from the subdevices of other COMEDI devices, although it currently only supports digital I/O subdevices. Although it checks that it is not trying to bind to itself, it is possible to end up with a cycle of "comedi_bond" devices bound to each other. For example: 1. Configure /dev/comedi0 to use some COMEDI hardware device with digital I/O subdevices, but not a "comedi_bond" device. 2. Configure /dev/comedi1 as a "comedi_bond" device bound to /dev/comedi0. 3. Unconfigure /dev/comedi0 and reconfigure it as a "comedi_bond" device bound to /dev/comedi1. Now we have /dev/comedi0 and /dev/comedi1 bound in a cycle. When an operation is performed on the digital I/O subdevice of /dev/comedi0 for example, it will try and perform the operation on /dev/comedi1, which will try and perform the operation on /dev/comedi0. The task will end up deadlocked trying to lock /dev/comedi0's mutex which it has already locked. I discovered that possibility while investigating fix sysbot crash https://syzkaller.appspot.com/bug?extid=4a6138c17a47937dcea1 ("possible deadlock in comedi_do_insn"), but I think that report may be a false positive. To avoid that, replace the calls to `comedi_open()` and `comedi_close()` in "kcomedilib" with calls to `comedi_open_from()` and `comedi_close_from()`. These take an extra parameter that indicates the COMEDI minor device number from which the open or close is being performed. `comedi_open_from()` will refuse to open the device if doing so would result in a cycle. The cycle detection depends on the extra parameter having the correct value for this device and also for existing devices in the chain. Signed-off-by: Ian Abbott Link: https://patch.msgid.link/20251027153748.4569-3-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/drivers/comedi_bond.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/comedi/drivers/comedi_bond.c b/drivers/comedi/drivers/comedi_bond.c index 78c39fa84177..30650fa36fff 100644 --- a/drivers/comedi/drivers/comedi_bond.c +++ b/drivers/comedi/drivers/comedi_bond.c @@ -205,7 +205,7 @@ static int do_dev_config(struct comedi_device *dev, struct comedi_devconfig *it) snprintf(file, sizeof(file), "/dev/comedi%d", minor); file[sizeof(file) - 1] = 0; - d = comedi_open(file); + d = comedi_open_from(file, dev->minor); if (!d) { dev_err(dev->class_dev, @@ -326,7 +326,7 @@ static void bonding_detach(struct comedi_device *dev) if (!bdev) continue; if (!test_and_set_bit(bdev->minor, devs_closed)) - comedi_close(bdev->dev); + comedi_close_from(bdev->dev, dev->minor); kfree(bdev); } kfree(devpriv->devs); From 98d86d87aafb01e7c60b46d327a0a32619a167ff Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Tue, 28 Oct 2025 11:28:33 +0000 Subject: [PATCH 282/304] comedi: 8255: Fail to attach if fail to request I/O port region The COMEDI standalone 8255 driver can be used to configure a COMEDI device consisting of one of more subdevices, each using an 8255 digital I/O chip mapped to a range of port I/O addresses. The base port I/O address of each chip is specified in an array of integer option values by the `COMEDI_DEVCONFIG` ioctl. When support for multiple 8255 subdevices per device was added in the out-of-tree comedi 0.7.27 back in 1999, if any port I/O region could not be requested, then the corresponding subdevice was set to be an "unused" subdevice, and the COMEDI device would still be set-up OK as long as those were the only types of errors. That has persisted until the present day, but seems a bit odd in retrospect. All the other COMEDI drivers that use port I/O or memory regions will fail to set up the device if any region cannot be requested. It seems unlikely that the sys admin would deliberately choose a port that cannot be requested just to leave a gap in the device's usable subdevice numbers, and failing to set-up the device will provide a more noticeable indication that something hasn't been set-up correctly, so change the driver to fail to set up the device if any of the port I/O regions cannot be requested. Signed-off-by: Ian Abbott Link: https://patch.msgid.link/20251028112833.15033-1-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/comedi/drivers/8255.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/comedi/drivers/8255.c b/drivers/comedi/drivers/8255.c index f45f7bd1c61a..5f70938b4477 100644 --- a/drivers/comedi/drivers/8255.c +++ b/drivers/comedi/drivers/8255.c @@ -77,19 +77,17 @@ static int dev_8255_attach(struct comedi_device *dev, * base address of the chip. */ ret = __comedi_request_region(dev, iobase, I8255_SIZE); + if (ret) + return ret; + ret = subdev_8255_io_init(dev, s, iobase); if (ret) { + /* + * Release the I/O port region here, as the + * "detach" handler cannot find it. + */ + release_region(iobase, I8255_SIZE); s->type = COMEDI_SUBD_UNUSED; - } else { - ret = subdev_8255_io_init(dev, s, iobase); - if (ret) { - /* - * Release the I/O port region here, as the - * "detach" handler cannot find it. - */ - release_region(iobase, I8255_SIZE); - s->type = COMEDI_SUBD_UNUSED; - return ret; - } + return ret; } } From 9906efa545d1d2cf25a614eeb219d3f8d5a302cd Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Thu, 6 Nov 2025 11:40:54 +0900 Subject: [PATCH 283/304] firmware_loader: make RUST_FW_LOADER_ABSTRACTIONS select FW_LOADER The use of firmware_loader is an implementation detail of drivers rather than a dependency. FW_LOADER is typically selected rather than depended on; the Rust abstractions should do the same thing. Fixes: de6582833db0 ("rust: add firmware abstractions") Signed-off-by: Alexandre Courbot Link: https://patch.msgid.link/20251106-b4-select-rust-fw-v3-1-771172257755@nvidia.com Signed-off-by: Greg Kroah-Hartman --- drivers/base/firmware_loader/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/firmware_loader/Kconfig b/drivers/base/firmware_loader/Kconfig index 752b9a9bea03..15eff8a4b505 100644 --- a/drivers/base/firmware_loader/Kconfig +++ b/drivers/base/firmware_loader/Kconfig @@ -38,7 +38,7 @@ config FW_LOADER_DEBUG config RUST_FW_LOADER_ABSTRACTIONS bool "Rust Firmware Loader abstractions" depends on RUST - depends on FW_LOADER=y + select FW_LOADER help This enables the Rust abstractions for the firmware loader API. From 3b4d1b226dc5f065bfb685263eb27312287752f9 Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Wed, 19 Nov 2025 10:19:44 +0100 Subject: [PATCH 284/304] char/mwave: remove dead code In mwave, there is a lot of commented code for a long time. Drop it. Signed-off-by: Jiri Slaby (SUSE) Acked-by: Arnd Bergmann Link: https://patch.msgid.link/20251119091949.825958-2-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/char/mwave/3780i.c | 29 ---------------- drivers/char/mwave/mwavedd.c | 67 ------------------------------------ drivers/char/mwave/smapi.c | 22 ------------ 3 files changed, 118 deletions(-) diff --git a/drivers/char/mwave/3780i.c b/drivers/char/mwave/3780i.c index 4a8937f80570..321dbd03d007 100644 --- a/drivers/char/mwave/3780i.c +++ b/drivers/char/mwave/3780i.c @@ -140,35 +140,6 @@ static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex, } -#if 0 -unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO, - unsigned uIndex) -{ - DSP_ISA_SLAVE_CONTROL rSlaveControl; - DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; - unsigned char ucValue; - - - PRINTK_3(TRACE_3780I, - "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n", - usDspBaseIO, uIndex); - - MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); - rSlaveControl_Save = rSlaveControl; - rSlaveControl.ConfigMode = true; - OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); - OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); - ucValue = InByteDsp(DSP_ConfigData); - OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); - - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue); - - - return ucValue; -} -#endif /* 0 */ - int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, unsigned short *pIrqMap, unsigned short *pDmaMap) diff --git a/drivers/char/mwave/mwavedd.c b/drivers/char/mwave/mwavedd.c index 11272d605ecd..86e33c28beac 100644 --- a/drivers/char/mwave/mwavedd.c +++ b/drivers/char/mwave/mwavedd.c @@ -492,42 +492,6 @@ static const struct file_operations mwave_fops = { static struct miscdevice mwave_misc_dev = { MWAVE_MINOR, "mwave", &mwave_fops }; -#if 0 /* totally b0rked */ -/* - * sysfs support - */ - -struct device mwave_device; - -/* Prevent code redundancy, create a macro for mwave_show_* functions. */ -#define mwave_show_function(attr_name, format_string, field) \ -static ssize_t mwave_show_##attr_name(struct device *dev, struct device_attribute *attr, char *buf) \ -{ \ - DSP_3780I_CONFIG_SETTINGS *pSettings = \ - &mwave_s_mdd.rBDData.rDspSettings; \ - return sprintf(buf, format_string, pSettings->field); \ -} - -/* All of our attributes are read attributes. */ -#define mwave_dev_rd_attr(attr_name, format_string, field) \ - mwave_show_function(attr_name, format_string, field) \ -static DEVICE_ATTR(attr_name, S_IRUGO, mwave_show_##attr_name, NULL) - -mwave_dev_rd_attr (3780i_dma, "%i\n", usDspDma); -mwave_dev_rd_attr (3780i_irq, "%i\n", usDspIrq); -mwave_dev_rd_attr (3780i_io, "%#.4x\n", usDspBaseIO); -mwave_dev_rd_attr (uart_irq, "%i\n", usUartIrq); -mwave_dev_rd_attr (uart_io, "%#.4x\n", usUartBaseIO); - -static struct device_attribute * const mwave_dev_attrs[] = { - &dev_attr_3780i_dma, - &dev_attr_3780i_irq, - &dev_attr_3780i_io, - &dev_attr_uart_irq, - &dev_attr_uart_io, -}; -#endif - /* * mwave_init is called on module load * @@ -540,17 +504,6 @@ static void mwave_exit(void) PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_exit entry\n"); -#if 0 - for (i = 0; i < pDrvData->nr_registered_attrs; i++) - device_remove_file(&mwave_device, mwave_dev_attrs[i]); - pDrvData->nr_registered_attrs = 0; - - if (pDrvData->device_registered) { - device_unregister(&mwave_device); - pDrvData->device_registered = false; - } -#endif - if ( pDrvData->sLine >= 0 ) { serial8250_unregister_port(pDrvData->sLine); } @@ -667,26 +620,6 @@ static int __init mwave_init(void) } /* uart is registered */ -#if 0 - /* sysfs */ - memset(&mwave_device, 0, sizeof (struct device)); - dev_set_name(&mwave_device, "mwave"); - - if (device_register(&mwave_device)) - goto cleanup_error; - pDrvData->device_registered = true; - for (i = 0; i < ARRAY_SIZE(mwave_dev_attrs); i++) { - if(device_create_file(&mwave_device, mwave_dev_attrs[i])) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd:mwave_init: Error:" - " Failed to create sysfs file %s\n", - mwave_dev_attrs[i]->attr.name); - goto cleanup_error; - } - pDrvData->nr_registered_attrs++; - } -#endif - /* SUCCESS! */ return 0; diff --git a/drivers/char/mwave/smapi.c b/drivers/char/mwave/smapi.c index f8d79d393b69..f586752ec463 100644 --- a/drivers/char/mwave/smapi.c +++ b/drivers/char/mwave/smapi.c @@ -513,28 +513,6 @@ int smapi_set_DSP_power_state(bool bOn) return bRC; } -#if 0 -static int SmapiQuerySystemID(void) -{ - int bRC = -EIO; - unsigned short usAX = 0xffff, usBX = 0xffff, usCX = 0xffff, - usDX = 0xffff, usDI = 0xffff, usSI = 0xffff; - - printk("smapi::SmapiQUerySystemID entry\n"); - bRC = smapi_request(0x0000, 0, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - - if (bRC == 0) { - printk("AX=%x, BX=%x, CX=%x, DX=%x, DI=%x, SI=%x\n", - usAX, usBX, usCX, usDX, usDI, usSI); - } else { - printk("smapi::SmapiQuerySystemID smapi_request error\n"); - } - - return bRC; -} -#endif /* 0 */ - int smapi_init(void) { int retval = -EIO; From 48e77862a73b7a24dbe96335e8f7790adf8e48be Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Wed, 19 Nov 2025 10:19:45 +0100 Subject: [PATCH 285/304] char/mwave: remove MWAVE_FUTZ_WITH_OTHER_DEVICES ifdeffery In mwave, a lot of code depends on the MWAVE_FUTZ_WITH_OTHER_DEVICES macro. That can be defined in Makefile to compile this in. 1) The code is completely unreadable. 2) Recompiling the kernel to have this untested code compiled in is not a good idea. Drop all this. Signed-off-by: Jiri Slaby (SUSE) Acked-by: Arnd Bergmann Link: https://patch.msgid.link/20251119091949.825958-3-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/char/mwave/Makefile | 3 - drivers/char/mwave/smapi.c | 108 ------------------------------------ 2 files changed, 111 deletions(-) diff --git a/drivers/char/mwave/Makefile b/drivers/char/mwave/Makefile index a24fe96e3c96..836bfa25c541 100644 --- a/drivers/char/mwave/Makefile +++ b/drivers/char/mwave/Makefile @@ -9,8 +9,5 @@ obj-$(CONFIG_MWAVE) += mwave.o mwave-y := mwavedd.o smapi.o tp3780i.o 3780i.o -# To have the mwave driver disable other uarts if necessary -# ccflags-y := -DMWAVE_FUTZ_WITH_OTHER_DEVICES - # To compile in lots (~20 KiB) of run-time enablable printk()s for debugging: ccflags-y += -DMW_TRACE diff --git a/drivers/char/mwave/smapi.c b/drivers/char/mwave/smapi.c index f586752ec463..5e2fe3235714 100644 --- a/drivers/char/mwave/smapi.c +++ b/drivers/char/mwave/smapi.c @@ -279,46 +279,14 @@ int smapi_set_DSP_cfg(void) if (usBX & 0x0100) { /* serial port A is present */ if (usCX & 1) { /* serial port is enabled */ if ((usSI & 0xFF) == mwave_uart_irq) { -#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Serial port A irq %x conflicts with mwave_uart_irq %x\n", usSI & 0xFF, mwave_uart_irq); -#else - PRINTK_3(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg: Serial port A irq %x conflicts with mwave_uart_irq %x\n", usSI & 0xFF, mwave_uart_irq); -#endif -#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES - PRINTK_1(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg Disabling conflicting serial port\n"); - bRC = smapi_request(0x1403, 0x0100, 0, usSI, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1402, 0x0000, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; -#else goto exit_conflict; -#endif } else { if ((usSI >> 8) == uartio_index) { -#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Serial port A base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI >> 8], ausUartBases[uartio_index]); -#else - PRINTK_3(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg: Serial port A base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI >> 8], ausUartBases[uartio_index]); -#endif -#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES - PRINTK_1(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg Disabling conflicting serial port A\n"); - bRC = smapi_request (0x1403, 0x0100, 0, usSI, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request (0x1402, 0x0000, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; -#else goto exit_conflict; -#endif } } } @@ -332,46 +300,14 @@ int smapi_set_DSP_cfg(void) if (usBX & 0x0100) { /* serial port B is present */ if (usCX & 1) { /* serial port is enabled */ if ((usSI & 0xFF) == mwave_uart_irq) { -#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Serial port B irq %x conflicts with mwave_uart_irq %x\n", usSI & 0xFF, mwave_uart_irq); -#else - PRINTK_3(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg: Serial port B irq %x conflicts with mwave_uart_irq %x\n", usSI & 0xFF, mwave_uart_irq); -#endif -#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES - PRINTK_1(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg Disabling conflicting serial port B\n"); - bRC = smapi_request(0x1405, 0x0100, 0, usSI, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1404, 0x0000, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; -#else goto exit_conflict; -#endif } else { if ((usSI >> 8) == uartio_index) { -#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Serial port B base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI >> 8], ausUartBases[uartio_index]); -#else - PRINTK_3(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg: Serial port B base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI >> 8], ausUartBases[uartio_index]); -#endif -#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES - PRINTK_1 (TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg Disabling conflicting serial port B\n"); - bRC = smapi_request (0x1405, 0x0100, 0, usSI, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request (0x1404, 0x0000, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; -#else goto exit_conflict; -#endif } } } @@ -387,58 +323,14 @@ int smapi_set_DSP_cfg(void) /* bRC == 0 */ if ((usCX & 0xff) != 0xff) { /* IR port not disabled */ if ((usCX & 0xff) == mwave_uart_irq) { -#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: IR port irq %x conflicts with mwave_uart_irq %x\n", usCX & 0xff, mwave_uart_irq); -#else - PRINTK_3(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg: IR port irq %x conflicts with mwave_uart_irq %x\n", usCX & 0xff, mwave_uart_irq); -#endif -#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES - PRINTK_1(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg Disabling conflicting IR port\n"); - bRC = smapi_request(0x1701, 0x0100, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1700, 0, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1705, 0x01ff, 0, usSI, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1704, 0x0000, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; -#else goto exit_conflict; -#endif } else { if ((usSI & 0xff) == uartio_index) { -#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: IR port base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI & 0xff], ausUartBases[uartio_index]); -#else - PRINTK_3(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg: IR port base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI & 0xff], ausUartBases[uartio_index]); -#endif -#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES - PRINTK_1(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg Disabling conflicting IR port\n"); - bRC = smapi_request(0x1701, 0x0100, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1700, 0, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1705, 0x01ff, 0, usSI, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; - bRC = smapi_request(0x1704, 0x0000, 0, 0, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - if (bRC) goto exit_smapi_request_error; -#else goto exit_conflict; -#endif } } } From 3b4df2320ef66a8762f5a283fdf9c0e09e6ca6b2 Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Wed, 19 Nov 2025 10:19:46 +0100 Subject: [PATCH 286/304] char/mwave: remove unneeded fops file_operations::{read/write/open/release} need not be defined. The core code return proper values already (the same as the being removed ones). So there is no need to preserve these just for tracing via printk. Signed-off-by: Jiri Slaby (SUSE) Acked-by: Arnd Bergmann Link: https://patch.msgid.link/20251119091949.825958-4-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/char/mwave/mwavedd.c | 62 ------------------------------------ 1 file changed, 62 deletions(-) diff --git a/drivers/char/mwave/mwavedd.c b/drivers/char/mwave/mwavedd.c index 86e33c28beac..b6d7a8b04183 100644 --- a/drivers/char/mwave/mwavedd.c +++ b/drivers/char/mwave/mwavedd.c @@ -86,40 +86,8 @@ module_param_hw(mwave_3780i_io, int, ioport, 0); module_param_hw(mwave_uart_irq, int, irq, 0); module_param_hw(mwave_uart_io, int, ioport, 0); -static int mwave_open(struct inode *inode, struct file *file); -static int mwave_close(struct inode *inode, struct file *file); -static long mwave_ioctl(struct file *filp, unsigned int iocmd, - unsigned long ioarg); - MWAVE_DEVICE_DATA mwave_s_mdd; -static int mwave_open(struct inode *inode, struct file *file) -{ - unsigned int retval = 0; - - PRINTK_3(TRACE_MWAVE, - "mwavedd::mwave_open, entry inode %p file %p\n", - inode, file); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_open, exit return retval %x\n", retval); - - return retval; -} - -static int mwave_close(struct inode *inode, struct file *file) -{ - unsigned int retval = 0; - - PRINTK_3(TRACE_MWAVE, - "mwavedd::mwave_close, entry inode %p file %p\n", - inode, file); - - PRINTK_2(TRACE_MWAVE, "mwavedd::mwave_close, exit retval %x\n", - retval); - - return retval; -} - static long mwave_ioctl(struct file *file, unsigned int iocmd, unsigned long ioarg) { @@ -410,30 +378,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, return retval; } - -static ssize_t mwave_read(struct file *file, char __user *buf, size_t count, - loff_t * ppos) -{ - PRINTK_5(TRACE_MWAVE, - "mwavedd::mwave_read entry file %p, buf %p, count %zx ppos %p\n", - file, buf, count, ppos); - - return -EINVAL; -} - - -static ssize_t mwave_write(struct file *file, const char __user *buf, - size_t count, loff_t * ppos) -{ - PRINTK_5(TRACE_MWAVE, - "mwavedd::mwave_write entry file %p, buf %p," - " count %zx ppos %p\n", - file, buf, count, ppos); - - return -EINVAL; -} - - static int register_serial_portandirq(unsigned int port, int irq) { struct uart_8250_port uart; @@ -478,18 +422,12 @@ static int register_serial_portandirq(unsigned int port, int irq) return serial8250_register_8250_port(&uart); } - static const struct file_operations mwave_fops = { .owner = THIS_MODULE, - .read = mwave_read, - .write = mwave_write, .unlocked_ioctl = mwave_ioctl, - .open = mwave_open, - .release = mwave_close, .llseek = default_llseek, }; - static struct miscdevice mwave_misc_dev = { MWAVE_MINOR, "mwave", &mwave_fops }; /* From 53688a9f3735588a57603f0edee58f6bd7b07b92 Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Wed, 19 Nov 2025 10:19:47 +0100 Subject: [PATCH 287/304] char/mwave: remove printk tracing The printk tracing makes the code hard to follow for no good benefit. Everyone can use dynamic tracing and/or kprobes. Drop this unreadable bloatware too. Signed-off-by: Jiri Slaby (SUSE) Acked-by: Arnd Bergmann Link: https://patch.msgid.link/20251119091949.825958-5-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/char/mwave/3780i.c | 177 +---------------------------------- drivers/char/mwave/Makefile | 3 - drivers/char/mwave/README | 10 -- drivers/char/mwave/mwavedd.c | 116 +---------------------- drivers/char/mwave/mwavedd.h | 59 ------------ drivers/char/mwave/smapi.c | 53 +---------- drivers/char/mwave/tp3780i.c | 120 ++---------------------- 7 files changed, 14 insertions(+), 524 deletions(-) diff --git a/drivers/char/mwave/3780i.c b/drivers/char/mwave/3780i.c index 321dbd03d007..6024cf7d5705 100644 --- a/drivers/char/mwave/3780i.c +++ b/drivers/char/mwave/3780i.c @@ -75,18 +75,12 @@ unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO, unsigned long flags; unsigned short val; - PRINTK_3(TRACE_3780I, - "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n", - usDspBaseIO, ulMsaAddr); - spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); val = InWordDsp(DSP_MsaDataDSISHigh); spin_unlock_irqrestore(&dsp_lock, flags); - PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val); - return val; } @@ -95,10 +89,6 @@ void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO, { unsigned long flags; - PRINTK_4(TRACE_3780I, - "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n", - usDspBaseIO, ulMsaAddr, usValue); - spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); @@ -112,32 +102,15 @@ static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex, DSP_ISA_SLAVE_CONTROL rSlaveControl; DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; - - PRINTK_4(TRACE_3780I, - "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n", - usDspBaseIO, uIndex, ucValue); - MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n", - MKBYTE(rSlaveControl)); - rSlaveControl_Save = rSlaveControl; rSlaveControl.ConfigMode = true; - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n", - MKBYTE(rSlaveControl)); - OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); OutByteDsp(DSP_ConfigData, ucValue); OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n"); - - } int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, @@ -162,25 +135,13 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, DSP_CLOCK_CONTROL_2 rClockControl2; DSP_ISA_SLAVE_CONTROL rSlaveControl; DSP_HBRIDGE_CONTROL rHBridgeControl; - unsigned short ChipID = 0; unsigned short tval; - - PRINTK_2(TRACE_3780I, - "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n", - pSettings->bDSPEnabled); - - if (!pSettings->bDSPEnabled) { PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" ); return -EIO; } - - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n", - pSettings->bModemEnabled); - if (pSettings->bModemEnabled) { rUartCfg1.Reserved = rUartCfg2.Reserved = 0; rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow; @@ -253,23 +214,10 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, rSlaveControl.ConfigMode = false; rSlaveControl.Reserved = 0; - PRINTK_4(TRACE_3780I, - "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n", - usDspBaseIO, DSP_IsaSlaveControl, - usDspBaseIO + DSP_IsaSlaveControl); - - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n", - MKWORD(rSlaveControl)); - spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval); - - for (i = 0; i < 11; i++) udelay(2000); @@ -278,10 +226,6 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); - PRINTK_2(TRACE_3780I, - "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval); - - /* Program our general configuration registers */ WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1)); WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2)); @@ -302,10 +246,6 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, rHBridgeControl.IoAutoInc = false; rHBridgeControl.DiagnosticMode = false; - PRINTK_3(TRACE_3780I, - "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n", - DSP_HBridgeControl, MKWORD(rHBridgeControl)); - OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable)); @@ -313,11 +253,7 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2)); WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset)); - ChipID = ReadMsaCfg(DSP_ChipID); - - PRINTK_2(TRACE_3780I, - "3780i::dsp3780I_EnableDSP exiting bRC=true, ChipID %x\n", - ChipID); + ReadMsaCfg(DSP_ChipID); return 0; } @@ -328,9 +264,6 @@ int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) unsigned short usDspBaseIO = pSettings->usDspBaseIO; DSP_ISA_SLAVE_CONTROL rSlaveControl; - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n"); - rSlaveControl.ClockControl = 0; rSlaveControl.SoftReset = true; rSlaveControl.ConfigMode = false; @@ -346,9 +279,6 @@ int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) udelay(5); - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n"); - return 0; } @@ -359,16 +289,10 @@ int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) DSP_BOOT_DOMAIN rBootDomain; DSP_HBRIDGE_CONTROL rHBridgeControl; - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n"); - spin_lock_irqsave(&dsp_lock, flags); /* Mask DSP to PC interrupt */ MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); - PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n", - MKWORD(rHBridgeControl)); - rHBridgeControl.EnableDspInt = false; OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); @@ -379,9 +303,6 @@ int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) rBootDomain.NMI = true; rBootDomain.Reserved = 0; - PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n", - MKWORD(rBootDomain)); - WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); /* Reset all the chiplets and then reactivate them */ @@ -390,9 +311,6 @@ int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) WriteMsaCfg(DSP_ChipReset, (unsigned short) (~pSettings->usChipletEnable)); - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n"); - return 0; } @@ -404,10 +322,6 @@ int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) DSP_BOOT_DOMAIN rBootDomain; DSP_HBRIDGE_CONTROL rHBridgeControl; - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n"); - - /* Transition the core to a running state */ rBootDomain.ResetCore = true; rBootDomain.Halt = false; @@ -430,15 +344,9 @@ int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); rHBridgeControl.EnableDspInt = true; - PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n", - MKWORD(rHBridgeControl)); - OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); - - PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=true\n"); - return 0; } @@ -450,12 +358,6 @@ int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned short __user *pusBuffer = pvBuffer; unsigned short val; - - PRINTK_5(TRACE_3780I, - "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", - usDspBaseIO, pusBuffer, uCount, ulDSPAddr); - - /* Set the initial MSA address. No adjustments need to be made to data store addresses */ spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); @@ -470,17 +372,9 @@ int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer, if(put_user(val, pusBuffer++)) return -EFAULT; - PRINTK_3(TRACE_3780I, - "3780I::dsp3780I_ReadDStore uCount %x val %x\n", - uCount, val); - PaceMsaAccess(usDspBaseIO); } - - PRINTK_1(TRACE_3780I, - "3780I::dsp3780I_ReadDStore exit bRC=true\n"); - return 0; } @@ -492,12 +386,6 @@ int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, unsigned short __user *pusBuffer = pvBuffer; unsigned short val; - - PRINTK_5(TRACE_3780I, - "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", - usDspBaseIO, pusBuffer, uCount, ulDSPAddr); - - /* Set the initial MSA address. No adjustments need to be made to data store addresses */ spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); @@ -512,17 +400,9 @@ int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, if(put_user(val, pusBuffer++)) return -EFAULT; - PRINTK_3(TRACE_3780I, - "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n", - uCount, val); - PaceMsaAccess(usDspBaseIO); } - - PRINTK_1(TRACE_3780I, - "3780I::dsp3780I_ReadAndClearDStore exit bRC=true\n"); - return 0; } @@ -533,12 +413,6 @@ int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; - - PRINTK_5(TRACE_3780I, - "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", - usDspBaseIO, pusBuffer, uCount, ulDSPAddr); - - /* Set the initial MSA address. No adjustments need to be made to data store addresses */ spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); @@ -554,17 +428,9 @@ int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer, OutWordDsp(DSP_MsaDataDSISHigh, val); spin_unlock_irqrestore(&dsp_lock, flags); - PRINTK_3(TRACE_3780I, - "3780I::dsp3780I_WriteDStore uCount %x val %x\n", - uCount, val); - PaceMsaAccess(usDspBaseIO); } - - PRINTK_1(TRACE_3780I, - "3780I::dsp3780D_WriteDStore exit bRC=true\n"); - return 0; } @@ -575,10 +441,6 @@ int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; - PRINTK_5(TRACE_3780I, - "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", - usDspBaseIO, pusBuffer, uCount, ulDSPAddr); - /* * Set the initial MSA address. To convert from an instruction store * address to an MSA address @@ -602,17 +464,10 @@ int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer, if(put_user(val_hi, pusBuffer++)) return -EFAULT; - PRINTK_4(TRACE_3780I, - "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n", - uCount, val_lo, val_hi); - PaceMsaAccess(usDspBaseIO); } - PRINTK_1(TRACE_3780I, - "3780I::dsp3780I_ReadIStore exit bRC=true\n"); - return 0; } @@ -623,11 +478,6 @@ int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; - PRINTK_5(TRACE_3780I, - "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", - usDspBaseIO, pusBuffer, uCount, ulDSPAddr); - - /* * Set the initial MSA address. To convert from an instruction store * address to an MSA address @@ -651,17 +501,9 @@ int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, OutWordDsp(DSP_MsaDataDSISHigh, val_hi); spin_unlock_irqrestore(&dsp_lock, flags); - PRINTK_4(TRACE_3780I, - "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n", - uCount, val_lo, val_hi); - PaceMsaAccess(usDspBaseIO); - } - PRINTK_1(TRACE_3780I, - "3780I::dsp3780I_WriteIStore exit bRC=true\n"); - return 0; } @@ -671,12 +513,6 @@ int dsp3780I_GetIPCSource(unsigned short usDspBaseIO, { unsigned long flags; DSP_HBRIDGE_CONTROL rHBridgeControl; - unsigned short temp; - - - PRINTK_3(TRACE_3780I, - "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n", - usDspBaseIO, pusIPCSource); /* * Disable DSP to PC interrupts, read the interrupt register, @@ -688,22 +524,11 @@ int dsp3780I_GetIPCSource(unsigned short usDspBaseIO, OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); *pusIPCSource = InWordDsp(DSP_Interrupt); - temp = (unsigned short) ~(*pusIPCSource); - - PRINTK_3(TRACE_3780I, - "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n", - *pusIPCSource, temp); - OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource)); rHBridgeControl.EnableDspInt = true; OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); - - PRINTK_2(TRACE_3780I, - "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n", - *pusIPCSource); - return 0; } diff --git a/drivers/char/mwave/Makefile b/drivers/char/mwave/Makefile index 836bfa25c541..e56c1a375535 100644 --- a/drivers/char/mwave/Makefile +++ b/drivers/char/mwave/Makefile @@ -8,6 +8,3 @@ obj-$(CONFIG_MWAVE) += mwave.o mwave-y := mwavedd.o smapi.o tp3780i.o 3780i.o - -# To compile in lots (~20 KiB) of run-time enablable printk()s for debugging: -ccflags-y += -DMW_TRACE diff --git a/drivers/char/mwave/README b/drivers/char/mwave/README index c2a58f428bc8..6224aa814c62 100644 --- a/drivers/char/mwave/README +++ b/drivers/char/mwave/README @@ -4,16 +4,6 @@ Module options The mwave module takes the following options. Note that these options are not saved by the BIOS and so do not persist after unload and reload. - mwave_debug=value, where value is bitwise OR of trace flags: - 0x0001 mwavedd api tracing - 0x0002 smapi api tracing - 0x0004 3780i tracing - 0x0008 tp3780i tracing - - Tracing only occurs if the driver has been compiled with the - MW_TRACE macro #defined (i.e. let ccflags-y := -DMW_TRACE - in the Makefile). - mwave_3780i_irq=5/7/10/11/15 If the dsp irq has not been setup and stored in bios by the thinkpad configuration utility then this parameter allows the diff --git a/drivers/char/mwave/mwavedd.c b/drivers/char/mwave/mwavedd.c index b6d7a8b04183..f01c6f7d54a3 100644 --- a/drivers/char/mwave/mwavedd.c +++ b/drivers/char/mwave/mwavedd.c @@ -75,12 +75,10 @@ MODULE_LICENSE("GPL"); * We'll depend on users using the tpctl utility to do that for now */ static DEFINE_MUTEX(mwave_mutex); -int mwave_debug = 0; int mwave_3780i_irq = 0; int mwave_3780i_io = 0; int mwave_uart_irq = 0; int mwave_uart_io = 0; -module_param(mwave_debug, int, 0); module_param_hw(mwave_3780i_irq, int, irq, 0); module_param_hw(mwave_3780i_io, int, ioport, 0); module_param_hw(mwave_uart_irq, int, irq, 0); @@ -95,62 +93,32 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; void __user *arg = (void __user *)ioarg; - PRINTK_4(TRACE_MWAVE, - "mwavedd::mwave_ioctl, entry file %p cmd %x arg %x\n", - file, iocmd, (int) ioarg); - switch (iocmd) { case IOCTL_MW_RESET: - PRINTK_1(TRACE_MWAVE, - "mwavedd::mwave_ioctl, IOCTL_MW_RESET" - " calling tp3780I_ResetDSP\n"); mutex_lock(&mwave_mutex); retval = tp3780I_ResetDSP(&pDrvData->rBDData); mutex_unlock(&mwave_mutex); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl, IOCTL_MW_RESET" - " retval %x from tp3780I_ResetDSP\n", - retval); break; case IOCTL_MW_RUN: - PRINTK_1(TRACE_MWAVE, - "mwavedd::mwave_ioctl, IOCTL_MW_RUN" - " calling tp3780I_StartDSP\n"); mutex_lock(&mwave_mutex); retval = tp3780I_StartDSP(&pDrvData->rBDData); mutex_unlock(&mwave_mutex); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl, IOCTL_MW_RUN" - " retval %x from tp3780I_StartDSP\n", - retval); break; case IOCTL_MW_DSP_ABILITIES: { MW_ABILITIES rAbilities; - PRINTK_1(TRACE_MWAVE, - "mwavedd::mwave_ioctl," - " IOCTL_MW_DSP_ABILITIES calling" - " tp3780I_QueryAbilities\n"); mutex_lock(&mwave_mutex); retval = tp3780I_QueryAbilities(&pDrvData->rBDData, &rAbilities); mutex_unlock(&mwave_mutex); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES" - " retval %x from tp3780I_QueryAbilities\n", - retval); if (retval == 0) { if( copy_to_user(arg, &rAbilities, sizeof(MW_ABILITIES)) ) return -EFAULT; } - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES" - " exit retval %x\n", - retval); } break; @@ -164,10 +132,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, return -EFAULT; pusBuffer = (unsigned short __user *) (rReadData.pBuf); - PRINTK_4(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_READ_DATA," - " size %lx, ioarg %lx pusBuffer %p\n", - rReadData.ulDataLength, ioarg, pusBuffer); mutex_lock(&mwave_mutex); retval = tp3780I_ReadWriteDspDStore(&pDrvData->rBDData, iocmd, @@ -187,11 +151,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, return -EFAULT; pusBuffer = (unsigned short __user *) (rReadData.pBuf); - PRINTK_4(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_READ_INST," - " size %lx, ioarg %lx pusBuffer %p\n", - rReadData.ulDataLength / 2, ioarg, - pusBuffer); mutex_lock(&mwave_mutex); retval = tp3780I_ReadWriteDspDStore(&pDrvData->rBDData, iocmd, pusBuffer, @@ -210,11 +169,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, return -EFAULT; pusBuffer = (unsigned short __user *) (rWriteData.pBuf); - PRINTK_4(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_WRITE_DATA," - " size %lx, ioarg %lx pusBuffer %p\n", - rWriteData.ulDataLength, ioarg, - pusBuffer); mutex_lock(&mwave_mutex); retval = tp3780I_ReadWriteDspDStore(&pDrvData->rBDData, iocmd, pusBuffer, @@ -233,11 +187,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, return -EFAULT; pusBuffer = (unsigned short __user *)(rWriteData.pBuf); - PRINTK_4(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_WRITE_INST," - " size %lx, ioarg %lx pusBuffer %p\n", - rWriteData.ulDataLength, ioarg, - pusBuffer); mutex_lock(&mwave_mutex); retval = tp3780I_ReadWriteDspIStore(&pDrvData->rBDData, iocmd, pusBuffer, @@ -260,21 +209,11 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, } ipcnum = array_index_nospec(ipcnum, ARRAY_SIZE(pDrvData->IPCs)); - PRINTK_3(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_REGISTER_IPC" - " ipcnum %x entry usIntCount %x\n", - ipcnum, - pDrvData->IPCs[ipcnum].usIntCount); mutex_lock(&mwave_mutex); pDrvData->IPCs[ipcnum].bIsHere = false; pDrvData->IPCs[ipcnum].bIsEnabled = true; mutex_unlock(&mwave_mutex); - - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_REGISTER_IPC" - " ipcnum %x exit\n", - ipcnum); } break; @@ -290,20 +229,11 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, } ipcnum = array_index_nospec(ipcnum, ARRAY_SIZE(pDrvData->IPCs)); - PRINTK_3(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_GET_IPC" - " ipcnum %x, usIntCount %x\n", - ipcnum, - pDrvData->IPCs[ipcnum].usIntCount); - + mutex_lock(&mwave_mutex); if (pDrvData->IPCs[ipcnum].bIsEnabled == true) { DECLARE_WAITQUEUE(wait, current); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl, thread for" - " ipc %x going to sleep\n", - ipcnum); add_wait_queue(&pDrvData->IPCs[ipcnum].ipc_wait_queue, &wait); pDrvData->IPCs[ipcnum].bIsHere = true; set_current_state(TASK_INTERRUPTIBLE); @@ -311,31 +241,15 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, /* the interrupt handler while we were gone */ if (pDrvData->IPCs[ipcnum].usIntCount == 1) { /* first int has occurred (race condition) */ pDrvData->IPCs[ipcnum].usIntCount = 2; /* first int has been handled */ - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl" - " IOCTL_MW_GET_IPC ipcnum %x" - " handling first int\n", - ipcnum); } else { /* either 1st int has not yet occurred, or we have already handled the first int */ schedule(); if (pDrvData->IPCs[ipcnum].usIntCount == 1) { pDrvData->IPCs[ipcnum].usIntCount = 2; } - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl" - " IOCTL_MW_GET_IPC ipcnum %x" - " woke up and returning to" - " application\n", - ipcnum); } pDrvData->IPCs[ipcnum].bIsHere = false; remove_wait_queue(&pDrvData->IPCs[ipcnum].ipc_wait_queue, &wait); set_current_state(TASK_RUNNING); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_GET_IPC," - " returning thread for ipc %x" - " processing\n", - ipcnum); } mutex_unlock(&mwave_mutex); } @@ -344,10 +258,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, case IOCTL_MW_UNREGISTER_IPC: { unsigned int ipcnum = (unsigned int) ioarg; - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_ioctl IOCTL_MW_UNREGISTER_IPC" - " ipcnum %x\n", - ipcnum); if (ipcnum >= ARRAY_SIZE(pDrvData->IPCs)) { PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_ioctl:" @@ -373,8 +283,6 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, return -ENOTTY; } /* switch */ - PRINTK_2(TRACE_MWAVE, "mwavedd::mwave_ioctl, exit retval %x\n", retval); - return retval; } @@ -440,8 +348,6 @@ static void mwave_exit(void) { pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; - PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_exit entry\n"); - if ( pDrvData->sLine >= 0 ) { serial8250_unregister_port(pDrvData->sLine); } @@ -457,8 +363,6 @@ static void mwave_exit(void) if (pDrvData->bBDInitialized) { tp3780I_Cleanup(&pDrvData->rBDData); } - - PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_exit exit\n"); } module_exit(mwave_exit); @@ -469,8 +373,6 @@ static int __init mwave_init(void) int retval = 0; pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; - PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_init entry\n"); - memset(&mwave_s_mdd, 0, sizeof(MWAVE_DEVICE_DATA)); pDrvData->bBDInitialized = false; @@ -488,10 +390,6 @@ static int __init mwave_init(void) } retval = tp3780I_InitializeBoardData(&pDrvData->rBDData); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_init, return from tp3780I_InitializeBoardData" - " retval %x\n", - retval); if (retval) { PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_init: Error:" @@ -501,10 +399,6 @@ static int __init mwave_init(void) pDrvData->bBDInitialized = true; retval = tp3780I_CalcResources(&pDrvData->rBDData); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_init, return from tp3780I_CalcResources" - " retval %x\n", - retval); if (retval) { PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error:" @@ -513,10 +407,6 @@ static int __init mwave_init(void) } retval = tp3780I_ClaimResources(&pDrvData->rBDData); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_init, return from tp3780I_ClaimResources" - " retval %x\n", - retval); if (retval) { PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error:" @@ -526,10 +416,6 @@ static int __init mwave_init(void) pDrvData->bResourcesClaimed = true; retval = tp3780I_EnableDSP(&pDrvData->rBDData); - PRINTK_2(TRACE_MWAVE, - "mwavedd::mwave_init, return from tp3780I_EnableDSP" - " retval %x\n", - retval); if (retval) { PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error:" diff --git a/drivers/char/mwave/mwavedd.h b/drivers/char/mwave/mwavedd.h index 21cb09c7bed7..fdd5dfdd3639 100644 --- a/drivers/char/mwave/mwavedd.h +++ b/drivers/char/mwave/mwavedd.h @@ -56,7 +56,6 @@ #include #include -extern int mwave_debug; extern int mwave_3780i_irq; extern int mwave_3780i_io; extern int mwave_uart_irq; @@ -65,64 +64,6 @@ extern int mwave_uart_io; #define PRINTK_ERROR printk #define KERN_ERR_MWAVE KERN_ERR "mwave: " -#define TRACE_MWAVE 0x0001 -#define TRACE_SMAPI 0x0002 -#define TRACE_3780I 0x0004 -#define TRACE_TP3780I 0x0008 - -#ifdef MW_TRACE -#define PRINTK_1(f,s) \ - if (f & (mwave_debug)) { \ - printk(s); \ - } - -#define PRINTK_2(f,s,v1) \ - if (f & (mwave_debug)) { \ - printk(s,v1); \ - } - -#define PRINTK_3(f,s,v1,v2) \ - if (f & (mwave_debug)) { \ - printk(s,v1,v2); \ - } - -#define PRINTK_4(f,s,v1,v2,v3) \ - if (f & (mwave_debug)) { \ - printk(s,v1,v2,v3); \ - } - -#define PRINTK_5(f,s,v1,v2,v3,v4) \ - if (f & (mwave_debug)) { \ - printk(s,v1,v2,v3,v4); \ - } - -#define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ - if (f & (mwave_debug)) { \ - printk(s,v1,v2,v3,v4,v5); \ - } - -#define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ - if (f & (mwave_debug)) { \ - printk(s,v1,v2,v3,v4,v5,v6); \ - } - -#define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ - if (f & (mwave_debug)) { \ - printk(s,v1,v2,v3,v4,v5,v6,v7); \ - } - -#else -#define PRINTK_1(f,s) -#define PRINTK_2(f,s,v1) -#define PRINTK_3(f,s,v1,v2) -#define PRINTK_4(f,s,v1,v2,v3) -#define PRINTK_5(f,s,v1,v2,v3,v4) -#define PRINTK_6(f,s,v1,v2,v3,v4,v5) -#define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) -#define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) -#endif - - typedef struct _MWAVE_IPC { unsigned short usIntCount; /* 0=none, 1=first, 2=greater than 1st */ bool bIsEnabled; diff --git a/drivers/char/mwave/smapi.c b/drivers/char/mwave/smapi.c index 5e2fe3235714..1efddb34bef0 100644 --- a/drivers/char/mwave/smapi.c +++ b/drivers/char/mwave/smapi.c @@ -69,10 +69,6 @@ static int smapi_request(unsigned short inBX, unsigned short inCX, unsigned short usSmapiOK = -EIO, *pusSmapiOK = &usSmapiOK; unsigned int inBXCX = (inBX << 16) | inCX; unsigned int inDISI = (inDI << 16) | inSI; - int retval = 0; - - PRINTK_5(TRACE_SMAPI, "inBX %x inCX %x inDI %x inSI %x\n", - inBX, inCX, inDI, inSI); __asm__ __volatile__("movw $0x5380,%%ax\n\t" "movl %7,%%ebx\n\t" @@ -107,10 +103,6 @@ static int smapi_request(unsigned short inBX, unsigned short inCX, :"%eax", "%ebx", "%ecx", "%edx", "%edi", "%esi"); - PRINTK_8(TRACE_SMAPI, - "myoutAX %x myoutBX %x myoutCX %x myoutDX %x myoutDI %x myoutSI %x usSmapiOK %x\n", - myoutAX, myoutBX, myoutCX, myoutDX, myoutDI, myoutSI, - usSmapiOK); *outAX = myoutAX; *outBX = myoutBX; *outCX = myoutCX; @@ -118,9 +110,7 @@ static int smapi_request(unsigned short inBX, unsigned short inCX, *outDI = myoutDI; *outSI = myoutSI; - retval = (usSmapiOK == 1) ? 0 : -EIO; - PRINTK_2(TRACE_SMAPI, "smapi::smapi_request exit retval %x\n", retval); - return retval; + return usSmapiOK == 1 ? 0 : -EIO; } @@ -134,8 +124,6 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) static const unsigned short ausUartBases[] = { 0x03F8, 0x02F8, 0x03E8, 0x02E8 }; - PRINTK_1(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg entry\n"); - bRC = smapi_request(0x1802, 0x0000, 0, 0, &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); if (bRC) { @@ -143,8 +131,6 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) return bRC; } - PRINTK_1(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg, smapi_request OK\n"); - pSettings->bDSPPresent = ((usBX & 0x0100) != 0); pSettings->bDSPEnabled = ((usCX & 0x0001) != 0); pSettings->usDspIRQ = usSI & 0x00FF; @@ -154,11 +140,6 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) } else { pSettings->usDspBaseIO = 0; } - PRINTK_6(TRACE_SMAPI, - "smapi::smapi_query_DSP_cfg get DSP Settings bDSPPresent %x bDSPEnabled %x usDspIRQ %x usDspDMA %x usDspBaseIO %x\n", - pSettings->bDSPPresent, pSettings->bDSPEnabled, - pSettings->usDspIRQ, pSettings->usDspDMA, - pSettings->usDspBaseIO); /* check for illegal values */ if ( pSettings->usDspBaseIO == 0 ) @@ -173,8 +154,6 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) return bRC; } - PRINTK_1(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg, smapi_request OK\n"); - pSettings->bModemEnabled = ((usCX & 0x0001) != 0); pSettings->usUartIRQ = usSI & 0x000F; if (((usSI & 0xFF00) >> 8) < ARRAY_SIZE(ausUartBases)) { @@ -183,20 +162,12 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) pSettings->usUartBaseIO = 0; } - PRINTK_4(TRACE_SMAPI, - "smapi::smapi_query_DSP_cfg get DSP modem settings bModemEnabled %x usUartIRQ %x usUartBaseIO %x\n", - pSettings->bModemEnabled, - pSettings->usUartIRQ, - pSettings->usUartBaseIO); - /* check for illegal values */ if ( pSettings->usUartBaseIO == 0 ) PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: UART base I/O address is 0\n"); if ( pSettings->usUartIRQ == 0 ) PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: UART IRQ line is 0\n"); - PRINTK_2(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg exit bRC %x\n", bRC); - return bRC; } @@ -218,10 +189,6 @@ int smapi_set_DSP_cfg(void) unsigned short dspio_index = 0, uartio_index = 0; - PRINTK_5(TRACE_SMAPI, - "smapi::smapi_set_DSP_cfg entry mwave_3780i_irq %x mwave_3780i_io %x mwave_uart_irq %x mwave_uart_io %x\n", - mwave_3780i_irq, mwave_3780i_io, mwave_uart_irq, mwave_uart_io); - if (mwave_3780i_io) { for (i = 0; i < ARRAY_SIZE(ausDspBases); i++) { if (mwave_3780i_io == ausDspBases[i]) @@ -374,7 +341,6 @@ int smapi_set_DSP_cfg(void) if (bRC) goto exit_smapi_request_error; /* normal exit: */ - PRINTK_1(TRACE_SMAPI, "smapi::smapi_set_DSP_cfg exit\n"); return 0; exit_conflict: @@ -389,20 +355,13 @@ exit_smapi_request_error: int smapi_set_DSP_power_state(bool bOn) { - int bRC; unsigned short usAX, usBX, usCX, usDX, usDI, usSI; unsigned short usPowerFunction; - PRINTK_2(TRACE_SMAPI, "smapi::smapi_set_DSP_power_state entry bOn %x\n", bOn); - usPowerFunction = (bOn) ? 1 : 0; - bRC = smapi_request(0x4901, 0x0000, 0, usPowerFunction, - &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); - - PRINTK_2(TRACE_SMAPI, "smapi::smapi_set_DSP_power_state exit bRC %x\n", bRC); - - return bRC; + return smapi_request(0x4901, 0x0000, 0, usPowerFunction, &usAX, &usBX, &usCX, &usDX, &usDI, + &usSI); } int smapi_init(void) @@ -411,13 +370,10 @@ int smapi_init(void) unsigned short usSmapiID = 0; unsigned long flags; - PRINTK_1(TRACE_SMAPI, "smapi::smapi_init entry\n"); - spin_lock_irqsave(&rtc_lock, flags); usSmapiID = CMOS_READ(0x7C); usSmapiID |= (CMOS_READ(0x7D) << 8); spin_unlock_irqrestore(&rtc_lock, flags); - PRINTK_2(TRACE_SMAPI, "smapi::smapi_init usSmapiID %x\n", usSmapiID); if (usSmapiID == 0x5349) { spin_lock_irqsave(&rtc_lock, flags); @@ -427,9 +383,6 @@ int smapi_init(void) if (g_usSmapiPort == 0) { PRINTK_ERROR("smapi::smapi_init, ERROR unable to read from SMAPI port\n"); } else { - PRINTK_2(TRACE_SMAPI, - "smapi::smapi_init, exit true g_usSmapiPort %x\n", - g_usSmapiPort); retval = 0; //SmapiQuerySystemID(); } diff --git a/drivers/char/mwave/tp3780i.c b/drivers/char/mwave/tp3780i.c index 83eaffeb22c8..b7e95c57a1c4 100644 --- a/drivers/char/mwave/tp3780i.c +++ b/drivers/char/mwave/tp3780i.c @@ -73,8 +73,6 @@ static void EnableSRAM(THINKPAD_BD_DATA * pBDData) DSP_GPIO_DRIVER_ENABLE_15_8 rGpioDriverEnable; DSP_GPIO_MODE_15_8 rGpioMode; - PRINTK_1(TRACE_TP3780I, "tp3780i::EnableSRAM, entry\n"); - MKWORD(rGpioMode) = ReadMsaCfg(DSP_GpioModeControl_15_8); rGpioMode.GpioMode10 = 0; WriteMsaCfg(DSP_GpioModeControl_15_8, MKWORD(rGpioMode)); @@ -88,15 +86,11 @@ static void EnableSRAM(THINKPAD_BD_DATA * pBDData) rGpioOutputData.Latch10 = 0; rGpioOutputData.Mask10 = true; WriteMsaCfg(DSP_GpioOutputData_15_8, MKWORD(rGpioOutputData)); - - PRINTK_1(TRACE_TP3780I, "tp3780i::EnableSRAM exit\n"); } static irqreturn_t UartInterrupt(int irq, void *dev_id) { - PRINTK_3(TRACE_TP3780I, - "tp3780i::UartInterrupt entry irq %x dev_id %p\n", irq, dev_id); return IRQ_HANDLED; } @@ -107,35 +101,16 @@ static irqreturn_t DspInterrupt(int irq, void *dev_id) unsigned short usDspBaseIO = pSettings->usDspBaseIO; unsigned short usIPCSource = 0, usIsolationMask, usPCNum; - PRINTK_3(TRACE_TP3780I, - "tp3780i::DspInterrupt entry irq %x dev_id %p\n", irq, dev_id); - if (dsp3780I_GetIPCSource(usDspBaseIO, &usIPCSource) == 0) { - PRINTK_2(TRACE_TP3780I, - "tp3780i::DspInterrupt, return from dsp3780i_GetIPCSource, usIPCSource %x\n", - usIPCSource); usIsolationMask = 1; for (usPCNum = 1; usPCNum <= 16; usPCNum++) { if (usIPCSource & usIsolationMask) { usIPCSource &= ~usIsolationMask; - PRINTK_3(TRACE_TP3780I, - "tp3780i::DspInterrupt usPCNum %x usIPCSource %x\n", - usPCNum, usIPCSource); if (pDrvData->IPCs[usPCNum - 1].usIntCount == 0) { pDrvData->IPCs[usPCNum - 1].usIntCount = 1; } - PRINTK_2(TRACE_TP3780I, - "tp3780i::DspInterrupt usIntCount %x\n", - pDrvData->IPCs[usPCNum - 1].usIntCount); if (pDrvData->IPCs[usPCNum - 1].bIsEnabled == true) { - PRINTK_2(TRACE_TP3780I, - "tp3780i::DspInterrupt, waking up usPCNum %x\n", - usPCNum - 1); wake_up_interruptible(&pDrvData->IPCs[usPCNum - 1].ipc_wait_queue); - } else { - PRINTK_2(TRACE_TP3780I, - "tp3780i::DspInterrupt, no one waiting for IPC %x\n", - usPCNum - 1); } } if (usIPCSource == 0) @@ -143,11 +118,7 @@ static irqreturn_t DspInterrupt(int irq, void *dev_id) /* try next IPC */ usIsolationMask = usIsolationMask << 1; } - } else { - PRINTK_1(TRACE_TP3780I, - "tp3780i::DspInterrupt, return false from dsp3780i_GetIPCSource\n"); } - PRINTK_1(TRACE_TP3780I, "tp3780i::DspInterrupt exit\n"); return IRQ_HANDLED; } @@ -157,9 +128,6 @@ int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData) int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; - - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_InitializeBoardData entry pBDData %p\n", pBDData); - pBDData->bDSPEnabled = false; pSettings->bInterruptClaimed = false; @@ -172,15 +140,11 @@ int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData) } } - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_InitializeBoardData exit retval %x\n", retval); - return retval; } void tp3780I_Cleanup(THINKPAD_BD_DATA *pBDData) { - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_Cleanup entry and exit pBDData %p\n", pBDData); } int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) @@ -188,9 +152,6 @@ int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) SMAPI_DSP_SETTINGS rSmapiInfo; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_CalcResources entry pBDData %p\n", pBDData); - if (smapi_query_DSP_cfg(&rSmapiInfo)) { PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Could not query DSP config. Aborting.\n"); return -EIO; @@ -225,8 +186,6 @@ int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) pBDData->bShareDspIrq = pBDData->bShareUartIrq = 0; } - PRINTK_1(TRACE_TP3780I, "tp3780i::tp3780I_CalcResources exit\n"); - return 0; } @@ -237,30 +196,21 @@ int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; struct resource *pres; - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_ClaimResources entry pBDData %p\n", pBDData); - pres = request_region(pSettings->usDspBaseIO, 16, "mwave_3780i"); if ( pres == NULL ) retval = -EIO; if (retval) { PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_ClaimResources: Error: Could not claim I/O region starting at %x\n", pSettings->usDspBaseIO); - retval = -EIO; + return -EIO; } - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ClaimResources exit retval %x\n", retval); - return retval; } int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData) { - int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_ReleaseResources entry pBDData %p\n", pBDData); - release_region(pSettings->usDspBaseIO & (~3), 16); if (pSettings->bInterruptClaimed) { @@ -268,10 +218,7 @@ int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData) pSettings->bInterruptClaimed = false; } - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_ReleaseResources exit retval %x\n", retval); - - return retval; + return 0; } @@ -281,8 +228,6 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; bool bDSPPoweredUp = false, bInterruptAllocated = false; - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_EnableDSP entry pBDData %p\n", pBDData); - if (pBDData->bDSPEnabled) { PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: DSP already enabled!\n"); goto exit_cleanup; @@ -366,9 +311,6 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Could not get 3780i IRQ %x\n", pSettings->usDspIrq); goto exit_cleanup; } else { - PRINTK_3(TRACE_TP3780I, - "tp3780i::tp3780I_EnableDSP, got interrupt %x bShareDspIrq %x\n", - pSettings->usDspIrq, pBDData->bShareDspIrq); bInterruptAllocated = true; pSettings->bInterruptClaimed = true; } @@ -390,8 +332,6 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) pBDData->bDSPEnabled = true; - PRINTK_1(TRACE_TP3780I, "tp3780i::tp3780I_EnableDSP exit\n"); - return 0; exit_cleanup: @@ -408,11 +348,8 @@ exit_cleanup: int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData) { - int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_DisableDSP entry pBDData %p\n", pBDData); - if (pBDData->bDSPEnabled) { dsp3780I_DisableDSP(&pBDData->rDspSettings); if (pSettings->bInterruptClaimed) { @@ -423,56 +360,38 @@ int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData) pBDData->bDSPEnabled = false; } - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_DisableDSP exit retval %x\n", retval); - - return retval; + return 0; } int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData) { - int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ResetDSP entry pBDData %p\n", - pBDData); - if (dsp3780I_Reset(pSettings) == 0) { EnableSRAM(pBDData); - } else { - retval = -EIO; + return 0; } - - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ResetDSP exit retval %x\n", retval); - - return retval; + return -EIO; } int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData) { - int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_StartDSP entry pBDData %p\n", pBDData); - if (dsp3780I_Run(pSettings) == 0) { // @BUG @TBD EnableSRAM(pBDData); } else { - retval = -EIO; + return -EIO; } - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_StartDSP exit retval %x\n", retval); - - return retval; + return 0; } int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities) { - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_QueryAbilities entry pBDData %p\n", pBDData); - memset(pAbilities, 0, sizeof(*pAbilities)); /* fill out standard constant fields */ pAbilities->instr_per_sec = pBDData->rDspSettings.uIps; @@ -497,9 +416,6 @@ int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities memcpy(pAbilities->bios_task_name, TP_ABILITIES_BIOSTASK_NAME, sizeof(TP_ABILITIES_BIOSTASK_NAME)); - PRINTK_1(TRACE_TP3780I, - "tp3780i::tp3780I_QueryAbilities exit retval=SUCCESSFUL\n"); - return 0; } @@ -507,15 +423,10 @@ int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, void __user *pvBuffer, unsigned int uCount, unsigned long ulDSPAddr) { - int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; unsigned short usDspBaseIO = pSettings->usDspBaseIO; bool bRC = 0; - PRINTK_6(TRACE_TP3780I, - "tp3780i::tp3780I_ReadWriteDspDStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx\n", - pBDData, uOpcode, pvBuffer, uCount, ulDSPAddr); - if (pBDData->bDSPEnabled) { switch (uOpcode) { case IOCTL_MW_READ_DATA: @@ -532,10 +443,7 @@ int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, } } - retval = (bRC) ? -EIO : 0; - PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ReadWriteDspDStore exit retval %x\n", retval); - - return retval; + return bRC ? -EIO : 0; } @@ -543,15 +451,10 @@ int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, void __user *pvBuffer, unsigned int uCount, unsigned long ulDSPAddr) { - int retval = 0; DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; unsigned short usDspBaseIO = pSettings->usDspBaseIO; bool bRC = 0; - PRINTK_6(TRACE_TP3780I, - "tp3780i::tp3780I_ReadWriteDspIStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx\n", - pBDData, uOpcode, pvBuffer, uCount, ulDSPAddr); - if (pBDData->bDSPEnabled) { switch (uOpcode) { case IOCTL_MW_READ_INST: @@ -564,11 +467,6 @@ int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, } } - retval = (bRC) ? -EIO : 0; - - PRINTK_2(TRACE_TP3780I, - "tp3780i::tp3780I_ReadWriteDspIStore exit retval %x\n", retval); - - return retval; + return bRC ? -EIO : 0; } From 1c7e15b0e5b411589c6c5e3935f19f60bb52dd6c Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Wed, 19 Nov 2025 10:19:48 +0100 Subject: [PATCH 288/304] char/mwave: drop printk wrapper PRINTK_ERROR() + KERN_ERR_MWAVE are just wrappers around printk() with a prefix. Instead, pr_fmt() can be used. Drop the former and use the latter. Signed-off-by: Jiri Slaby (SUSE) Acked-by: Arnd Bergmann Link: https://patch.msgid.link/20251119091949.825958-6-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/char/mwave/3780i.c | 4 ++- drivers/char/mwave/mwavedd.c | 58 +++++++++++------------------------ drivers/char/mwave/mwavedd.h | 3 -- drivers/char/mwave/smapi.c | 59 +++++++++++++++++++++--------------- drivers/char/mwave/tp3780i.c | 35 ++++++++++++--------- 5 files changed, 74 insertions(+), 85 deletions(-) diff --git a/drivers/char/mwave/3780i.c b/drivers/char/mwave/3780i.c index 6024cf7d5705..a1bd9dd36d21 100644 --- a/drivers/char/mwave/3780i.c +++ b/drivers/char/mwave/3780i.c @@ -46,6 +46,8 @@ * First release to the public */ +#define pr_fmt(fmt) "3780i: " fmt + #include #include #include @@ -138,7 +140,7 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, unsigned short tval; if (!pSettings->bDSPEnabled) { - PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" ); + pr_err("%s: Error: DSP not enabled. Aborting.\n", __func__); return -EIO; } diff --git a/drivers/char/mwave/mwavedd.c b/drivers/char/mwave/mwavedd.c index f01c6f7d54a3..6ab355cfe43e 100644 --- a/drivers/char/mwave/mwavedd.c +++ b/drivers/char/mwave/mwavedd.c @@ -46,6 +46,8 @@ * First release to the public */ +#define pr_fmt(fmt) "mwavedd: " fmt + #include #include #include @@ -200,11 +202,8 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, unsigned int ipcnum = (unsigned int) ioarg; if (ipcnum >= ARRAY_SIZE(pDrvData->IPCs)) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::mwave_ioctl:" - " IOCTL_MW_REGISTER_IPC:" - " Error: Invalid ipcnum %x\n", - ipcnum); + pr_err("%s: IOCTL_MW_REGISTER_IPC: Error: Invalid ipcnum %x\n", + __func__, ipcnum); return -EINVAL; } ipcnum = array_index_nospec(ipcnum, @@ -221,10 +220,8 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, unsigned int ipcnum = (unsigned int) ioarg; if (ipcnum >= ARRAY_SIZE(pDrvData->IPCs)) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::mwave_ioctl:" - " IOCTL_MW_GET_IPC: Error:" - " Invalid ipcnum %x\n", ipcnum); + pr_err("%s: IOCTL_MW_GET_IPC: Error: Invalid ipcnum %x\n", __func__, + ipcnum); return -EINVAL; } ipcnum = array_index_nospec(ipcnum, @@ -259,11 +256,8 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, unsigned int ipcnum = (unsigned int) ioarg; if (ipcnum >= ARRAY_SIZE(pDrvData->IPCs)) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::mwave_ioctl:" - " IOCTL_MW_UNREGISTER_IPC:" - " Error: Invalid ipcnum %x\n", - ipcnum); + pr_err("%s: IOCTL_MW_UNREGISTER_IPC: Error: Invalid ipcnum %x\n", + __func__, ipcnum); return -EINVAL; } ipcnum = array_index_nospec(ipcnum, @@ -298,9 +292,7 @@ static int register_serial_portandirq(unsigned int port, int irq) /* OK */ break; default: - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::register_serial_portandirq:" - " Error: Illegal port %x\n", port ); + pr_err("%s: Error: Illegal port %x\n", __func__, port); return -1; } /* switch */ /* port is okay */ @@ -313,9 +305,7 @@ static int register_serial_portandirq(unsigned int port, int irq) /* OK */ break; default: - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::register_serial_portandirq:" - " Error: Illegal irq %x\n", irq ); + pr_err("%s: Error: Illegal irq %x\n", __func__, irq); return -1; } /* switch */ /* irq is okay */ @@ -391,43 +381,33 @@ static int __init mwave_init(void) retval = tp3780I_InitializeBoardData(&pDrvData->rBDData); if (retval) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::mwave_init: Error:" - " Failed to initialize board data\n"); + pr_err("%s: Error: Failed to initialize board data\n", __func__); goto cleanup_error; } pDrvData->bBDInitialized = true; retval = tp3780I_CalcResources(&pDrvData->rBDData); if (retval) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd:mwave_init: Error:" - " Failed to calculate resources\n"); + pr_err("%s: Error: Failed to calculate resources\n", __func__); goto cleanup_error; } retval = tp3780I_ClaimResources(&pDrvData->rBDData); if (retval) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd:mwave_init: Error:" - " Failed to claim resources\n"); + pr_err("%s: Error: Failed to claim resources\n", __func__); goto cleanup_error; } pDrvData->bResourcesClaimed = true; retval = tp3780I_EnableDSP(&pDrvData->rBDData); if (retval) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd:mwave_init: Error:" - " Failed to enable DSP\n"); + pr_err("%s: Error: Failed to enable DSP\n", __func__); goto cleanup_error; } pDrvData->bDSPEnabled = true; if (misc_register(&mwave_misc_dev) < 0) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd:mwave_init: Error:" - " Failed to register misc device\n"); + pr_err("%s: Error: Failed to register misc device\n", __func__); goto cleanup_error; } pDrvData->bMwaveDevRegistered = true; @@ -437,9 +417,7 @@ static int __init mwave_init(void) pDrvData->rBDData.rDspSettings.usUartIrq ); if (pDrvData->sLine < 0) { - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd:mwave_init: Error:" - " Failed to register serial driver\n"); + pr_err("%s: Error: Failed to register serial driver\n", __func__); goto cleanup_error; } /* uart is registered */ @@ -448,9 +426,7 @@ static int __init mwave_init(void) return 0; cleanup_error: - PRINTK_ERROR(KERN_ERR_MWAVE - "mwavedd::mwave_init: Error:" - " Failed to initialize\n"); + pr_err("%s: Error: Failed to initialize\n", __func__); mwave_exit(); /* clean up */ return -EIO; diff --git a/drivers/char/mwave/mwavedd.h b/drivers/char/mwave/mwavedd.h index fdd5dfdd3639..453305494d12 100644 --- a/drivers/char/mwave/mwavedd.h +++ b/drivers/char/mwave/mwavedd.h @@ -61,9 +61,6 @@ extern int mwave_3780i_io; extern int mwave_uart_irq; extern int mwave_uart_io; -#define PRINTK_ERROR printk -#define KERN_ERR_MWAVE KERN_ERR "mwave: " - typedef struct _MWAVE_IPC { unsigned short usIntCount; /* 0=none, 1=first, 2=greater than 1st */ bool bIsEnabled; diff --git a/drivers/char/mwave/smapi.c b/drivers/char/mwave/smapi.c index 1efddb34bef0..107a2cb9c31c 100644 --- a/drivers/char/mwave/smapi.c +++ b/drivers/char/mwave/smapi.c @@ -46,6 +46,8 @@ * First release to the public */ +#define pr_fmt(fmt) "smapi: " fmt + #include #include /* CMOS defines */ #include "smapi.h" @@ -127,7 +129,7 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) bRC = smapi_request(0x1802, 0x0000, 0, 0, &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); if (bRC) { - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Error: Could not get DSP Settings. Aborting.\n"); + pr_err("%s: Error: Could not get DSP Settings. Aborting.\n", __func__); return bRC; } @@ -143,14 +145,14 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) /* check for illegal values */ if ( pSettings->usDspBaseIO == 0 ) - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: DSP base I/O address is 0\n"); + pr_err("%s: Worry: DSP base I/O address is 0\n", __func__); if ( pSettings->usDspIRQ == 0 ) - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: DSP IRQ line is 0\n"); + pr_err("%s: Worry: DSP IRQ line is 0\n", __func__); bRC = smapi_request(0x1804, 0x0000, 0, 0, &usAX, &usBX, &usCX, &usDX, &usDI, &usSI); if (bRC) { - PRINTK_ERROR("smapi::smapi_query_DSP_cfg: Error: Could not get DSP modem settings. Aborting.\n"); + pr_err("%s: Error: Could not get DSP modem settings. Aborting.\n", __func__); return bRC; } @@ -164,9 +166,9 @@ int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) /* check for illegal values */ if ( pSettings->usUartBaseIO == 0 ) - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: UART base I/O address is 0\n"); + pr_err("%s: Worry: UART base I/O address is 0\n", __func__); if ( pSettings->usUartIRQ == 0 ) - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: UART IRQ line is 0\n"); + pr_err("%s: Worry: UART IRQ line is 0\n", __func__); return bRC; } @@ -195,7 +197,8 @@ int smapi_set_DSP_cfg(void) break; } if (i == ARRAY_SIZE(ausDspBases)) { - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_3780i_io address %x. Aborting.\n", mwave_3780i_io); + pr_err("%s: Error: Invalid mwave_3780i_io address %x. Aborting.\n", + __func__, mwave_3780i_io); return bRC; } dspio_index = i; @@ -207,7 +210,8 @@ int smapi_set_DSP_cfg(void) break; } if (i == ARRAY_SIZE(ausDspIrqs)) { - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_3780i_irq %x. Aborting.\n", mwave_3780i_irq); + pr_err("%s: Error: Invalid mwave_3780i_irq %x. Aborting.\n", __func__, + mwave_3780i_irq); return bRC; } } @@ -218,7 +222,8 @@ int smapi_set_DSP_cfg(void) break; } if (i == ARRAY_SIZE(ausUartBases)) { - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_uart_io address %x. Aborting.\n", mwave_uart_io); + pr_err("%s: Error: Invalid mwave_uart_io address %x. Aborting.\n", __func__, + mwave_uart_io); return bRC; } uartio_index = i; @@ -231,7 +236,8 @@ int smapi_set_DSP_cfg(void) break; } if (i == ARRAY_SIZE(ausUartIrqs)) { - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_uart_irq %x. Aborting.\n", mwave_uart_irq); + pr_err("%s: Error: Invalid mwave_uart_irq %x. Aborting.\n", __func__, + mwave_uart_irq); return bRC; } } @@ -246,13 +252,14 @@ int smapi_set_DSP_cfg(void) if (usBX & 0x0100) { /* serial port A is present */ if (usCX & 1) { /* serial port is enabled */ if ((usSI & 0xFF) == mwave_uart_irq) { - PRINTK_ERROR(KERN_ERR_MWAVE - "smapi::smapi_set_DSP_cfg: Serial port A irq %x conflicts with mwave_uart_irq %x\n", usSI & 0xFF, mwave_uart_irq); + pr_err("%s: Serial port A irq %x conflicts with mwave_uart_irq %x\n", + __func__, usSI & 0xFF, mwave_uart_irq); goto exit_conflict; } else { if ((usSI >> 8) == uartio_index) { - PRINTK_ERROR(KERN_ERR_MWAVE - "smapi::smapi_set_DSP_cfg: Serial port A base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI >> 8], ausUartBases[uartio_index]); + pr_err("%s: Serial port A base I/O address %x conflicts with mwave uart I/O %x\n", + __func__, ausUartBases[usSI >> 8], + ausUartBases[uartio_index]); goto exit_conflict; } } @@ -267,13 +274,14 @@ int smapi_set_DSP_cfg(void) if (usBX & 0x0100) { /* serial port B is present */ if (usCX & 1) { /* serial port is enabled */ if ((usSI & 0xFF) == mwave_uart_irq) { - PRINTK_ERROR(KERN_ERR_MWAVE - "smapi::smapi_set_DSP_cfg: Serial port B irq %x conflicts with mwave_uart_irq %x\n", usSI & 0xFF, mwave_uart_irq); + pr_err("%s: Serial port B irq %x conflicts with mwave_uart_irq %x\n", + __func__, usSI & 0xFF, mwave_uart_irq); goto exit_conflict; } else { if ((usSI >> 8) == uartio_index) { - PRINTK_ERROR(KERN_ERR_MWAVE - "smapi::smapi_set_DSP_cfg: Serial port B base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI >> 8], ausUartBases[uartio_index]); + pr_err("%s: Serial port B base I/O address %x conflicts with mwave uart I/O %x\n", + __func__, ausUartBases[usSI >> 8], + ausUartBases[uartio_index]); goto exit_conflict; } } @@ -290,13 +298,14 @@ int smapi_set_DSP_cfg(void) /* bRC == 0 */ if ((usCX & 0xff) != 0xff) { /* IR port not disabled */ if ((usCX & 0xff) == mwave_uart_irq) { - PRINTK_ERROR(KERN_ERR_MWAVE - "smapi::smapi_set_DSP_cfg: IR port irq %x conflicts with mwave_uart_irq %x\n", usCX & 0xff, mwave_uart_irq); + pr_err("%s: IR port irq %x conflicts with mwave_uart_irq %x\n", + __func__, usCX & 0xff, mwave_uart_irq); goto exit_conflict; } else { if ((usSI & 0xff) == uartio_index) { - PRINTK_ERROR(KERN_ERR_MWAVE - "smapi::smapi_set_DSP_cfg: IR port base I/O address %x conflicts with mwave uart I/O %x\n", ausUartBases[usSI & 0xff], ausUartBases[uartio_index]); + pr_err("%s: IR port base I/O address %x conflicts with mwave uart I/O %x\n", + __func__, ausUartBases[usSI & 0xff], + ausUartBases[uartio_index]); goto exit_conflict; } } @@ -348,7 +357,7 @@ exit_conflict: return -EIO; exit_smapi_request_error: - PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg exit on smapi_request error bRC %x\n", bRC); + pr_err("%s: exit on smapi_request error bRC %x\n", __func__, bRC); return bRC; } @@ -381,13 +390,13 @@ int smapi_init(void) g_usSmapiPort |= (CMOS_READ(0x7F) << 8); spin_unlock_irqrestore(&rtc_lock, flags); if (g_usSmapiPort == 0) { - PRINTK_ERROR("smapi::smapi_init, ERROR unable to read from SMAPI port\n"); + pr_err("%s: ERROR unable to read from SMAPI port\n", __func__); } else { retval = 0; //SmapiQuerySystemID(); } } else { - PRINTK_ERROR("smapi::smapi_init, ERROR invalid usSmapiID\n"); + pr_err("%s: ERROR invalid usSmapiID\n", __func__); retval = -ENXIO; } diff --git a/drivers/char/mwave/tp3780i.c b/drivers/char/mwave/tp3780i.c index b7e95c57a1c4..6a924e1bc678 100644 --- a/drivers/char/mwave/tp3780i.c +++ b/drivers/char/mwave/tp3780i.c @@ -46,6 +46,8 @@ * First release to the public */ +#define pr_fmt(fmt) "tp3780i: " fmt + #include #include #include @@ -133,7 +135,7 @@ int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData) retval = smapi_init(); if (retval) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_InitializeBoardData: Error: SMAPI is not available on this machine\n"); + pr_err("%s: Error: SMAPI is not available on this machine\n", __func__); } else { if (mwave_3780i_irq || mwave_3780i_io || mwave_uart_irq || mwave_uart_io) { retval = smapi_set_DSP_cfg(); @@ -153,7 +155,7 @@ int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; if (smapi_query_DSP_cfg(&rSmapiInfo)) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Could not query DSP config. Aborting.\n"); + pr_err("%s: Error: Could not query DSP config. Aborting.\n", __func__); return -EIO; } @@ -164,7 +166,7 @@ int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) || ( rSmapiInfo.usUartIRQ == 0 ) || ( rSmapiInfo.usUartBaseIO == 0 ) ) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Illegal resource setting. Aborting.\n"); + pr_err("%s: Error: Illegal resource setting. Aborting.\n", __func__); return -EIO; } @@ -200,7 +202,8 @@ int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData) if ( pres == NULL ) retval = -EIO; if (retval) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_ClaimResources: Error: Could not claim I/O region starting at %x\n", pSettings->usDspBaseIO); + pr_err("%s: Error: Could not claim I/O region starting at %x\n", __func__, + pSettings->usDspBaseIO); return -EIO; } @@ -229,12 +232,12 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) bool bDSPPoweredUp = false, bInterruptAllocated = false; if (pBDData->bDSPEnabled) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: DSP already enabled!\n"); + pr_err("%s: Error: DSP already enabled!\n", __func__); goto exit_cleanup; } if (!pSettings->bDSPEnabled) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780::tp3780I_EnableDSP: Error: pSettings->bDSPEnabled not set\n"); + pr_err("%s: Error: pSettings->bDSPEnabled not set\n", __func__); goto exit_cleanup; } @@ -244,7 +247,7 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) || (s_ausThinkpadIrqToField[pSettings->usDspIrq] == 0xFFFF) || (s_ausThinkpadDmaToField[pSettings->usDspDma] == 0xFFFF) ) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: invalid irq %x\n", pSettings->usDspIrq); + pr_err("%s: Error: invalid irq %x\n", __func__, pSettings->usDspIrq); goto exit_cleanup; } @@ -252,7 +255,8 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) ((pSettings->usDspBaseIO & 0xF00F) != 0) || (pSettings->usDspBaseIO & 0x0FF0) == 0 ) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Invalid DSP base I/O address %x\n", pSettings->usDspBaseIO); + pr_err("%s: Error: Invalid DSP base I/O address %x\n", __func__, + pSettings->usDspBaseIO); goto exit_cleanup; } @@ -261,7 +265,7 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) pSettings->usUartIrq >= s_numIrqs || s_ausThinkpadIrqToField[pSettings->usUartIrq] == 0xFFFF ) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Invalid UART IRQ %x\n", pSettings->usUartIrq); + pr_err("%s: Error: Invalid UART IRQ %x\n", __func__, pSettings->usUartIrq); goto exit_cleanup; } switch (pSettings->usUartBaseIO) { @@ -272,7 +276,8 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) break; default: - PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Invalid UART base I/O address %x\n", pSettings->usUartBaseIO); + pr_err("%s: Error: Invalid UART base I/O address %x\n", __func__, + pSettings->usUartBaseIO); goto exit_cleanup; } } @@ -301,14 +306,14 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) pSettings->usChipletEnable = TP_CFG_ChipletEnable; if (request_irq(pSettings->usUartIrq, &UartInterrupt, 0, "mwave_uart", NULL)) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Could not get UART IRQ %x\n", pSettings->usUartIrq); + pr_err("%s: Error: Could not get UART IRQ %x\n", __func__, pSettings->usUartIrq); goto exit_cleanup; } else { /* no conflict just release */ free_irq(pSettings->usUartIrq, NULL); } if (request_irq(pSettings->usDspIrq, &DspInterrupt, 0, "mwave_3780i", NULL)) { - PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Could not get 3780i IRQ %x\n", pSettings->usDspIrq); + pr_err("%s: Error: Could not get 3780i IRQ %x\n", __func__, pSettings->usDspIrq); goto exit_cleanup; } else { bInterruptAllocated = true; @@ -317,14 +322,14 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) smapi_set_DSP_power_state(false); if (smapi_set_DSP_power_state(true)) { - PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: smapi_set_DSP_power_state(true) failed\n"); + pr_err("%s: Error: smapi_set_DSP_power_state(true) failed\n", __func__); goto exit_cleanup; } else { bDSPPoweredUp = true; } if (dsp3780I_EnableDSP(pSettings, s_ausThinkpadIrqToField, s_ausThinkpadDmaToField)) { - PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: dsp7880I_EnableDSP() failed\n"); + pr_err("%s: Error: dsp7880I_EnableDSP() failed\n", __func__); goto exit_cleanup; } @@ -335,7 +340,7 @@ int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) return 0; exit_cleanup: - PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Cleaning up\n"); + pr_err("%s: Cleaning up\n", __func__); if (bDSPPoweredUp) smapi_set_DSP_power_state(false); if (bInterruptAllocated) { From 00a925eee854e41bb6654e40246b8e7cf183ea0f Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Wed, 19 Nov 2025 10:19:49 +0100 Subject: [PATCH 289/304] char/mwave: drop typedefs typedefs are unnecessary here. They rather obfuscate the code than help. So drop them and use the types directly. Signed-off-by: Jiri Slaby (SUSE) Acked-by: Arnd Bergmann Link: https://patch.msgid.link/20251119091949.825958-7-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/char/mwave/3780i.c | 8 +++--- drivers/char/mwave/3780i.h | 12 ++++---- drivers/char/mwave/mwavedd.c | 34 ++++++++++------------ drivers/char/mwave/mwavedd.h | 14 ++++----- drivers/char/mwave/mwavepub.h | 22 +++++++------- drivers/char/mwave/smapi.c | 2 +- drivers/char/mwave/smapi.h | 6 ++-- drivers/char/mwave/tp3780i.c | 54 +++++++++++++++++------------------ drivers/char/mwave/tp3780i.h | 30 +++++++++---------- 9 files changed, 89 insertions(+), 93 deletions(-) diff --git a/drivers/char/mwave/3780i.c b/drivers/char/mwave/3780i.c index a1bd9dd36d21..90f93cefb21c 100644 --- a/drivers/char/mwave/3780i.c +++ b/drivers/char/mwave/3780i.c @@ -115,7 +115,7 @@ static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex, OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); } -int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, +int dsp3780I_EnableDSP(struct dsp_3780i_config_settings *pSettings, unsigned short *pIrqMap, unsigned short *pDmaMap) { @@ -260,7 +260,7 @@ int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, return 0; } -int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) +int dsp3780I_DisableDSP(struct dsp_3780i_config_settings *pSettings) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; @@ -284,7 +284,7 @@ int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) return 0; } -int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) +int dsp3780I_Reset(struct dsp_3780i_config_settings *pSettings) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; @@ -317,7 +317,7 @@ int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) } -int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) +int dsp3780I_Run(struct dsp_3780i_config_settings *pSettings) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; diff --git a/drivers/char/mwave/3780i.h b/drivers/char/mwave/3780i.h index 95164246afd1..53dafceb20e0 100644 --- a/drivers/char/mwave/3780i.h +++ b/drivers/char/mwave/3780i.h @@ -261,7 +261,7 @@ typedef struct { * the only values maintained by the 3780i support layer are the saved UART * registers. */ -typedef struct _DSP_3780I_CONFIG_SETTINGS { +struct dsp_3780i_config_settings { /* Location of base configuration register */ unsigned short usBaseConfigIO; @@ -313,16 +313,16 @@ typedef struct _DSP_3780I_CONFIG_SETTINGS { unsigned char ucSCR; /* Scratch register */ unsigned char ucDLL; /* Divisor latch, low byte */ unsigned char ucDLM; /* Divisor latch, high byte */ -} DSP_3780I_CONFIG_SETTINGS; +}; /* 3780i support functions */ -int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, +int dsp3780I_EnableDSP(struct dsp_3780i_config_settings *pSettings, unsigned short *pIrqMap, unsigned short *pDmaMap); -int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings); -int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings); -int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings); +int dsp3780I_DisableDSP(struct dsp_3780i_config_settings *pSettings); +int dsp3780I_Reset(struct dsp_3780i_config_settings *pSettings); +int dsp3780I_Run(struct dsp_3780i_config_settings *pSettings); int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned uCount, unsigned long ulDSPAddr); int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, diff --git a/drivers/char/mwave/mwavedd.c b/drivers/char/mwave/mwavedd.c index 6ab355cfe43e..640a9cb0dd8d 100644 --- a/drivers/char/mwave/mwavedd.c +++ b/drivers/char/mwave/mwavedd.c @@ -86,13 +86,13 @@ module_param_hw(mwave_3780i_io, int, ioport, 0); module_param_hw(mwave_uart_irq, int, irq, 0); module_param_hw(mwave_uart_io, int, ioport, 0); -MWAVE_DEVICE_DATA mwave_s_mdd; +struct mwave_device_data mwave_s_mdd; static long mwave_ioctl(struct file *file, unsigned int iocmd, unsigned long ioarg) { unsigned int retval = 0; - pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; + struct mwave_device_data *pDrvData = &mwave_s_mdd; void __user *arg = (void __user *)ioarg; switch (iocmd) { @@ -110,15 +110,14 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, break; case IOCTL_MW_DSP_ABILITIES: { - MW_ABILITIES rAbilities; + struct mw_abilities rAbilities; mutex_lock(&mwave_mutex); retval = tp3780I_QueryAbilities(&pDrvData->rBDData, &rAbilities); mutex_unlock(&mwave_mutex); if (retval == 0) { - if( copy_to_user(arg, &rAbilities, - sizeof(MW_ABILITIES)) ) + if (copy_to_user(arg, &rAbilities, sizeof(rAbilities))) return -EFAULT; } } @@ -126,11 +125,11 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, case IOCTL_MW_READ_DATA: case IOCTL_MW_READCLEAR_DATA: { - MW_READWRITE rReadData; + struct mw_readwrite rReadData; unsigned short __user *pusBuffer = NULL; if( copy_from_user(&rReadData, arg, - sizeof(MW_READWRITE)) ) + sizeof(struct mw_readwrite)) ) return -EFAULT; pusBuffer = (unsigned short __user *) (rReadData.pBuf); @@ -145,11 +144,10 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, break; case IOCTL_MW_READ_INST: { - MW_READWRITE rReadData; + struct mw_readwrite rReadData; unsigned short __user *pusBuffer = NULL; - if( copy_from_user(&rReadData, arg, - sizeof(MW_READWRITE)) ) + if (copy_from_user(&rReadData, arg, sizeof(rReadData))) return -EFAULT; pusBuffer = (unsigned short __user *) (rReadData.pBuf); @@ -163,11 +161,10 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, break; case IOCTL_MW_WRITE_DATA: { - MW_READWRITE rWriteData; + struct mw_readwrite rWriteData; unsigned short __user *pusBuffer = NULL; - if( copy_from_user(&rWriteData, arg, - sizeof(MW_READWRITE)) ) + if (copy_from_user(&rWriteData, arg, sizeof(rWriteData))) return -EFAULT; pusBuffer = (unsigned short __user *) (rWriteData.pBuf); @@ -181,11 +178,10 @@ static long mwave_ioctl(struct file *file, unsigned int iocmd, break; case IOCTL_MW_WRITE_INST: { - MW_READWRITE rWriteData; + struct mw_readwrite rWriteData; unsigned short __user *pusBuffer = NULL; - if( copy_from_user(&rWriteData, arg, - sizeof(MW_READWRITE)) ) + if (copy_from_user(&rWriteData, arg, sizeof(rWriteData))) return -EFAULT; pusBuffer = (unsigned short __user *)(rWriteData.pBuf); @@ -336,7 +332,7 @@ static struct miscdevice mwave_misc_dev = { MWAVE_MINOR, "mwave", &mwave_fops }; */ static void mwave_exit(void) { - pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; + struct mwave_device_data *pDrvData = &mwave_s_mdd; if ( pDrvData->sLine >= 0 ) { serial8250_unregister_port(pDrvData->sLine); @@ -361,9 +357,9 @@ static int __init mwave_init(void) { int i; int retval = 0; - pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; + struct mwave_device_data *pDrvData = &mwave_s_mdd; - memset(&mwave_s_mdd, 0, sizeof(MWAVE_DEVICE_DATA)); + memset(&mwave_s_mdd, 0, sizeof(mwave_s_mdd)); pDrvData->bBDInitialized = false; pDrvData->bResourcesClaimed = false; diff --git a/drivers/char/mwave/mwavedd.h b/drivers/char/mwave/mwavedd.h index 453305494d12..e1da1493eec5 100644 --- a/drivers/char/mwave/mwavedd.h +++ b/drivers/char/mwave/mwavedd.h @@ -61,30 +61,30 @@ extern int mwave_3780i_io; extern int mwave_uart_irq; extern int mwave_uart_io; -typedef struct _MWAVE_IPC { +struct mwave_ipc { unsigned short usIntCount; /* 0=none, 1=first, 2=greater than 1st */ bool bIsEnabled; bool bIsHere; /* entry spin lock */ wait_queue_head_t ipc_wait_queue; -} MWAVE_IPC; +}; -typedef struct _MWAVE_DEVICE_DATA { - THINKPAD_BD_DATA rBDData; /* board driver's data area */ +struct mwave_device_data { + struct thinkpad_bd_data rBDData; /* board driver's data area */ unsigned long ulIPCSource_ISR; /* IPC source bits for recently processed intr, set during ISR processing */ unsigned long ulIPCSource_DPC; /* IPC source bits for recently processed intr, set during DPC processing */ bool bBDInitialized; bool bResourcesClaimed; bool bDSPEnabled; bool bDSPReset; - MWAVE_IPC IPCs[16]; + struct mwave_ipc IPCs[16]; bool bMwaveDevRegistered; short sLine; int nr_registered_attrs; int device_registered; -} MWAVE_DEVICE_DATA, *pMWAVE_DEVICE_DATA; +}; -extern MWAVE_DEVICE_DATA mwave_s_mdd; +extern struct mwave_device_data mwave_s_mdd; #endif diff --git a/drivers/char/mwave/mwavepub.h b/drivers/char/mwave/mwavepub.h index 60c961ae23b4..280327bdaa38 100644 --- a/drivers/char/mwave/mwavepub.h +++ b/drivers/char/mwave/mwavepub.h @@ -53,7 +53,7 @@ #include -typedef struct _MW_ABILITIES { +struct mw_abilities { unsigned long instr_per_sec; unsigned long data_size; unsigned long inst_size; @@ -63,27 +63,27 @@ typedef struct _MW_ABILITIES { unsigned long component_list[7]; char mwave_os_name[16]; char bios_task_name[16]; -} MW_ABILITIES, *pMW_ABILITIES; +}; -typedef struct _MW_READWRITE { +struct mw_readwrite { unsigned short usDspAddress; /* The dsp address */ unsigned long ulDataLength; /* The size in bytes of the data or user buffer */ void __user *pBuf; /* Input:variable sized buffer */ -} MW_READWRITE, *pMW_READWRITE; +}; #define IOCTL_MW_RESET _IO(MWAVE_MINOR,1) #define IOCTL_MW_RUN _IO(MWAVE_MINOR,2) -#define IOCTL_MW_DSP_ABILITIES _IOR(MWAVE_MINOR,3,MW_ABILITIES) -#define IOCTL_MW_READ_DATA _IOR(MWAVE_MINOR,4,MW_READWRITE) -#define IOCTL_MW_READCLEAR_DATA _IOR(MWAVE_MINOR,5,MW_READWRITE) -#define IOCTL_MW_READ_INST _IOR(MWAVE_MINOR,6,MW_READWRITE) -#define IOCTL_MW_WRITE_DATA _IOW(MWAVE_MINOR,7,MW_READWRITE) -#define IOCTL_MW_WRITE_INST _IOW(MWAVE_MINOR,8,MW_READWRITE) +#define IOCTL_MW_DSP_ABILITIES _IOR(MWAVE_MINOR,3,struct mw_abilities) +#define IOCTL_MW_READ_DATA _IOR(MWAVE_MINOR,4,struct mw_readwrite) +#define IOCTL_MW_READCLEAR_DATA _IOR(MWAVE_MINOR,5,struct mw_readwrite) +#define IOCTL_MW_READ_INST _IOR(MWAVE_MINOR,6,struct mw_readwrite) +#define IOCTL_MW_WRITE_DATA _IOW(MWAVE_MINOR,7,struct mw_readwrite) +#define IOCTL_MW_WRITE_INST _IOW(MWAVE_MINOR,8,struct mw_readwrite) #define IOCTL_MW_REGISTER_IPC _IOW(MWAVE_MINOR,9,int) #define IOCTL_MW_UNREGISTER_IPC _IOW(MWAVE_MINOR,10,int) #define IOCTL_MW_GET_IPC _IOW(MWAVE_MINOR,11,int) -#define IOCTL_MW_TRACE _IOR(MWAVE_MINOR,12,MW_READWRITE) +#define IOCTL_MW_TRACE _IOR(MWAVE_MINOR,12,struct mw_readwrite) #endif diff --git a/drivers/char/mwave/smapi.c b/drivers/char/mwave/smapi.c index 107a2cb9c31c..df6354b24339 100644 --- a/drivers/char/mwave/smapi.c +++ b/drivers/char/mwave/smapi.c @@ -116,7 +116,7 @@ static int smapi_request(unsigned short inBX, unsigned short inCX, } -int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings) +int smapi_query_DSP_cfg(struct smapi_dsp_settings *pSettings) { int bRC; unsigned short usAX, usBX, usCX, usDX, usDI, usSI; diff --git a/drivers/char/mwave/smapi.h b/drivers/char/mwave/smapi.h index ebc206b000b9..e605b16ed23c 100644 --- a/drivers/char/mwave/smapi.h +++ b/drivers/char/mwave/smapi.h @@ -49,7 +49,7 @@ #ifndef _LINUX_SMAPI_H #define _LINUX_SMAPI_H -typedef struct { +struct smapi_dsp_settings { int bDSPPresent; int bDSPEnabled; int bModemEnabled; @@ -65,10 +65,10 @@ typedef struct { unsigned short usSndblstIRQ; unsigned short usSndblstDMA; unsigned short usSndblstBaseIO; -} SMAPI_DSP_SETTINGS; +}; int smapi_init(void); -int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings); +int smapi_query_DSP_cfg(struct smapi_dsp_settings *pSettings); int smapi_set_DSP_cfg(void); int smapi_set_DSP_power_state(bool bOn); diff --git a/drivers/char/mwave/tp3780i.c b/drivers/char/mwave/tp3780i.c index 6a924e1bc678..7363b0f764e0 100644 --- a/drivers/char/mwave/tp3780i.c +++ b/drivers/char/mwave/tp3780i.c @@ -67,9 +67,9 @@ static unsigned short s_ausThinkpadDmaToField[8] = static unsigned short s_numIrqs = 16, s_numDmas = 8; -static void EnableSRAM(THINKPAD_BD_DATA * pBDData) +static void EnableSRAM(struct thinkpad_bd_data *pBDData) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; unsigned short usDspBaseIO = pSettings->usDspBaseIO; DSP_GPIO_OUTPUT_DATA_15_8 rGpioOutputData; DSP_GPIO_DRIVER_ENABLE_15_8 rGpioDriverEnable; @@ -98,8 +98,8 @@ static irqreturn_t UartInterrupt(int irq, void *dev_id) static irqreturn_t DspInterrupt(int irq, void *dev_id) { - pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd; - DSP_3780I_CONFIG_SETTINGS *pSettings = &pDrvData->rBDData.rDspSettings; + struct mwave_device_data *pDrvData = &mwave_s_mdd; + struct dsp_3780i_config_settings *pSettings = &pDrvData->rBDData.rDspSettings; unsigned short usDspBaseIO = pSettings->usDspBaseIO; unsigned short usIPCSource = 0, usIsolationMask, usPCNum; @@ -125,10 +125,10 @@ static irqreturn_t DspInterrupt(int irq, void *dev_id) } -int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData) +int tp3780I_InitializeBoardData(struct thinkpad_bd_data *pBDData) { int retval = 0; - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; pBDData->bDSPEnabled = false; pSettings->bInterruptClaimed = false; @@ -145,14 +145,14 @@ int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData) return retval; } -void tp3780I_Cleanup(THINKPAD_BD_DATA *pBDData) +void tp3780I_Cleanup(struct thinkpad_bd_data *pBDData) { } -int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) +int tp3780I_CalcResources(struct thinkpad_bd_data *pBDData) { - SMAPI_DSP_SETTINGS rSmapiInfo; - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct smapi_dsp_settings rSmapiInfo; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; if (smapi_query_DSP_cfg(&rSmapiInfo)) { pr_err("%s: Error: Could not query DSP config. Aborting.\n", __func__); @@ -192,10 +192,10 @@ int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData) } -int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData) +int tp3780I_ClaimResources(struct thinkpad_bd_data *pBDData) { int retval = 0; - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; struct resource *pres; pres = request_region(pSettings->usDspBaseIO, 16, "mwave_3780i"); @@ -210,9 +210,9 @@ int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData) return retval; } -int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData) +int tp3780I_ReleaseResources(struct thinkpad_bd_data *pBDData) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; release_region(pSettings->usDspBaseIO & (~3), 16); @@ -226,9 +226,9 @@ int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData) -int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData) +int tp3780I_EnableDSP(struct thinkpad_bd_data *pBDData) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; bool bDSPPoweredUp = false, bInterruptAllocated = false; if (pBDData->bDSPEnabled) { @@ -351,9 +351,9 @@ exit_cleanup: } -int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData) +int tp3780I_DisableDSP(struct thinkpad_bd_data *pBDData) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; if (pBDData->bDSPEnabled) { dsp3780I_DisableDSP(&pBDData->rDspSettings); @@ -369,9 +369,9 @@ int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData) } -int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData) +int tp3780I_ResetDSP(struct thinkpad_bd_data *pBDData) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; if (dsp3780I_Reset(pSettings) == 0) { EnableSRAM(pBDData); @@ -381,9 +381,9 @@ int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData) } -int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData) +int tp3780I_StartDSP(struct thinkpad_bd_data *pBDData) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; if (dsp3780I_Run(pSettings) == 0) { // @BUG @TBD EnableSRAM(pBDData); @@ -395,7 +395,7 @@ int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData) } -int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities) +int tp3780I_QueryAbilities(struct thinkpad_bd_data *pBDData, struct mw_abilities *pAbilities) { memset(pAbilities, 0, sizeof(*pAbilities)); /* fill out standard constant fields */ @@ -424,11 +424,11 @@ int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities return 0; } -int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, +int tp3780I_ReadWriteDspDStore(struct thinkpad_bd_data *pBDData, unsigned int uOpcode, void __user *pvBuffer, unsigned int uCount, unsigned long ulDSPAddr) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; unsigned short usDspBaseIO = pSettings->usDspBaseIO; bool bRC = 0; @@ -452,11 +452,11 @@ int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, } -int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, +int tp3780I_ReadWriteDspIStore(struct thinkpad_bd_data *pBDData, unsigned int uOpcode, void __user *pvBuffer, unsigned int uCount, unsigned long ulDSPAddr) { - DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings; + struct dsp_3780i_config_settings *pSettings = &pBDData->rDspSettings; unsigned short usDspBaseIO = pSettings->usDspBaseIO; bool bRC = 0; diff --git a/drivers/char/mwave/tp3780i.h b/drivers/char/mwave/tp3780i.h index 8bd976d42fae..c0001a344741 100644 --- a/drivers/char/mwave/tp3780i.h +++ b/drivers/char/mwave/tp3780i.h @@ -75,27 +75,27 @@ #define TP_CFG_PllBypass 0 /* don't bypass */ #define TP_CFG_ChipletEnable 0xFFFF /* Enable all chiplets */ -typedef struct { +struct thinkpad_bd_data { int bDSPEnabled; int bShareDspIrq; int bShareUartIrq; - DSP_3780I_CONFIG_SETTINGS rDspSettings; -} THINKPAD_BD_DATA; + struct dsp_3780i_config_settings rDspSettings; +}; -int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData); -int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData); -int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData); -int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData); -int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData); -int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData); -int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData); -int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData); -int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities); -void tp3780I_Cleanup(THINKPAD_BD_DATA *pBDData); -int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, +int tp3780I_InitializeBoardData(struct thinkpad_bd_data *pBDData); +int tp3780I_CalcResources(struct thinkpad_bd_data *pBDData); +int tp3780I_ClaimResources(struct thinkpad_bd_data *pBDData); +int tp3780I_ReleaseResources(struct thinkpad_bd_data *pBDData); +int tp3780I_EnableDSP(struct thinkpad_bd_data *pBDData); +int tp3780I_DisableDSP(struct thinkpad_bd_data *pBDData); +int tp3780I_ResetDSP(struct thinkpad_bd_data *pBDData); +int tp3780I_StartDSP(struct thinkpad_bd_data *pBDData); +int tp3780I_QueryAbilities(struct thinkpad_bd_data *pBDData, struct mw_abilities *pAbilities); +void tp3780I_Cleanup(struct thinkpad_bd_data *pBDData); +int tp3780I_ReadWriteDspDStore(struct thinkpad_bd_data *pBDData, unsigned int uOpcode, void __user *pvBuffer, unsigned int uCount, unsigned long ulDSPAddr); -int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode, +int tp3780I_ReadWriteDspIStore(struct thinkpad_bd_data *pBDData, unsigned int uOpcode, void __user *pvBuffer, unsigned int uCount, unsigned long ulDSPAddr); From 8c5d9488b9c0e07dc648d9dfceeed6ad068daba2 Mon Sep 17 00:00:00 2001 From: Marco Crivellari Date: Wed, 12 Nov 2025 16:27:10 +0100 Subject: [PATCH 290/304] greybus: add WQ_PERCPU to alloc_workqueue users MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This continues the effort to refactor workqueue APIs, which began with the introduction of new workqueues and a new alloc_workqueue flag in: commit 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") commit 930c2ea566af ("workqueue: Add new WQ_PERCPU flag") This change adds a new WQ_PERCPU flag to explicitly request alloc_workqueue() to be per-cpu when WQ_UNBOUND has not been specified. With the introduction of the WQ_PERCPU flag (equivalent to !WQ_UNBOUND), any alloc_workqueue() caller that doesn’t explicitly specify WQ_UNBOUND must now use WQ_PERCPU. Once migration is complete, WQ_UNBOUND can be removed and unbound will become the implicit default. Suggested-by: Tejun Heo Signed-off-by: Marco Crivellari Reviewed-by: Johan Hovold Link: https://patch.msgid.link/20251112152710.207577-1-marco.crivellari@suse.com Signed-off-by: Greg Kroah-Hartman --- drivers/greybus/operation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/greybus/operation.c b/drivers/greybus/operation.c index 54ccc434a1f7..7e12ffb2dd60 100644 --- a/drivers/greybus/operation.c +++ b/drivers/greybus/operation.c @@ -1238,7 +1238,7 @@ int __init gb_operation_init(void) goto err_destroy_message_cache; gb_operation_completion_wq = alloc_workqueue("greybus_completion", - 0, 0); + WQ_PERCPU, 0); if (!gb_operation_completion_wq) goto err_destroy_operation_cache; From e6df0f649cff08da7a2feb6d963b39076ca129f9 Mon Sep 17 00:00:00 2001 From: Haotian Zhang Date: Fri, 21 Nov 2025 14:40:27 +0800 Subject: [PATCH 291/304] greybus: gb-beagleplay: Fix timeout handling in bootloader functions wait_for_completion_timeout() returns the remaining jiffies (at least 1) on success or 0 on timeout, but never negative error codes. The current code incorrectly checks for negative values, causing timeouts to be ignored and treated as success. Check for a zero return value to correctly identify and handle timeout events. Fixes: 0cf7befa3ea2 ("greybus: gb-beagleplay: Add firmware upload API") Signed-off-by: Haotian Zhang Link: https://patch.msgid.link/20251121064027.571-1-vulab@iscas.ac.cn Signed-off-by: Greg Kroah-Hartman --- drivers/greybus/gb-beagleplay.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/greybus/gb-beagleplay.c b/drivers/greybus/gb-beagleplay.c index 9610f878da1b..87186f891a6a 100644 --- a/drivers/greybus/gb-beagleplay.c +++ b/drivers/greybus/gb-beagleplay.c @@ -644,8 +644,8 @@ static int cc1352_bootloader_wait_for_ack(struct gb_beagleplay *bg) ret = wait_for_completion_timeout( &bg->fwl_ack_com, msecs_to_jiffies(CC1352_BOOTLOADER_TIMEOUT)); - if (ret < 0) - return dev_err_probe(&bg->sd->dev, ret, + if (!ret) + return dev_err_probe(&bg->sd->dev, -ETIMEDOUT, "Failed to acquire ack semaphore"); switch (READ_ONCE(bg->fwl_ack)) { @@ -683,8 +683,8 @@ static int cc1352_bootloader_get_status(struct gb_beagleplay *bg) ret = wait_for_completion_timeout( &bg->fwl_cmd_response_com, msecs_to_jiffies(CC1352_BOOTLOADER_TIMEOUT)); - if (ret < 0) - return dev_err_probe(&bg->sd->dev, ret, + if (!ret) + return dev_err_probe(&bg->sd->dev, -ETIMEDOUT, "Failed to acquire last status semaphore"); switch (READ_ONCE(bg->fwl_cmd_response)) { @@ -768,8 +768,8 @@ static int cc1352_bootloader_crc32(struct gb_beagleplay *bg, u32 *crc32) ret = wait_for_completion_timeout( &bg->fwl_cmd_response_com, msecs_to_jiffies(CC1352_BOOTLOADER_TIMEOUT)); - if (ret < 0) - return dev_err_probe(&bg->sd->dev, ret, + if (!ret) + return dev_err_probe(&bg->sd->dev, -ETIMEDOUT, "Failed to acquire last status semaphore"); *crc32 = READ_ONCE(bg->fwl_cmd_response); From f0fdaa4ad55b7c6e46a5ccb9102bc9a96cad360f Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 27 Oct 2025 21:04:09 -0700 Subject: [PATCH 292/304] virt: acrn: split acrn_mmio_dev_res out of acrn_mmiodev Add struct acrn_mmio_dev_res before struct acrn_mmio_dev. The former is used in the latter and breaking them up provides better kernel-doc documentation for the struct members. Suggested-by: Fei Li Signed-off-by: Randy Dunlap Acked-by: Fei Li Link: https://patch.msgid.link/20251028040409.868254-1-rdunlap@infradead.org Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/acrn.h | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/include/uapi/linux/acrn.h b/include/uapi/linux/acrn.h index 7b714c1902eb..79e7855a8c42 100644 --- a/include/uapi/linux/acrn.h +++ b/include/uapi/linux/acrn.h @@ -418,26 +418,32 @@ struct acrn_pcidev { }; /** - * struct acrn_mmiodev - Info for assigning or de-assigning a MMIO device - * @name: Name of the MMIO device. - * @res[].user_vm_pa: Physical address of User VM of the MMIO region - * for the MMIO device. - * @res[].service_vm_pa: Physical address of Service VM of the MMIO - * region for the MMIO device. - * @res[].size: Size of the MMIO region for the MMIO device. - * @res[].mem_type: Memory type of the MMIO region for the MMIO - * device. + * struct acrn_mmio_dev_res - MMIO device resource description + * @user_vm_pa: Physical address of User VM of the MMIO region + * for the MMIO device. + * @service_vm_pa: Physical address of Service VM of the MMIO + * region for the MMIO device. + * @size: Size of the MMIO region for the MMIO device. + * @mem_type: Memory type of the MMIO region for the MMIO + * device. + */ +struct acrn_mmio_dev_res { + __u64 user_vm_pa; + __u64 service_vm_pa; + __u64 size; + __u64 mem_type; +}; + +/** + * struct acrn_mmiodev - Info for assigning or de-assigning an MMIO device + * @name: Name of the MMIO device. + * @res: Array of MMIO device descriptions * * This structure will be passed to hypervisor directly. */ struct acrn_mmiodev { __u8 name[8]; - struct { - __u64 user_vm_pa; - __u64 service_vm_pa; - __u64 size; - __u64 mem_type; - } res[ACRN_MMIODEV_RES_NUM]; + struct acrn_mmio_dev_res res[ACRN_MMIODEV_RES_NUM]; }; /** From 4863cb2b0f505c77f7b4632246d4de4859b86ed2 Mon Sep 17 00:00:00 2001 From: "Thomas Richard (TI.com)" Date: Mon, 13 Oct 2025 15:04:44 +0200 Subject: [PATCH 293/304] mux: mmio: Add suspend and resume support The status of each mux is read during suspend and stored in the private memory of the mux_chip. Then the state is restored during the resume. Reviewed-by: Andrew Davis Signed-off-by: Thomas Richard (TI.com) Link: https://patch.msgid.link/20251013-mux-mmio-resume-support-v5-1-de9467ceb2b2@bootlin.com Signed-off-by: Greg Kroah-Hartman --- drivers/mux/mmio.c | 82 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 73 insertions(+), 9 deletions(-) diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c index 9993ce38a818..e4ddb1e61923 100644 --- a/drivers/mux/mmio.c +++ b/drivers/mux/mmio.c @@ -15,11 +15,25 @@ #include #include +struct mux_mmio { + struct regmap_field **fields; + unsigned int *hardware_states; +}; + +static int mux_mmio_get(struct mux_control *mux, int *state) +{ + struct mux_mmio *mux_mmio = mux_chip_priv(mux->chip); + unsigned int index = mux_control_get_index(mux); + + return regmap_field_read(mux_mmio->fields[index], state); +} + static int mux_mmio_set(struct mux_control *mux, int state) { - struct regmap_field **fields = mux_chip_priv(mux->chip); + struct mux_mmio *mux_mmio = mux_chip_priv(mux->chip); + unsigned int index = mux_control_get_index(mux); - return regmap_field_write(fields[mux_control_get_index(mux)], state); + return regmap_field_write(mux_mmio->fields[index], state); } static const struct mux_control_ops mux_mmio_ops = { @@ -43,8 +57,8 @@ static int mux_mmio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - struct regmap_field **fields; struct mux_chip *mux_chip; + struct mux_mmio *mux_mmio; struct regmap *regmap; void __iomem *base; int num_fields; @@ -80,12 +94,20 @@ static int mux_mmio_probe(struct platform_device *pdev) } num_fields = ret / 2; - mux_chip = devm_mux_chip_alloc(dev, num_fields, num_fields * - sizeof(*fields)); + mux_chip = devm_mux_chip_alloc(dev, num_fields, sizeof(struct mux_mmio)); if (IS_ERR(mux_chip)) return PTR_ERR(mux_chip); - fields = mux_chip_priv(mux_chip); + mux_mmio = mux_chip_priv(mux_chip); + + mux_mmio->fields = devm_kmalloc(dev, num_fields * sizeof(*mux_mmio->fields), GFP_KERNEL); + if (IS_ERR(mux_mmio->fields)) + return PTR_ERR(mux_mmio->fields); + + mux_mmio->hardware_states = devm_kmalloc(dev, num_fields * + sizeof(*mux_mmio->hardware_states), GFP_KERNEL); + if (IS_ERR(mux_mmio->hardware_states)) + return PTR_ERR(mux_mmio->hardware_states); for (i = 0; i < num_fields; i++) { struct mux_control *mux = &mux_chip->mux[i]; @@ -115,9 +137,9 @@ static int mux_mmio_probe(struct platform_device *pdev) return -EINVAL; } - fields[i] = devm_regmap_field_alloc(dev, regmap, field); - if (IS_ERR(fields[i])) { - ret = PTR_ERR(fields[i]); + mux_mmio->fields[i] = devm_regmap_field_alloc(dev, regmap, field); + if (IS_ERR(mux_mmio->fields[i])) { + ret = PTR_ERR(mux_mmio->fields[i]); dev_err(dev, "bitfield %d: failed to allocate: %d\n", i, ret); return ret; @@ -141,13 +163,55 @@ static int mux_mmio_probe(struct platform_device *pdev) mux_chip->ops = &mux_mmio_ops; + dev_set_drvdata(dev, mux_chip); + return devm_mux_chip_register(dev, mux_chip); } +static int mux_mmio_suspend_noirq(struct device *dev) +{ + struct mux_chip *mux_chip = dev_get_drvdata(dev); + struct mux_mmio *mux_mmio = mux_chip_priv(mux_chip); + unsigned int state; + int ret, i; + + for (i = 0; i < mux_chip->controllers; i++) { + ret = mux_mmio_get(&mux_chip->mux[i], &state); + if (ret) { + dev_err(dev, "control %u: error saving mux: %d\n", i, ret); + return ret; + } + + mux_mmio->hardware_states[i] = state; + } + + return 0; +} + +static int mux_mmio_resume_noirq(struct device *dev) +{ + struct mux_chip *mux_chip = dev_get_drvdata(dev); + struct mux_mmio *mux_mmio = mux_chip_priv(mux_chip); + int ret, i; + + for (i = 0; i < mux_chip->controllers; i++) { + ret = mux_mmio_set(&mux_chip->mux[i], mux_mmio->hardware_states[i]); + if (ret) { + dev_err(dev, "control %u: error restoring mux: %d\n", i, ret); + return ret; + } + } + + return 0; +} + +static DEFINE_NOIRQ_DEV_PM_OPS(mux_mmio_pm_ops, mux_mmio_suspend_noirq, mux_mmio_resume_noirq); + static struct platform_driver mux_mmio_driver = { .driver = { .name = "mmio-mux", .of_match_table = mux_mmio_dt_ids, + .pm = pm_sleep_ptr(&mux_mmio_pm_ops), }, .probe = mux_mmio_probe, }; From 05d36a5931d92310819e64fdee0cc1a35e14944c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 29 Oct 2025 16:13:56 +0300 Subject: [PATCH 294/304] misc: cb710: Fix a NULL vs IS_ERR() check in probe() The pcim_iomap_region() function never returns NULL, it returns error pointers. Update the checking to match. Fixes: b91c13534a63 ("misc: cb710: Replace deprecated PCI functions") Signed-off-by: Dan Carpenter Acked-by: Arnd Bergmann Link: https://patch.msgid.link/aQITFDPyuzjNN4GN@stanley.mountain Signed-off-by: Greg Kroah-Hartman --- drivers/misc/cb710/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/cb710/core.c b/drivers/misc/cb710/core.c index a1e6ba62c298..2dd212f04fed 100644 --- a/drivers/misc/cb710/core.c +++ b/drivers/misc/cb710/core.c @@ -226,8 +226,8 @@ static int cb710_probe(struct pci_dev *pdev, spin_lock_init(&chip->irq_lock); chip->pdev = pdev; chip->iobase = pcim_iomap_region(pdev, 0, KBUILD_MODNAME); - if (!chip->iobase) - return -ENOMEM; + if (IS_ERR(chip->iobase)) + return PTR_ERR(chip->iobase); pci_set_drvdata(pdev, chip); From ef48f0f19ec9d77888a23ab62fd2c9e409d81a3e Mon Sep 17 00:00:00 2001 From: Vivek BalachandharTN Date: Thu, 30 Oct 2025 12:00:22 +0000 Subject: [PATCH 295/304] misc: bh1770glc: use pm_runtime_resume_and_get() in power_state_store pm_runtime_get_sync() may increment the runtime PM usage count even if the resume fails, which requires an explicit pm_runtime_put_noidle() to balance it. This driver ignored the return value, risking a usage-count leak on resume failure. Replace it with pm_runtime_resume_and_get(), which returns 0 on success and a negative errno on failure, and only increments the usage count on success. This simplifies the error path and avoids possible leaks. Also check for errors explicitly with `if (ret < 0)`. Signed-off-by: Vivek BalachandharTN Link: https://patch.msgid.link/20251030120022.239951-1-vivek.balachandhar@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/bh1770glc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/misc/bh1770glc.c b/drivers/misc/bh1770glc.c index 0c052b05ab6a..45f8fc69a711 100644 --- a/drivers/misc/bh1770glc.c +++ b/drivers/misc/bh1770glc.c @@ -640,7 +640,9 @@ static ssize_t bh1770_power_state_store(struct device *dev, mutex_lock(&chip->mutex); if (value) { - pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + goto leave; ret = bh1770_lux_rate(chip, chip->lux_rate_index); if (ret < 0) { From 85e83789582ff478888b9c9f904a9203660544af Mon Sep 17 00:00:00 2001 From: Marco Crivellari Date: Fri, 7 Nov 2025 17:37:55 +0100 Subject: [PATCH 296/304] char: xillybus: add WQ_UNBOUND to alloc_workqueue users MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently if a user enqueues a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistency cannot be addressed without refactoring the API. alloc_workqueue() treats all queues as per-CPU by default, while unbound workqueues must opt-in via WQ_UNBOUND. This default is suboptimal: most workloads benefit from unbound queues, allowing the scheduler to place worker threads where they’re needed and reducing noise when CPUs are isolated. This continues the effort to refactor workqueue APIs, which began with the introduction of new workqueues and a new alloc_workqueue flag in: commit 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") commit 930c2ea566af ("workqueue: Add new WQ_PERCPU flag") This change adds the WQ_UNBOUND flag to explicitly request alloc_workqueue() to be unbound, because this specific workload has no benefit being per-cpu. With the introduction of the WQ_PERCPU flag (equivalent to !WQ_UNBOUND), any alloc_workqueue() caller that doesn’t explicitly specify WQ_UNBOUND must now use WQ_PERCPU. Once migration is complete, WQ_UNBOUND can be removed and unbound will become the implicit default. Suggested-by: Tejun Heo Signed-off-by: Marco Crivellari Acked-by: Eli Billauer Link: https://patch.msgid.link/20251107163755.356187-1-marco.crivellari@suse.com Signed-off-by: Greg Kroah-Hartman --- drivers/char/xillybus/xillybus_core.c | 2 +- drivers/char/xillybus/xillyusb.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/char/xillybus/xillybus_core.c b/drivers/char/xillybus/xillybus_core.c index efb1ae834265..fc4e69b5cb6a 100644 --- a/drivers/char/xillybus/xillybus_core.c +++ b/drivers/char/xillybus/xillybus_core.c @@ -1973,7 +1973,7 @@ EXPORT_SYMBOL(xillybus_endpoint_remove); static int __init xillybus_init(void) { - xillybus_wq = alloc_workqueue(xillyname, 0, 0); + xillybus_wq = alloc_workqueue(xillyname, WQ_UNBOUND, 0); if (!xillybus_wq) return -ENOMEM; diff --git a/drivers/char/xillybus/xillyusb.c b/drivers/char/xillybus/xillyusb.c index 45771b1a3716..386531474213 100644 --- a/drivers/char/xillybus/xillyusb.c +++ b/drivers/char/xillybus/xillyusb.c @@ -2163,7 +2163,7 @@ static int xillyusb_probe(struct usb_interface *interface, spin_lock_init(&xdev->error_lock); xdev->in_counter = 0; xdev->in_bytes_left = 0; - xdev->workq = alloc_workqueue(xillyname, WQ_HIGHPRI, 0); + xdev->workq = alloc_workqueue(xillyname, WQ_HIGHPRI | WQ_UNBOUND, 0); if (!xdev->workq) { dev_err(&interface->dev, "Failed to allocate work queue\n"); @@ -2275,7 +2275,7 @@ static int __init xillyusb_init(void) { int rc = 0; - wakeup_wq = alloc_workqueue(xillyname, 0, 0); + wakeup_wq = alloc_workqueue(xillyname, WQ_UNBOUND, 0); if (!wakeup_wq) return -ENOMEM; From 43cd4b634ef90c4e2ff75eaeb361786fa04c8874 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 8 Nov 2025 08:14:04 +0100 Subject: [PATCH 297/304] misc: rp1: Fix an error handling path in rp1_probe() When DT is used to get the reference of 'rp1_node', it should be released when not needed anymore, otherwise it is leaking. In such a case, add the missing of_node_put() call at the end of the probe, as already done in the error handling path. Fixes: 49d63971f963 ("misc: rp1: RaspberryPi RP1 misc driver") Signed-off-by: Christophe JAILLET Reviewed-by: Andrea della Porta Link: https://patch.msgid.link/9bc1206de787fa86384f3e5ba0a8027947bc00ff.1762585959.git.christophe.jaillet@wanadoo.fr Signed-off-by: Greg Kroah-Hartman --- drivers/misc/rp1/rp1_pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/misc/rp1/rp1_pci.c b/drivers/misc/rp1/rp1_pci.c index 803832006ec8..a342bcc6164b 100644 --- a/drivers/misc/rp1/rp1_pci.c +++ b/drivers/misc/rp1/rp1_pci.c @@ -289,6 +289,9 @@ static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_unload_overlay; } + if (skip_ovl) + of_node_put(rp1_node); + return 0; err_unload_overlay: From 6d5925b667e4ed9e77c8278cc215191d29454a3f Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Wed, 12 Nov 2025 17:17:23 +0800 Subject: [PATCH 298/304] intel_th: Fix error handling in intel_th_output_open intel_th_output_open() calls bus_find_device_by_devt() which internally increments the device reference count via get_device(), but this reference is not properly released in several error paths. When device driver is unavailable, file operations cannot be obtained, or the driver's open method fails, the function returns without calling put_device(), leading to a permanent device reference count leak. This prevents the device from being properly released and could cause resource exhaustion over time. Found by code review. Cc: stable Fixes: 39f4034693b7 ("intel_th: Add driver infrastructure for Intel(R) Trace Hub devices") Signed-off-by: Ma Ke Link: https://patch.msgid.link/20251112091723.35963-1-make24@iscas.ac.cn Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/intel_th/core.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/intel_th/core.c b/drivers/hwtracing/intel_th/core.c index ba7c8b184cbc..591b7c12aae5 100644 --- a/drivers/hwtracing/intel_th/core.c +++ b/drivers/hwtracing/intel_th/core.c @@ -810,13 +810,17 @@ static int intel_th_output_open(struct inode *inode, struct file *file) int err; dev = bus_find_device_by_devt(&intel_th_bus, inode->i_rdev); - if (!dev || !dev->driver) - return -ENODEV; + if (!dev || !dev->driver) { + err = -ENODEV; + goto out_no_device; + } thdrv = to_intel_th_driver(dev->driver); fops = fops_get(thdrv->fops); - if (!fops) - return -ENODEV; + if (!fops) { + err = -ENODEV; + goto out_put_device; + } replace_fops(file, fops); @@ -824,10 +828,16 @@ static int intel_th_output_open(struct inode *inode, struct file *file) if (file->f_op->open) { err = file->f_op->open(inode, file); - return err; + if (err) + goto out_put_device; } return 0; + +out_put_device: + put_device(dev); +out_no_device: + return err; } static const struct file_operations intel_th_output_fops = { From 4d4e746aa9f0f07261dcb41e4f51edb98723dcaa Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 14 Nov 2025 11:05:05 +0000 Subject: [PATCH 299/304] dt-bindings: slimbus: fix warning from example Fix below warnings generated dt_bindings_check for examples in the bindings. Documentation/devicetree/bindings/slimbus/slimbus.example.dtb: slim@28080000 (qcom,slim-ngd-v1.5.0): 'audio-codec@1,0' does not match any of the regexes: '^pinctrl-[0-9]+$', '^slim@[0-9a-f]+$' from schema $id: http://devicetree.org/schemas/slimbus/qcom,slim-ngd.yaml# Documentation/devicetree/bindings/slimbus/slimbus.example.dtb: slim@28080000 (qcom,slim-ngd-v1.5.0): #address-cells: 1 was expected from schema $id: http://devicetree.org/schemas/slimbus/qcom,slim-ngd.yaml# Documentation/devicetree/bindings/slimbus/slimbus.example.dtb: slim@28080000 (qcom,slim-ngd-v1.5.0): 'dmas' is a required property from schema $id: http://devicetree.org/schemas/slimbus/qcom,slim-ngd.yaml# Documentation/devicetree/bindings/slimbus/slimbus.example.dtb: slim@28080000 (qcom,slim-ngd-v1.5.0): 'dma-names' is a required property from schema $id: http://devicetree.org/schemas/slimbus/qcom,slim-ngd.yaml# Fixes: 7cbba32a2d62 ("slimbus: qcom: remove unused qcom controller driver") Cc: stable Reported-by: Rob Herring Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20251114110505.143105-1-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/slimbus/slimbus.yaml | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/slimbus/slimbus.yaml b/Documentation/devicetree/bindings/slimbus/slimbus.yaml index 89017d9cda10..5a941610ce4e 100644 --- a/Documentation/devicetree/bindings/slimbus/slimbus.yaml +++ b/Documentation/devicetree/bindings/slimbus/slimbus.yaml @@ -75,16 +75,22 @@ examples: #size-cells = <1>; ranges; - slim@28080000 { + controller@28080000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2c000>; interrupts = ; - #address-cells = <2>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; #size-cells = <0>; - - audio-codec@1,0 { + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + codec@1,0 { compatible = "slim217,1a0"; reg = <1 0>; + }; }; + }; }; - }; From 3397c3cd859a2c51962ad032dcf97961d42f9db2 Mon Sep 17 00:00:00 2001 From: Yaxing Guo Date: Fri, 26 Sep 2025 17:58:28 +0800 Subject: [PATCH 300/304] uio: Add SVA support for PCI devices via uio_pci_generic_sva.c This patch introduces a new UIO driver, uio_pci_generic_sva, which extends the functionality of uio_pci_generic by adding support for Shared Virtual Addressing (SVA) when IOMMU is enabled in the system. The key enhancement allows PCI devices to directly use user-space virtual addresses for DMA operations, eliminating the need for bounce buffers or explicit IOVA mapping. This is achieved by leveraging the kernel's IOMMU-SVA subsystem, including process address space attachment, page fault handling, and shared context management between CPU and device. With this driver, userspace applications can perform zero-copy DMA using native pointers: void *addr = malloc(N); set_dma_addr((uint64_t)addr); // Passing user VA directly start_dma(); The device can now access 'addr' through the IOMMU's PASID-based translation, provided that the underlying IOMMU hardware (e.g., Intel VT-d 3.1+, AMD-Vi, ARM SMMU, RISCV IOMMU) and platform support SVA. Dependencies: - CONFIG_IOMMU_SVA must be enabled. - The platform must support PRI (Page Request Interface) and PASID. - Device drivers/userspace must handle page faults if demand-paging is used. The implementation reuses core logic from uio_pci_generic.c while adding PASID setting, and integration with the IOMMU SVA APIs. Also, add a read-only sysfs attribute 'pasid' to expose the Process Address Space ID assigned by IOMMU driver when binding an SVA-enabled device. For details, refer to the ABI documentation for uio_pci_sva driver sysfs attribute (Documentation/ABI/testing/sysfs-driver-uio_pci_sva-pasid). Signed-off-by: Yaxing Guo Link: https://patch.msgid.link/20250926095828.506-1-guoyaxing@bosc.ac.cn Signed-off-by: Greg Kroah-Hartman --- .../testing/sysfs-driver-uio_pci_sva-pasid | 29 +++ drivers/uio/Kconfig | 12 ++ drivers/uio/Makefile | 1 + drivers/uio/uio_pci_generic_sva.c | 192 ++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-uio_pci_sva-pasid create mode 100644 drivers/uio/uio_pci_generic_sva.c diff --git a/Documentation/ABI/testing/sysfs-driver-uio_pci_sva-pasid b/Documentation/ABI/testing/sysfs-driver-uio_pci_sva-pasid new file mode 100644 index 000000000000..6892fe46cea8 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-uio_pci_sva-pasid @@ -0,0 +1,29 @@ +What: /sys/bus/pci/drivers/uio_pci_sva//pasid +Date: September 2025 +Contact: Yaxing Guo +Description: + Process Address Space ID (PASID) assigned by IOMMU driver to + the device for use with Shared Virtual Addressing (SVA). + + This read-only attribute exposes the PASID (A 20-bit identifier + used in PCIe Address Translation Services and iommu table walks) + allocated by the IOMMU driver during sva device binding. + + User-space UIO applications must read this attribute to obtain + the PASID and program it into the device's configuration registers. + This enables the device to perform DMA using user-space virtual + address, with address translation handled by IOMMU. + + UIO User-space applications must: + - Opening device and Mapping the device's register space via /dev/uioX + (This triggers the IOMMU driver to allocate the PASID) + - Reading the PASID from sysfs + - Writing the PASID to a device-specific register (with example offset) + The code may be like: + + map = mmap(..., "/dev/uio0", ...); + + f = fopen("/sys/.../pasid", "r"); + fscanf(f, "%d", &pasid); + + map[REG_PASID_OFFSET] = pasid; diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig index 6f86a61231e6..9242e77385c6 100644 --- a/drivers/uio/Kconfig +++ b/drivers/uio/Kconfig @@ -164,4 +164,16 @@ config UIO_DFL opae-sdk/tools/libopaeuio/ If you compile this as a module, it will be called uio_dfl. + +config UIO_PCI_GENERIC_SVA + tristate "Generic driver for PCI Express that supports sva" + depends on PCI && IOMMU_SVA + help + Userspace I/O driver for PCI devices that support Shared Virtual + Addressing (SVA), enabling direct use of user-space virtual + addresses in device DMA operations via IOMMU hardware. + + This driver binds to PCI devices and exposes them to userspace + via the UIO framework. + endif diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile index 1c5f3b5a95cf..5352e21e918d 100644 --- a/drivers/uio/Makefile +++ b/drivers/uio/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_UIO_MF624) += uio_mf624.o obj-$(CONFIG_UIO_FSL_ELBC_GPCM) += uio_fsl_elbc_gpcm.o obj-$(CONFIG_UIO_HV_GENERIC) += uio_hv_generic.o obj-$(CONFIG_UIO_DFL) += uio_dfl.o +obj-$(CONFIG_UIO_PCI_GENERIC_SVA) += uio_pci_generic_sva.o diff --git a/drivers/uio/uio_pci_generic_sva.c b/drivers/uio/uio_pci_generic_sva.c new file mode 100644 index 000000000000..97e9ab9a081a --- /dev/null +++ b/drivers/uio/uio_pci_generic_sva.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * UIO PCI Express sva driver + * + * Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) + */ + +#include +#include +#include +#include +#include + +struct uio_pci_sva_dev { + struct pci_dev *pdev; + struct uio_info info; + struct iommu_sva *sva_handle; + int pasid; +}; + +static irqreturn_t irq_handler(int irq, struct uio_info *dev_info) +{ + return IRQ_HANDLED; +} + +static int uio_pci_sva_open(struct uio_info *info, struct inode *inode) +{ + struct iommu_sva *handle; + struct uio_pci_sva_dev *udev = info->priv; + struct iommu_domain *domain; + + if (!udev && !udev->pdev) + return -ENODEV; + + domain = iommu_get_domain_for_dev(&udev->pdev->dev); + if (domain) + iommu_detach_device(domain, &udev->pdev->dev); + + handle = iommu_sva_bind_device(&udev->pdev->dev, current->mm); + if (IS_ERR(handle)) + return -EINVAL; + + udev->pasid = iommu_sva_get_pasid(handle); + + udev->sva_handle = handle; + + return 0; +} + +static int uio_pci_sva_release(struct uio_info *info, struct inode *inode) +{ + struct uio_pci_sva_dev *udev = info->priv; + + if (!udev && !udev->pdev) + return -ENODEV; + + iommu_sva_unbind_device(udev->sva_handle); + + return 0; +} + +static int probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct uio_pci_sva_dev *udev; + int ret, i, irq = 0; + + ret = pci_enable_device(pdev); + if (ret) { + dev_err(&pdev->dev, "pci_enable_device failed: %d\n", ret); + return ret; + } + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret) + goto out_disable; + + pci_set_master(pdev); + + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX | PCI_IRQ_MSI); + if (ret > 0) { + irq = pci_irq_vector(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "Failed to get MSI vector\n"); + ret = irq; + goto out_disable; + } + } else + dev_warn(&pdev->dev, + "No IRQ vectors available (%d), using polling\n", ret); + + udev = devm_kzalloc(&pdev->dev, sizeof(struct uio_pci_sva_dev), + GFP_KERNEL); + if (!udev) { + ret = -ENOMEM; + goto out_disable; + } + + udev->pdev = pdev; + udev->info.name = "uio_pci_sva"; + udev->info.version = "0.0.1"; + udev->info.open = uio_pci_sva_open; + udev->info.release = uio_pci_sva_release; + udev->info.irq = irq; + udev->info.handler = irq_handler; + udev->info.priv = udev; + + for (i = 0; i < MAX_UIO_MAPS; i++) { + struct resource *r = &pdev->resource[i]; + struct uio_mem *uiomem = &udev->info.mem[i]; + + if (r->flags != (IORESOURCE_SIZEALIGN | IORESOURCE_MEM)) + continue; + + if (uiomem >= &udev->info.mem[MAX_UIO_MAPS]) { + dev_warn(&pdev->dev, "Do not support more than %d iomem\n", + MAX_UIO_MAPS); + break; + } + + uiomem->memtype = UIO_MEM_PHYS; + uiomem->addr = r->start & PAGE_MASK; + uiomem->offs = r->start & ~PAGE_MASK; + uiomem->size = + (uiomem->offs + resource_size(r) + PAGE_SIZE - 1) & + PAGE_MASK; + uiomem->name = r->name; + } + + ret = devm_uio_register_device(&pdev->dev, &udev->info); + if (ret) { + dev_err(&pdev->dev, "Failed to register uio device\n"); + goto out_free; + } + + pci_set_drvdata(pdev, udev); + + return 0; + +out_free: + kfree(udev); +out_disable: + pci_disable_device(pdev); + + return ret; +} + +static void remove(struct pci_dev *pdev) +{ + struct uio_pci_sva_dev *udev = pci_get_drvdata(pdev); + + pci_release_regions(pdev); + pci_disable_device(pdev); + kfree(udev); +} + +static ssize_t pasid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct uio_pci_sva_dev *udev = pci_get_drvdata(pdev); + + return sysfs_emit(buf, "%d\n", udev->pasid); +} +static DEVICE_ATTR_RO(pasid); + +static struct attribute *uio_pci_sva_attrs[] = { + &dev_attr_pasid.attr, + NULL +}; + +static const struct attribute_group uio_pci_sva_attr_group = { + .attrs = uio_pci_sva_attrs, +}; + +static const struct attribute_group *uio_pci_sva_attr_groups[] = { + &uio_pci_sva_attr_group, + NULL +}; + +static struct pci_driver uio_pci_generic_sva_driver = { + .name = "uio_pci_sva", + .dev_groups = uio_pci_sva_attr_groups, + .id_table = NULL, + .probe = probe, + .remove = remove, +}; + +module_pci_driver(uio_pci_generic_sva_driver); +MODULE_VERSION("0.0.01"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Yaxing Guo "); +MODULE_DESCRIPTION("Generic UIO sva driver for PCI"); From 75d19e368640f69a3c8532001ec99685d0e2ce89 Mon Sep 17 00:00:00 2001 From: Clint George Date: Tue, 11 Nov 2025 20:43:38 +0530 Subject: [PATCH 301/304] hangcheck-timer: replace printk(KERN_CRIT) with pr_crit Replace printk(KERN_CRIT ...) with pr_crit(...) and printk() with pr_debug(). The change aims to make logging more consistent and readable. Signed-off-by: Clint George Link: https://patch.msgid.link/20251111151340.9162-2-clintbgeorge@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/char/hangcheck-timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/char/hangcheck-timer.c b/drivers/char/hangcheck-timer.c index 497fc167cb8c..21ef8a6a0463 100644 --- a/drivers/char/hangcheck-timer.c +++ b/drivers/char/hangcheck-timer.c @@ -126,23 +126,23 @@ static void hangcheck_fire(struct timer_list *unused) if (tsc_diff > hangcheck_tsc_margin) { if (hangcheck_dump_tasks) { - printk(KERN_CRIT "Hangcheck: Task state:\n"); + pr_crit("Hangcheck: Task state:\n"); #ifdef CONFIG_MAGIC_SYSRQ handle_sysrq('t'); #endif /* CONFIG_MAGIC_SYSRQ */ } if (hangcheck_reboot) { - printk(KERN_CRIT "Hangcheck: hangcheck is restarting the machine.\n"); + pr_crit("Hangcheck: hangcheck is restarting the machine.\n"); emergency_restart(); } else { - printk(KERN_CRIT "Hangcheck: hangcheck value past margin!\n"); + pr_crit("Hangcheck: hangcheck value past margin!\n"); } } #if 0 /* * Enable to investigate delays in detail */ - printk("Hangcheck: called %Ld ns since last time (%Ld ns overshoot)\n", + pr_debug("Hangcheck: called %Ld ns since last time (%Ld ns overshoot)\n", tsc_diff, tsc_diff - hangcheck_tick*TIMER_FREQ); #endif mod_timer(&hangcheck_ticktock, jiffies + (hangcheck_tick*HZ)); @@ -152,7 +152,7 @@ static void hangcheck_fire(struct timer_list *unused) static int __init hangcheck_init(void) { - printk("Hangcheck: starting hangcheck timer %s (tick is %d seconds, margin is %d seconds).\n", + pr_debug("Hangcheck: starting hangcheck timer %s (tick is %d seconds, margin is %d seconds).\n", VERSION_STR, hangcheck_tick, hangcheck_margin); hangcheck_tsc_margin = (unsigned long long)hangcheck_margin + hangcheck_tick; @@ -168,7 +168,7 @@ static int __init hangcheck_init(void) static void __exit hangcheck_exit(void) { timer_delete_sync(&hangcheck_ticktock); - printk("Hangcheck: Stopped hangcheck timer.\n"); + pr_debug("Hangcheck: Stopped hangcheck timer.\n"); } module_init(hangcheck_init); From e03a2f7df72e8b7b56cdd0e19c295bf7633ed4ea Mon Sep 17 00:00:00 2001 From: Clint George Date: Tue, 11 Nov 2025 20:43:39 +0530 Subject: [PATCH 302/304] hangcheck-timer: Replace %Ld with %lld Replace non-standard %Ld with %lld to ensure compliance with the kernel coding style and potential formatting issues. Signed-off-by: Clint George Link: https://patch.msgid.link/20251111151340.9162-3-clintbgeorge@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/char/hangcheck-timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/char/hangcheck-timer.c b/drivers/char/hangcheck-timer.c index 21ef8a6a0463..ff141fdb437a 100644 --- a/drivers/char/hangcheck-timer.c +++ b/drivers/char/hangcheck-timer.c @@ -142,7 +142,7 @@ static void hangcheck_fire(struct timer_list *unused) /* * Enable to investigate delays in detail */ - pr_debug("Hangcheck: called %Ld ns since last time (%Ld ns overshoot)\n", + pr_debug("Hangcheck: called %lld ns since last time (%lld ns overshoot)\n", tsc_diff, tsc_diff - hangcheck_tick*TIMER_FREQ); #endif mod_timer(&hangcheck_ticktock, jiffies + (hangcheck_tick*HZ)); From cbe1d77ed84ae9ab3355d61aca0c30d561a61d5a Mon Sep 17 00:00:00 2001 From: Clint George Date: Tue, 11 Nov 2025 20:43:40 +0530 Subject: [PATCH 303/304] hangcheck-timer: fix coding style spacing Fix minor styling issues for proper compliance to the kernel coding style. Signed-off-by: Clint George Link: https://patch.msgid.link/20251111151340.9162-4-clintbgeorge@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/char/hangcheck-timer.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/char/hangcheck-timer.c b/drivers/char/hangcheck-timer.c index ff141fdb437a..231cbf7b300f 100644 --- a/drivers/char/hangcheck-timer.c +++ b/drivers/char/hangcheck-timer.c @@ -69,7 +69,8 @@ MODULE_VERSION(VERSION_STR); static int __init hangcheck_parse_tick(char *str) { int par; - if (get_option(&str,&par)) + + if (get_option(&str, &par)) hangcheck_tick = par; return 1; } @@ -77,7 +78,8 @@ static int __init hangcheck_parse_tick(char *str) static int __init hangcheck_parse_margin(char *str) { int par; - if (get_option(&str,&par)) + + if (get_option(&str, &par)) hangcheck_margin = par; return 1; } @@ -85,7 +87,8 @@ static int __init hangcheck_parse_margin(char *str) static int __init hangcheck_parse_reboot(char *str) { int par; - if (get_option(&str,&par)) + + if (get_option(&str, &par)) hangcheck_reboot = par; return 1; } @@ -93,7 +96,8 @@ static int __init hangcheck_parse_reboot(char *str) static int __init hangcheck_parse_dump_tasks(char *str) { int par; - if (get_option(&str,&par)) + + if (get_option(&str, &par)) hangcheck_dump_tasks = par; return 1; } @@ -168,7 +172,7 @@ static int __init hangcheck_init(void) static void __exit hangcheck_exit(void) { timer_delete_sync(&hangcheck_ticktock); - pr_debug("Hangcheck: Stopped hangcheck timer.\n"); + pr_debug("Hangcheck: Stopped hangcheck timer.\n"); } module_init(hangcheck_init); From 82d12088c297fa1cef670e1718b3d24f414c23f7 Mon Sep 17 00:00:00 2001 From: Tianchu Chen Date: Fri, 28 Nov 2025 15:53:23 +0800 Subject: [PATCH 304/304] char: applicom: fix NULL pointer dereference in ac_ioctl Discovered by Atuin - Automated Vulnerability Discovery Engine. In ac_ioctl, the validation of IndexCard and the check for a valid RamIO pointer are skipped when cmd is 6. However, the function unconditionally executes readb(apbs[IndexCard].RamIO + VERS) at the end. If cmd is 6, IndexCard may reference a board that does not exist (where RamIO is NULL), leading to a NULL pointer dereference. Fix this by skipping the readb access when cmd is 6, as this command is a global information query and does not target a specific board context. Signed-off-by: Tianchu Chen Acked-by: Arnd Bergmann Cc: stable Link: https://patch.msgid.link/20251128155323.a786fde92ebb926cbe96fcb1@linux.dev Signed-off-by: Greg Kroah-Hartman --- drivers/char/applicom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/char/applicom.c b/drivers/char/applicom.c index 9fed9706d9cd..c138c468f3a4 100644 --- a/drivers/char/applicom.c +++ b/drivers/char/applicom.c @@ -835,7 +835,10 @@ static long ac_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ret = -ENOTTY; break; } - Dummy = readb(apbs[IndexCard].RamIO + VERS); + + if (cmd != 6) + Dummy = readb(apbs[IndexCard].RamIO + VERS); + kfree(adgl); mutex_unlock(&ac_mutex); return ret;