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drm/xe: Convert xe_mmio_wait32 to us so we can stop using wait_for_us.

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Another clean-up towards killing the usage of i915_utils.h

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
This commit is contained in:
Rodrigo Vivi
2023-01-12 17:25:11 -05:00
parent eeb8019d8c
commit 81593af6c8
7 changed files with 16 additions and 19 deletions
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6
drivers/gpu/drm/xe/xe_force_wake.c
View File

@@ -124,7 +124,8 @@ static int domain_wake_wait(struct xe_gt *gt,
struct xe_force_wake_domain *domain)
{
return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,
XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
NULL);
}
static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
@@ -136,7 +137,8 @@ static int domain_sleep_wait(struct xe_gt *gt,
struct xe_force_wake_domain *domain)
{
return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,
XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
NULL);
}
#define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \

3
drivers/gpu/drm/xe/xe_gt.c
View File

@@ -599,7 +599,8 @@ int do_gt_reset(struct xe_gt *gt)
int err;
xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);
err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5, NULL);
err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000,
NULL);
if (err)
drm_err(&xe->drm,
"GT reset failed to clear GEN11_GRDOM_FULL\n");

9
drivers/gpu/drm/xe/xe_gt_mcr.c
View File

@@ -11,13 +11,6 @@
#include "gt/intel_gt_regs.h"
#include <linux/delay.h>
/*
* FIXME: This header has been deemed evil and we need to kill it. Temporar
* including so we can use 'wait_for'.
*/
#include "i915_utils.h"
/**
* DOC: GT Multicast/Replicated (MCR) Register Support
*
@@ -383,7 +376,7 @@ static void mcr_lock(struct xe_gt *gt)
* shares the same steering control register.
*/
if (GRAPHICS_VERx100(xe) >= 1270)
ret = wait_for_us(xe_mmio_read32(gt, STEER_SEMAPHORE) == 0x1, 10);
ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL);
drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
}

9
drivers/gpu/drm/xe/xe_guc.c
View File

@@ -324,7 +324,8 @@ int xe_guc_reset(struct xe_guc *guc)
xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);
ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5, &gdrst);
ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000,
&gdrst);
if (ret) {
drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
gdrst);
@@ -422,7 +423,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
FIELD_PREP(GS_UKERNEL_MASK,
XE_GUC_LOAD_STATUS_READY),
GS_UKERNEL_MASK, 200, &status);
GS_UKERNEL_MASK, 200000, &status);
if (ret) {
struct drm_device *drm = &xe->drm;
@@ -670,7 +671,7 @@ retry:
ret = xe_mmio_wait32(gt, reply_reg,
FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
GUC_HXG_ORIGIN_GUC),
GUC_HXG_MSG_0_ORIGIN, 50, &reply);
GUC_HXG_MSG_0_ORIGIN, 50000, &reply);
if (ret) {
timeout:
drm_err(&xe->drm, "mmio request 0x%08x: no reply 0x%08x\n",
@@ -685,7 +686,7 @@ timeout:
ret = xe_mmio_wait32(gt, reply_reg,
FIELD_PREP(GUC_HXG_MSG_0_TYPE,
GUC_HXG_TYPE_RESPONSE_SUCCESS),
GUC_HXG_MSG_0_TYPE, 1000, &header);
GUC_HXG_MSG_0_TYPE, 1000000, &header);
if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
GUC_HXG_ORIGIN_GUC))

2
drivers/gpu/drm/xe/xe_huc.c
View File

@@ -85,7 +85,7 @@ int xe_huc_auth(struct xe_huc *huc)
ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,
HUC_LOAD_SUCCESSFUL,
HUC_LOAD_SUCCESSFUL, 100, NULL);
HUC_LOAD_SUCCESSFUL, 100000, NULL);
if (ret) {
drm_err(&xe->drm, "HuC: Firmware not verified %d\n", ret);
goto fail;

4
drivers/gpu/drm/xe/xe_mmio.h
View File

@@ -83,10 +83,10 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
}
static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val,
u32 mask, u32 timeout_ms, u32 *out_val)
u32 mask, u32 timeout_us, u32 *out_val)
{
ktime_t cur = ktime_get_raw();
const ktime_t end = ktime_add_ms(cur, timeout_ms);
const ktime_t end = ktime_add_us(cur, timeout_us);
int ret = -ETIMEDOUT;
s64 wait = 10;
u32 read;

2
drivers/gpu/drm/xe/xe_uc_fw.c
View File

@@ -352,7 +352,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
/* Wait for DMA to finish */
ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100, &dma_ctrl);
ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl);
if (ret)
drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);