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arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable GBETH

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Enable the GBETH nodes on the RZ/V2H Evaluation Kit.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513131412.253091-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2025-05-13 14:14:12 +01:00
committed by Geert Uytterhoeven
parent 050ee38d00
commit 802292ee27
1 changed files with 66 additions and 0 deletions
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66
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
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@@ -16,6 +16,8 @@
compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -78,6 +80,22 @@
clock-frequency = <22579200>;
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};
&gpu {
status = "okay";
mali-supply = <&reg_0p8v>;
@@ -139,6 +157,44 @@
status = "okay";
};
&mdio0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&mdio1 {
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&ostm0 {
status = "okay";
};
@@ -172,6 +228,16 @@
};
&pinctrl {
eth0_pins: eth0 {
pins = "ET0_TXC_TXCLK";
output-enable;
};
eth1_pins: eth0 {
pins = "ET1_TXC_TXCLK";
output-enable;
};
i2c0_pins: i2c0 {
pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
<RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */