From fbf76e4bc278d7cd447af6a6fddc4f1a4ac0d45f Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:53 -0700 Subject: [PATCH 01/24] dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC Document vendor prefix for Tenstorrent in DT bindings. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..21921be22207 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1610,6 +1610,8 @@ patternProperties: description: Tempo Semiconductor "^tenda,.*": description: Shenzhen Tenda Technology Co., Ltd. + "^tenstorrent,.*": + description: Tenstorrent AI ULC "^terasic,.*": description: Terasic Inc. "^tesla,.*": From 4de28f1edcfbd22ade0a69b97a10a43d09f5d4b4 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:54 -0700 Subject: [PATCH 02/24] dt-bindings: riscv: Add Tenstorrent Blackhole compatible Add compatibles for the Tenstorrent Blackhole SoC PCIe card. Reviewed-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- .../bindings/riscv/tenstorrent.yaml | 28 +++++++++++++++++++ MAINTAINERS | 8 ++++++ 2 files changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/tenstorrent.yaml diff --git a/Documentation/devicetree/bindings/riscv/tenstorrent.yaml b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml new file mode 100644 index 000000000000..e15359b2aab6 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/tenstorrent.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tenstorrent SoC-based boards + +maintainers: + - Drew Fustini + - Joel Stanley + +description: + Tenstorrent SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Tenstorrent Blackhole PCIe card + items: + - const: tenstorrent,blackhole-card + - const: tenstorrent,blackhole + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..5a29636b2df0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22158,6 +22158,14 @@ F: arch/riscv/boot/dts/spacemit/ N: spacemit K: spacemit +RISC-V TENSTORRENT SoC SUPPORT +M: Drew Fustini +M: Joel Stanley +L: linux-riscv@lists.infradead.org +S: Maintained +T: git https://github.com/tenstorrent/linux.git +F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml + RISC-V THEAD SoC SUPPORT M: Drew Fustini M: Guo Ren From 571e42a1197c432d6bb78e1feb9586b4feb0a981 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:55 -0700 Subject: [PATCH 03/24] dt-bindings: riscv: cpus: Add SiFive X280 compatible Document compatible for the SiFive X280 RISC-V core. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb..afb8533f6a08 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -70,6 +70,7 @@ properties: - enum: - sifive,e51 - sifive,u54-mc + - sifive,x280 - const: sifive,rocket0 - const: riscv - const: riscv # Simulator only From b5951b25d72c9c790575fef5656ddde6a9277bd3 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:56 -0700 Subject: [PATCH 04/24] dt-bindings: timers: Add Tenstorrent Blackhole compatible Document clint compatible for the Tenstorrent Blackhole SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index d85a1a088b35..0d3b8dc362ba 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -36,6 +36,7 @@ properties: - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 + - tenstorrent,blackhole-clint # Tenstorrent Blackhole - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} From d6133f79da9f2276e4acdb60864b3a3c5f3ab60d Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:57 -0700 Subject: [PATCH 05/24] dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible Document compatible for the PLIC in the Tenstorrent Blackhole SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f683d696909b..9886b7d73d3c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -64,6 +64,7 @@ properties: - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic + - tenstorrent,blackhole-plic - const: sifive,plic-1.0.0 - items: - enum: From 8e88602e99a7523270be29fecc722605aaf1ba03 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:58 -0700 Subject: [PATCH 06/24] riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards Add device tree source describing the Tenstorrent Blackhole SoC and the Blackhole P100 and P150 PCIe cards. There are no differences between the P100 and P150 cards from the perspective of an OS kernel like Linux running on the X280 cores. There is a virtual UART implemented in OpenSBI firmware that allows a console program on the PCIe host to communicate through shared memory with Linux running on the Blackhole card. CONFIG_HVC_RISCV_SBI needs to be enabled. The boot script on the host adds 'console=hvc0' so that the full boot output appears in the console program on the host. Link: https://github.com/tenstorrent/opensbi/ Link: https://github.com/tenstorrent/tt-bh-linux Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/tenstorrent/Makefile | 2 + .../boot/dts/tenstorrent/blackhole-card.dts | 14 +++ .../riscv/boot/dts/tenstorrent/blackhole.dtsi | 108 ++++++++++++++++++ 5 files changed, 126 insertions(+) create mode 100644 arch/riscv/boot/dts/tenstorrent/Makefile create mode 100644 arch/riscv/boot/dts/tenstorrent/blackhole-card.dts create mode 100644 arch/riscv/boot/dts/tenstorrent/blackhole.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 5a29636b2df0..b49471cc3139 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22165,6 +22165,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/tenstorrent/linux.git F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml +F: arch/riscv/boot/dts/tenstorrent/ RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3763d199c70a..cf179c6253ce 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -9,4 +9,5 @@ subdir-y += sifive subdir-y += sophgo subdir-y += spacemit subdir-y += starfive +subdir-y += tenstorrent subdir-y += thead diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile new file mode 100644 index 000000000000..2c81faaba462 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts new file mode 100644 index 000000000000..f53667ce73a9 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include "blackhole.dtsi" + +/ { + model = "Tenstorrent Blackhole"; + compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole"; + + memory@400030000000 { + device_type = "memory"; + reg = <0x4000 0x30000000 0x1 0x00000000>; + }; +}; diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi new file mode 100644 index 000000000000..6408810d8d80 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright 2025 Tenstorrent AI ULC +/dts-v1/; + +/ { + compatible = "tenstorrent,blackhole"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <50000000>; + + cpu@0 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <0>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@1 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <1>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@2 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <2>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@3 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <3>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + clint0: timer@2000000 { + compatible = "tenstorrent,blackhole-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>, + <&cpu1_intc 0x3>, <&cpu1_intc 0x7>, + <&cpu2_intc 0x3>, <&cpu2_intc 0x7>, + <&cpu3_intc 0x3>, <&cpu3_intc 0x7>; + }; + + plic0: interrupt-controller@c000000 { + compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x0c000000 0x0 0x04000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <128>; + }; + }; +}; From 16eb4e02a631b06a12b3170c8ec3f64a03b9d3ce Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:59 -0700 Subject: [PATCH 07/24] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the Blackhole. Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- arch/riscv/Kconfig.socs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 848e7149e443..0b4d408aebfa 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -63,6 +63,14 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_TENSTORRENT + bool "Tenstorrent SoCs" + help + This enables support for Tenstorrent SoC platforms. + Current support is for Blackhole P100 and P150 PCIe cards. + The Blackhole SoC contains four RISC-V CPU tiles each + consisting of 4x SiFive X280 cores. + config ARCH_THEAD bool "T-HEAD RISC-V SoCs" depends on MMU && !XIP_KERNEL From a71e6e8eea8ae2d624f097911f43357bba06d2a5 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:12:00 -0700 Subject: [PATCH 08/24] riscv: defconfig: Enable Tenstorrent SoCs Enable support for Tenstorrent SoCs in the default configuration. Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc2725cbca18..95d5230c0027 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -29,6 +29,7 @@ CONFIG_ARCH_SOPHGO=y CONFIG_ARCH_SPACEMIT=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_TENSTORRENT=y CONFIG_ARCH_THEAD=y CONFIG_ARCH_VIRT=y CONFIG_ARCH_CANAAN=y From c86ee66e14acb15d7d20b329ea49f751c9df8bc9 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:36 +0800 Subject: [PATCH 09/24] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Add vendor prefixes for "anlogic", "milianke" and "nuclei". These are required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC from Anlogic, which uses a processor core designed by Nuclei. Acked-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..23e74b96bfb7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -132,6 +132,8 @@ patternProperties: description: Anbernic "^andestech,.*": description: Andes Technology Corporation + "^anlogic,.*": + description: Shanghai Anlogic Infotech Co., Ltd. "^anvo,.*": description: Anvo-Systems Dresden GmbH "^aoly,.*": @@ -1023,6 +1025,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milianke,.*": + description: Changzhou Milianke Electronic Technology Co., Ltd "^milkv,.*": description: MilkV Technology Co., Ltd "^miniand,.*": @@ -1140,6 +1144,8 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^numonyx,.*": description: Numonyx (deprecated, use micron) deprecated: true From 66c2a3173cdaf7b776552203609f008c8709dd22 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:37 +0800 Subject: [PATCH 10/24] dt-bindings: riscv: Add Nuclei UX900 compatibles The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC. It features a 64-bit architecture and dual-issue, 9-stage pipeline, with lots of optional extensions including V, K, Zc, and more. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb..20b7c834559c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 From 4689d4422ac47ffb0a4c06fdb0e165388f585d01 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:38 +0800 Subject: [PATCH 11/24] dt-bindings: riscv: Add Anlogic DR1V90 Add Anlogic DR1V90 FPSoC, featuring a UX900 RISC-V core as the processing system (PS) and 94,464 LUTs programmable logic (PL). It is used by the Milianke MLKPAI-FS01 board, a SBC equipped with 512MB DDR3 memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/anlogic.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/anlogic.yaml diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documentation/devicetree/bindings/riscv/anlogic.yaml new file mode 100644 index 000000000000..91b1526c99aa --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/anlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic SoC-based boards + +maintainers: + - Junhui Liu + +description: + Anlogic SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milianke,mlkpai-fs01 + - const: anlogic,dr1v90 + +additionalProperties: true + +... From ccc3fd3ebeef2686f005733858c0a1b2cb89aaeb Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:42 +0800 Subject: [PATCH 12/24] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Add MTIMER support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a TIMER unit compliant with the ACLINT specification. Signed-off-by: Junhui Liu Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../timer/thead,c900-aclint-mtimer.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml index 4ed30efe4052..cf7c82e980f6 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -4,18 +4,23 @@ $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sophgo CLINT Timer +title: ACLINT Machine-level Timer Device maintainers: - Inochi Amaoto properties: compatible: - items: - - enum: - - sophgo,sg2042-aclint-mtimer - - sophgo,sg2044-aclint-mtimer - - const: thead,c900-aclint-mtimer + oneOf: + - items: + - enum: + - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer + - const: thead,c900-aclint-mtimer + - items: + - enum: + - anlogic,dr1v90-aclint-mtimer + - const: nuclei,ux900-aclint-mtimer reg: items: From a94f9be29464f85e97683901162ca236dde40dc7 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:43 +0800 Subject: [PATCH 13/24] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart The Anlogic DR1V90 SoC integrates a UART controller compatible with snps,dw-apb-uart, operating at a 50 MHz clock. Acked-by: Rob Herring (Arm) Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97afc..691bd0bac6be 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart From 9c96219602b1a29c1959c5799aa3e6c5e14e395c Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:45 +0800 Subject: [PATCH 14/24] riscv: Add Anlogic SoC famly Kconfig support The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 848e7149e443..25f7e58cbf74 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config ARCH_ANDES help This enables support for Andes SoC platform hardware. +config ARCH_ANLOGIC + bool "Anlogic SoCs" + help + This enables support for Anlogic SoC platform hardware. + config ARCH_ESWIN bool "ESWIN SoCs" help From 77874ebd4032b1f407b01a7bbdfcad752da05592 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:46 +0800 Subject: [PATCH 15/24] riscv: dts: Add initial Anlogic DR1V90 SoC device tree DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS part and 94,464 LUTs for the PL part. The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible UART controllers. Some basic information of the processor can be obtained by running a simple application from nuclei-sdk [1]: -----Nuclei RISC-V CPU Configuration Information----- MARCHID: 0xc900 MIMPID: 0x20300 ISA: RV64 A B C D F I M P S U MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-Safety-Mechanism DLEN=VLEN/2 ILM: 256 KB has-ecc DLM: 256 KB has-ecc ICACHE: 32 KB(set=256,way=2,lsize=64,ecc=1) DCACHE: 32 KB(set=256,way=2,lsize=64,ecc=1) TLB: MainTLB(set=32,way=2,entry=1,ecc=1) ITLB(entry=8) DTLB(entry=8) IREGION: 0x68000000 128 MB Unit Size Address INFO 64KB 0x68000000 DEBUG 64KB 0x68010000 ECLIC 64KB 0x68020000 TIMER 64KB 0x68030000 PLIC 64MB 0x6c000000 INFO-Detail: mpasize : 0 PPI: 0xf8000000 128 MB -----End of Nuclei CPU INFO----- Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application/baremetal/cpuinfo/main.c [1] Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 100 ++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 arch/riscv/boot/dts/anlogic/dr1v90.dtsi diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi new file mode 100644 index 000000000000..a5d0765ade32 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Anlogic DR1V90"; + compatible = "anlogic,dr1v90"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <800000000>; + + cpu@0 { + compatible = "nuclei,ux900", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + reg = <0>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aclint_mswi: interrupt-controller@68031000 { + compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; + reg = <0x0 0x68031000 0x0 0x4000>; + interrupts-extended = <&cpu0_intc 3>; + }; + + aclint_mtimer: timer@68035000 { + compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer"; + reg = <0x0 0x68035000 0x0 0x8000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu0_intc 7>; + }; + + aclint_sswi: interrupt-controller@6803d000 { + compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; + reg = <0x0 0x6803d000 0x0 0x3000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 1>; + }; + + plic: interrupt-controller@6c000000 { + compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x6c000000 0x0 0x4000000>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + riscv,ndev = <150>; + }; + + uart0: serial@f8400000 { + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf8400000 0x0 0x1000>; + clock-frequency = <50000000>; + interrupts = <71>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@f8401000 { + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf8401000 0x0 0x1000>; + clock-frequency = <50000000>; + interrupts = <72>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; From 7e6fd69c12f464c21e489aba763f0cef5cdd1373 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:47 +0800 Subject: [PATCH 16/24] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Add support for the Milianke MLKPAI FS01 board based on the Anlogic DR1V90 SoC. The board features 512MB of onboard memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Currently, the board can boot to a console via UART1, which is connected to the onboard serial chip and routed to the Type-C interface. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/anlogic/Makefile | 2 ++ .../boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 +++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/boot/dts/anlogic/Makefile create mode 100644 arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3763d199c70a..f99d38ee1aad 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner subdir-y += andes +subdir-y += anlogic subdir-y += canaan subdir-y += eswin subdir-y += microchip diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anlogic/Makefile new file mode 100644 index 000000000000..87f3b2f418cf --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts new file mode 100644 index 000000000000..597407655efd --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +#include "dr1v90.dtsi" + +/ { + model = "Milianke MLKPAI-FS01"; + compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; From fa9311d9499fedf0f6d06c22e016b228f2f5d473 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Tue, 21 Oct 2025 17:41:48 +0800 Subject: [PATCH 17/24] riscv: defconfig: Enable Anlogic SoC Enable Anlogic SoC config in defconfig to allow the default upstream kernel booting on Milianke MLKPAI-FS01 board. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc2725cbca18..14b82f770efe 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_PROFILING=y CONFIG_ARCH_ANDES=y +CONFIG_ARCH_ANLOGIC=y CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y From d5c3f49b75832553ba0dafabc2d394a885106498 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 12 Nov 2025 17:09:25 +0000 Subject: [PATCH 18/24] MAINTAINERS: Setup support for Anlogic tree Add myself as the maintainer of the Anlogic DR1V90 SoC tree, including the corresponding DTS and DT bindings paths for Anlogic RISC-V-based SoCs. I don't really want to look after this platform, but am due to irritation of the vendor's behaviour towards the contributor of support. Hence, Odd Fixes as the status. Signed-off-by: Conor Dooley --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..8c153489d2fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22055,6 +22055,14 @@ F: Documentation/devicetree/bindings/riscv/andes.yaml F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml F: arch/riscv/boot/dts/andes/ +RISC-V ANLOGIC SoC SUPPORT +M: Conor Dooley +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +L: linux-riscv@lists.infradead.org +S: Odd Fixes +F: Documentation/devicetree/bindings/riscv/anlogic.yaml +F: arch/riscv/boot/dts/anlogic/ + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt From 9371cd418346cee110e352c3b4bc9d583672d7e3 Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Thu, 16 Oct 2025 20:05:53 +0800 Subject: [PATCH 19/24] dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. Black Sesame Technologies Co., Ltd.s a leading automotive-grade computing SoC and SoC-based intelligent vehicle solution provider. Link: https://bst.ai/. Signed-off-by: Albert Yang Acked-by: Rob Herring (Arm) Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..df0a50b5437b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -251,6 +251,8 @@ patternProperties: description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^bsh,.*": description: BSH Hausgeraete GmbH + "^bst,.*": + description: Black Sesame Technologies Co., Ltd. "^bticino,.*": description: Bticino International "^buffalo,.*": From fc77dc0620b70e533c506f120eb4afd5d6cadf3a Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Thu, 16 Oct 2025 20:05:54 +0800 Subject: [PATCH 20/24] dt-bindings: arm: add Black Sesame Technologies (bst) SoC Add device tree bindings for Black Sesame Technologies Arm SoC, it consists several SoC models like C1200, etc. Signed-off-by: Albert Yang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/arm/bst.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bst.yaml diff --git a/Documentation/devicetree/bindings/arm/bst.yaml b/Documentation/devicetree/bindings/arm/bst.yaml new file mode 100644 index 000000000000..a3a7f424fd57 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bst.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BST platforms + +description: + Black Sesame Technologies (BST) is a semiconductor company that produces + automotive-grade system-on-chips (SoCs) for intelligent driving, focusing + on computer vision and AI capabilities. The BST C1200 family includes SoCs + for ADAS (Advanced Driver Assistance Systems) and autonomous driving + applications. + +maintainers: + - Ge Gordon + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BST C1200 CDCU1.0 ADAS 4C2G board + items: + - const: bst,c1200-cdcu1.0-adas-4c2g + - const: bst,c1200 + +additionalProperties: true + +... From 154121941643395be89fc051628e83ad746330d5 Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Thu, 16 Oct 2025 20:05:55 +0800 Subject: [PATCH 21/24] arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs Add ARCH_BST configuration option to enable support for Black Sesame Technologies SoC family. BST produces automotive-grade system-on-chips for intelligent driving, focusing on computer vision and AI capabilities. The BST C1200 family includes SoCs for ADAS and autonomous driving applications. Signed-off-by: Albert Yang Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 13173795c43d..0ef07343cc3d 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -119,6 +119,14 @@ config ARCH_BLAIZE help This enables support for the Blaize SoC family +config ARCH_BST + bool "Black Sesame Technologies SoC Family" + help + This enables support for Black Sesame Technologies (BST) SoC family. + BST produces automotive-grade system-on-chips for intelligent driving, + focusing on computer vision and AI capabilities. The BST C1200 family + includes SoCs for ADAS and autonomous driving applications. + config ARCH_CIX bool "Cixtech SoC family" help From c03a37773bf0eaf3b4aa08143e2faf7400f152ad Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Thu, 16 Oct 2025 20:05:56 +0800 Subject: [PATCH 22/24] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, and interrupt controller. Signed-off-by: Albert Yang Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bst/Makefile | 2 + .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 24 +++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 97 +++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/bst/Makefile create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index b0844404eda1..98ec8f1b76e4 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y += axiado subdir-y += bitmain subdir-y += blaize subdir-y += broadcom +subdir-y += bst subdir-y += cavium subdir-y += cix subdir-y += exynos diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile new file mode 100644 index 000000000000..4c1b8b4cdad8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 000000000000..5eb9ef369d8c --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model = "BST C1200-96 CDCU1.0 4C2G"; + compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@810000000 { + device_type = "memory"; + reg = <0x8 0x10000000 0x0 0x30000000>, + <0x8 0xc0000000 0x1 0x0>, + <0xc 0x00000000 0x0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi new file mode 100644 index 000000000000..dd13c6bfc3c8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible = "bst,c1200"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + uart0: serial@20008000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20008000 0x0 0x1000>; + clock-frequency = <25000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x32800000 0x0 0x10000>, + <0x0 0x32880000 0x0 0x100000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + always-on; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; From be64ae6fe2c076427d6bd3c6bbe05af0478046d2 Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Thu, 16 Oct 2025 20:05:57 +0800 Subject: [PATCH 23/24] arm64: defconfig: enable BST platform support Enable support for Black Sesame Technologies (BST) platform in the ARM64 defconfig: - CONFIG_ARCH_BST: Enable BST SoC platform support Signed-off-by: Albert Yang Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e3a2d37bd104..972cae9bee88 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -47,6 +47,7 @@ CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BRCMSTB=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_BLAIZE=y +CONFIG_ARCH_BST=y CONFIG_ARCH_CIX=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_SPARX5=y From 92bcb8cc7b2440cd9074736d14a2417fe0b396bc Mon Sep 17 00:00:00 2001 From: Albert Yang Date: Thu, 16 Oct 2025 20:05:58 +0800 Subject: [PATCH 24/24] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support Add a MAINTAINERS entry for Black Sesame Technologies (BST) ARM SoC support. This entry covers device tree bindings, drivers, and board files for BST SoCs, and platform support. Signed-off-by: Albert Yang Signed-off-by: Arnd Bergmann --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3da2c26a796b..04c133921494 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2547,6 +2547,14 @@ S: Maintained F: Documentation/devicetree/bindings/arm/blaize.yaml F: arch/arm64/boot/dts/blaize/ +ARM/BST SOC SUPPORT +M: Ge Gordon +R: BST Linux Kernel Upstream Group +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/arm/bst.yaml +F: arch/arm64/boot/dts/bst/ + ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)