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arm64: dts: ti: k3-am62l: add initial infrastructure
Add the initial infrastructure needed for the AM62L. ALl of which can be
found in the Technical Reference Manual (TRM) located here:
https://www.ti.com/lit/pdf/sprujb4
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://patch.msgid.link/20251105-am62lx-v8-2-496f353e8237@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Vignesh Raghavendra
580
arch/arm64/boot/dts/ti/k3-am62l-main.dtsi
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580
arch/arm64/boot/dts/ti/k3-am62l-main.dtsi
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@@ -0,0 +1,580 @@
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// SPDX-License-Identifier: GPL-2.0-only or MIT
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/*
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* Device Tree file for the AM62L main domain peripherals
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* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
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*
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* Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
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*/
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&cbass_main {
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01840000 0x00 0xc0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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interrupt-controller;
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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gpio0: gpio@600000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x00 0x00600000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 267 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&scmi_pds 34>;
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clocks = <&scmi_clk 140>;
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clock-names = "gpio";
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ti,ngpio = <126>;
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ti,davinci-gpio-unbanked = <0>;
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};
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gpio2: gpio@610000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x00 0x00610000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 281 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&scmi_pds 35>;
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clocks = <&scmi_clk 141>;
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clock-names = "gpio";
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ti,ngpio = <79>;
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ti,davinci-gpio-unbanked = <0>;
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};
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timer0: timer@2400000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x2400000 0x00 0x400>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 58>;
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clock-names = "fck";
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power-domains = <&scmi_pds 15>;
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ti,timer-pwm;
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};
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timer1: timer@2410000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x2410000 0x00 0x400>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 63>;
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clock-names = "fck";
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power-domains = <&scmi_pds 16>;
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ti,timer-pwm;
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};
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timer2: timer@2420000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x2420000 0x00 0x400>;
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 77>;
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clock-names = "fck";
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power-domains = <&scmi_pds 17>;
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ti,timer-pwm;
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};
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timer3: timer@2430000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x2430000 0x00 0x400>;
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk 82>;
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clock-names = "fck";
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power-domains = <&scmi_pds 18>;
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ti,timer-pwm;
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};
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uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 89>;
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clocks = <&scmi_clk 358>;
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clock-names = "fclk";
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status = "disabled";
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};
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uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 77>;
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clocks = <&scmi_clk 312>;
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clock-names = "fclk";
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status = "disabled";
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};
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uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 78>;
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clocks = <&scmi_clk 314>;
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clock-names = "fclk";
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status = "disabled";
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};
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uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 79>;
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clocks = <&scmi_clk 316>;
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clock-names = "fclk";
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status = "disabled";
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};
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uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 80>;
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clocks = <&scmi_clk 318>;
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clock-names = "fclk";
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status = "disabled";
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};
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uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 81>;
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clocks = <&scmi_clk 320>;
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clock-names = "fclk";
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status = "disabled";
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};
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uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 82>;
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clocks = <&scmi_clk 322>;
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clock-names = "fclk";
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status = "disabled";
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};
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conf: bus@9000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x09000000 0x380000>;
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phy_gmii_sel: phy@1be000 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x1be000 0x8>;
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#phy-cells = <1>;
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};
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epwm_tbclk: clock-controller@1e9100 {
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compatible = "ti,am62-epwm-tbclk";
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reg = <0x1e9100 0x4>;
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#clock-cells = <1>;
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};
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};
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usbss0: dwc3-usb@f900000 {
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compatible = "ti,am62-usb";
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reg = <0x00 0x0f900000 0x00 0x800>,
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<0x00 0x0f908000 0x00 0x400>;
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clocks = <&scmi_clk 331>;
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clock-names = "ref";
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ti,syscon-phy-pll-refclk = <&usb_phy_ctrl 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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power-domains = <&scmi_pds 95>;
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ranges;
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status = "disabled";
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usb0: usb@31000000 {
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compatible = "snps,dwc3";
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reg = <0x00 0x31000000 0x00 0x50000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
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interrupt-names = "host", "peripheral";
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maximum-speed = "high-speed";
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dr_mode = "otg";
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snps,usb2-gadget-lpm-disable;
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snps,usb2-lpm-disable;
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};
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};
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usbss1: dwc3-usb@f910000 {
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compatible = "ti,am62-usb";
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reg = <0x00 0x0f910000 0x00 0x800>,
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<0x00 0x0f918000 0x00 0x400>;
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clocks = <&scmi_clk 338>;
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clock-names = "ref";
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ti,syscon-phy-pll-refclk = <&usb_phy_ctrl 0x4>;
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#address-cells = <2>;
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#size-cells = <2>;
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power-domains = <&scmi_pds 96>;
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ranges;
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status = "disabled";
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usb1: usb@31100000 {
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compatible = "snps,dwc3";
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reg = <0x00 0x31100000 0x00 0x50000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
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interrupt-names = "host", "peripheral";
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maximum-speed = "high-speed";
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dr_mode = "otg";
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snps,usb2-gadget-lpm-disable;
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snps,usb2-lpm-disable;
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};
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};
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sdhci1: mmc@fa00000 {
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compatible = "ti,j721e-sdhci-4bit";
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reg = <0x00 0x0fa00000 0x00 0x1000>,
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<0x00 0x0fa08000 0x00 0x400>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 26>;
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clocks = <&scmi_clk 106>, <&scmi_clk 109>;
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clock-names = "clk_ahb", "clk_xin";
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assigned-clocks = <&scmi_clk 109>;
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bus-width = <4>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-legacy = <0x0>;
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status = "disabled";
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};
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sdhci0: mmc@fa10000 {
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compatible = "ti,am62-sdhci";
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reg = <0x00 0xfa10000 0x00 0x1000>,
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<0x00 0xfa18000 0x00 0x400>;
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interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 28>;
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clocks = <&scmi_clk 122>, <&scmi_clk 125>;
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clock-names = "clk_ahb", "clk_xin";
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assigned-clocks = <&scmi_clk 125>;
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bus-width = <8>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-hs200 = <0x6>;
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status = "disabled";
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};
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sdhci2: mmc@fa20000 {
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compatible = "ti,am62-sdhci";
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reg = <0x00 0x0fa20000 0x00 0x1000>,
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<0x00 0x0fa28000 0x00 0x400>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&scmi_pds 27>;
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clocks = <&scmi_clk 114>, <&scmi_clk 117>;
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clock-names = "clk_ahb", "clk_xin";
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assigned-clocks = <&scmi_clk 117>;
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bus-width = <4>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-legacy = <0x0>;
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status = "disabled";
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};
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i2c0: i2c@20000000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20000000 0x00 0x100>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&scmi_pds 53>;
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clocks = <&scmi_clk 246>;
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clock-names = "fck";
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status = "disabled";
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};
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i2c1: i2c@20010000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20010000 0x00 0x100>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&scmi_pds 54>;
|
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clocks = <&scmi_clk 250>;
|
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clock-names = "fck";
|
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status = "disabled";
|
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};
|
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i2c2: i2c@20020000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
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reg = <0x00 0x20020000 0x00 0x100>;
|
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 55>;
|
||||
clocks = <&scmi_clk 254>;
|
||||
clock-names = "fck";
|
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status = "disabled";
|
||||
};
|
||||
|
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i2c3: i2c@20030000 {
|
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 56>;
|
||||
clocks = <&scmi_clk 258>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcan0: can@20701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20701000 0x00 0x200>,
|
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<0x00 0x20708000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&scmi_pds 47>;
|
||||
clocks = <&scmi_clk 179>, <&scmi_clk 178>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcan1: can@20711000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20711000 0x00 0x200>,
|
||||
<0x00 0x20718000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&scmi_pds 48>;
|
||||
clocks = <&scmi_clk 185>, <&scmi_clk 184>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcan2: can@20721000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20721000 0x00 0x200>,
|
||||
<0x00 0x20728000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&scmi_pds 49>;
|
||||
clocks = <&scmi_clk 191>, <&scmi_clk 190>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 72>;
|
||||
clocks = <&scmi_clk 299>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 73>;
|
||||
clocks = <&scmi_clk 302>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 74>;
|
||||
clocks = <&scmi_clk 305>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@20130000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20130000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 75>;
|
||||
clocks = <&scmi_clk 308>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
epwm0: pwm@23000000 {
|
||||
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x23000000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 40>;
|
||||
clocks = <&epwm_tbclk 0>, <&scmi_clk 164>;
|
||||
clock-names = "tbclk", "fck";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
epwm1: pwm@23010000 {
|
||||
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x23010000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 41>;
|
||||
clocks = <&epwm_tbclk 1>, <&scmi_clk 165>;
|
||||
clock-names = "tbclk", "fck";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
epwm2: pwm@23020000 {
|
||||
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x23020000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 42>;
|
||||
clocks = <&epwm_tbclk 2>, <&scmi_clk 166>;
|
||||
clock-names = "tbclk", "fck";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap0: pwm@23100000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
reg = <0x00 0x23100000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 23>;
|
||||
clocks = <&scmi_clk 99>;
|
||||
clock-names = "fck";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap1: pwm@23110000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
reg = <0x00 0x23110000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 24>;
|
||||
clocks = <&scmi_clk 100>;
|
||||
clock-names = "fck";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap2: pwm@23120000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
reg = <0x00 0x23120000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 25>;
|
||||
clocks = <&scmi_clk 101>;
|
||||
clock-names = "fck";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep0: counter@23200000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23200000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 29>;
|
||||
clocks = <&scmi_clk 127>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep1: counter@23210000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23210000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 30>;
|
||||
clocks = <&scmi_clk 128>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqep2: counter@23220000 {
|
||||
compatible = "ti,am62-eqep";
|
||||
reg = <0x00 0x23220000 0x00 0x100>;
|
||||
power-domains = <&scmi_pds 31>;
|
||||
clocks = <&scmi_clk 129>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
elm0: ecc@25010000 {
|
||||
compatible = "ti,am64-elm";
|
||||
reg = <0x00 0x25010000 0x00 0x2000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&scmi_pds 25>;
|
||||
clocks = <&scmi_clk 102>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpmc0: memory-controller@3b000000 {
|
||||
compatible = "ti,am64-gpmc";
|
||||
power-domains = <&scmi_pds 37>;
|
||||
clocks = <&scmi_clk 149>;
|
||||
clock-names = "fck";
|
||||
reg = <0x00 0x3b000000 0x00 0x400>,
|
||||
<0x00 0x50000000 0x00 0x8000000>;
|
||||
reg-names = "cfg", "data";
|
||||
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <3>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
oc_sram: sram@70800000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x70800000 0x00 0x10000>;
|
||||
ranges = <0x00 0x00 0x70800000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
scmi_shmem: sram@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x00 0x100>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
141
arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
Normal file
141
arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
Normal file
@@ -0,0 +1,141 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only or MIT
|
||||
/*
|
||||
* Device Tree file for the AM62L wakeup domain peripherals
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
|
||||
*/
|
||||
|
||||
#include <dt-bindings/bus/ti-sysc.h>
|
||||
|
||||
&cbass_wakeup {
|
||||
vtm0: temperature-sensor@b00000 {
|
||||
compatible = "ti,j7200-vtm";
|
||||
reg = <0x00 0xb00000 0x00 0x400>,
|
||||
<0x00 0xb01000 0x00 0x400>;
|
||||
power-domains = <&scmi_pds 46>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
pmx0: pinctrl@4084000 {
|
||||
compatible = "ti,am62l-padconf", "pinctrl-single";
|
||||
reg = <0x00 0x4084000 0x00 0x24c>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
#pinctrl-cells = <1>;
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@4201000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x04201000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 706 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 707 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
power-domains = <&scmi_pds 36>;
|
||||
clocks = <&scmi_clk 146>;
|
||||
clock-names = "gpio";
|
||||
ti,ngpio = <7>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_timer0: timer@2b100000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2b100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 93>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&scmi_pds 19>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
wkup_timer1: timer@2b110000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x00 0x2b110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 98>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&scmi_pds 20>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@2b200000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x2b200000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 57>;
|
||||
clocks = <&scmi_clk 262>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@2b300050 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x00 0x2b300050 0x00 0x4>,
|
||||
<0x00 0x2b300054 0x00 0x4>,
|
||||
<0x00 0x2b300058 0x00 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ranges = <0x00 0x00 0x2b300000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&scmi_pds 83>;
|
||||
clocks = <&scmi_clk 324>;
|
||||
clock-names = "fck";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,syss-mask = <1>;
|
||||
ti,no-reset-on-init;
|
||||
status = "disabled";
|
||||
|
||||
wkup_uart0: serial@0 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 324>;
|
||||
assigned-clocks = <&scmi_clk 324>;
|
||||
clock-names = "fclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
wkup_conf: bus@43000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00 0x00 0x43000000 0x80000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@2000 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x2000 0x8>;
|
||||
};
|
||||
|
||||
usb_phy_ctrl: syscon@45000 {
|
||||
compatible = "ti,am62-usb-phy-ctrl", "syscon";
|
||||
reg = <0x45000 0x1000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
118
arch/arm64/boot/dts/ti/k3-am62l.dtsi
Normal file
118
arch/arm64/boot/dts/ti/k3-am62l.dtsi
Normal file
@@ -0,0 +1,118 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only or MIT
|
||||
/*
|
||||
* Device Tree Source for AM62L SoC Family
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM62L3 SoC";
|
||||
compatible = "ti,am62l3";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
scmi: scmi {
|
||||
compatible = "arm,scmi-smc";
|
||||
arm,smc-id = <0x82004000>;
|
||||
shmem = <&scmi_shmem>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
scmi_pds: protocol@11 {
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f0000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */
|
||||
<0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
|
||||
<0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */
|
||||
<0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */
|
||||
<0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */
|
||||
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */
|
||||
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */
|
||||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */
|
||||
<0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */
|
||||
<0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */
|
||||
|
||||
/* Wakeup Domain Range */
|
||||
<0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
|
||||
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
|
||||
<0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
|
||||
<0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
|
||||
<0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
|
||||
<0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cbass_wakeup: bus@43000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
|
||||
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
|
||||
<0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
|
||||
<0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
|
||||
<0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
|
||||
<0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include peripherals for each bus segment */
|
||||
#include "k3-am62l-main.dtsi"
|
||||
#include "k3-am62l-wakeup.dtsi"
|
||||
67
arch/arm64/boot/dts/ti/k3-am62l3.dtsi
Normal file
67
arch/arm64/boot/dts/ti/k3-am62l3.dtsi
Normal file
@@ -0,0 +1,67 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only or MIT
|
||||
/*
|
||||
* Device Tree file for the AM62L3 SoC family (Dual Core A53)
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62l.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
l2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <256>;
|
||||
};
|
||||
};
|
||||
@@ -123,6 +123,8 @@
|
||||
#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
|
||||
Reference in New Issue
Block a user