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arm64: dts: imx8qxp: add flexcan in adma

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Add FlexCAN decive in adma subsystem.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # TQMa8XQP
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Joakim Zhang
2023-02-08 07:56:36 +01:00
committed by Shawn Guo
parent 033f5e7ef8
commit 5e7d5b023e
1 changed files with 72 additions and 0 deletions
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72
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
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@@ -298,6 +298,65 @@ dma_subsys: bus@5a000000 {
status = "disabled"; status = "disabled";
}; };
flexcan1: can@5a8d0000 {
compatible = "fsl,imx8qm-flexcan";
reg = <0x5a8d0000 0x10000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&can0_lpcg 1>,
<&can0_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
power-domains = <&pd IMX_SC_R_CAN_0>;
/* SLSlice[4] */
fsl,clk-source = /bits/ 8 <0>;
fsl,scu-index = /bits/ 8 <0>;
status = "disabled";
};
flexcan2: can@5a8e0000 {
compatible = "fsl,imx8qm-flexcan";
reg = <0x5a8e0000 0x10000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* CAN0 clock and PD is shared among all CAN instances as
* CAN1 shares CAN0's clock and to enable CAN0's clock it
* has to be powered on.
*/
clocks = <&can0_lpcg 1>,
<&can0_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
power-domains = <&pd IMX_SC_R_CAN_1>;
/* SLSlice[4] */
fsl,clk-source = /bits/ 8 <0>;
fsl,scu-index = /bits/ 8 <1>;
status = "disabled";
};
flexcan3: can@5a8f0000 {
compatible = "fsl,imx8qm-flexcan";
reg = <0x5a8f0000 0x10000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* CAN0 clock and PD is shared among all CAN instances as
* CAN2 shares CAN0's clock and to enable CAN0's clock it
* has to be powered on.
*/
clocks = <&can0_lpcg 1>,
<&can0_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
power-domains = <&pd IMX_SC_R_CAN_2>;
/* SLSlice[4] */
fsl,clk-source = /bits/ 8 <0>;
fsl,scu-index = /bits/ 8 <2>;
status = "disabled";
};
i2c0_lpcg: clock-controller@5ac00000 { i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg"; compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>; reg = <0x5ac00000 0x10000>;
@@ -369,4 +428,17 @@ dma_subsys: bus@5a000000 {
"adc1_lpcg_ipg_clk"; "adc1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ADC_1>; power-domains = <&pd IMX_SC_R_ADC_1>;
}; };
can0_lpcg: clock-controller@5acd0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5acd0000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>, <&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "can0_lpcg_pe_clk",
"can0_lpcg_ipg_clk",
"can0_lpcg_chi_clk";
power-domains = <&pd IMX_SC_R_CAN_0>;
};
}; };