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lib/xz: remove dead IA-64 (Itanium) support code
Support for the IA-64 (Itanium) architecture was removed in commit
cf8e865810 ("arch: Remove Itanium (IA-64) architecture").
This patch drops the IA-64 specific decompression code from lib/xz, which
was conditionally compiled with the now-obsolete CONFIG_XZ_DEC_IA64
option.
Link: https://lkml.kernel.org/r/20251014052738.31185-1-spyjetfayed@gmail.com
Signed-off-by: Ankan Biswas <spyjetfayed@gmail.com>
Reviewed-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Khalid Aziz <khalid@kernel.org>
Acked-by: Lasse Collin <lasse.collin@tukaani.org>
Cc: David Hunter <david.hunter.linux@gmail.com>
Cc: Shuah Khan <skhan@linuxfoundation.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
This commit is contained in:
committed by
Andrew Morton
parent
9544f9e694
commit
57f3d89691
@@ -20,7 +20,6 @@ struct xz_dec_bcj {
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enum {
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BCJ_X86 = 4, /* x86 or x86-64 */
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BCJ_POWERPC = 5, /* Big endian only */
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BCJ_IA64 = 6, /* Big or little endian */
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BCJ_ARM = 7, /* Little endian only */
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BCJ_ARMTHUMB = 8, /* Little endian only */
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BCJ_SPARC = 9, /* Big or little endian */
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@@ -180,92 +179,6 @@ static size_t bcj_powerpc(struct xz_dec_bcj *s, uint8_t *buf, size_t size)
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}
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#endif
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#ifdef XZ_DEC_IA64
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static size_t bcj_ia64(struct xz_dec_bcj *s, uint8_t *buf, size_t size)
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{
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static const uint8_t branch_table[32] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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4, 4, 6, 6, 0, 0, 7, 7,
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4, 4, 0, 0, 4, 4, 0, 0
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};
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/*
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* The local variables take a little bit stack space, but it's less
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* than what LZMA2 decoder takes, so it doesn't make sense to reduce
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* stack usage here without doing that for the LZMA2 decoder too.
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*/
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/* Loop counters */
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size_t i;
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size_t j;
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/* Instruction slot (0, 1, or 2) in the 128-bit instruction word */
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uint32_t slot;
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/* Bitwise offset of the instruction indicated by slot */
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uint32_t bit_pos;
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/* bit_pos split into byte and bit parts */
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uint32_t byte_pos;
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uint32_t bit_res;
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/* Address part of an instruction */
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uint32_t addr;
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/* Mask used to detect which instructions to convert */
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uint32_t mask;
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/* 41-bit instruction stored somewhere in the lowest 48 bits */
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uint64_t instr;
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/* Instruction normalized with bit_res for easier manipulation */
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uint64_t norm;
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size &= ~(size_t)15;
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for (i = 0; i < size; i += 16) {
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mask = branch_table[buf[i] & 0x1F];
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for (slot = 0, bit_pos = 5; slot < 3; ++slot, bit_pos += 41) {
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if (((mask >> slot) & 1) == 0)
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continue;
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byte_pos = bit_pos >> 3;
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bit_res = bit_pos & 7;
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instr = 0;
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for (j = 0; j < 6; ++j)
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instr |= (uint64_t)(buf[i + j + byte_pos])
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<< (8 * j);
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norm = instr >> bit_res;
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if (((norm >> 37) & 0x0F) == 0x05
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&& ((norm >> 9) & 0x07) == 0) {
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addr = (norm >> 13) & 0x0FFFFF;
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addr |= ((uint32_t)(norm >> 36) & 1) << 20;
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addr <<= 4;
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addr -= s->pos + (uint32_t)i;
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addr >>= 4;
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norm &= ~((uint64_t)0x8FFFFF << 13);
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norm |= (uint64_t)(addr & 0x0FFFFF) << 13;
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norm |= (uint64_t)(addr & 0x100000)
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<< (36 - 20);
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instr &= (1 << bit_res) - 1;
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instr |= norm << bit_res;
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for (j = 0; j < 6; j++)
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buf[i + j + byte_pos]
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= (uint8_t)(instr >> (8 * j));
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}
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}
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}
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return i;
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}
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#endif
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#ifdef XZ_DEC_ARM
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static size_t bcj_arm(struct xz_dec_bcj *s, uint8_t *buf, size_t size)
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{
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@@ -509,11 +422,6 @@ static void bcj_apply(struct xz_dec_bcj *s,
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filtered = bcj_powerpc(s, buf, size);
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break;
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#endif
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#ifdef XZ_DEC_IA64
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case BCJ_IA64:
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filtered = bcj_ia64(s, buf, size);
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break;
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#endif
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#ifdef XZ_DEC_ARM
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case BCJ_ARM:
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filtered = bcj_arm(s, buf, size);
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@@ -699,9 +607,6 @@ enum xz_ret xz_dec_bcj_reset(struct xz_dec_bcj *s, uint8_t id)
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#ifdef XZ_DEC_POWERPC
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case BCJ_POWERPC:
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#endif
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#ifdef XZ_DEC_IA64
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case BCJ_IA64:
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#endif
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#ifdef XZ_DEC_ARM
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case BCJ_ARM:
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#endif
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@@ -24,9 +24,6 @@
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# ifdef CONFIG_XZ_DEC_POWERPC
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# define XZ_DEC_POWERPC
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# endif
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# ifdef CONFIG_XZ_DEC_IA64
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# define XZ_DEC_IA64
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# endif
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# ifdef CONFIG_XZ_DEC_ARM
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# define XZ_DEC_ARM
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# endif
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@@ -103,7 +100,6 @@
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*/
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#ifndef XZ_DEC_BCJ
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# if defined(XZ_DEC_X86) || defined(XZ_DEC_POWERPC) \
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|| defined(XZ_DEC_IA64) \
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|| defined(XZ_DEC_ARM) || defined(XZ_DEC_ARMTHUMB) \
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|| defined(XZ_DEC_SPARC) || defined(XZ_DEC_ARM64) \
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|| defined(XZ_DEC_RISCV)
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