Merge tag 'parisc-for-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc architecture updates from Helge Deller:
 "A fix which allows booting on the very old 710 workstations, and two
  fixes in the syscall entry/exit path which allow to execute 64-bit
  userspace binaries.

  Note that although we currently have a 64-bit (static) kernel to allow
  more than 4 GB physical RAM, there is no support for 64-bit userspace
  for parisc-linux yet, but Dave and Sven are making slowly progress to
  port and fix glibc and gcc.

  Summary:

   - Fix boot on 710 workstation by not reprogramming ASP chip

   - Fix 64bit userspace syscalls (64-bit userspace is still being
     developed)

   - minor code cleanups in asm/bug.h and perf_regs.c"

* tag 'parisc-for-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: Do not reprogram affinitiy on ASP chip
  parisc: Drop linux/kernel.h include from asm/bug.h header
  parisc: remove unneeded semicolon in perf_regs.c
  parisc: entry.S: fix space adjustment on interruption for 64-bit userspace
  parisc: entry: set W bit for !compat tasks in syscall_restore_rfi()
  parisc: Drop padding fields and layers entries from inventory log
This commit is contained in:
Linus Torvalds
2025-12-06 16:24:52 -08:00
6 changed files with 19 additions and 15 deletions

View File

@@ -2,8 +2,6 @@
#ifndef _PARISC_BUG_H
#define _PARISC_BUG_H
#include <linux/kernel.h> /* for BUGFLAG_TAINT */
/*
* Tell the user there is some problem.
* The offending file and line are encoded in the __bug_table section.

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@@ -258,6 +258,8 @@ int main(void)
BLANK();
DEFINE(TIF_BLOCKSTEP_PA_BIT, 31-TIF_BLOCKSTEP);
DEFINE(TIF_SINGLESTEP_PA_BIT, 31-TIF_SINGLESTEP);
DEFINE(TIF_32BIT_PA_BIT, 31-TIF_32BIT);
BLANK();
DEFINE(ASM_PMD_SHIFT, PMD_SHIFT);
DEFINE(ASM_PGDIR_SHIFT, PGDIR_SHIFT);

View File

@@ -1043,11 +1043,7 @@ static __init int qemu_print_iodc_data(struct device *lin_dev, void *data)
(unsigned char)mod_path.path.bc[3],
(unsigned char)mod_path.path.bc[4],
(unsigned char)mod_path.path.bc[5]);
pr_cont(".mod = 0x%x ", mod_path.path.mod);
pr_cont(" },\n");
pr_cont("\t.layers = { 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x }\n",
mod_path.layers[0], mod_path.layers[1], mod_path.layers[2],
mod_path.layers[3], mod_path.layers[4], mod_path.layers[5]);
pr_cont(".mod = 0x%x }\n", mod_path.path.mod);
pr_cont("};\n");
pr_info("static struct pdc_iodc iodc_data_hpa_%08lx = {\n", hpa);
@@ -1067,8 +1063,6 @@ static __init int qemu_print_iodc_data(struct device *lin_dev, void *data)
DO(checksum);
DO(length);
#undef DO
pr_cont("\t/* pad: 0x%04x, 0x%04x */\n",
iodc_data.pad[0], iodc_data.pad[1]);
pr_cont("};\n");
pr_info("#define HPA_%08lx_num_addr %d\n", hpa, dev->num_addrs);

View File

@@ -1059,8 +1059,6 @@ ENTRY_CFI(intr_save) /* for os_hpmc */
STREG %r17, PT_IOR(%r29)
#if defined(CONFIG_64BIT)
b,n intr_save2
skip_save_ior:
/* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
* need to adjust iasq/iaoq here in the same way we adjusted isr/ior
@@ -1069,10 +1067,17 @@ skip_save_ior:
bb,COND(>=),n %r8,PSW_W_BIT,intr_save2
LDREG PT_IASQ0(%r29), %r16
LDREG PT_IAOQ0(%r29), %r17
/* adjust iasq/iaoq */
/* adjust iasq0/iaoq0 */
space_adjust %r16,%r17,%r1
STREG %r16, PT_IASQ0(%r29)
STREG %r17, PT_IAOQ0(%r29)
LDREG PT_IASQ1(%r29), %r16
LDREG PT_IAOQ1(%r29), %r17
/* adjust iasq1/iaoq1 */
space_adjust %r16,%r17,%r1
STREG %r16, PT_IASQ1(%r29)
STREG %r17, PT_IAOQ1(%r29)
#else
skip_save_ior:
#endif
@@ -1841,6 +1846,10 @@ syscall_restore_rfi:
extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
depi -1,7,1,%r20 /* T bit */
#ifdef CONFIG_64BIT
extru,<> %r19,TIF_32BIT_PA_BIT,1,%r0
depi -1,4,1,%r20 /* W bit */
#endif
STREG %r20,TASK_PT_PSW(%r1)
/* Always store space registers, since sr3 can be changed (e.g. fork) */
@@ -1854,7 +1863,6 @@ syscall_restore_rfi:
STREG %r25,TASK_PT_IASQ0(%r1)
STREG %r25,TASK_PT_IASQ1(%r1)
/* XXX W bit??? */
/* Now if old D bit is clear, it means we didn't save all registers
* on syscall entry, so do that now. This only happens on TRACEME
* calls, or if someone attached to us while we were on a syscall.

View File

@@ -27,7 +27,7 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
return regs->ior;
case PERF_REG_PARISC_IPSW: /* CR22 */
return regs->ipsw;
};
}
WARN_ON_ONCE((u32)idx >= PERF_REG_PARISC_MAX);
return 0;
}

View File

@@ -154,7 +154,9 @@ static int gsc_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
gsc_dev->eim = ((u32) gsc_dev->gsc_irq.txn_addr) | gsc_dev->gsc_irq.txn_data;
/* switch IRQ's for devices below LASI/WAX to other CPU */
gsc_writel(gsc_dev->eim, gsc_dev->hpa + OFFSET_IAR);
/* ASP chip (svers 0x70) does not support reprogramming */
if (gsc_dev->gsc->id.sversion != 0x70)
gsc_writel(gsc_dev->eim, gsc_dev->hpa + OFFSET_IAR);
irq_data_update_effective_affinity(d, &tmask);