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clk: amlogic: naming consistency alignment

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Amlogic clock controller drivers are all doing the same thing, more or
less. Yet, over the years, tiny (and often pointless) differences have
emerged.

This makes reviews more difficult, allows some errors to slip through and
make it more difficult to exploit SoC commonalities, leading to code
duplication.

This change enforce, wherever possible, a consistent and predictable scheme
when it comes to code organisation and naming, The scheme chosen is what
was used the most already, to try and minimise the size of the ugly
resulting diff. Here are some of the rules applied:
- Aligning clock names, variable names and IDs.
  - ID cannot change (used in DT)
  - Variable names w/ SoC name prefixes
  - Clock names w/o SoC name prefixes, except pclks for historic reasons
- Composite clock systematic naming : mux: X_sel, div:X_div, gate:X
- Parent table systematically named with the same name as the clock and
  a '_parents' suffix
- Group various tables next to the related clock
- etc ...

Doing so removes what would otherwise show up as unrelated diff in
following changes. It will allow to introduce common definitions for
peripheral clocks, probe helpers, composite clocks, etc ... making further
review and maintenance easier.

Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-1-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-2-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-3-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-4-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-5-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-6-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-7-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-8-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-9-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-10-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-11-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-12-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-13-e163c9a1fc21@baylibre.com
Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-14-e163c9a1fc21@baylibre.com
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> # For c3 and s4
[jbrunet: squashed all naming alignment changes together]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet
2025-07-02 17:25:59 +02:00
parent 8f5ae30d69
commit 4c4e17f270
14 changed files with 3564 additions and 3621 deletions
Download Patch File Download Diff File Expand all files Collapse all files

944
drivers/clk/meson/a1-peripherals.c
View File

File diff suppressed because it is too large Load Diff

76
drivers/clk/meson/a1-pll.c
View File

@@ -26,7 +26,7 @@
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
static struct clk_regmap fixed_pll_dco = {
static struct clk_regmap a1_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
.reg_off = ANACTRL_FIXPLL_CTRL0,
@@ -69,7 +69,7 @@ static struct clk_regmap fixed_pll_dco = {
},
};
static struct clk_regmap fixed_pll = {
static struct clk_regmap a1_fixed_pll = {
.data = &(struct clk_regmap_gate_data){
.offset = ANACTRL_FIXPLL_CTRL0,
.bit_idx = 20,
@@ -78,18 +78,18 @@ static struct clk_regmap fixed_pll = {
.name = "fixed_pll",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&fixed_pll_dco.hw
&a1_fixed_pll_dco.hw
},
.num_parents = 1,
},
};
static const struct pll_mult_range hifi_pll_mult_range = {
static const struct pll_mult_range a1_hifi_pll_range = {
.min = 32,
.max = 64,
};
static const struct reg_sequence hifi_init_regs[] = {
static const struct reg_sequence a1_hifi_pll_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 },
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x100a1100 },
@@ -97,7 +97,7 @@ static const struct reg_sequence hifi_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18000 },
};
static struct clk_regmap hifi_pll = {
static struct clk_regmap a1_hifi_pll = {
.data = &(struct meson_clk_pll_data){
.en = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
@@ -134,9 +134,9 @@ static struct clk_regmap hifi_pll = {
.shift = 6,
.width = 1,
},
.range = &hifi_pll_mult_range,
.init_regs = hifi_init_regs,
.init_count = ARRAY_SIZE(hifi_init_regs),
.range = &a1_hifi_pll_range,
.init_regs = a1_hifi_pll_init_regs,
.init_count = ARRAY_SIZE(a1_hifi_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "hifi_pll",
@@ -148,20 +148,20 @@ static struct clk_regmap hifi_pll = {
},
};
static struct clk_fixed_factor fclk_div2_div = {
static struct clk_fixed_factor a1_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
&fixed_pll.hw
&a1_fixed_pll.hw
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div2 = {
static struct clk_regmap a1_fclk_div2 = {
.data = &(struct clk_regmap_gate_data){
.offset = ANACTRL_FIXPLL_CTRL0,
.bit_idx = 21,
@@ -170,7 +170,7 @@ static struct clk_regmap fclk_div2 = {
.name = "fclk_div2",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div2_div.hw
&a1_fclk_div2_div.hw
},
.num_parents = 1,
/*
@@ -186,20 +186,20 @@ static struct clk_regmap fclk_div2 = {
},
};
static struct clk_fixed_factor fclk_div3_div = {
static struct clk_fixed_factor a1_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data){
.name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
&fixed_pll.hw
&a1_fixed_pll.hw
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div3 = {
static struct clk_regmap a1_fclk_div3 = {
.data = &(struct clk_regmap_gate_data){
.offset = ANACTRL_FIXPLL_CTRL0,
.bit_idx = 22,
@@ -208,7 +208,7 @@ static struct clk_regmap fclk_div3 = {
.name = "fclk_div3",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div3_div.hw
&a1_fclk_div3_div.hw
},
.num_parents = 1,
/*
@@ -219,20 +219,20 @@ static struct clk_regmap fclk_div3 = {
},
};
static struct clk_fixed_factor fclk_div5_div = {
static struct clk_fixed_factor a1_fclk_div5_div = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data){
.name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
&fixed_pll.hw
&a1_fixed_pll.hw
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div5 = {
static struct clk_regmap a1_fclk_div5 = {
.data = &(struct clk_regmap_gate_data){
.offset = ANACTRL_FIXPLL_CTRL0,
.bit_idx = 23,
@@ -241,7 +241,7 @@ static struct clk_regmap fclk_div5 = {
.name = "fclk_div5",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div5_div.hw
&a1_fclk_div5_div.hw
},
.num_parents = 1,
/*
@@ -252,20 +252,20 @@ static struct clk_regmap fclk_div5 = {
},
};
static struct clk_fixed_factor fclk_div7_div = {
static struct clk_fixed_factor a1_fclk_div7_div = {
.mult = 1,
.div = 7,
.hw.init = &(struct clk_init_data){
.name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
&fixed_pll.hw
&a1_fixed_pll.hw
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div7 = {
static struct clk_regmap a1_fclk_div7 = {
.data = &(struct clk_regmap_gate_data){
.offset = ANACTRL_FIXPLL_CTRL0,
.bit_idx = 24,
@@ -274,7 +274,7 @@ static struct clk_regmap fclk_div7 = {
.name = "fclk_div7",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div7_div.hw
&a1_fclk_div7_div.hw
},
.num_parents = 1,
},
@@ -282,17 +282,17 @@ static struct clk_regmap fclk_div7 = {
/* Array of all clocks registered by this provider */
static struct clk_hw *a1_pll_hw_clks[] = {
[CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
[CLKID_FIXED_PLL] = &fixed_pll.hw,
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
[CLKID_HIFI_PLL] = &hifi_pll.hw,
[CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw,
[CLKID_FIXED_PLL] = &a1_fixed_pll.hw,
[CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw,
[CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw,
[CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw,
[CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
[CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
[CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
[CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
[CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
};
static const struct regmap_config a1_pll_regmap_cfg = {
@@ -307,7 +307,7 @@ static struct meson_clk_hw_data a1_pll_clks = {
.num = ARRAY_SIZE(a1_pll_hw_clks),
};
static int meson_a1_pll_probe(struct platform_device *pdev)
static int a1_pll_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
void __iomem *base;
@@ -344,7 +344,7 @@ static const struct of_device_id a1_pll_clkc_match_table[] = {
MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table);
static struct platform_driver a1_pll_clkc_driver = {
.probe = meson_a1_pll_probe,
.probe = a1_pll_clkc_probe,
.driver = {
.name = "a1-pll-clkc",
.of_match_table = a1_pll_clkc_match_table,

116
drivers/clk/meson/axg-aoclk.c
View File

@@ -35,7 +35,7 @@
#define AO_RTC_ALT_CLK_CNTL1 0x98
#define AXG_AO_GATE(_name, _bit) \
static struct clk_regmap axg_aoclk_##_name = { \
static struct clk_regmap axg_ao_##_name = { \
.data = &(struct clk_regmap_gate_data) { \
.offset = (AO_RTI_GEN_CNTL_REG0), \
.bit_idx = (_bit), \
@@ -59,7 +59,7 @@ AXG_AO_GATE(uart2, 5);
AXG_AO_GATE(ir_blaster, 6);
AXG_AO_GATE(saradc, 7);
static struct clk_regmap axg_aoclk_cts_oscin = {
static struct clk_regmap axg_ao_cts_oscin = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTI_PWR_CNTL_REG0,
.bit_idx = 14,
@@ -74,7 +74,7 @@ static struct clk_regmap axg_aoclk_cts_oscin = {
},
};
static struct clk_regmap axg_aoclk_32k_pre = {
static struct clk_regmap axg_ao_32k_pre = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 31,
@@ -83,7 +83,7 @@ static struct clk_regmap axg_aoclk_32k_pre = {
.name = "axg_ao_32k_pre",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_cts_oscin.hw
&axg_ao_cts_oscin.hw
},
.num_parents = 1,
},
@@ -99,7 +99,7 @@ static const struct meson_clk_dualdiv_param axg_32k_div_table[] = {
}, {}
};
static struct clk_regmap axg_aoclk_32k_div = {
static struct clk_regmap axg_ao_32k_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_RTC_ALT_CLK_CNTL0,
@@ -132,13 +132,13 @@ static struct clk_regmap axg_aoclk_32k_div = {
.name = "axg_ao_32k_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_32k_pre.hw
&axg_ao_32k_pre.hw
},
.num_parents = 1,
},
};
static struct clk_regmap axg_aoclk_32k_sel = {
static struct clk_regmap axg_ao_32k_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTC_ALT_CLK_CNTL1,
.mask = 0x1,
@@ -149,15 +149,15 @@ static struct clk_regmap axg_aoclk_32k_sel = {
.name = "axg_ao_32k_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_32k_div.hw,
&axg_aoclk_32k_pre.hw,
&axg_ao_32k_div.hw,
&axg_ao_32k_pre.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_aoclk_32k = {
static struct clk_regmap axg_ao_32k = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 30,
@@ -166,14 +166,14 @@ static struct clk_regmap axg_aoclk_32k = {
.name = "axg_ao_32k",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_32k_sel.hw
&axg_ao_32k_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
static struct clk_regmap axg_ao_cts_rtc_oscin = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
@@ -184,7 +184,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
.name = "axg_ao_cts_rtc_oscin",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .hw = &axg_aoclk_32k.hw },
{ .hw = &axg_ao_32k.hw },
{ .fw_name = "ext_32k-0", },
},
.num_parents = 2,
@@ -192,7 +192,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
},
};
static struct clk_regmap axg_aoclk_clk81 = {
static struct clk_regmap axg_ao_clk81 = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
@@ -200,68 +200,74 @@ static struct clk_regmap axg_aoclk_clk81 = {
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
/*
* NOTE: this is one of the infamous clock the pwm driver
* can request directly by its global name. It's wrong but
* there is not much we can do about it until the support
* for the old pwm bindings is dropped
*/
.name = "axg_ao_clk81",
.ops = &clk_regmap_mux_ro_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "mpeg-clk", },
{ .hw = &axg_aoclk_cts_rtc_oscin.hw },
{ .hw = &axg_ao_cts_rtc_oscin.hw },
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_aoclk_saradc_mux = {
static struct clk_regmap axg_ao_saradc_mux = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_SAR_CLK,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "axg_ao_saradc_mux",
.name = "ao_saradc_mux",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &axg_aoclk_clk81.hw },
{ .hw = &axg_ao_clk81.hw },
},
.num_parents = 2,
},
};
static struct clk_regmap axg_aoclk_saradc_div = {
static struct clk_regmap axg_ao_saradc_div = {
.data = &(struct clk_regmap_div_data) {
.offset = AO_SAR_CLK,
.shift = 0,
.width = 8,
},
.hw.init = &(struct clk_init_data){
.name = "axg_ao_saradc_div",
.name = "ao_saradc_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_saradc_mux.hw
&axg_ao_saradc_mux.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_aoclk_saradc_gate = {
static struct clk_regmap axg_ao_saradc_gate = {
.data = &(struct clk_regmap_gate_data) {
.offset = AO_SAR_CLK,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data){
.name = "axg_ao_saradc_gate",
.name = "ao_saradc_gate",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_aoclk_saradc_div.hw
&axg_ao_saradc_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const unsigned int axg_aoclk_reset[] = {
static const unsigned int axg_ao_reset[] = {
[RESET_AO_REMOTE] = 16,
[RESET_AO_I2C_MASTER] = 18,
[RESET_AO_I2C_SLAVE] = 19,
@@ -270,53 +276,53 @@ static const unsigned int axg_aoclk_reset[] = {
[RESET_AO_IR_BLASTER] = 23,
};
static struct clk_hw *axg_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
static struct clk_hw *axg_ao_hw_clks[] = {
[CLKID_AO_REMOTE] = &axg_ao_remote.hw,
[CLKID_AO_I2C_MASTER] = &axg_ao_i2c_master.hw,
[CLKID_AO_I2C_SLAVE] = &axg_ao_i2c_slave.hw,
[CLKID_AO_UART1] = &axg_ao_uart1.hw,
[CLKID_AO_UART2] = &axg_ao_uart2.hw,
[CLKID_AO_IR_BLASTER] = &axg_ao_ir_blaster.hw,
[CLKID_AO_SAR_ADC] = &axg_ao_saradc.hw,
[CLKID_AO_CLK81] = &axg_ao_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &axg_ao_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &axg_ao_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &axg_ao_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &axg_ao_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &axg_ao_32k_pre.hw,
[CLKID_AO_32K_DIV] = &axg_ao_32k_div.hw,
[CLKID_AO_32K_SEL] = &axg_ao_32k_sel.hw,
[CLKID_AO_32K] = &axg_ao_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &axg_ao_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data axg_aoclkc_data = {
static const struct meson_aoclk_data axg_ao_clkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(axg_aoclk_reset),
.reset = axg_aoclk_reset,
.num_reset = ARRAY_SIZE(axg_ao_reset),
.reset = axg_ao_reset,
.hw_clks = {
.hws = axg_aoclk_hw_clks,
.num = ARRAY_SIZE(axg_aoclk_hw_clks),
.hws = axg_ao_hw_clks,
.num = ARRAY_SIZE(axg_ao_hw_clks),
},
};
static const struct of_device_id axg_aoclkc_match_table[] = {
static const struct of_device_id axg_ao_clkc_match_table[] = {
{
.compatible = "amlogic,meson-axg-aoclkc",
.data = &axg_aoclkc_data,
.data = &axg_ao_clkc_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, axg_aoclkc_match_table);
MODULE_DEVICE_TABLE(of, axg_ao_clkc_match_table);
static struct platform_driver axg_aoclkc_driver = {
static struct platform_driver axg_ao_clkc_driver = {
.probe = meson_aoclkc_probe,
.driver = {
.name = "axg-aoclkc",
.of_match_table = axg_aoclkc_match_table,
.name = "axg-ao-clkc",
.of_match_table = axg_ao_clkc_match_table,
},
};
module_platform_driver(axg_aoclkc_driver);
module_platform_driver(axg_ao_clkc_driver);
MODULE_DESCRIPTION("Amlogic AXG Always-ON Clock Controller driver");
MODULE_LICENSE("GPL");

211
drivers/clk/meson/axg.c
View File

@@ -333,7 +333,7 @@ static struct clk_regmap axg_gp0_pll = {
},
};
static const struct reg_sequence axg_hifi_init_regs[] = {
static const struct reg_sequence axg_hifi_pll_init_regs[] = {
{ .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
@@ -374,8 +374,8 @@ static struct clk_regmap axg_hifi_pll_dco = {
.width = 1,
},
.table = axg_gp0_pll_params_table,
.init_regs = axg_hifi_init_regs,
.init_count = ARRAY_SIZE(axg_hifi_init_regs),
.init_regs = axg_hifi_pll_init_regs,
.init_count = ARRAY_SIZE(axg_hifi_pll_init_regs),
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
@@ -780,7 +780,7 @@ static const struct pll_params_table axg_pcie_pll_params_table[] = {
{ /* sentinel */ },
};
static const struct reg_sequence axg_pcie_init_regs[] = {
static const struct reg_sequence axg_pcie_pll_init_regs[] = {
{ .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
@@ -823,8 +823,8 @@ static struct clk_regmap axg_pcie_pll_dco = {
.width = 1,
},
.table = axg_pcie_pll_params_table,
.init_regs = axg_pcie_init_regs,
.init_count = ARRAY_SIZE(axg_pcie_init_regs),
.init_regs = axg_pcie_pll_init_regs,
.init_count = ARRAY_SIZE(axg_pcie_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "pcie_pll_dco",
@@ -935,8 +935,9 @@ static struct clk_regmap axg_pcie_cml_en1 = {
},
};
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const struct clk_parent_data clk81_parent_data[] = {
/* clk81 is often referred as "mpeg_clk" */
static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
static const struct clk_parent_data clk81_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &axg_fclk_div7.hw },
{ .hw = &axg_mpll1.hw },
@@ -946,32 +947,32 @@ static const struct clk_parent_data clk81_parent_data[] = {
{ .hw = &axg_fclk_div5.hw },
};
static struct clk_regmap axg_mpeg_clk_sel = {
static struct clk_regmap axg_clk81_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_MPEG_CLK_CNTL,
.mask = 0x7,
.shift = 12,
.table = mux_table_clk81,
.table = clk81_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.name = "clk81_sel",
.ops = &clk_regmap_mux_ro_ops,
.parent_data = clk81_parent_data,
.num_parents = ARRAY_SIZE(clk81_parent_data),
.parent_data = clk81_parents,
.num_parents = ARRAY_SIZE(clk81_parents),
},
};
static struct clk_regmap axg_mpeg_clk_div = {
static struct clk_regmap axg_clk81_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.name = "clk81_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_mpeg_clk_sel.hw
&axg_clk81_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -987,14 +988,14 @@ static struct clk_regmap axg_clk81 = {
.name = "clk81",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&axg_mpeg_clk_div.hw
&axg_clk81_div.hw
},
.num_parents = 1,
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
},
};
static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
static const struct clk_parent_data axg_sd_emmc_clk0_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &axg_fclk_div2.hw },
{ .hw = &axg_fclk_div3.hw },
@@ -1018,8 +1019,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = axg_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
.parent_data = axg_sd_emmc_clk0_parents,
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1068,8 +1069,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = axg_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
.parent_data = axg_sd_emmc_clk0_parents,
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1110,7 +1111,7 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
/* VPU Clock */
static const struct clk_hw *axg_vpu_parent_hws[] = {
static const struct clk_hw *axg_vpu_parents[] = {
&axg_fclk_div4.hw,
&axg_fclk_div3.hw,
&axg_fclk_div5.hw,
@@ -1126,8 +1127,8 @@ static struct clk_regmap axg_vpu_0_sel = {
.hw.init = &(struct clk_init_data){
.name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_vpu_parent_hws,
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
.parent_hws = axg_vpu_parents,
.num_parents = ARRAY_SIZE(axg_vpu_parents),
/* We need a specific parent for VPU clock source, let it be set in DT */
.flags = CLK_SET_RATE_NO_REPARENT,
},
@@ -1175,8 +1176,8 @@ static struct clk_regmap axg_vpu_1_sel = {
.hw.init = &(struct clk_init_data){
.name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_vpu_parent_hws,
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
.parent_hws = axg_vpu_parents,
.num_parents = ARRAY_SIZE(axg_vpu_parents),
/* We need a specific parent for VPU clock source, let it be set in DT */
.flags = CLK_SET_RATE_NO_REPARENT,
},
@@ -1244,8 +1245,8 @@ static struct clk_regmap axg_vapb_0_sel = {
.hw.init = &(struct clk_init_data){
.name = "vapb_0_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_vpu_parent_hws,
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
.parent_hws = axg_vpu_parents,
.num_parents = ARRAY_SIZE(axg_vpu_parents),
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1292,8 +1293,8 @@ static struct clk_regmap axg_vapb_1_sel = {
.hw.init = &(struct clk_init_data){
.name = "vapb_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_vpu_parent_hws,
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
.parent_hws = axg_vpu_parents,
.num_parents = ARRAY_SIZE(axg_vpu_parents),
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1365,7 +1366,7 @@ static struct clk_regmap axg_vapb = {
/* Video Clocks */
static const struct clk_hw *axg_vclk_parent_hws[] = {
static const struct clk_hw *axg_vclk_parents[] = {
&axg_gp0_pll.hw,
&axg_fclk_div4.hw,
&axg_fclk_div3.hw,
@@ -1384,8 +1385,8 @@ static struct clk_regmap axg_vclk_sel = {
.hw.init = &(struct clk_init_data){
.name = "vclk_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_vclk_parent_hws,
.num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
.parent_hws = axg_vclk_parents,
.num_parents = ARRAY_SIZE(axg_vclk_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -1399,8 +1400,8 @@ static struct clk_regmap axg_vclk2_sel = {
.hw.init = &(struct clk_init_data){
.name = "vclk2_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_vclk_parent_hws,
.num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
.parent_hws = axg_vclk_parents,
.num_parents = ARRAY_SIZE(axg_vclk_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -1739,8 +1740,8 @@ static struct clk_fixed_factor axg_vclk2_div12 = {
},
};
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const struct clk_hw *axg_cts_parent_hws[] = {
static u32 axg_cts_encl_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const struct clk_hw *axg_cts_encl_parents[] = {
&axg_vclk_div1.hw,
&axg_vclk_div2.hw,
&axg_vclk_div4.hw,
@@ -1758,13 +1759,13 @@ static struct clk_regmap axg_cts_encl_sel = {
.offset = HHI_VIID_CLK_DIV,
.mask = 0xf,
.shift = 12,
.table = mux_table_cts_sel,
.table = axg_cts_encl_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "cts_encl_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = axg_cts_parent_hws,
.num_parents = ARRAY_SIZE(axg_cts_parent_hws),
.parent_hws = axg_cts_encl_parents,
.num_parents = ARRAY_SIZE(axg_cts_encl_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -1787,8 +1788,8 @@ static struct clk_regmap axg_cts_encl = {
/* MIPI DSI Host Clock */
static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
static u32 axg_vdin_meas_parents_val_table[] = { 0, 1, 2, 3, 6, 7 };
static const struct clk_parent_data axg_vdin_meas_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &axg_fclk_div4.hw },
{ .hw = &axg_fclk_div3.hw },
@@ -1803,13 +1804,13 @@ static struct clk_regmap axg_vdin_meas_sel = {
.mask = 0x7,
.shift = 21,
.flags = CLK_MUX_ROUND_CLOSEST,
.table = mux_table_axg_vdin_meas,
.table = axg_vdin_meas_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "vdin_meas_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = axg_vdin_meas_parent_data,
.num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
.parent_data = axg_vdin_meas_parents,
.num_parents = ARRAY_SIZE(axg_vdin_meas_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1845,9 +1846,8 @@ static struct clk_regmap axg_vdin_meas = {
},
};
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9, 10, 11, 13, 14, };
static const struct clk_parent_data gen_clk_parent_data[] = {
static u32 gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, };
static const struct clk_parent_data gen_clk_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &axg_hifi_pll.hw },
{ .hw = &axg_mpll0.hw },
@@ -1866,7 +1866,7 @@ static struct clk_regmap axg_gen_clk_sel = {
.offset = HHI_GEN_CLK_CNTL,
.mask = 0xf,
.shift = 12,
.table = mux_table_gen_clk,
.table = gen_clk_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "gen_clk_sel",
@@ -1877,8 +1877,8 @@ static struct clk_regmap axg_gen_clk_sel = {
* hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
*/
.parent_data = gen_clk_parent_data,
.num_parents = ARRAY_SIZE(gen_clk_parent_data),
.parent_data = gen_clk_parents,
.num_parents = ARRAY_SIZE(gen_clk_parents),
},
};
@@ -1915,59 +1915,59 @@ static struct clk_regmap axg_gen_clk = {
},
};
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
#define AXG_PCLK(_name, _reg, _bit) \
MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw)
/* Everything Else (EE) domain gates */
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0);
static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2);
static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3);
static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5);
static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6);
static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7);
static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8);
static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9);
static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12);
static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13);
static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15);
static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16);
static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17);
static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19);
static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23);
static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25);
static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26);
static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27);
static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30);
static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0);
static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3);
static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16);
static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20);
static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21);
static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22);
static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23);
static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26);
static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29);
static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30);
static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31);
static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1);
static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8);
static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9);
static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11);
static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25);
static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30);
/* Always On (AO) domain gates */
static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0);
static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1);
static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2);
static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3);
static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4);
/* Array of all clocks provided by this provider */
@@ -1980,8 +1980,8 @@ static struct clk_hw *axg_hw_clks[] = {
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
[CLKID_MPEG_SEL] = &axg_clk81_sel.hw,
[CLKID_MPEG_DIV] = &axg_clk81_div.hw,
[CLKID_CLK81] = &axg_clk81.hw,
[CLKID_MPLL0] = &axg_mpll0.hw,
[CLKID_MPLL1] = &axg_mpll1.hw,
@@ -2117,21 +2117,20 @@ static const struct meson_eeclkc_data axg_clkc_data = {
},
};
static const struct of_device_id clkc_match_table[] = {
static const struct of_device_id axg_clkc_match_table[] = {
{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
{}
};
MODULE_DEVICE_TABLE(of, clkc_match_table);
MODULE_DEVICE_TABLE(of, axg_clkc_match_table);
static struct platform_driver axg_driver = {
static struct platform_driver axg_clkc_driver = {
.probe = meson_eeclkc_probe,
.driver = {
.name = "axg-clkc",
.of_match_table = clkc_match_table,
.of_match_table = axg_clkc_match_table,
},
};
module_platform_driver(axg_driver);
module_platform_driver(axg_clkc_driver);
MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver");
MODULE_LICENSE("GPL");

1227
drivers/clk/meson/c3-peripherals.c
View File

File diff suppressed because it is too large Load Diff

198
drivers/clk/meson/c3-pll.c
View File

@@ -34,7 +34,7 @@
#define ANACTRL_MPLL_CTRL3 0x18c
#define ANACTRL_MPLL_CTRL4 0x190
static struct clk_regmap fclk_50m_en = {
static struct clk_regmap c3_fclk_50m_en = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 0,
@@ -49,20 +49,20 @@ static struct clk_regmap fclk_50m_en = {
},
};
static struct clk_fixed_factor fclk_50m = {
static struct clk_fixed_factor c3_fclk_50m = {
.mult = 1,
.div = 40,
.hw.init = &(struct clk_init_data) {
.name = "fclk_50m",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_50m_en.hw
&c3_fclk_50m_en.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div2_div = {
static struct clk_fixed_factor c3_fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
@@ -75,7 +75,7 @@ static struct clk_fixed_factor fclk_div2_div = {
},
};
static struct clk_regmap fclk_div2 = {
static struct clk_regmap c3_fclk_div2 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 24,
@@ -84,13 +84,13 @@ static struct clk_regmap fclk_div2 = {
.name = "fclk_div2",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div2_div.hw
&c3_fclk_div2_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div2p5_div = {
static struct clk_fixed_factor c3_fclk_div2p5_div = {
.mult = 2,
.div = 5,
.hw.init = &(struct clk_init_data) {
@@ -103,7 +103,7 @@ static struct clk_fixed_factor fclk_div2p5_div = {
},
};
static struct clk_regmap fclk_div2p5 = {
static struct clk_regmap c3_fclk_div2p5 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 4,
@@ -112,13 +112,13 @@ static struct clk_regmap fclk_div2p5 = {
.name = "fclk_div2p5",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div2p5_div.hw
&c3_fclk_div2p5_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div3_div = {
static struct clk_fixed_factor c3_fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data) {
@@ -131,7 +131,7 @@ static struct clk_fixed_factor fclk_div3_div = {
},
};
static struct clk_regmap fclk_div3 = {
static struct clk_regmap c3_fclk_div3 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 20,
@@ -140,13 +140,13 @@ static struct clk_regmap fclk_div3 = {
.name = "fclk_div3",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div3_div.hw
&c3_fclk_div3_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div4_div = {
static struct clk_fixed_factor c3_fclk_div4_div = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data) {
@@ -159,7 +159,7 @@ static struct clk_fixed_factor fclk_div4_div = {
},
};
static struct clk_regmap fclk_div4 = {
static struct clk_regmap c3_fclk_div4 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 21,
@@ -168,13 +168,13 @@ static struct clk_regmap fclk_div4 = {
.name = "fclk_div4",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div4_div.hw
&c3_fclk_div4_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div5_div = {
static struct clk_fixed_factor c3_fclk_div5_div = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data) {
@@ -187,7 +187,7 @@ static struct clk_fixed_factor fclk_div5_div = {
},
};
static struct clk_regmap fclk_div5 = {
static struct clk_regmap c3_fclk_div5 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 22,
@@ -196,13 +196,13 @@ static struct clk_regmap fclk_div5 = {
.name = "fclk_div5",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div5_div.hw
&c3_fclk_div5_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div7_div = {
static struct clk_fixed_factor c3_fclk_div7_div = {
.mult = 1,
.div = 7,
.hw.init = &(struct clk_init_data) {
@@ -215,7 +215,7 @@ static struct clk_fixed_factor fclk_div7_div = {
},
};
static struct clk_regmap fclk_div7 = {
static struct clk_regmap c3_fclk_div7 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 23,
@@ -224,13 +224,13 @@ static struct clk_regmap fclk_div7 = {
.name = "fclk_div7",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div7_div.hw
&c3_fclk_div7_div.hw
},
.num_parents = 1,
},
};
static const struct reg_sequence c3_gp0_init_regs[] = {
static const struct reg_sequence c3_gp0_pll_init_regs[] = {
{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x0 },
{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
{ .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
@@ -243,7 +243,7 @@ static const struct pll_mult_range c3_gp0_pll_mult_range = {
.max = 250,
};
static struct clk_regmap gp0_pll_dco = {
static struct clk_regmap c3_gp0_pll_dco = {
.data = &(struct meson_clk_pll_data) {
.en = {
.reg_off = ANACTRL_GP0PLL_CTRL0,
@@ -276,8 +276,8 @@ static struct clk_regmap gp0_pll_dco = {
.width = 1,
},
.range = &c3_gp0_pll_mult_range,
.init_regs = c3_gp0_init_regs,
.init_count = ARRAY_SIZE(c3_gp0_init_regs),
.init_regs = c3_gp0_pll_init_regs,
.init_count = ARRAY_SIZE(c3_gp0_pll_init_regs),
},
.hw.init = &(struct clk_init_data) {
.name = "gp0_pll_dco",
@@ -300,7 +300,7 @@ static const struct clk_div_table c3_gp0_pll_od_table[] = {
{ /* sentinel */ }
};
static struct clk_regmap gp0_pll = {
static struct clk_regmap c3_gp0_pll = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_GP0PLL_CTRL0,
.shift = 16,
@@ -311,14 +311,14 @@ static struct clk_regmap gp0_pll = {
.name = "gp0_pll",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&gp0_pll_dco.hw
&c3_gp0_pll_dco.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct reg_sequence c3_hifi_init_regs[] = {
static const struct reg_sequence c3_hifi_pll_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x0 },
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
@@ -326,7 +326,7 @@ static const struct reg_sequence c3_hifi_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 },
};
static struct clk_regmap hifi_pll_dco = {
static struct clk_regmap c3_hifi_pll_dco = {
.data = &(struct meson_clk_pll_data) {
.en = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
@@ -359,8 +359,8 @@ static struct clk_regmap hifi_pll_dco = {
.width = 1,
},
.range = &c3_gp0_pll_mult_range,
.init_regs = c3_hifi_init_regs,
.init_count = ARRAY_SIZE(c3_hifi_init_regs),
.init_regs = c3_hifi_pll_init_regs,
.init_count = ARRAY_SIZE(c3_hifi_pll_init_regs),
.frac_max = 100000,
},
.hw.init = &(struct clk_init_data) {
@@ -373,7 +373,7 @@ static struct clk_regmap hifi_pll_dco = {
},
};
static struct clk_regmap hifi_pll = {
static struct clk_regmap c3_hifi_pll = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_HIFIPLL_CTRL0,
.shift = 16,
@@ -384,14 +384,14 @@ static struct clk_regmap hifi_pll = {
.name = "hifi_pll",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&hifi_pll_dco.hw
&c3_hifi_pll_dco.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct reg_sequence c3_mclk_init_regs[] = {
static const struct reg_sequence c3_mclk_pll_init_regs[] = {
{ .reg = ANACTRL_MPLL_CTRL1, .def = 0x1420500f },
{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x00023041 },
{ .reg = ANACTRL_MPLL_CTRL3, .def = 0x18180000 },
@@ -403,7 +403,7 @@ static const struct pll_mult_range c3_mclk_pll_mult_range = {
.max = 133,
};
static struct clk_regmap mclk_pll_dco = {
static struct clk_regmap c3_mclk_pll_dco = {
.data = &(struct meson_clk_pll_data) {
.en = {
.reg_off = ANACTRL_MPLL_CTRL0,
@@ -431,8 +431,8 @@ static struct clk_regmap mclk_pll_dco = {
.width = 1,
},
.range = &c3_mclk_pll_mult_range,
.init_regs = c3_mclk_init_regs,
.init_count = ARRAY_SIZE(c3_mclk_init_regs),
.init_regs = c3_mclk_pll_init_regs,
.init_count = ARRAY_SIZE(c3_mclk_pll_init_regs),
},
.hw.init = &(struct clk_init_data) {
.name = "mclk_pll_dco",
@@ -444,7 +444,7 @@ static struct clk_regmap mclk_pll_dco = {
},
};
static const struct clk_div_table c3_mpll_od_table[] = {
static const struct clk_div_table c3_mpll_pll_od_table[] = {
{ 0, 1 },
{ 1, 2 },
{ 2, 4 },
@@ -453,25 +453,25 @@ static const struct clk_div_table c3_mpll_od_table[] = {
{ /* sentinel */ }
};
static struct clk_regmap mclk_pll_od = {
static struct clk_regmap c3_mclk_pll_od = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL0,
.shift = 12,
.width = 3,
.table = c3_mpll_od_table,
.table = c3_mpll_pll_od_table,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk_pll_od",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk_pll_dco.hw },
&c3_mclk_pll_dco.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* both value 0 and 1 gives divide the input rate by one */
static struct clk_regmap mclk_pll = {
static struct clk_regmap c3_mclk_pll = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL4,
.shift = 16,
@@ -482,20 +482,20 @@ static struct clk_regmap mclk_pll = {
.name = "mclk_pll",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk_pll_od.hw
&c3_mclk_pll_od.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_parent_data mclk_parent[] = {
{ .hw = &mclk_pll.hw },
static const struct clk_parent_data c3_mclk_parents[] = {
{ .hw = &c3_mclk_pll.hw },
{ .fw_name = "mclk" },
{ .hw = &fclk_50m.hw }
{ .hw = &c3_fclk_50m.hw }
};
static struct clk_regmap mclk0_sel = {
static struct clk_regmap c3_mclk0_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = ANACTRL_MPLL_CTRL4,
.mask = 0x3,
@@ -504,12 +504,12 @@ static struct clk_regmap mclk0_sel = {
.hw.init = &(struct clk_init_data) {
.name = "mclk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = mclk_parent,
.num_parents = ARRAY_SIZE(mclk_parent),
.parent_data = c3_mclk_parents,
.num_parents = ARRAY_SIZE(c3_mclk_parents),
},
};
static struct clk_regmap mclk0_div_en = {
static struct clk_regmap c3_mclk0_div_en = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 1,
@@ -518,14 +518,14 @@ static struct clk_regmap mclk0_div_en = {
.name = "mclk0_div_en",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk0_sel.hw
&c3_mclk0_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk0_div = {
static struct clk_regmap c3_mclk0_div = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL4,
.shift = 2,
@@ -535,14 +535,14 @@ static struct clk_regmap mclk0_div = {
.name = "mclk0_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk0_div_en.hw
&c3_mclk0_div_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk0 = {
static struct clk_regmap c3_mclk0 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 0,
@@ -551,14 +551,14 @@ static struct clk_regmap mclk0 = {
.name = "mclk0",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk0_div.hw
&c3_mclk0_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk1_sel = {
static struct clk_regmap c3_mclk1_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = ANACTRL_MPLL_CTRL4,
.mask = 0x3,
@@ -567,12 +567,12 @@ static struct clk_regmap mclk1_sel = {
.hw.init = &(struct clk_init_data) {
.name = "mclk1_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = mclk_parent,
.num_parents = ARRAY_SIZE(mclk_parent),
.parent_data = c3_mclk_parents,
.num_parents = ARRAY_SIZE(c3_mclk_parents),
},
};
static struct clk_regmap mclk1_div_en = {
static struct clk_regmap c3_mclk1_div_en = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 9,
@@ -581,14 +581,14 @@ static struct clk_regmap mclk1_div_en = {
.name = "mclk1_div_en",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk1_sel.hw
&c3_mclk1_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk1_div = {
static struct clk_regmap c3_mclk1_div = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL4,
.shift = 10,
@@ -598,14 +598,14 @@ static struct clk_regmap mclk1_div = {
.name = "mclk1_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk1_div_en.hw
&c3_mclk1_div_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk1 = {
static struct clk_regmap c3_mclk1 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 8,
@@ -614,7 +614,7 @@ static struct clk_regmap mclk1 = {
.name = "mclk1",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk1_div.hw
&c3_mclk1_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -622,38 +622,38 @@ static struct clk_regmap mclk1 = {
};
static struct clk_hw *c3_pll_hw_clks[] = {
[CLKID_FCLK_50M_EN] = &fclk_50m_en.hw,
[CLKID_FCLK_50M] = &fclk_50m.hw,
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
[CLKID_FCLK_DIV2P5_DIV] = &fclk_div2p5_div.hw,
[CLKID_FCLK_DIV2P5] = &fclk_div2p5.hw,
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
[CLKID_FCLK_DIV4_DIV] = &fclk_div4_div.hw,
[CLKID_FCLK_DIV4] = &fclk_div4.hw,
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
[CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw,
[CLKID_GP0_PLL] = &gp0_pll.hw,
[CLKID_HIFI_PLL_DCO] = &hifi_pll_dco.hw,
[CLKID_HIFI_PLL] = &hifi_pll.hw,
[CLKID_MCLK_PLL_DCO] = &mclk_pll_dco.hw,
[CLKID_MCLK_PLL_OD] = &mclk_pll_od.hw,
[CLKID_MCLK_PLL] = &mclk_pll.hw,
[CLKID_MCLK0_SEL] = &mclk0_sel.hw,
[CLKID_MCLK0_SEL_EN] = &mclk0_div_en.hw,
[CLKID_MCLK0_DIV] = &mclk0_div.hw,
[CLKID_MCLK0] = &mclk0.hw,
[CLKID_MCLK1_SEL] = &mclk1_sel.hw,
[CLKID_MCLK1_SEL_EN] = &mclk1_div_en.hw,
[CLKID_MCLK1_DIV] = &mclk1_div.hw,
[CLKID_MCLK1] = &mclk1.hw
[CLKID_FCLK_50M_EN] = &c3_fclk_50m_en.hw,
[CLKID_FCLK_50M] = &c3_fclk_50m.hw,
[CLKID_FCLK_DIV2_DIV] = &c3_fclk_div2_div.hw,
[CLKID_FCLK_DIV2] = &c3_fclk_div2.hw,
[CLKID_FCLK_DIV2P5_DIV] = &c3_fclk_div2p5_div.hw,
[CLKID_FCLK_DIV2P5] = &c3_fclk_div2p5.hw,
[CLKID_FCLK_DIV3_DIV] = &c3_fclk_div3_div.hw,
[CLKID_FCLK_DIV3] = &c3_fclk_div3.hw,
[CLKID_FCLK_DIV4_DIV] = &c3_fclk_div4_div.hw,
[CLKID_FCLK_DIV4] = &c3_fclk_div4.hw,
[CLKID_FCLK_DIV5_DIV] = &c3_fclk_div5_div.hw,
[CLKID_FCLK_DIV5] = &c3_fclk_div5.hw,
[CLKID_FCLK_DIV7_DIV] = &c3_fclk_div7_div.hw,
[CLKID_FCLK_DIV7] = &c3_fclk_div7.hw,
[CLKID_GP0_PLL_DCO] = &c3_gp0_pll_dco.hw,
[CLKID_GP0_PLL] = &c3_gp0_pll.hw,
[CLKID_HIFI_PLL_DCO] = &c3_hifi_pll_dco.hw,
[CLKID_HIFI_PLL] = &c3_hifi_pll.hw,
[CLKID_MCLK_PLL_DCO] = &c3_mclk_pll_dco.hw,
[CLKID_MCLK_PLL_OD] = &c3_mclk_pll_od.hw,
[CLKID_MCLK_PLL] = &c3_mclk_pll.hw,
[CLKID_MCLK0_SEL] = &c3_mclk0_sel.hw,
[CLKID_MCLK0_SEL_EN] = &c3_mclk0_div_en.hw,
[CLKID_MCLK0_DIV] = &c3_mclk0_div.hw,
[CLKID_MCLK0] = &c3_mclk0.hw,
[CLKID_MCLK1_SEL] = &c3_mclk1_sel.hw,
[CLKID_MCLK1_SEL_EN] = &c3_mclk1_div_en.hw,
[CLKID_MCLK1_DIV] = &c3_mclk1_div.hw,
[CLKID_MCLK1] = &c3_mclk1.hw
};
static const struct regmap_config clkc_regmap_config = {
static const struct regmap_config c3_pll_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
@@ -665,7 +665,7 @@ static struct meson_clk_hw_data c3_pll_clks = {
.num = ARRAY_SIZE(c3_pll_hw_clks),
};
static int c3_pll_probe(struct platform_device *pdev)
static int c3_pll_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
@@ -676,7 +676,7 @@ static int c3_pll_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
regmap = devm_regmap_init_mmio(dev, base, &c3_pll_regmap_cfg);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
@@ -704,14 +704,14 @@ static const struct of_device_id c3_pll_clkc_match_table[] = {
};
MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table);
static struct platform_driver c3_pll_driver = {
.probe = c3_pll_probe,
static struct platform_driver c3_pll_clkc_driver = {
.probe = c3_pll_clkc_probe,
.driver = {
.name = "c3-pll-clkc",
.of_match_table = c3_pll_clkc_match_table,
},
};
module_platform_driver(c3_pll_driver);
module_platform_driver(c3_pll_clkc_driver);
MODULE_DESCRIPTION("Amlogic C3 PLL Clock Controller driver");
MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");

207
drivers/clk/meson/g12a-aoclk.c
View File

@@ -43,8 +43,8 @@
* bootloader. The goal is to remove this flag at some point.
* Actually removing it will require some extensive test to be done safely.
*/
#define AXG_AO_GATE(_name, _reg, _bit) \
static struct clk_regmap g12a_aoclk_##_name = { \
#define G12A_AO_PCLK(_name, _reg, _bit) \
static struct clk_regmap g12a_ao_##_name = { \
.data = &(struct clk_regmap_gate_data) { \
.offset = (_reg), \
.bit_idx = (_bit), \
@@ -60,23 +60,24 @@ static struct clk_regmap g12a_aoclk_##_name = { \
}, \
}
AXG_AO_GATE(ahb, AO_CLK_GATE0, 0);
AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1);
AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2);
AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3);
AXG_AO_GATE(uart, AO_CLK_GATE0, 4);
AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5);
AXG_AO_GATE(uart2, AO_CLK_GATE0, 6);
AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7);
AXG_AO_GATE(saradc, AO_CLK_GATE0, 8);
AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0);
AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1);
AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2);
AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3);
AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4);
AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5);
G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0);
G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1);
G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2);
G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3);
G12A_AO_PCLK(uart, AO_CLK_GATE0, 4);
G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5);
G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6);
G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7);
G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8);
static struct clk_regmap g12a_aoclk_cts_oscin = {
G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0);
G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1);
G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2);
G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3);
G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4);
G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5);
static struct clk_regmap g12a_ao_cts_oscin = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTI_PWR_CNTL_REG0,
.bit_idx = 14,
@@ -103,22 +104,22 @@ static const struct meson_clk_dualdiv_param g12a_32k_div_table[] = {
/* 32k_by_oscin clock */
static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
static struct clk_regmap g12a_ao_32k_by_oscin_pre = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 31,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_pre",
.name = "ao_32k_by_oscin_pre",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cts_oscin.hw
&g12a_ao_cts_oscin.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
static struct clk_regmap g12a_ao_32k_by_oscin_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_RTC_ALT_CLK_CNTL0,
@@ -148,16 +149,16 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
.table = g12a_32k_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_div",
.name = "ao_32k_by_oscin_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_pre.hw
&g12a_ao_32k_by_oscin_pre.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
static struct clk_regmap g12a_ao_32k_by_oscin_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTC_ALT_CLK_CNTL1,
.mask = 0x1,
@@ -165,27 +166,27 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_sel",
.name = "ao_32k_by_oscin_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_div.hw,
&g12a_aoclk_32k_by_oscin_pre.hw,
&g12a_ao_32k_by_oscin_div.hw,
&g12a_ao_32k_by_oscin_pre.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_32k_by_oscin = {
static struct clk_regmap g12a_ao_32k_by_oscin = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 30,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin",
.name = "ao_32k_by_oscin",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_sel.hw
&g12a_ao_32k_by_oscin_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -194,22 +195,22 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin = {
/* cec clock */
static struct clk_regmap g12a_aoclk_cec_pre = {
static struct clk_regmap g12a_ao_cec_pre = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_CEC_CLK_CNTL_REG0,
.bit_idx = 31,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_pre",
.name = "ao_cec_pre",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cts_oscin.hw
&g12a_ao_cts_oscin.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_cec_div = {
static struct clk_regmap g12a_ao_cec_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_CEC_CLK_CNTL_REG0,
@@ -239,16 +240,16 @@ static struct clk_regmap g12a_aoclk_cec_div = {
.table = g12a_32k_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_div",
.name = "ao_cec_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_pre.hw
&g12a_ao_cec_pre.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_cec_sel = {
static struct clk_regmap g12a_ao_cec_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_CEC_CLK_CNTL_REG1,
.mask = 0x1,
@@ -256,34 +257,34 @@ static struct clk_regmap g12a_aoclk_cec_sel = {
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_sel",
.name = "ao_cec_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_div.hw,
&g12a_aoclk_cec_pre.hw,
&g12a_ao_cec_div.hw,
&g12a_ao_cec_pre.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_cec = {
static struct clk_regmap g12a_ao_cec = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_CEC_CLK_CNTL_REG0,
.bit_idx = 30,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec",
.name = "ao_cec",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_sel.hw
&g12a_ao_cec_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
static struct clk_regmap g12a_ao_cts_rtc_oscin = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
@@ -291,10 +292,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cts_rtc_oscin",
.name = "ao_cts_rtc_oscin",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .hw = &g12a_aoclk_32k_by_oscin.hw },
{ .hw = &g12a_ao_32k_by_oscin.hw },
{ .fw_name = "ext-32k-0", },
},
.num_parents = 2,
@@ -302,7 +303,7 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
},
};
static struct clk_regmap g12a_aoclk_clk81 = {
static struct clk_regmap g12a_ao_clk81 = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
@@ -310,68 +311,74 @@ static struct clk_regmap g12a_aoclk_clk81 = {
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
/*
* NOTE: this is one of the infamous clock the pwm driver
* can request directly by its global name. It's wrong but
* there is not much we can do about it until the support
* for the old pwm bindings is dropped
*/
.name = "g12a_ao_clk81",
.ops = &clk_regmap_mux_ro_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "mpeg-clk", },
{ .hw = &g12a_aoclk_cts_rtc_oscin.hw },
{ .hw = &g12a_ao_cts_rtc_oscin.hw },
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_saradc_mux = {
static struct clk_regmap g12a_ao_saradc_mux = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_SAR_CLK,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_mux",
.name = "ao_saradc_mux",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &g12a_aoclk_clk81.hw },
{ .hw = &g12a_ao_clk81.hw },
},
.num_parents = 2,
},
};
static struct clk_regmap g12a_aoclk_saradc_div = {
static struct clk_regmap g12a_ao_saradc_div = {
.data = &(struct clk_regmap_div_data) {
.offset = AO_SAR_CLK,
.shift = 0,
.width = 8,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_div",
.name = "ao_saradc_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_saradc_mux.hw
&g12a_ao_saradc_mux.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_saradc_gate = {
static struct clk_regmap g12a_ao_saradc_gate = {
.data = &(struct clk_regmap_gate_data) {
.offset = AO_SAR_CLK,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_gate",
.name = "ao_saradc_gate",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_saradc_div.hw
&g12a_ao_saradc_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const unsigned int g12a_aoclk_reset[] = {
static const unsigned int g12a_ao_reset[] = {
[RESET_AO_IR_IN] = 16,
[RESET_AO_UART] = 17,
[RESET_AO_I2C_M] = 18,
@@ -381,65 +388,65 @@ static const unsigned int g12a_aoclk_reset[] = {
[RESET_AO_IR_OUT] = 23,
};
static struct clk_hw *g12a_aoclk_hw_clks[] = {
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
static struct clk_hw *g12a_ao_hw_clks[] = {
[CLKID_AO_AHB] = &g12a_ao_ahb.hw,
[CLKID_AO_IR_IN] = &g12a_ao_ir_in.hw,
[CLKID_AO_I2C_M0] = &g12a_ao_i2c_m0.hw,
[CLKID_AO_I2C_S0] = &g12a_ao_i2c_s0.hw,
[CLKID_AO_UART] = &g12a_ao_uart.hw,
[CLKID_AO_PROD_I2C] = &g12a_ao_prod_i2c.hw,
[CLKID_AO_UART2] = &g12a_ao_uart2.hw,
[CLKID_AO_IR_OUT] = &g12a_ao_ir_out.hw,
[CLKID_AO_SAR_ADC] = &g12a_ao_saradc.hw,
[CLKID_AO_MAILBOX] = &g12a_ao_mailbox.hw,
[CLKID_AO_M3] = &g12a_ao_m3.hw,
[CLKID_AO_AHB_SRAM] = &g12a_ao_ahb_sram.hw,
[CLKID_AO_RTI] = &g12a_ao_rti.hw,
[CLKID_AO_M4_FCLK] = &g12a_ao_m4_fclk.hw,
[CLKID_AO_M4_HCLK] = &g12a_ao_m4_hclk.hw,
[CLKID_AO_CLK81] = &g12a_ao_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &g12a_ao_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &g12a_ao_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &g12a_ao_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &g12a_ao_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &g12a_ao_32k_by_oscin_pre.hw,
[CLKID_AO_32K_DIV] = &g12a_ao_32k_by_oscin_div.hw,
[CLKID_AO_32K_SEL] = &g12a_ao_32k_by_oscin_sel.hw,
[CLKID_AO_32K] = &g12a_ao_32k_by_oscin.hw,
[CLKID_AO_CEC_PRE] = &g12a_ao_cec_pre.hw,
[CLKID_AO_CEC_DIV] = &g12a_ao_cec_div.hw,
[CLKID_AO_CEC_SEL] = &g12a_ao_cec_sel.hw,
[CLKID_AO_CEC] = &g12a_ao_cec.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_ao_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data g12a_aoclkc_data = {
static const struct meson_aoclk_data g12a_ao_clkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
.reset = g12a_aoclk_reset,
.num_reset = ARRAY_SIZE(g12a_ao_reset),
.reset = g12a_ao_reset,
.hw_clks = {
.hws = g12a_aoclk_hw_clks,
.num = ARRAY_SIZE(g12a_aoclk_hw_clks),
.hws = g12a_ao_hw_clks,
.num = ARRAY_SIZE(g12a_ao_hw_clks),
},
};
static const struct of_device_id g12a_aoclkc_match_table[] = {
static const struct of_device_id g12a_ao_clkc_match_table[] = {
{
.compatible = "amlogic,meson-g12a-aoclkc",
.data = &g12a_aoclkc_data,
.data = &g12a_ao_clkc_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, g12a_aoclkc_match_table);
MODULE_DEVICE_TABLE(of, g12a_ao_clkc_match_table);
static struct platform_driver g12a_aoclkc_driver = {
static struct platform_driver g12a_ao_clkc_driver = {
.probe = meson_aoclkc_probe,
.driver = {
.name = "g12a-aoclkc",
.of_match_table = g12a_aoclkc_match_table,
.of_match_table = g12a_ao_clkc_match_table,
},
};
module_platform_driver(g12a_aoclkc_driver);
module_platform_driver(g12a_ao_clkc_driver);
MODULE_DESCRIPTION("Amlogic G12A Always-ON Clock Controller driver");
MODULE_LICENSE("GPL");

2008
drivers/clk/meson/g12a.c
View File

File diff suppressed because it is too large Load Diff

104
drivers/clk/meson/gxbb-aoclk.c
View File

@@ -23,14 +23,14 @@
#define AO_RTC_ALT_CLK_CNTL0 0x94
#define AO_RTC_ALT_CLK_CNTL1 0x98
#define GXBB_AO_GATE(_name, _bit) \
static struct clk_regmap _name##_ao = { \
#define GXBB_AO_PCLK(_name, _bit) \
static struct clk_regmap gxbb_ao_##_name = { \
.data = &(struct clk_regmap_gate_data) { \
.offset = AO_RTI_GEN_CNTL_REG0, \
.bit_idx = (_bit), \
}, \
.hw.init = &(struct clk_init_data) { \
.name = #_name "_ao", \
.name = "gxbb_ao_" #_name, \
.ops = &clk_regmap_gate_ops, \
.parent_data = &(const struct clk_parent_data) { \
.fw_name = "mpeg-clk", \
@@ -40,14 +40,14 @@ static struct clk_regmap _name##_ao = { \
}, \
}
GXBB_AO_GATE(remote, 0);
GXBB_AO_GATE(i2c_master, 1);
GXBB_AO_GATE(i2c_slave, 2);
GXBB_AO_GATE(uart1, 3);
GXBB_AO_GATE(uart2, 5);
GXBB_AO_GATE(ir_blaster, 6);
GXBB_AO_PCLK(remote, 0);
GXBB_AO_PCLK(i2c_master, 1);
GXBB_AO_PCLK(i2c_slave, 2);
GXBB_AO_PCLK(uart1, 3);
GXBB_AO_PCLK(uart2, 5);
GXBB_AO_PCLK(ir_blaster, 6);
static struct clk_regmap ao_cts_oscin = {
static struct clk_regmap gxbb_ao_cts_oscin = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTI_PWR_CNTL_REG0,
.bit_idx = 6,
@@ -62,7 +62,7 @@ static struct clk_regmap ao_cts_oscin = {
},
};
static struct clk_regmap ao_32k_pre = {
static struct clk_regmap gxbb_ao_32k_pre = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 31,
@@ -70,7 +70,7 @@ static struct clk_regmap ao_32k_pre = {
.hw.init = &(struct clk_init_data){
.name = "ao_32k_pre",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
.parent_hws = (const struct clk_hw *[]) { &gxbb_ao_cts_oscin.hw },
.num_parents = 1,
},
};
@@ -85,7 +85,7 @@ static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
}, {}
};
static struct clk_regmap ao_32k_div = {
static struct clk_regmap gxbb_ao_32k_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_RTC_ALT_CLK_CNTL0,
@@ -117,12 +117,12 @@ static struct clk_regmap ao_32k_div = {
.hw.init = &(struct clk_init_data){
.name = "ao_32k_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
.parent_hws = (const struct clk_hw *[]) { &gxbb_ao_32k_pre.hw },
.num_parents = 1,
},
};
static struct clk_regmap ao_32k_sel = {
static struct clk_regmap gxbb_ao_32k_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTC_ALT_CLK_CNTL1,
.mask = 0x1,
@@ -133,15 +133,15 @@ static struct clk_regmap ao_32k_sel = {
.name = "ao_32k_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&ao_32k_div.hw,
&ao_32k_pre.hw
&gxbb_ao_32k_div.hw,
&gxbb_ao_32k_pre.hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap ao_32k = {
static struct clk_regmap gxbb_ao_32k = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 30,
@@ -149,13 +149,13 @@ static struct clk_regmap ao_32k = {
.hw.init = &(struct clk_init_data){
.name = "ao_32k",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
.parent_hws = (const struct clk_hw *[]) { &gxbb_ao_32k_sel.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap ao_cts_rtc_oscin = {
static struct clk_regmap gxbb_ao_cts_rtc_oscin = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x7,
@@ -170,14 +170,14 @@ static struct clk_regmap ao_cts_rtc_oscin = {
{ .fw_name = "ext-32k-0", },
{ .fw_name = "ext-32k-1", },
{ .fw_name = "ext-32k-2", },
{ .hw = &ao_32k.hw },
{ .hw = &gxbb_ao_32k.hw },
},
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap ao_clk81 = {
static struct clk_regmap gxbb_ao_clk81 = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
@@ -189,14 +189,14 @@ static struct clk_regmap ao_clk81 = {
.ops = &clk_regmap_mux_ro_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "mpeg-clk", },
{ .hw = &ao_cts_rtc_oscin.hw },
{ .hw = &gxbb_ao_cts_rtc_oscin.hw },
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap ao_cts_cec = {
static struct clk_regmap gxbb_ao_cts_cec = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_CRT_CLK_CNTL1,
.mask = 0x1,
@@ -221,14 +221,14 @@ static struct clk_regmap ao_cts_cec = {
*/
.parent_data = (const struct clk_parent_data []) {
{ .name = "fixme", .index = -1, },
{ .hw = &ao_cts_rtc_oscin.hw },
{ .hw = &gxbb_ao_cts_rtc_oscin.hw },
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static const unsigned int gxbb_aoclk_reset[] = {
static const unsigned int gxbb_ao_reset[] = {
[RESET_AO_REMOTE] = 16,
[RESET_AO_I2C_MASTER] = 18,
[RESET_AO_I2C_SLAVE] = 19,
@@ -237,50 +237,50 @@ static const unsigned int gxbb_aoclk_reset[] = {
[RESET_AO_IR_BLASTER] = 23,
};
static struct clk_hw *gxbb_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &remote_ao.hw,
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
[CLKID_AO_UART1] = &uart1_ao.hw,
[CLKID_AO_UART2] = &uart2_ao.hw,
[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
[CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
[CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
[CLKID_AO_32K_DIV] = &ao_32k_div.hw,
[CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
[CLKID_AO_32K] = &ao_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
[CLKID_AO_CLK81] = &ao_clk81.hw,
static struct clk_hw *gxbb_ao_hw_clks[] = {
[CLKID_AO_REMOTE] = &gxbb_ao_remote.hw,
[CLKID_AO_I2C_MASTER] = &gxbb_ao_i2c_master.hw,
[CLKID_AO_I2C_SLAVE] = &gxbb_ao_i2c_slave.hw,
[CLKID_AO_UART1] = &gxbb_ao_uart1.hw,
[CLKID_AO_UART2] = &gxbb_ao_uart2.hw,
[CLKID_AO_IR_BLASTER] = &gxbb_ao_ir_blaster.hw,
[CLKID_AO_CEC_32K] = &gxbb_ao_cts_cec.hw,
[CLKID_AO_CTS_OSCIN] = &gxbb_ao_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &gxbb_ao_32k_pre.hw,
[CLKID_AO_32K_DIV] = &gxbb_ao_32k_div.hw,
[CLKID_AO_32K_SEL] = &gxbb_ao_32k_sel.hw,
[CLKID_AO_32K] = &gxbb_ao_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &gxbb_ao_cts_rtc_oscin.hw,
[CLKID_AO_CLK81] = &gxbb_ao_clk81.hw,
};
static const struct meson_aoclk_data gxbb_aoclkc_data = {
static const struct meson_aoclk_data gxbb_ao_clkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
.reset = gxbb_aoclk_reset,
.num_reset = ARRAY_SIZE(gxbb_ao_reset),
.reset = gxbb_ao_reset,
.hw_clks = {
.hws = gxbb_aoclk_hw_clks,
.num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
.hws = gxbb_ao_hw_clks,
.num = ARRAY_SIZE(gxbb_ao_hw_clks),
},
};
static const struct of_device_id gxbb_aoclkc_match_table[] = {
static const struct of_device_id gxbb_ao_clkc_match_table[] = {
{
.compatible = "amlogic,meson-gx-aoclkc",
.data = &gxbb_aoclkc_data,
.data = &gxbb_ao_clkc_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table);
MODULE_DEVICE_TABLE(of, gxbb_ao_clkc_match_table);
static struct platform_driver gxbb_aoclkc_driver = {
static struct platform_driver gxbb_ao_clkc_driver = {
.probe = meson_aoclkc_probe,
.driver = {
.name = "gxbb-aoclkc",
.of_match_table = gxbb_aoclkc_match_table,
.of_match_table = gxbb_ao_clkc_match_table,
},
};
module_platform_driver(gxbb_aoclkc_driver);
module_platform_driver(gxbb_ao_clkc_driver);
MODULE_DESCRIPTION("Amlogic GXBB Always-ON Clock Controller driver");
MODULE_LICENSE("GPL");

573
drivers/clk/meson/gxbb.c
View File

@@ -116,70 +116,6 @@
#define HHI_BT656_CLK_CNTL 0x3d4
#define HHI_SAR_CLK_CNTL 0x3d8
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
PLL_PARAMS(32, 1),
PLL_PARAMS(33, 1),
PLL_PARAMS(34, 1),
PLL_PARAMS(35, 1),
PLL_PARAMS(36, 1),
PLL_PARAMS(37, 1),
PLL_PARAMS(38, 1),
PLL_PARAMS(39, 1),
PLL_PARAMS(40, 1),
PLL_PARAMS(41, 1),
PLL_PARAMS(42, 1),
PLL_PARAMS(43, 1),
PLL_PARAMS(44, 1),
PLL_PARAMS(45, 1),
PLL_PARAMS(46, 1),
PLL_PARAMS(47, 1),
PLL_PARAMS(48, 1),
PLL_PARAMS(49, 1),
PLL_PARAMS(50, 1),
PLL_PARAMS(51, 1),
PLL_PARAMS(52, 1),
PLL_PARAMS(53, 1),
PLL_PARAMS(54, 1),
PLL_PARAMS(55, 1),
PLL_PARAMS(56, 1),
PLL_PARAMS(57, 1),
PLL_PARAMS(58, 1),
PLL_PARAMS(59, 1),
PLL_PARAMS(60, 1),
PLL_PARAMS(61, 1),
PLL_PARAMS(62, 1),
{ /* sentinel */ },
};
static const struct pll_params_table gxl_gp0_pll_params_table[] = {
PLL_PARAMS(42, 1),
PLL_PARAMS(43, 1),
PLL_PARAMS(44, 1),
PLL_PARAMS(45, 1),
PLL_PARAMS(46, 1),
PLL_PARAMS(47, 1),
PLL_PARAMS(48, 1),
PLL_PARAMS(49, 1),
PLL_PARAMS(50, 1),
PLL_PARAMS(51, 1),
PLL_PARAMS(52, 1),
PLL_PARAMS(53, 1),
PLL_PARAMS(54, 1),
PLL_PARAMS(55, 1),
PLL_PARAMS(56, 1),
PLL_PARAMS(57, 1),
PLL_PARAMS(58, 1),
PLL_PARAMS(59, 1),
PLL_PARAMS(60, 1),
PLL_PARAMS(61, 1),
PLL_PARAMS(62, 1),
PLL_PARAMS(63, 1),
PLL_PARAMS(64, 1),
PLL_PARAMS(65, 1),
PLL_PARAMS(66, 1),
{ /* sentinel */ },
};
static struct clk_regmap gxbb_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@@ -523,7 +459,42 @@ static struct clk_regmap gxbb_sys_pll = {
},
};
static const struct reg_sequence gxbb_gp0_init_regs[] = {
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
PLL_PARAMS(32, 1),
PLL_PARAMS(33, 1),
PLL_PARAMS(34, 1),
PLL_PARAMS(35, 1),
PLL_PARAMS(36, 1),
PLL_PARAMS(37, 1),
PLL_PARAMS(38, 1),
PLL_PARAMS(39, 1),
PLL_PARAMS(40, 1),
PLL_PARAMS(41, 1),
PLL_PARAMS(42, 1),
PLL_PARAMS(43, 1),
PLL_PARAMS(44, 1),
PLL_PARAMS(45, 1),
PLL_PARAMS(46, 1),
PLL_PARAMS(47, 1),
PLL_PARAMS(48, 1),
PLL_PARAMS(49, 1),
PLL_PARAMS(50, 1),
PLL_PARAMS(51, 1),
PLL_PARAMS(52, 1),
PLL_PARAMS(53, 1),
PLL_PARAMS(54, 1),
PLL_PARAMS(55, 1),
PLL_PARAMS(56, 1),
PLL_PARAMS(57, 1),
PLL_PARAMS(58, 1),
PLL_PARAMS(59, 1),
PLL_PARAMS(60, 1),
PLL_PARAMS(61, 1),
PLL_PARAMS(62, 1),
{ /* sentinel */ },
};
static const struct reg_sequence gxbb_gp0_pll_init_regs[] = {
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
@@ -557,8 +528,8 @@ static struct clk_regmap gxbb_gp0_pll_dco = {
.width = 1,
},
.table = gxbb_gp0_pll_params_table,
.init_regs = gxbb_gp0_init_regs,
.init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
.init_regs = gxbb_gp0_pll_init_regs,
.init_count = ARRAY_SIZE(gxbb_gp0_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco",
@@ -570,7 +541,36 @@ static struct clk_regmap gxbb_gp0_pll_dco = {
},
};
static const struct reg_sequence gxl_gp0_init_regs[] = {
static const struct pll_params_table gxl_gp0_pll_params_table[] = {
PLL_PARAMS(42, 1),
PLL_PARAMS(43, 1),
PLL_PARAMS(44, 1),
PLL_PARAMS(45, 1),
PLL_PARAMS(46, 1),
PLL_PARAMS(47, 1),
PLL_PARAMS(48, 1),
PLL_PARAMS(49, 1),
PLL_PARAMS(50, 1),
PLL_PARAMS(51, 1),
PLL_PARAMS(52, 1),
PLL_PARAMS(53, 1),
PLL_PARAMS(54, 1),
PLL_PARAMS(55, 1),
PLL_PARAMS(56, 1),
PLL_PARAMS(57, 1),
PLL_PARAMS(58, 1),
PLL_PARAMS(59, 1),
PLL_PARAMS(60, 1),
PLL_PARAMS(61, 1),
PLL_PARAMS(62, 1),
PLL_PARAMS(63, 1),
PLL_PARAMS(64, 1),
PLL_PARAMS(65, 1),
PLL_PARAMS(66, 1),
{ /* sentinel */ },
};
static const struct reg_sequence gxl_gp0_pll_init_regs[] = {
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
@@ -611,8 +611,8 @@ static struct clk_regmap gxl_gp0_pll_dco = {
.width = 1,
},
.table = gxl_gp0_pll_params_table,
.init_regs = gxl_gp0_init_regs,
.init_count = ARRAY_SIZE(gxl_gp0_init_regs),
.init_regs = gxl_gp0_pll_init_regs,
.init_count = ARRAY_SIZE(gxl_gp0_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco",
@@ -972,8 +972,9 @@ static struct clk_regmap gxbb_mpll2 = {
},
};
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const struct clk_parent_data clk81_parent_data[] = {
/* clk81 is often referred as "mpeg_clk" */
static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
static const struct clk_parent_data clk81_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &gxbb_fclk_div7.hw },
{ .hw = &gxbb_mpll1.hw },
@@ -983,37 +984,37 @@ static const struct clk_parent_data clk81_parent_data[] = {
{ .hw = &gxbb_fclk_div5.hw },
};
static struct clk_regmap gxbb_mpeg_clk_sel = {
static struct clk_regmap gxbb_clk81_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_MPEG_CLK_CNTL,
.mask = 0x7,
.shift = 12,
.table = mux_table_clk81,
.table = clk81_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.name = "clk81_sel",
.ops = &clk_regmap_mux_ro_ops,
/*
* bits 14:12 selects from 8 possible parents:
* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
* fclk_div4, fclk_div3, fclk_div5
*/
.parent_data = clk81_parent_data,
.num_parents = ARRAY_SIZE(clk81_parent_data),
.parent_data = clk81_parents,
.num_parents = ARRAY_SIZE(clk81_parents),
},
};
static struct clk_regmap gxbb_mpeg_clk_div = {
static struct clk_regmap gxbb_clk81_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.name = "clk81_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&gxbb_mpeg_clk_sel.hw
&gxbb_clk81_sel.hw
},
.num_parents = 1,
},
@@ -1029,7 +1030,7 @@ static struct clk_regmap gxbb_clk81 = {
.name = "clk81",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&gxbb_mpeg_clk_div.hw
&gxbb_clk81_div.hw
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL,
@@ -1094,7 +1095,7 @@ static struct clk_regmap gxbb_sar_adc_clk = {
* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
*/
static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
static const struct clk_parent_data gxbb_mali_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &gxbb_gp0_pll.hw },
{ .hw = &gxbb_mpll2.hw },
@@ -1114,8 +1115,8 @@ static struct clk_regmap gxbb_mali_0_sel = {
.hw.init = &(struct clk_init_data){
.name = "mali_0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_mali_0_1_parent_data,
.num_parents = 8,
.parent_data = gxbb_mali_parents,
.num_parents = ARRAY_SIZE(gxbb_mali_parents),
/*
* Don't request the parent to change the rate because
* all GPU frequencies can be derived from the fclk_*
@@ -1168,8 +1169,8 @@ static struct clk_regmap gxbb_mali_1_sel = {
.hw.init = &(struct clk_init_data){
.name = "mali_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_mali_0_1_parent_data,
.num_parents = 8,
.parent_data = gxbb_mali_parents,
.num_parents = ARRAY_SIZE(gxbb_mali_parents),
/*
* Don't request the parent to change the rate because
* all GPU frequencies can be derived from the fclk_*
@@ -1213,11 +1214,6 @@ static struct clk_regmap gxbb_mali_1 = {
},
};
static const struct clk_hw *gxbb_mali_parent_hws[] = {
&gxbb_mali_0.hw,
&gxbb_mali_1.hw,
};
static struct clk_regmap gxbb_mali = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_MALI_CLK_CNTL,
@@ -1227,29 +1223,35 @@ static struct clk_regmap gxbb_mali = {
.hw.init = &(struct clk_init_data){
.name = "mali",
.ops = &clk_regmap_mux_ops,
.parent_hws = gxbb_mali_parent_hws,
.parent_hws = (const struct clk_hw *[]) {
&gxbb_mali_0.hw,
&gxbb_mali_1.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static u32 gxbb_cts_mclk_parents_val_table[] = { 1, 2, 3 };
static const struct clk_hw *gxbb_cts_mclk_parents[] = {
&gxbb_mpll0.hw,
&gxbb_mpll1.hw,
&gxbb_mpll2.hw,
};
static struct clk_regmap gxbb_cts_amclk_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_AUD_CLK_CNTL,
.mask = 0x3,
.shift = 9,
.table = (u32[]){ 1, 2, 3 },
.table = gxbb_cts_mclk_parents_val_table,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "cts_amclk_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll0.hw,
&gxbb_mpll1.hw,
&gxbb_mpll2.hw,
},
.num_parents = 3,
.parent_hws = gxbb_cts_mclk_parents,
.num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents),
},
};
@@ -1292,18 +1294,14 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = {
.offset = HHI_AUD_CLK_CNTL2,
.mask = 0x3,
.shift = 25,
.table = (u32[]){ 1, 2, 3 },
.table = gxbb_cts_mclk_parents_val_table,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&gxbb_mpll0.hw,
&gxbb_mpll1.hw,
&gxbb_mpll2.hw,
},
.num_parents = 3,
.parent_hws = gxbb_cts_mclk_parents,
.num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents),
},
};
@@ -1368,7 +1366,7 @@ static struct clk_regmap gxbb_cts_i958 = {
* This clock does not exist yet in this controller or the AO one
*/
static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 };
static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
static const struct clk_parent_data gxbb_32k_clk_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &gxbb_fclk_div3.hw },
{ .hw = &gxbb_fclk_div5.hw },
@@ -1380,11 +1378,11 @@ static struct clk_regmap gxbb_32k_clk_sel = {
.mask = 0x3,
.shift = 16,
.table = gxbb_32k_clk_parents_val_table,
},
},
.hw.init = &(struct clk_init_data){
.name = "32k_clk_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_32k_clk_parent_data,
.parent_data = gxbb_32k_clk_parents,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1423,7 +1421,7 @@ static struct clk_regmap gxbb_32k_clk = {
},
};
static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
static const struct clk_parent_data gxbb_sd_emmc_clk0_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &gxbb_fclk_div2.hw },
{ .hw = &gxbb_fclk_div3.hw },
@@ -1447,8 +1445,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
.parent_data = gxbb_sd_emmc_clk0_parents,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1497,8 +1495,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
.parent_data = gxbb_sd_emmc_clk0_parents,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1547,8 +1545,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_sd_emmc_clk0_parent_data,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
.parent_data = gxbb_sd_emmc_clk0_parents,
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1589,7 +1587,7 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
/* VPU Clock */
static const struct clk_hw *gxbb_vpu_parent_hws[] = {
static const struct clk_hw *gxbb_vpu_parents[] = {
&gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
@@ -1609,8 +1607,8 @@ static struct clk_regmap gxbb_vpu_0_sel = {
* bits 9:10 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/
.parent_hws = gxbb_vpu_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
.parent_hws = gxbb_vpu_parents,
.num_parents = ARRAY_SIZE(gxbb_vpu_parents),
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1657,8 +1655,8 @@ static struct clk_regmap gxbb_vpu_1_sel = {
* bits 25:26 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/
.parent_hws = gxbb_vpu_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
.parent_hws = gxbb_vpu_parents,
.num_parents = ARRAY_SIZE(gxbb_vpu_parents),
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1716,7 +1714,7 @@ static struct clk_regmap gxbb_vpu = {
/* VAPB Clock */
static const struct clk_hw *gxbb_vapb_parent_hws[] = {
static const struct clk_hw *gxbb_vapb_parents[] = {
&gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
@@ -1736,8 +1734,8 @@ static struct clk_regmap gxbb_vapb_0_sel = {
* bits 9:10 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/
.parent_hws = gxbb_vapb_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
.parent_hws = gxbb_vapb_parents,
.num_parents = ARRAY_SIZE(gxbb_vapb_parents),
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1788,8 +1786,8 @@ static struct clk_regmap gxbb_vapb_1_sel = {
* bits 25:26 selects from 4 possible parents:
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
*/
.parent_hws = gxbb_vapb_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
.parent_hws = gxbb_vapb_parents,
.num_parents = ARRAY_SIZE(gxbb_vapb_parents),
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1897,7 +1895,7 @@ static struct clk_regmap gxbb_vid_pll_div = {
},
};
static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
static const struct clk_parent_data gxbb_vid_pll_parents[] = {
{ .hw = &gxbb_vid_pll_div.hw },
/*
* Note:
@@ -1922,8 +1920,8 @@ static struct clk_regmap gxbb_vid_pll_sel = {
* bit 18 selects from 2 possible parents:
* vid_pll_div or hdmi_pll
*/
.parent_data = gxbb_vid_pll_parent_data,
.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
.parent_data = gxbb_vid_pll_parents,
.num_parents = ARRAY_SIZE(gxbb_vid_pll_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -1944,7 +1942,7 @@ static struct clk_regmap gxbb_vid_pll = {
},
};
static const struct clk_hw *gxbb_vclk_parent_hws[] = {
static const struct clk_hw *gxbb_vclk_parents[] = {
&gxbb_vid_pll.hw,
&gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
@@ -1968,8 +1966,8 @@ static struct clk_regmap gxbb_vclk_sel = {
* vid_pll, fclk_div4, fclk_div3, fclk_div5,
* vid_pll, fclk_div7, mp1
*/
.parent_hws = gxbb_vclk_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
.parent_hws = gxbb_vclk_parents,
.num_parents = ARRAY_SIZE(gxbb_vclk_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -1988,8 +1986,8 @@ static struct clk_regmap gxbb_vclk2_sel = {
* vid_pll, fclk_div4, fclk_div3, fclk_div5,
* vid_pll, fclk_div7, mp1
*/
.parent_hws = gxbb_vclk_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
.parent_hws = gxbb_vclk_parents,
.num_parents = ARRAY_SIZE(gxbb_vclk_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -2328,8 +2326,8 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = {
},
};
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const struct clk_hw *gxbb_cts_parent_hws[] = {
static u32 gxbb_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const struct clk_hw *gxbb_cts_parents[] = {
&gxbb_vclk_div1.hw,
&gxbb_vclk_div2.hw,
&gxbb_vclk_div4.hw,
@@ -2347,13 +2345,13 @@ static struct clk_regmap gxbb_cts_enci_sel = {
.offset = HHI_VID_CLK_DIV,
.mask = 0xf,
.shift = 28,
.table = mux_table_cts_sel,
.table = gxbb_cts_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "cts_enci_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = gxbb_cts_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
.parent_hws = gxbb_cts_parents,
.num_parents = ARRAY_SIZE(gxbb_cts_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -2363,13 +2361,13 @@ static struct clk_regmap gxbb_cts_encp_sel = {
.offset = HHI_VID_CLK_DIV,
.mask = 0xf,
.shift = 20,
.table = mux_table_cts_sel,
.table = gxbb_cts_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "cts_encp_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = gxbb_cts_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
.parent_hws = gxbb_cts_parents,
.num_parents = ARRAY_SIZE(gxbb_cts_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -2379,50 +2377,13 @@ static struct clk_regmap gxbb_cts_vdac_sel = {
.offset = HHI_VIID_CLK_DIV,
.mask = 0xf,
.shift = 28,
.table = mux_table_cts_sel,
.table = gxbb_cts_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "cts_vdac_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = gxbb_cts_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
/* TOFIX: add support for cts_tcon */
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
&gxbb_vclk_div1.hw,
&gxbb_vclk_div2.hw,
&gxbb_vclk_div4.hw,
&gxbb_vclk_div6.hw,
&gxbb_vclk_div12.hw,
&gxbb_vclk2_div1.hw,
&gxbb_vclk2_div2.hw,
&gxbb_vclk2_div4.hw,
&gxbb_vclk2_div6.hw,
&gxbb_vclk2_div12.hw,
};
static struct clk_regmap gxbb_hdmi_tx_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_HDMI_CLK_CNTL,
.mask = 0xf,
.shift = 16,
.table = mux_table_hdmi_tx_sel,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_tx_sel",
.ops = &clk_regmap_mux_ops,
/*
* bits 31:28 selects from 12 possible parents:
* vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
* cts_tcon
*/
.parent_hws = gxbb_cts_hdmi_tx_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
.parent_hws = gxbb_cts_parents,
.num_parents = ARRAY_SIZE(gxbb_cts_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -2475,6 +2436,43 @@ static struct clk_regmap gxbb_cts_vdac = {
},
};
/* TOFIX: add support for cts_tcon */
static u32 gxbb_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
static const struct clk_hw *gxbb_hdmi_tx_parents[] = {
&gxbb_vclk_div1.hw,
&gxbb_vclk_div2.hw,
&gxbb_vclk_div4.hw,
&gxbb_vclk_div6.hw,
&gxbb_vclk_div12.hw,
&gxbb_vclk2_div1.hw,
&gxbb_vclk2_div2.hw,
&gxbb_vclk2_div4.hw,
&gxbb_vclk2_div6.hw,
&gxbb_vclk2_div12.hw,
};
static struct clk_regmap gxbb_hdmi_tx_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_HDMI_CLK_CNTL,
.mask = 0xf,
.shift = 16,
.table = gxbb_hdmi_tx_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_tx_sel",
.ops = &clk_regmap_mux_ops,
/*
* bits 31:28 selects from 12 possible parents:
* vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
* cts_tcon
*/
.parent_hws = gxbb_hdmi_tx_parents,
.num_parents = ARRAY_SIZE(gxbb_hdmi_tx_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_regmap gxbb_hdmi_tx = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_CNTL2,
@@ -2493,7 +2491,7 @@ static struct clk_regmap gxbb_hdmi_tx = {
/* HDMI Clocks */
static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
static const struct clk_parent_data gxbb_hdmi_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &gxbb_fclk_div4.hw },
{ .hw = &gxbb_fclk_div3.hw },
@@ -2510,8 +2508,8 @@ static struct clk_regmap gxbb_hdmi_sel = {
.hw.init = &(struct clk_init_data){
.name = "hdmi_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_hdmi_parent_data,
.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
.parent_data = gxbb_hdmi_parents,
.num_parents = ARRAY_SIZE(gxbb_hdmi_parents),
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
},
};
@@ -2547,7 +2545,7 @@ static struct clk_regmap gxbb_hdmi = {
/* VDEC clocks */
static const struct clk_hw *gxbb_vdec_parent_hws[] = {
static const struct clk_hw *gxbb_vdec_parents[] = {
&gxbb_fclk_div4.hw,
&gxbb_fclk_div3.hw,
&gxbb_fclk_div5.hw,
@@ -2564,8 +2562,8 @@ static struct clk_regmap gxbb_vdec_1_sel = {
.hw.init = &(struct clk_init_data){
.name = "vdec_1_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = gxbb_vdec_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
.parent_hws = gxbb_vdec_parents,
.num_parents = ARRAY_SIZE(gxbb_vdec_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -2614,8 +2612,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel = {
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = gxbb_vdec_parent_hws,
.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
.parent_hws = gxbb_vdec_parents,
.num_parents = ARRAY_SIZE(gxbb_vdec_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -2654,9 +2652,8 @@ static struct clk_regmap gxbb_vdec_hevc = {
},
};
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
9, 10, 11, 13, 14, };
static const struct clk_parent_data gen_clk_parent_data[] = {
static u32 gxbb_gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, };
static const struct clk_parent_data gxbb_gen_clk_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &gxbb_vdec_1.hw },
{ .hw = &gxbb_vdec_hevc.hw },
@@ -2675,7 +2672,7 @@ static struct clk_regmap gxbb_gen_clk_sel = {
.offset = HHI_GEN_CLK_CNTL,
.mask = 0xf,
.shift = 12,
.table = mux_table_gen_clk,
.table = gxbb_gen_clk_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "gen_clk_sel",
@@ -2686,8 +2683,8 @@ static struct clk_regmap gxbb_gen_clk_sel = {
* vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
*/
.parent_data = gen_clk_parent_data,
.num_parents = ARRAY_SIZE(gen_clk_parent_data),
.parent_data = gxbb_gen_clk_parents,
.num_parents = ARRAY_SIZE(gxbb_gen_clk_parents),
},
};
@@ -2724,100 +2721,100 @@ static struct clk_regmap gxbb_gen_clk = {
},
};
#define MESON_GATE(_name, _reg, _bit) \
#define GXBB_PCLK(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1);
static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5);
static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6);
static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7);
static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8);
static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9);
static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10);
static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12);
static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13);
static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15);
static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17);
static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18);
static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28);
static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30);
static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3);
static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4);
static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15);
static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16);
static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20);
static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21);
static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22);
static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23);
static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24);
static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26);
static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30);
static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12);
static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15);
static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20);
static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21);
static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31);
/* Always On (AO) domain gates */
static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3);
static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4);
/* AIU gates */
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
/* Array of all clocks provided by this provider */
@@ -2831,8 +2828,8 @@ static struct clk_hw *gxbb_hw_clks[] = {
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
[CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw,
[CLKID_MPEG_DIV] = &gxbb_clk81_div.hw,
[CLKID_CLK81] = &gxbb_clk81.hw,
[CLKID_MPLL0] = &gxbb_mpll0.hw,
[CLKID_MPLL1] = &gxbb_mpll1.hw,
@@ -3039,8 +3036,8 @@ static struct clk_hw *gxl_hw_clks[] = {
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
[CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw,
[CLKID_MPEG_DIV] = &gxbb_clk81_div.hw,
[CLKID_CLK81] = &gxbb_clk81.hw,
[CLKID_MPLL0] = &gxbb_mpll0.hw,
[CLKID_MPLL1] = &gxbb_mpll1.hw,
@@ -3251,21 +3248,21 @@ static const struct meson_eeclkc_data gxl_clkc_data = {
},
};
static const struct of_device_id clkc_match_table[] = {
static const struct of_device_id gxbb_clkc_match_table[] = {
{ .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
{ .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
{},
};
MODULE_DEVICE_TABLE(of, clkc_match_table);
MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table);
static struct platform_driver gxbb_driver = {
static struct platform_driver gxbb_clkc_driver = {
.probe = meson_eeclkc_probe,
.driver = {
.name = "gxbb-clkc",
.of_match_table = clkc_match_table,
.of_match_table = gxbb_clkc_match_table,
},
};
module_platform_driver(gxbb_driver);
module_platform_driver(gxbb_clkc_driver);
MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver");
MODULE_LICENSE("GPL");

27
drivers/clk/meson/meson8-ddr.c
View File

@@ -12,6 +12,7 @@
#include "clk-regmap.h"
#include "clk-pll.h"
#include "meson-clkc-utils.h"
#define AM_DDR_PLL_CNTL 0x00
#define AM_DDR_PLL_CNTL1 0x04
@@ -77,15 +78,17 @@ static struct clk_regmap meson8_ddr_pll = {
},
};
static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
.hws = {
[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
},
.num = 2,
static struct clk_hw *meson8_ddr_hw_clks[] = {
[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
};
static const struct regmap_config meson8_ddr_clkc_regmap_config = {
static struct meson_clk_hw_data meson8_ddr_clks = {
.hws = meson8_ddr_hw_clks,
.num = ARRAY_SIZE(meson8_ddr_hw_clks),
};
static const struct regmap_config meson8_ddr_regmap_cfg = {
.reg_bits = 8,
.val_bits = 32,
.reg_stride = 4,
@@ -104,13 +107,13 @@ static int meson8_ddr_clkc_probe(struct platform_device *pdev)
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(&pdev->dev, base,
&meson8_ddr_clkc_regmap_config);
&meson8_ddr_regmap_cfg);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Register all clks */
for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) {
hw = meson8_ddr_clk_hw_onecell_data.hws[i];
for (i = 0; i < meson8_ddr_clks.num; i++) {
hw = meson8_ddr_clks.hws[i];
ret = devm_clk_hw_register(&pdev->dev, hw);
if (ret) {
@@ -119,8 +122,8 @@ static int meson8_ddr_clkc_probe(struct platform_device *pdev)
}
}
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
&meson8_ddr_clk_hw_onecell_data);
return devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get,
&meson8_ddr_clks);
}
static const struct of_device_id meson8_ddr_clkc_match_table[] = {

714
drivers/clk/meson/meson8b.c
View File

File diff suppressed because it is too large Load Diff

746
drivers/clk/meson/s4-peripherals.c
View File

File diff suppressed because it is too large Load Diff

34
drivers/clk/meson/s4-pll.c
View File

@@ -281,7 +281,7 @@ static const struct pll_mult_range s4_gp0_pll_mult_range = {
/*
* Internal gp0 pll emulation configuration parameters
*/
static const struct reg_sequence s4_gp0_init_regs[] = {
static const struct reg_sequence s4_gp0_pll_init_regs[] = {
{ .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
@@ -318,8 +318,8 @@ static struct clk_regmap s4_gp0_pll_dco = {
.width = 1,
},
.range = &s4_gp0_pll_mult_range,
.init_regs = s4_gp0_init_regs,
.init_count = ARRAY_SIZE(s4_gp0_init_regs),
.init_regs = s4_gp0_pll_init_regs,
.init_count = ARRAY_SIZE(s4_gp0_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "gp0_pll_dco",
@@ -353,7 +353,7 @@ static struct clk_regmap s4_gp0_pll = {
/*
* Internal hifi pll emulation configuration parameters
*/
static const struct reg_sequence s4_hifi_init_regs[] = {
static const struct reg_sequence s4_hifi_pll_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
@@ -394,8 +394,8 @@ static struct clk_regmap s4_hifi_pll_dco = {
.width = 1,
},
.range = &s4_gp0_pll_mult_range,
.init_regs = s4_hifi_init_regs,
.init_count = ARRAY_SIZE(s4_hifi_init_regs),
.init_regs = s4_hifi_pll_init_regs,
.init_count = ARRAY_SIZE(s4_hifi_pll_init_regs),
.frac_max = 100000,
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
},
@@ -794,11 +794,11 @@ static struct clk_hw *s4_pll_hw_clks[] = {
[CLKID_MPLL3] = &s4_mpll3.hw,
};
static const struct reg_sequence s4_init_regs[] = {
static const struct reg_sequence s4_pll_init_regs[] = {
{ .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
};
static const struct regmap_config clkc_regmap_config = {
static const struct regmap_config s4_pll_clkc_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
@@ -810,7 +810,7 @@ static struct meson_clk_hw_data s4_pll_clks = {
.num = ARRAY_SIZE(s4_pll_hw_clks),
};
static int meson_s4_pll_probe(struct platform_device *pdev)
static int s4_pll_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
@@ -822,12 +822,12 @@ static int meson_s4_pll_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(base),
"can't ioremap resource\n");
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
regmap = devm_regmap_init_mmio(dev, base, &s4_pll_clkc_regmap_cfg);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"can't init regmap mmio region\n");
ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
ret = regmap_multi_reg_write(regmap, s4_pll_init_regs, ARRAY_SIZE(s4_pll_init_regs));
if (ret)
return dev_err_probe(dev, ret,
"Failed to init registers\n");
@@ -848,22 +848,22 @@ static int meson_s4_pll_probe(struct platform_device *pdev)
&s4_pll_clks);
}
static const struct of_device_id clkc_match_table[] = {
static const struct of_device_id s4_pll_clkc_match_table[] = {
{
.compatible = "amlogic,s4-pll-clkc",
},
{}
};
MODULE_DEVICE_TABLE(of, clkc_match_table);
MODULE_DEVICE_TABLE(of, s4_pll_clkc_match_table);
static struct platform_driver s4_driver = {
.probe = meson_s4_pll_probe,
static struct platform_driver s4_pll_clkc_driver = {
.probe = s4_pll_clkc_probe,
.driver = {
.name = "s4-pll-clkc",
.of_match_table = clkc_match_table,
.of_match_table = s4_pll_clkc_match_table,
},
};
module_platform_driver(s4_driver);
module_platform_driver(s4_pll_clkc_driver);
MODULE_DESCRIPTION("Amlogic S4 PLL Clock Controller driver");
MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");