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arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes

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Address various dt-binding warnings for most of the MDP3 nodes by
adding and removing interrupts and power domains where required.

Also, remove the mediatek,mt8195-mdp3-rdma fallback compatible
from the main MDP3 RDMA node as the two have never really been
fully compatible.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250520104024.3706723-1-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno
2025-05-20 12:40:24 +02:00
parent cfe035d866
commit 4a81656c8e
1 changed files with 31 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

76
arch/arm64/boot/dts/mediatek/mt8188.dtsi
View File

@@ -2243,27 +2243,17 @@
};
dma-controller@14001000 {
compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
compatible = "mediatek,mt8188-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
<&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
<&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
<&vppsys0 CLK_VPP0_WARP0_RELAY>,
<&vppsys0 CLK_VPP0_WARP0_ASYNC>,
<&vppsys0 CLK_VPP02VPP1_RELAY>,
<&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
<&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
<&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>;
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
<&gce0 14 CMDQ_THR_PRIO_1>,
<&gce0 16 CMDQ_THR_PRIO_1>,
<&gce0 21 CMDQ_THR_PRIO_1>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>,
<&vpp_iommu M4U_PORT_L4_MDP_WROT>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>,
<&spm MT8188_POWER_DOMAIN_VPPSYS1>;
<&gce0 21 CMDQ_THR_PRIO_1>,
<&gce0 22 CMDQ_THR_PRIO_1>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
<CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
@@ -2274,7 +2264,6 @@
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
reg = <0 0x14002000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
};
@@ -2282,13 +2271,13 @@
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
reg = <0 0x14004000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
};
display@14005000 {
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
reg = <0 0x14005000 0 0x1000>;
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -2298,21 +2287,22 @@
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
reg = <0 0x14006000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
<CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
};
display@14007000 {
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
reg = <0 0x14007000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
};
display@14008000 {
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
@@ -2321,9 +2311,11 @@
display@14009000 {
compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
};
display@1400a000 {
@@ -2338,13 +2330,13 @@
compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
reg = <0 0x1400b000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
};
display@1400c000 {
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
reg = <0 0x1400c000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
@@ -2394,14 +2386,11 @@
};
dma-controller@14f09000 {
compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
compatible = "mediatek,mt8188-mdp3-rdma";
reg = <0 0x14f09000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>,
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
<&topckgen CLK_TOP_CFGREG_F26M_VPP1>;
iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>,
<&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
@@ -2409,14 +2398,11 @@
};
dma-controller@14f0a000 {
compatible = "mediatek,mt8188-mdp3-rdma", "mediatek,mt8195-mdp3-rdma";
compatible = "mediatek,mt8188-mdp3-rdma";
reg = <0 0x14f0a000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>,
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
<&topckgen CLK_TOP_CFGREG_F26M_VPP1>;
iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>,
<&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
@@ -2427,7 +2413,6 @@
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
reg = <0 0x14f0c000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
};
@@ -2435,7 +2420,6 @@
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
reg = <0 0x14f0d000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
};
@@ -2443,7 +2427,6 @@
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
reg = <0 0x14f0f000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
};
@@ -2451,13 +2434,13 @@
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
reg = <0 0x14f10000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
};
display@14f12000 {
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
reg = <0 0x14f12000 0 0x1000>;
interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
@@ -2466,6 +2449,7 @@
display@14f13000 {
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
reg = <0 0x14f13000 0 0x1000>;
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
@@ -2474,26 +2458,25 @@
display@14f15000 {
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
reg = <0 0x14f15000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>,
<&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
<CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
};
display@14f16000 {
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
reg = <0 0x14f16000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>,
<&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
<CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
};
display@14f18000 {
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
reg = <0 0x14f18000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
};
@@ -2501,7 +2484,6 @@
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
reg = <0 0x14f19000 0 0x1000>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
};
@@ -2524,6 +2506,7 @@
display@14f1d000 {
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
reg = <0 0x14f1d000 0 0x1000>;
interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
@@ -2532,6 +2515,7 @@
display@14f1e000 {
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
reg = <0 0x14f1e000 0 0x1000>;
interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
@@ -2558,6 +2542,7 @@
display@14f24000 {
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14f24000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
@@ -2569,6 +2554,7 @@
display@14f25000 {
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14f25000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;