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arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1

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On RZ/G2LC SMARC EVK, CAN0 is not populated.

CAN1 is multiplexed with SCIF1 using SW1[3] or RSPI using SW1[4].

This patch adds support for the CAN1 interface on RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
2022-02-03 17:06:36 +00:00
committed by Geert Uytterhoeven
parent fa00d6dc19
commit 46da632734
3 changed files with 36 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
View File

@@ -14,12 +14,6 @@
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;

23
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
View File

@@ -17,6 +17,14 @@
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
#if SW_SCIF_CAN
/* SW8 should be at position 2->1 */
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
};
#endif
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
@@ -24,6 +32,21 @@
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb {
gpio-hog;
gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can1_stb";
};
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */
<RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
};
#endif
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;

13
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View File

@@ -44,6 +44,19 @@
};
};
#if (SW_SCIF_CAN || SW_RSPI_CAN)
&canfd {
pinctrl-0 = <&can1_pins>;
/delete-node/ channel@0;
};
#else
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
#endif
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated