admin/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2025-12-07 20:06:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: ti: Introduce J742S2 SoC family

Browse Source 
This device is a subset of J784S4 and shares the same memory map and
thus the nodes are being reused from J784S4 to avoid duplication.

Here are some of the salient features of the J742S2 automotive grade
application processor:

The J742S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive, ADAS and industrial
applications requiring AI at the network edge. This SoC extends the K3
Jacinto 7 family of SoCs with focus on raising performance and
integration while providing interfaces, memory architecture and compute
performance for multi-sensor, high concurrency applications.

Some changes that this devices has from J784S4 are:
* 4x Cortex-A72 vs 8x Cortex-A72
* 3x C7x DSP vs 4x C7x DSP
* 4 port ethernet switch vs 8 port ethernet switch

( Refer Table 2-1 for Device comparison with J7AHP )

Link: https://www.ti.com/lit/pdf/spruje3 (TRM)
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-4-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Manorit Chawdhry
2024-09-02 17:56:52 +05:30
committed by Vignesh Raghavendra
parent 9c65033884
commit 38fd90a3e1
2 changed files with 143 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi Normal file
View File

@@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J742S2 SoC Family
*
* TRM: https://www.ti.com/lit/pdf/spruje3
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*
*/
&c71_0 {
firmware-name = "j742s2-c71_0-fw";
};
&c71_1 {
firmware-name = "j742s2-c71_1-fw";
};
&c71_2 {
firmware-name = "j742s2-c71_2-fw";
};
&main_r5fss0_core0 {
firmware-name = "j742s2-main-r5f0_0-fw";
};
&main_r5fss0_core1 {
firmware-name = "j742s2-main-r5f0_1-fw";
};
&main_r5fss1_core0 {
firmware-name = "j742s2-main-r5f1_0-fw";
};
&main_r5fss1_core1 {
firmware-name = "j742s2-main-r5f1_1-fw";
};
&main_r5fss2_core0 {
firmware-name = "j742s2-main-r5f2_0-fw";
};
&main_r5fss2_core1 {
firmware-name = "j742s2-main-r5f2_1-fw";
};

98
arch/arm64/boot/dts/ti/k3-j742s2.dtsi Normal file
View File

@@ -0,0 +1,98 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J742S2 SoC Family
*
* TRM: https://www.ti.com/lit/pdf/spruje3
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*
*/
#include "k3-j784s4-j742s2-common.dtsi"
/ {
model = "Texas Instruments K3 J742S2 SoC";
compatible = "ti,j742s2";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a72";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a72";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a72";
reg = <0x002>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a72";
reg = <0x003>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
};
};
#include "k3-j742s2-main.dtsi"