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Merge tag 'v5.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

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Pull Rockchip clk driver updates from Heiko Stuebner:

 - Reduce memory footprint of PLL rate tables
 - A fix for the newly added rk3568 clk driver
 - exported clock for the newly added video decoder

* tag 'v5.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: export ACLK_VCODEC for RK3036
  clk: rockchip: fix rk3568 cpll clk gate bits
  clk: rockchip: Optimize PLL table memory usage
This commit is contained in:
Stephen Boyd
2021-06-21 16:43:07 -07:00
parent 6efb943b86 2adafc0512
commit 14de023dc0
3 changed files with 28 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/rockchip/clk-rk3036.c
View File

@@ -259,7 +259,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(1), 13, GFLAGS, RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3036_uart2_fracmux), &rk3036_uart2_fracmux),
COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS), RK2928_CLKGATE_CON(3), 11, GFLAGS),
FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,

18
drivers/clk/rockchip/clk-rk3568.c
View File

@@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 10, GFLAGS), RK3568_CLKGATE_CON(35), 10, GFLAGS),
COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 11, GFLAGS),
COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 12, GFLAGS),
COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 13, GFLAGS),
COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 11, GFLAGS),
COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 12, GFLAGS),
COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 13, GFLAGS),
COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 14, GFLAGS), RK3568_CLKGATE_CON(35), 14, GFLAGS),
COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,

7
drivers/clk/rockchip/clk.h
View File

@@ -271,10 +271,15 @@ struct rockchip_clk_provider {
struct rockchip_pll_rate_table { struct rockchip_pll_rate_table {
unsigned long rate; unsigned long rate;
union {
struct {
/* for RK3066 */
unsigned int nr; unsigned int nr;
unsigned int nf; unsigned int nf;
unsigned int no; unsigned int no;
unsigned int nb; unsigned int nb;
};
struct {
/* for RK3036/RK3399 */ /* for RK3036/RK3399 */
unsigned int fbdiv; unsigned int fbdiv;
unsigned int postdiv1; unsigned int postdiv1;
@@ -282,6 +287,8 @@ struct rockchip_pll_rate_table {
unsigned int postdiv2; unsigned int postdiv2;
unsigned int dsmpd; unsigned int dsmpd;
unsigned int frac; unsigned int frac;
};
};
}; };
/** /**