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spi: add support for microchip "soft" spi controller
Introduce driver support for the Microchip FPGA CoreSPI IP. This driver supports only Motorola SPI mode and frame size of 8-bits. TI/NSC modes and wider frame sizes are not currently supported. Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251114104545.284765-4-prajna.rajendrakumar@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Prajna Rajendra Kumar
committed by
Mark Brown
Mark Brown
parent
8ce9a2ed15
commit
059f545832
@@ -715,6 +715,15 @@ config SPI_MICROCHIP_CORE_QSPI
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PolarFire SoC.
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If built as a module, it will be called spi-microchip-core-qspi.
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config SPI_MICROCHIP_CORE_SPI
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tristate "Microchip FPGA CoreSPI controller"
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depends on SPI_MASTER
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help
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This enables the SPI driver for Microchip FPGA CoreSPI controller.
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Say Y or M here if you want to use the "soft" controllers on
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PolarFire SoC.
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If built as a module, it will be called spi-microchip-core-spi.
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config SPI_MT65XX
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tristate "MediaTek SPI controller"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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@@ -87,6 +87,7 @@ obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
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obj-$(CONFIG_SPI_MESON_SPICC) += spi-meson-spicc.o
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obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
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obj-$(CONFIG_SPI_MICROCHIP_CORE_QSPI) += spi-microchip-core-qspi.o
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obj-$(CONFIG_SPI_MICROCHIP_CORE_SPI) += spi-microchip-core-spi.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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442
drivers/spi/spi-microchip-core-spi.c
Normal file
442
drivers/spi/spi-microchip-core-spi.c
Normal file
@@ -0,0 +1,442 @@
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// SPDX-License-Identifier: (GPL-2.0)
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//
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// Microchip CoreSPI controller driver
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//
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// Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries
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//
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// Author: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define MCHP_CORESPI_MAX_CS (8)
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#define MCHP_CORESPI_DEFAULT_FIFO_DEPTH (4)
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#define MCHP_CORESPI_DEFAULT_MOTOROLA_MODE (3)
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#define MCHP_CORESPI_CONTROL_ENABLE BIT(0)
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#define MCHP_CORESPI_CONTROL_MASTER BIT(1)
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#define MCHP_CORESPI_CONTROL_TX_DATA_INT BIT(3)
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#define MCHP_CORESPI_CONTROL_RX_OVER_INT BIT(4)
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#define MCHP_CORESPI_CONTROL_TX_UNDER_INT BIT(5)
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#define MCHP_CORESPI_CONTROL_FRAMEURUN BIT(6)
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#define MCHP_CORESPI_CONTROL_OENOFF BIT(7)
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#define MCHP_CORESPI_STATUS_ACTIVE BIT(7)
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#define MCHP_CORESPI_STATUS_SSEL BIT(6)
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#define MCHP_CORESPI_STATUS_TXFIFO_UNDERFLOW BIT(5)
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#define MCHP_CORESPI_STATUS_RXFIFO_FULL BIT(4)
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#define MCHP_CORESPI_STATUS_TXFIFO_FULL BIT(3)
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#define MCHP_CORESPI_STATUS_RXFIFO_EMPTY BIT(2)
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#define MCHP_CORESPI_STATUS_DONE BIT(1)
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#define MCHP_CORESPI_STATUS_FIRSTFRAME BIT(0)
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#define MCHP_CORESPI_INT_TXDONE BIT(0)
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#define MCHP_CORESPI_INT_RX_CHANNEL_OVERFLOW BIT(2)
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#define MCHP_CORESPI_INT_TX_CHANNEL_UNDERRUN BIT(3)
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#define MCHP_CORESPI_INT_CMDINT BIT(4)
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#define MCHP_CORESPI_INT_SSEND BIT(5)
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#define MCHP_CORESPI_INT_DATA_RX BIT(6)
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#define MCHP_CORESPI_INT_TXRFM BIT(7)
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#define MCHP_CORESPI_CONTROL2_INTEN_TXRFMT BIT(7)
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#define MCHP_CORESPI_CONTROL2_INTEN_DATA_RX BIT(6)
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#define MCHP_CORESPI_CONTROL2_INTEN_SSEND BIT(5)
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#define MCHP_CORESPI_CONTROL2_INTEN_CMD BIT(4)
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#define INT_ENABLE_MASK (MCHP_CORESPI_CONTROL_TX_DATA_INT | MCHP_CORESPI_CONTROL_RX_OVER_INT | \
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MCHP_CORESPI_CONTROL_TX_UNDER_INT)
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#define MCHP_CORESPI_REG_CONTROL (0x00)
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#define MCHP_CORESPI_REG_INTCLEAR (0x04)
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#define MCHP_CORESPI_REG_RXDATA (0x08)
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#define MCHP_CORESPI_REG_TXDATA (0x0c)
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#define MCHP_CORESPI_REG_INTMASK (0X10)
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#define MCHP_CORESPI_REG_INTRAW (0X14)
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#define MCHP_CORESPI_REG_CONTROL2 (0x18)
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#define MCHP_CORESPI_REG_COMMAND (0x1c)
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#define MCHP_CORESPI_REG_STAT (0x20)
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#define MCHP_CORESPI_REG_SSEL (0x24)
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#define MCHP_CORESPI_REG_TXDATA_LAST (0X28)
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#define MCHP_CORESPI_REG_CLK_DIV (0x2c)
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struct mchp_corespi {
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void __iomem *regs;
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struct clk *clk;
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const u8 *tx_buf;
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u8 *rx_buf;
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u32 clk_gen;
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int irq;
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int tx_len;
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int rx_len;
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u32 fifo_depth;
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};
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static inline void mchp_corespi_disable(struct mchp_corespi *spi)
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{
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u8 control = readb(spi->regs + MCHP_CORESPI_REG_CONTROL);
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control &= ~MCHP_CORESPI_CONTROL_ENABLE;
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writeb(control, spi->regs + MCHP_CORESPI_REG_CONTROL);
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}
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static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi, u32 fifo_max)
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{
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for (int i = 0; i < fifo_max; i++) {
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u32 data;
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while (readb(spi->regs + MCHP_CORESPI_REG_STAT) &
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MCHP_CORESPI_STATUS_RXFIFO_EMPTY)
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;
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data = readb(spi->regs + MCHP_CORESPI_REG_RXDATA);
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spi->rx_len--;
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if (!spi->rx_buf)
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continue;
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*spi->rx_buf = data;
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spi->rx_buf++;
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}
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}
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static void mchp_corespi_enable_ints(struct mchp_corespi *spi)
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{
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u8 control = readb(spi->regs + MCHP_CORESPI_REG_CONTROL);
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control |= INT_ENABLE_MASK;
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writeb(control, spi->regs + MCHP_CORESPI_REG_CONTROL);
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}
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static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
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{
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u8 control = readb(spi->regs + MCHP_CORESPI_REG_CONTROL);
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control &= ~INT_ENABLE_MASK;
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writeb(control, spi->regs + MCHP_CORESPI_REG_CONTROL);
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}
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static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32 fifo_max)
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{
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int i = 0;
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while ((i < fifo_max) &&
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!(readb(spi->regs + MCHP_CORESPI_REG_STAT) &
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MCHP_CORESPI_STATUS_TXFIFO_FULL)) {
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u32 word;
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word = spi->tx_buf ? *spi->tx_buf : 0xaa;
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writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA);
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if (spi->tx_buf)
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spi->tx_buf++;
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i++;
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}
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spi->tx_len -= i;
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}
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static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
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{
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struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
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u32 reg;
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reg = readb(corespi->regs + MCHP_CORESPI_REG_SSEL);
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reg &= ~BIT(spi_get_chipselect(spi, 0));
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reg |= !disable << spi_get_chipselect(spi, 0);
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writeb(reg, corespi->regs + MCHP_CORESPI_REG_SSEL);
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}
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static int mchp_corespi_setup(struct spi_device *spi)
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{
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u32 dev_mode = spi->mode & (SPI_CPOL | SPI_CPHA);
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if (spi_get_csgpiod(spi, 0))
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return 0;
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if (spi->mode & (SPI_CS_HIGH)) {
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dev_err(&spi->dev, "unable to support active-high CS in Motorola mode\n");
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return -EOPNOTSUPP;
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}
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if (dev_mode & ~spi->controller->mode_bits) {
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dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Motorola mode\n");
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return -EINVAL;
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}
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return 0;
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}
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static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi)
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{
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u8 control = readb(spi->regs + MCHP_CORESPI_REG_CONTROL);
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/* Master mode changes require core to be disabled.*/
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control = (control & ~MCHP_CORESPI_CONTROL_ENABLE) | MCHP_CORESPI_CONTROL_MASTER;
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writeb(control, spi->regs + MCHP_CORESPI_REG_CONTROL);
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mchp_corespi_enable_ints(spi);
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control = readb(spi->regs + MCHP_CORESPI_REG_CONTROL);
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control |= MCHP_CORESPI_CONTROL_ENABLE;
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writeb(control, spi->regs + MCHP_CORESPI_REG_CONTROL);
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}
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static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
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{
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struct spi_controller *host = dev_id;
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struct mchp_corespi *spi = spi_controller_get_devdata(host);
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u8 intfield = readb(spi->regs + MCHP_CORESPI_REG_INTMASK) & 0xff;
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bool finalise = false;
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/* Interrupt line may be shared and not for us at all */
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if (intfield == 0)
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return IRQ_NONE;
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if (intfield & MCHP_CORESPI_INT_TXDONE)
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writeb(MCHP_CORESPI_INT_TXDONE, spi->regs + MCHP_CORESPI_REG_INTCLEAR);
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if (intfield & MCHP_CORESPI_INT_RX_CHANNEL_OVERFLOW) {
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writeb(MCHP_CORESPI_INT_RX_CHANNEL_OVERFLOW,
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spi->regs + MCHP_CORESPI_REG_INTCLEAR);
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finalise = true;
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dev_err(&host->dev,
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"RX OVERFLOW: rxlen: %d, txlen: %d\n",
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spi->rx_len, spi->tx_len);
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}
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if (intfield & MCHP_CORESPI_INT_TX_CHANNEL_UNDERRUN) {
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writeb(MCHP_CORESPI_INT_TX_CHANNEL_UNDERRUN,
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spi->regs + MCHP_CORESPI_REG_INTCLEAR);
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finalise = true;
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dev_err(&host->dev,
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"TX UNDERFLOW: rxlen: %d, txlen: %d\n",
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spi->rx_len, spi->tx_len);
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}
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if (finalise)
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spi_finalize_current_transfer(host);
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return IRQ_HANDLED;
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}
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static int mchp_corespi_set_clk_div(struct mchp_corespi *spi,
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unsigned long target_hz)
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{
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unsigned long pclk_hz, spi_hz;
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u32 clk_div;
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/* Get peripheral clock rate */
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pclk_hz = clk_get_rate(spi->clk);
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if (!pclk_hz)
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return -EINVAL;
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/*
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* Calculate clock rate generated by SPI master
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* Formula: SPICLK = PCLK / (2 * (CLK_DIV + 1))
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*/
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clk_div = DIV_ROUND_UP(pclk_hz, 2 * target_hz) - 1;
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if (clk_div > 0xFF)
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return -EINVAL;
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spi_hz = pclk_hz / (2 * (clk_div + 1));
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if (spi_hz > target_hz)
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return -EINVAL;
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writeb(clk_div, spi->regs + MCHP_CORESPI_REG_CLK_DIV);
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return 0;
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}
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static int mchp_corespi_transfer_one(struct spi_controller *host,
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struct spi_device *spi_dev,
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struct spi_transfer *xfer)
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{
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struct mchp_corespi *spi = spi_controller_get_devdata(host);
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int ret;
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ret = mchp_corespi_set_clk_div(spi, (unsigned long)xfer->speed_hz);
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if (ret) {
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dev_err(&host->dev, "failed to set clock divider for target %u Hz\n",
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xfer->speed_hz);
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return ret;
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}
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spi->tx_buf = xfer->tx_buf;
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spi->rx_buf = xfer->rx_buf;
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spi->tx_len = xfer->len;
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spi->rx_len = xfer->len;
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while (spi->tx_len) {
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int fifo_max = min_t(int, spi->tx_len, spi->fifo_depth);
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mchp_corespi_write_fifo(spi, fifo_max);
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mchp_corespi_read_fifo(spi, fifo_max);
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}
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spi_finalize_current_transfer(host);
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return 1;
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}
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static int mchp_corespi_probe(struct platform_device *pdev)
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{
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struct spi_controller *host;
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struct mchp_corespi *spi;
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struct resource *res;
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const char *protocol;
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u32 num_cs, mode, frame_size;
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bool assert_ssel;
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int ret = 0;
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host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
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if (!host)
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return dev_err_probe(&pdev->dev, -ENOMEM,
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"unable to allocate host for SPI controller\n");
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platform_set_drvdata(pdev, host);
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if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
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num_cs = MCHP_CORESPI_MAX_CS;
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/*
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* Protocol: CFG_MODE
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* CoreSPI can be configured for Motorola, TI or NSC.
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* The current driver supports only Motorola mode.
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*/
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ret = of_property_read_string(pdev->dev.of_node, "microchip,protocol-configuration",
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&protocol);
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if (strcmp(protocol, "motorola") != 0)
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return dev_err_probe(&pdev->dev, -EINVAL,
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"CoreSPI: protocol '%s' not supported by this driver\n",
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protocol);
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/*
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* Motorola mode (0-3): CFG_MOT_MODE
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* Mode is fixed in the IP configurator.
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*/
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ret = of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode", &mode);
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if (ret)
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mode = MCHP_CORESPI_DEFAULT_MOTOROLA_MODE;
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else if (mode > 3)
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return dev_err_probe(&pdev->dev, -EINVAL,
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"invalid 'microchip,motorola-mode' value %u\n", mode);
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/*
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* Frame size: CFG_FRAME_SIZE
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* The hardware allows frame sizes <= APB data width.
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* However, this driver currently only supports 8-bit frames.
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*/
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ret = of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &frame_size);
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if (!ret && frame_size != 8)
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return dev_err_probe(&pdev->dev, -EINVAL,
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"CoreSPI: frame size %u not supported by this driver\n",
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frame_size);
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/*
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* SSEL: CFG_MOT_SSEL
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* CoreSPI deasserts SSEL when the TX FIFO empties.
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* To prevent CS deassertion when TX FIFO drains, the ssel-active property
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* keeps CS asserted for the full SPI transfer.
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*/
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assert_ssel = of_property_read_bool(pdev->dev.of_node, "microchip,ssel-active");
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if (!assert_ssel)
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return dev_err_probe(&pdev->dev, -EINVAL,
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"hardware must enable 'microchip,ssel-active' to keep CS asserted for the SPI transfer\n");
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spi = spi_controller_get_devdata(host);
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host->num_chipselect = num_cs;
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host->mode_bits = mode;
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host->setup = mchp_corespi_setup;
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host->use_gpio_descriptors = true;
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host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
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host->transfer_one = mchp_corespi_transfer_one;
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host->set_cs = mchp_corespi_set_cs;
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host->dev.of_node = pdev->dev.of_node;
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ret = of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_depth);
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if (ret)
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spi->fifo_depth = MCHP_CORESPI_DEFAULT_FIFO_DEPTH;
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spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(spi->regs))
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return PTR_ERR(spi->regs);
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spi->irq = platform_get_irq(pdev, 0);
|
||||
if (spi->irq < 0)
|
||||
return spi->irq;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
|
||||
IRQF_SHARED, dev_name(&pdev->dev), host);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret,
|
||||
"could not request irq\n");
|
||||
|
||||
spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);
|
||||
if (IS_ERR(spi->clk))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),
|
||||
"could not get clk\n");
|
||||
|
||||
mchp_corespi_init(host, spi);
|
||||
|
||||
ret = devm_spi_register_controller(&pdev->dev, host);
|
||||
if (ret) {
|
||||
mchp_corespi_disable(spi);
|
||||
return dev_err_probe(&pdev->dev, ret,
|
||||
"unable to register host for CoreSPI controller\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mchp_corespi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct mchp_corespi *spi = spi_controller_get_devdata(host);
|
||||
|
||||
mchp_corespi_disable_ints(spi);
|
||||
mchp_corespi_disable(spi);
|
||||
}
|
||||
|
||||
#define MICROCHIP_SPI_PM_OPS (NULL)
|
||||
|
||||
/*
|
||||
* Platform driver data structure
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
static const struct of_device_id mchp_corespi_dt_ids[] = {
|
||||
{ .compatible = "microchip,corespi-rtl-v5" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids);
|
||||
#endif
|
||||
|
||||
static struct platform_driver mchp_corespi_driver = {
|
||||
.probe = mchp_corespi_probe,
|
||||
.driver = {
|
||||
.name = "microchip-corespi",
|
||||
.pm = MICROCHIP_SPI_PM_OPS,
|
||||
.of_match_table = of_match_ptr(mchp_corespi_dt_ids),
|
||||
},
|
||||
.remove = mchp_corespi_remove,
|
||||
};
|
||||
module_platform_driver(mchp_corespi_driver);
|
||||
MODULE_DESCRIPTION("Microchip CoreSPI controller driver");
|
||||
MODULE_AUTHOR("Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user